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	#include "hwpmc_powerpc.h"			#include "hwpmc_powerpc.h"

	#define POWERPC_PMC_CAPS (PMC_CAP_INTERRUPT \| PMC_CAP_USER \| \			#define POWERPC_PMC_CAPS (PMC_CAP_INTERRUPT \| PMC_CAP_USER \| \
	PMC_CAP_SYSTEM \| PMC_CAP_EDGE \| \			PMC_CAP_SYSTEM \| PMC_CAP_EDGE \| \
	PMC_CAP_THRESHOLD \| PMC_CAP_READ \| \			PMC_CAP_THRESHOLD \| PMC_CAP_READ \| \
	PMC_CAP_WRITE \| PMC_CAP_INVERT \| \			PMC_CAP_WRITE \| PMC_CAP_INVERT \| \
	PMC_CAP_QUALIFIER)			PMC_CAP_QUALIFIER)

	#define E500_PMC_HAS_OVERFLOWED(x) (e500_pmcn_read(x) & (0x1 << 31))			#define E500_PMC_HAS_OVERFLOWED(x) (e500_pmcn_read(x) & (0x1U << 31))

	struct e500_event_code_map {			struct e500_event_code_map {
	enum pmc_event pe_ev; /* enum value */			enum pmc_event pe_ev; /* enum value */
	uint8_t pe_counter_mask; /* Which counter this can be counted in. */			uint8_t pe_counter_mask; /* Which counter this can be counted in. */
	uint8_t pe_code; /* numeric code */			uint8_t pe_code; /* numeric code */
	uint8_t pe_cpu; /* e500 core (v1,v2,mc), mask */			uint8_t pe_cpu; /* e500 core (v1,v2,mc), mask */
	};			};

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