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sys/dev/e1000/e1000_regs.h
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| /* Queues priority masks where _n and _p can be 0-3. */ | /* Queues priority masks where _n and _p can be 0-3. */ | ||||
| #define E1000_TQAVARBCTRL_QUEUE_PRI(_n, _p) ((_p) << (2 * (_n))) | #define E1000_TQAVARBCTRL_QUEUE_PRI(_n, _p) ((_p) << (2 * (_n))) | ||||
| /* QAV Tx mode control registers where _n can be 0 or 1. */ | /* QAV Tx mode control registers where _n can be 0 or 1. */ | ||||
| #define E1000_I210_TQAVCC(_n) (0x3004 + 0x40 * (_n)) | #define E1000_I210_TQAVCC(_n) (0x3004 + 0x40 * (_n)) | ||||
| /* QAV Tx mode control register bitfields masks */ | /* QAV Tx mode control register bitfields masks */ | ||||
| #define E1000_TQAVCC_IDLE_SLOPE 0xFFFF /* Idle slope */ | #define E1000_TQAVCC_IDLE_SLOPE 0xFFFF /* Idle slope */ | ||||
| #define E1000_TQAVCC_KEEP_CREDITS (1 << 30) /* Keep credits opt enable */ | #define E1000_TQAVCC_KEEP_CREDITS (1 << 30) /* Keep credits opt enable */ | ||||
| #define E1000_TQAVCC_QUEUE_MODE (1 << 31) /* SP vs. SR Tx mode */ | #define E1000_TQAVCC_QUEUE_MODE (1U << 31) /* SP vs. SR Tx mode */ | ||||
| /* Good transmitted packets counter registers */ | /* Good transmitted packets counter registers */ | ||||
| #define E1000_PQGPTC(_n) (0x010014 + (0x100 * (_n))) | #define E1000_PQGPTC(_n) (0x010014 + (0x100 * (_n))) | ||||
| /* Queues packet buffer size masks where _n can be 0-3 and _s 0-63 [kB] */ | /* Queues packet buffer size masks where _n can be 0-3 and _s 0-63 [kB] */ | ||||
| #define E1000_I210_TXPBS_SIZE(_n, _s) ((_s) << (6 * (_n))) | #define E1000_I210_TXPBS_SIZE(_n, _s) ((_s) << (6 * (_n))) | ||||
| #define E1000_MMDAC 13 /* MMD Access Control */ | #define E1000_MMDAC 13 /* MMD Access Control */ | ||||
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