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Show First 20 Lines • Show All 2,477 Lines • ▼ Show 20 Lines	void gen6_set_rps(struct drm_device *dev, u8 val)
dev_priv->rps.cur_delay = val;		dev_priv->rps.cur_delay = val;
}		}

static void gen6_disable_rps(struct drm_device *dev)		static void gen6_disable_rps(struct drm_device *dev)
{		{
struct drm_i915_private *dev_priv = dev->dev_private;		struct drm_i915_private *dev_priv = dev->dev_private;

I915_WRITE(GEN6_RC_CONTROL, 0);		I915_WRITE(GEN6_RC_CONTROL, 0);
I915_WRITE(GEN6_RPNSWREQ, 1 << 31);		I915_WRITE(GEN6_RPNSWREQ, 1U << 31);
I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);		I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
I915_WRITE(GEN6_PMIER, 0);		I915_WRITE(GEN6_PMIER, 0);
/* Complete PM interrupt masking here doesn't race with the rps work		/* Complete PM interrupt masking here doesn't race with the rps work
* item again unmasking PM interrupts because that is using a different		* item again unmasking PM interrupts because that is using a different
* register (PMIMR) to mask PM interrupts. The only risk is in leaving		* register (PMIMR) to mask PM interrupts. The only risk is in leaving
* stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */		* stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */

mtx_lock(&dev_priv->rps.lock);		mtx_lock(&dev_priv->rps.lock);
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