Differential D13858 Diff 37788 sys/arm/samsung/exynos/exynos5_usb_phy.c

Changeset View

Standalone View

sys/arm/samsung/exynos/exynos5_usb_phy.c

	Show First 20 Lines • Show All 62 Lines • ▼ Show 20 Lines
	#define USB_DRD_PHYUTMI 0x08			#define USB_DRD_PHYUTMI 0x08
	#define PHYUTMI_OTGDISABLE (1 << 6)			#define PHYUTMI_OTGDISABLE (1 << 6)
	#define PHYUTMI_FORCESUSPEND (1 << 1)			#define PHYUTMI_FORCESUSPEND (1 << 1)
	#define PHYUTMI_FORCESLEEP (1 << 0)			#define PHYUTMI_FORCESLEEP (1 << 0)
	#define USB_DRD_PHYPIPE 0x0c			#define USB_DRD_PHYPIPE 0x0c
	#define USB_DRD_PHYCLKRST 0x10			#define USB_DRD_PHYCLKRST 0x10
	#define PHYCLKRST_PORTRESET (1 << 1)			#define PHYCLKRST_PORTRESET (1 << 1)
	#define PHYCLKRST_COMMONONN (1 << 0)			#define PHYCLKRST_COMMONONN (1 << 0)
	#define PHYCLKRST_EN_UTMISUSPEND (1 << 31)			#define PHYCLKRST_EN_UTMISUSPEND (1U << 31)
	#define PHYCLKRST_SSC_REFCLKSEL_MASK (0xff << 23)			#define PHYCLKRST_SSC_REFCLKSEL_MASK (0xff << 23)
	#define PHYCLKRST_SSC_REFCLKSEL(x) ((x) << 23)			#define PHYCLKRST_SSC_REFCLKSEL(x) ((x) << 23)
	#define PHYCLKRST_SSC_RANGE_MASK (0x03 << 21)			#define PHYCLKRST_SSC_RANGE_MASK (0x03 << 21)
	#define PHYCLKRST_SSC_RANGE(x) ((x) << 21)			#define PHYCLKRST_SSC_RANGE(x) ((x) << 21)
	#define PHYCLKRST_SSC_EN (1 << 20)			#define PHYCLKRST_SSC_EN (1 << 20)
	#define PHYCLKRST_REF_SSP_EN (1 << 19)			#define PHYCLKRST_REF_SSP_EN (1 << 19)
	#define PHYCLKRST_REF_CLKDIV2 (1 << 18)			#define PHYCLKRST_REF_CLKDIV2 (1 << 18)
	#define PHYCLKRST_MPLL_MLTPR_MASK (0x7f << 11)			#define PHYCLKRST_MPLL_MLTPR_MASK (0x7f << 11)
	Show All 14 Lines
	#define PHYCLKRST_FSEL_50MHZ 0x7			#define PHYCLKRST_FSEL_50MHZ 0x7
	#define PHYCLKRST_RETENABLEN (1 << 4)			#define PHYCLKRST_RETENABLEN (1 << 4)
	#define PHYCLKRST_REFCLKSEL_MASK (0x03 << 2)			#define PHYCLKRST_REFCLKSEL_MASK (0x03 << 2)
	#define PHYCLKRST_REFCLKSEL_PAD_REFCLK (0x2 << 2)			#define PHYCLKRST_REFCLKSEL_PAD_REFCLK (0x2 << 2)
	#define PHYCLKRST_REFCLKSEL_EXT_REFCLK (0x3 << 2)			#define PHYCLKRST_REFCLKSEL_EXT_REFCLK (0x3 << 2)
	#define USB_DRD_PHYREG0 0x14			#define USB_DRD_PHYREG0 0x14
	#define USB_DRD_PHYREG1 0x18			#define USB_DRD_PHYREG1 0x18
	#define USB_DRD_PHYPARAM0 0x1c			#define USB_DRD_PHYPARAM0 0x1c
	#define PHYPARAM0_REF_USE_PAD (1 << 31)			#define PHYPARAM0_REF_USE_PAD (1U << 31)
	#define PHYPARAM0_REF_LOSLEVEL_MASK (0x1f << 26)			#define PHYPARAM0_REF_LOSLEVEL_MASK (0x1f << 26)
	#define PHYPARAM0_REF_LOSLEVEL (0x9 << 26)			#define PHYPARAM0_REF_LOSLEVEL (0x9 << 26)
	#define USB_DRD_PHYPARAM1 0x20			#define USB_DRD_PHYPARAM1 0x20
	#define PHYPARAM1_PCS_TXDEEMPH_MASK (0x1f << 0)			#define PHYPARAM1_PCS_TXDEEMPH_MASK (0x1f << 0)
	#define PHYPARAM1_PCS_TXDEEMPH (0x1c)			#define PHYPARAM1_PCS_TXDEEMPH (0x1c)
	#define USB_DRD_PHYTERM 0x24			#define USB_DRD_PHYTERM 0x24
	#define USB_DRD_PHYTEST 0x28			#define USB_DRD_PHYTEST 0x28
	#define PHYTEST_POWERDOWN_SSP (1 << 3)			#define PHYTEST_POWERDOWN_SSP (1 << 3)
	▲ Show 20 Lines • Show All 161 Lines • Show Last 20 Lines