Changeset View
Changeset View
Standalone View
Standalone View
sys/arm/freescale/vybrid/vf_spi.c
| Show First 20 Lines • Show All 55 Lines • ▼ Show 20 Lines | |||||
| #include <machine/cpu.h> | #include <machine/cpu.h> | ||||
| #include <machine/intr.h> | #include <machine/intr.h> | ||||
| #include <arm/freescale/vybrid/vf_common.h> | #include <arm/freescale/vybrid/vf_common.h> | ||||
| #define SPI_FIFO_SIZE 4 | #define SPI_FIFO_SIZE 4 | ||||
| #define SPI_MCR 0x00 /* Module Configuration */ | #define SPI_MCR 0x00 /* Module Configuration */ | ||||
| #define MCR_MSTR (1 << 31) /* Master/Slave Mode Select */ | #define MCR_MSTR (1U << 31) /* Master/Slave Mode Select */ | ||||
| #define MCR_CONT_SCKE (1 << 30) /* Continuous SCK Enable */ | #define MCR_CONT_SCKE (1 << 30) /* Continuous SCK Enable */ | ||||
| #define MCR_FRZ (1 << 27) /* Freeze */ | #define MCR_FRZ (1 << 27) /* Freeze */ | ||||
| #define MCR_PCSIS_S 16 /* Peripheral Chip Select */ | #define MCR_PCSIS_S 16 /* Peripheral Chip Select */ | ||||
| #define MCR_PCSIS_M 0x3f | #define MCR_PCSIS_M 0x3f | ||||
| #define MCR_MDIS (1 << 14) /* Module Disable */ | #define MCR_MDIS (1 << 14) /* Module Disable */ | ||||
| #define MCR_CLR_TXF (1 << 11) /* Clear TX FIFO */ | #define MCR_CLR_TXF (1 << 11) /* Clear TX FIFO */ | ||||
| #define MCR_CLR_RXF (1 << 10) /* Clear RX FIFO */ | #define MCR_CLR_RXF (1 << 10) /* Clear RX FIFO */ | ||||
| #define MCR_HALT (1 << 0) /* Starts and stops SPI transfers */ | #define MCR_HALT (1 << 0) /* Starts and stops SPI transfers */ | ||||
| Show All 14 Lines | |||||
| #define CTAR_PBR_M 0x3 | #define CTAR_PBR_M 0x3 | ||||
| #define CTAR_PBR_S 16 /* Baud Rate Prescaler */ | #define CTAR_PBR_S 16 /* Baud Rate Prescaler */ | ||||
| #define CTAR_PBR_7 0x3 /* Divide by 7 */ | #define CTAR_PBR_7 0x3 /* Divide by 7 */ | ||||
| #define CTAR_CSSCK_M 0xf | #define CTAR_CSSCK_M 0xf | ||||
| #define CTAR_CSSCK_S 12 /* PCS to SCK Delay Scaler */ | #define CTAR_CSSCK_S 12 /* PCS to SCK Delay Scaler */ | ||||
| #define CTAR_BR_M 0xf | #define CTAR_BR_M 0xf | ||||
| #define CTAR_BR_S 0 /* Baud Rate Scaler */ | #define CTAR_BR_S 0 /* Baud Rate Scaler */ | ||||
| #define SPI_SR 0x2C /* Status Register */ | #define SPI_SR 0x2C /* Status Register */ | ||||
| #define SR_TCF (1 << 31) /* Transfer Complete Flag */ | #define SR_TCF (1U << 31) /* Transfer Complete Flag */ | ||||
| #define SR_EOQF (1 << 28) /* End of Queue Flag */ | #define SR_EOQF (1 << 28) /* End of Queue Flag */ | ||||
| #define SR_TFFF (1 << 25) /* Transmit FIFO Fill Flag */ | #define SR_TFFF (1 << 25) /* Transmit FIFO Fill Flag */ | ||||
| #define SR_RFDF (1 << 17) /* Receive FIFO Drain Flag */ | #define SR_RFDF (1 << 17) /* Receive FIFO Drain Flag */ | ||||
| #define SPI_RSER 0x30 /* DMA/Interrupt Select */ | #define SPI_RSER 0x30 /* DMA/Interrupt Select */ | ||||
| #define RSER_EOQF_RE (1 << 28) /* Finished Request Enable */ | #define RSER_EOQF_RE (1 << 28) /* Finished Request Enable */ | ||||
| #define SPI_PUSHR 0x34 /* PUSH TX FIFO In Master Mode */ | #define SPI_PUSHR 0x34 /* PUSH TX FIFO In Master Mode */ | ||||
| #define PUSHR_CONT (1 << 31) /* Continuous Peripheral CS */ | #define PUSHR_CONT (1U << 31) /* Continuous Peripheral CS */ | ||||
| #define PUSHR_EOQ (1 << 27) /* End Of Queue */ | #define PUSHR_EOQ (1 << 27) /* End Of Queue */ | ||||
| #define PUSHR_CTCNT (1 << 26) /* Clear Transfer Counter */ | #define PUSHR_CTCNT (1 << 26) /* Clear Transfer Counter */ | ||||
| #define PUSHR_PCS_M 0x3f | #define PUSHR_PCS_M 0x3f | ||||
| #define PUSHR_PCS_S 16 /* Select PCS signals */ | #define PUSHR_PCS_S 16 /* Select PCS signals */ | ||||
| #define SPI_PUSHR_SLAVE 0x34 /* PUSH TX FIFO Register In Slave Mode */ | #define SPI_PUSHR_SLAVE 0x34 /* PUSH TX FIFO Register In Slave Mode */ | ||||
| #define SPI_POPR 0x38 /* POP RX FIFO Register */ | #define SPI_POPR 0x38 /* POP RX FIFO Register */ | ||||
| #define SPI_TXFR0 0x3C /* Transmit FIFO Registers */ | #define SPI_TXFR0 0x3C /* Transmit FIFO Registers */ | ||||
| ▲ Show 20 Lines • Show All 183 Lines • Show Last 20 Lines | |||||