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sys/arm/freescale/vybrid/vf_sai.c
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| #define TCR4_FSP (1 << 1) /* Frame Sync Polarity Low */ | #define TCR4_FSP (1 << 1) /* Frame Sync Polarity Low */ | ||||
| #define TCR4_FSD (1 << 0) /* Frame Sync Direction Master */ | #define TCR4_FSD (1 << 0) /* Frame Sync Direction Master */ | ||||
| #define TCR5_FBT_M 0x1f /* First Bit Shifted */ | #define TCR5_FBT_M 0x1f /* First Bit Shifted */ | ||||
| #define TCR5_FBT_S 8 /* First Bit Shifted */ | #define TCR5_FBT_S 8 /* First Bit Shifted */ | ||||
| #define TCR5_W0W_M 0x1f /* Word 0 Width */ | #define TCR5_W0W_M 0x1f /* Word 0 Width */ | ||||
| #define TCR5_W0W_S 16 /* Word 0 Width */ | #define TCR5_W0W_S 16 /* Word 0 Width */ | ||||
| #define TCR5_WNW_M 0x1f /* Word N Width */ | #define TCR5_WNW_M 0x1f /* Word N Width */ | ||||
| #define TCR5_WNW_S 24 /* Word N Width */ | #define TCR5_WNW_S 24 /* Word N Width */ | ||||
| #define TCSR_TE (1 << 31) /* Transmitter Enable */ | #define TCSR_TE (1U << 31) /* Transmitter Enable */ | ||||
| #define TCSR_BCE (1 << 28) /* Bit Clock Enable */ | #define TCSR_BCE (1 << 28) /* Bit Clock Enable */ | ||||
| #define TCSR_FRDE (1 << 0) /* FIFO Request DMA Enable */ | #define TCSR_FRDE (1 << 0) /* FIFO Request DMA Enable */ | ||||
| #define SAI_NCHANNELS 1 | #define SAI_NCHANNELS 1 | ||||
| static MALLOC_DEFINE(M_SAI, "sai", "sai audio"); | static MALLOC_DEFINE(M_SAI, "sai", "sai audio"); | ||||
| struct sai_rate { | struct sai_rate { | ||||
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