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sys/arm/freescale/vybrid/vf_dcu4.c
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#define DCU_LYR_INTPOL_EN 0x0B4 /* Layer Interpolation Enable */ | #define DCU_LYR_INTPOL_EN 0x0B4 /* Layer Interpolation Enable */ | ||||
#define DCU_LYR_LUMA_COMP 0x0B8 /* Layer Luminance Component */ | #define DCU_LYR_LUMA_COMP 0x0B8 /* Layer Luminance Component */ | ||||
#define DCU_LYR_CHRM_RED 0x0BC /* Layer Chroma Red */ | #define DCU_LYR_CHRM_RED 0x0BC /* Layer Chroma Red */ | ||||
#define DCU_LYR_CHRM_GRN 0x0C0 /* Layer Chroma Green */ | #define DCU_LYR_CHRM_GRN 0x0C0 /* Layer Chroma Green */ | ||||
#define DCU_LYR_CHRM_BLUE 0x0C4 /* Layer Chroma Blue */ | #define DCU_LYR_CHRM_BLUE 0x0C4 /* Layer Chroma Blue */ | ||||
#define DCU_COMP_IMSIZE 0x0C8 /* Compression Image Size */ | #define DCU_COMP_IMSIZE 0x0C8 /* Compression Image Size */ | ||||
#define DCU_UPDATE_MODE 0x0CC /* Update Mode */ | #define DCU_UPDATE_MODE 0x0CC /* Update Mode */ | ||||
#define READREG (1 << 30) | #define READREG (1 << 30) | ||||
#define MODE (1 << 31) | #define MODE (1U << 31) | ||||
#define DCU_UNDERRUN 0x0D0 /* Underrun */ | #define DCU_UNDERRUN 0x0D0 /* Underrun */ | ||||
#define DCU_GLBL_PROTECT 0x100 /* Global Protection */ | #define DCU_GLBL_PROTECT 0x100 /* Global Protection */ | ||||
#define DCU_SFT_LCK_BIT_L0 0x104 /* Soft Lock Bit Layer 0 */ | #define DCU_SFT_LCK_BIT_L0 0x104 /* Soft Lock Bit Layer 0 */ | ||||
#define DCU_SFT_LCK_BIT_L1 0x108 /* Soft Lock Bit Layer 1 */ | #define DCU_SFT_LCK_BIT_L1 0x108 /* Soft Lock Bit Layer 1 */ | ||||
#define DCU_SFT_LCK_DISP_SIZE 0x10C /* Soft Lock Display Size */ | #define DCU_SFT_LCK_DISP_SIZE 0x10C /* Soft Lock Display Size */ | ||||
#define DCU_SFT_LCK_HS_VS_PARA 0x110 /* Soft Lock Hsync/Vsync Parameter */ | #define DCU_SFT_LCK_HS_VS_PARA 0x110 /* Soft Lock Hsync/Vsync Parameter */ | ||||
#define DCU_SFT_LCK_POL 0x114 /* Soft Lock POL */ | #define DCU_SFT_LCK_POL 0x114 /* Soft Lock POL */ | ||||
#define DCU_SFT_LCK_L0_TRANSP 0x118 /* Soft Lock L0 Transparency */ | #define DCU_SFT_LCK_L0_TRANSP 0x118 /* Soft Lock L0 Transparency */ | ||||
#define DCU_SFT_LCK_L1_TRANSP 0x11C /* Soft Lock L1 Transparency */ | #define DCU_SFT_LCK_L1_TRANSP 0x11C /* Soft Lock L1 Transparency */ | ||||
/* Control Descriptor */ | /* Control Descriptor */ | ||||
#define DCU_CTRLDESCL(n, m) 0x200 + (0x40 * n) + 0x4 * (m - 1) | #define DCU_CTRLDESCL(n, m) 0x200 + (0x40 * n) + 0x4 * (m - 1) | ||||
#define DCU_CTRLDESCLn_1(n) DCU_CTRLDESCL(n, 1) | #define DCU_CTRLDESCLn_1(n) DCU_CTRLDESCL(n, 1) | ||||
#define DCU_CTRLDESCLn_2(n) DCU_CTRLDESCL(n, 2) | #define DCU_CTRLDESCLn_2(n) DCU_CTRLDESCL(n, 2) | ||||
#define DCU_CTRLDESCLn_3(n) DCU_CTRLDESCL(n, 3) | #define DCU_CTRLDESCLn_3(n) DCU_CTRLDESCL(n, 3) | ||||
#define TRANS_SHIFT 20 | #define TRANS_SHIFT 20 | ||||
#define DCU_CTRLDESCLn_4(n) DCU_CTRLDESCL(n, 4) | #define DCU_CTRLDESCLn_4(n) DCU_CTRLDESCL(n, 4) | ||||
#define BPP_MASK 0xf /* Bit per pixel Mask */ | #define BPP_MASK 0xf /* Bit per pixel Mask */ | ||||
#define BPP_SHIFT 16 /* Bit per pixel Shift */ | #define BPP_SHIFT 16 /* Bit per pixel Shift */ | ||||
#define BPP24 0x5 | #define BPP24 0x5 | ||||
#define EN_LAYER (1 << 31) /* Enable the layer */ | #define EN_LAYER (1U << 31) /* Enable the layer */ | ||||
#define DCU_CTRLDESCLn_5(n) DCU_CTRLDESCL(n, 5) | #define DCU_CTRLDESCLn_5(n) DCU_CTRLDESCL(n, 5) | ||||
#define DCU_CTRLDESCLn_6(n) DCU_CTRLDESCL(n, 6) | #define DCU_CTRLDESCLn_6(n) DCU_CTRLDESCL(n, 6) | ||||
#define DCU_CTRLDESCLn_7(n) DCU_CTRLDESCL(n, 7) | #define DCU_CTRLDESCLn_7(n) DCU_CTRLDESCL(n, 7) | ||||
#define DCU_CTRLDESCLn_8(n) DCU_CTRLDESCL(n, 8) | #define DCU_CTRLDESCLn_8(n) DCU_CTRLDESCL(n, 8) | ||||
#define DCU_CTRLDESCLn_9(n) DCU_CTRLDESCL(n, 9) | #define DCU_CTRLDESCLn_9(n) DCU_CTRLDESCL(n, 9) | ||||
#define NUM_LAYERS 64 | #define NUM_LAYERS 64 | ||||
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