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Differential D13858 Diff 37788 sys/arm/allwinner/if_awgreg.h

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sys/arm/allwinner/if_awgreg.h

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#define EMAC_INT_EN 0x0c #define EMAC_INT_EN 0x0c
#define RX_BUF_UA_INT_EN (1 << 10) #define RX_BUF_UA_INT_EN (1 << 10)
#define RX_INT_EN (1 << 8) #define RX_INT_EN (1 << 8)
#define TX_UNDERFLOW_INT_EN (1 << 4) #define TX_UNDERFLOW_INT_EN (1 << 4)
#define TX_BUF_UA_INT_EN (1 << 2) #define TX_BUF_UA_INT_EN (1 << 2)
#define TX_DMA_STOPPED_INT_EN (1 << 1) #define TX_DMA_STOPPED_INT_EN (1 << 1)
#define TX_INT_EN (1 << 0) #define TX_INT_EN (1 << 0)
#define EMAC_TX_CTL_0 0x10 #define EMAC_TX_CTL_0 0x10
#define TX_EN (1 << 31) #define TX_EN (1U << 31)
#define EMAC_TX_CTL_1 0x14 #define EMAC_TX_CTL_1 0x14
#define TX_DMA_START (1 << 31) #define TX_DMA_START (1U << 31)
#define TX_DMA_EN (1 << 30) #define TX_DMA_EN (1 << 30)
#define TX_NEXT_FRAME (1 << 2) #define TX_NEXT_FRAME (1 << 2)
#define TX_MD (1 << 1) #define TX_MD (1 << 1)
#define FLUSH_TX_FIFO (1 << 0) #define FLUSH_TX_FIFO (1 << 0)
#define EMAC_TX_FLOW_CTL 0x1c #define EMAC_TX_FLOW_CTL 0x1c
#define PAUSE_TIME (0xffff << 4) #define PAUSE_TIME (0xffff << 4)
#define PAUSE_TIME_SHIFT 4 #define PAUSE_TIME_SHIFT 4
#define TX_FLOW_CTL_EN (1 << 0) #define TX_FLOW_CTL_EN (1 << 0)
#define EMAC_TX_DMA_LIST 0x20 #define EMAC_TX_DMA_LIST 0x20
#define EMAC_RX_CTL_0 0x24 #define EMAC_RX_CTL_0 0x24
#define RX_EN (1 << 31) #define RX_EN (1U << 31)
#define JUMBO_FRM_EN (1 << 29) #define JUMBO_FRM_EN (1 << 29)
#define STRIP_FCS (1 << 28) #define STRIP_FCS (1 << 28)
#define CHECK_CRC (1 << 27) #define CHECK_CRC (1 << 27)
#define RX_FLOW_CTL_EN (1 << 16) #define RX_FLOW_CTL_EN (1 << 16)
#define EMAC_RX_CTL_1 0x28 #define EMAC_RX_CTL_1 0x28
#define RX_DMA_START (1 << 31) #define RX_DMA_START (1U << 31)
#define RX_DMA_EN (1 << 30) #define RX_DMA_EN (1 << 30)
#define RX_MD (1 << 1) #define RX_MD (1 << 1)
#define EMAC_RX_DMA_LIST 0x34 #define EMAC_RX_DMA_LIST 0x34
#define EMAC_RX_FRM_FLT 0x38 #define EMAC_RX_FRM_FLT 0x38
#define DIS_ADDR_FILTER (1 << 31) #define DIS_ADDR_FILTER (1U << 31)
#define DIS_BROADCAST (1 << 17) #define DIS_BROADCAST (1 << 17)
#define RX_ALL_MULTICAST (1 << 16) #define RX_ALL_MULTICAST (1 << 16)
#define CTL_FRM_FILTER (0x3 << 12) #define CTL_FRM_FILTER (0x3 << 12)
#define CTL_FRM_FILTER_SHIFT 12 #define CTL_FRM_FILTER_SHIFT 12
#define HASH_MULTICAST (1 << 9) #define HASH_MULTICAST (1 << 9)
#define HASH_UNICAST (1 << 8) #define HASH_UNICAST (1 << 8)
#define SA_FILTER_EN (1 << 6) #define SA_FILTER_EN (1 << 6)
#define SA_INV_FILTER (1 << 5) #define SA_INV_FILTER (1 << 5)
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#define EMAC_RX_DMA_STA 0xc0 #define EMAC_RX_DMA_STA 0xc0
#define EMAC_RX_DMA_CUR_DESC 0xc4 #define EMAC_RX_DMA_CUR_DESC 0xc4
#define EMAC_RX_DMA_CUR_BUF 0xc8 #define EMAC_RX_DMA_CUR_BUF 0xc8
#define EMAC_RGMII_STA 0xd0 #define EMAC_RGMII_STA 0xd0
struct emac_desc { struct emac_desc {
uint32_t status; uint32_t status;
/* Transmit */ /* Transmit */
#define TX_DESC_CTL (1 << 31) #define TX_DESC_CTL (1U << 31)
#define TX_HEADER_ERR (1 << 16) #define TX_HEADER_ERR (1 << 16)
#define TX_LENGTH_ERR (1 << 14) #define TX_LENGTH_ERR (1 << 14)
#define TX_PAYLOAD_ERR (1 << 12) #define TX_PAYLOAD_ERR (1 << 12)
#define TX_CRS_ERR (1 << 10) #define TX_CRS_ERR (1 << 10)
#define TX_COL_ERR_0 (1 << 9) #define TX_COL_ERR_0 (1 << 9)
#define TX_COL_ERR_1 (1 << 8) #define TX_COL_ERR_1 (1 << 8)
#define TX_COL_CNT (0xf << 3) #define TX_COL_CNT (0xf << 3)
#define TX_COL_CNT_SHIFT 3 #define TX_COL_CNT_SHIFT 3
#define TX_DEFER_ERR (1 << 2) #define TX_DEFER_ERR (1 << 2)
#define TX_UNDERFLOW_ERR (1 << 1) #define TX_UNDERFLOW_ERR (1 << 1)
#define TX_DEFER (1 << 0) #define TX_DEFER (1 << 0)
/* Receive */ /* Receive */
#define RX_DESC_CTL (1 << 31) #define RX_DESC_CTL (1U << 31)
#define RX_DAF_FAIL (1 << 30) #define RX_DAF_FAIL (1 << 30)
#define RX_FRM_LEN (0x3fff << 16) #define RX_FRM_LEN (0x3fff << 16)
#define RX_FRM_LEN_SHIFT 16 #define RX_FRM_LEN_SHIFT 16
#define RX_NO_ENOUGH_BUF_ERR (1 << 14) #define RX_NO_ENOUGH_BUF_ERR (1 << 14)
#define RX_SAF_FAIL (1 << 13) #define RX_SAF_FAIL (1 << 13)
#define RX_OVERFLOW_ERR (1 << 11) #define RX_OVERFLOW_ERR (1 << 11)
#define RX_FIR_DESC (1 << 9) #define RX_FIR_DESC (1 << 9)
#define RX_LAST_DESC (1 << 8) #define RX_LAST_DESC (1 << 8)
#define RX_HEADER_ERR (1 << 7) #define RX_HEADER_ERR (1 << 7)
#define RX_COL_ERR (1 << 6) #define RX_COL_ERR (1 << 6)
#define RX_FRM_TYPE (1 << 5) #define RX_FRM_TYPE (1 << 5)
#define RX_LENGTH_ERR (1 << 4) #define RX_LENGTH_ERR (1 << 4)
#define RX_PHY_ERR (1 << 3) #define RX_PHY_ERR (1 << 3)
#define RX_CRC_ERR (1 << 1) #define RX_CRC_ERR (1 << 1)
#define RX_PAYLOAD_ERR (1 << 0) #define RX_PAYLOAD_ERR (1 << 0)
uint32_t size; uint32_t size;
/* Transmit */ /* Transmit */
#define TX_INT_CTL (1 << 31) #define TX_INT_CTL (1U << 31)
#define TX_LAST_DESC (1 << 30) #define TX_LAST_DESC (1 << 30)
#define TX_FIR_DESC (1 << 29) #define TX_FIR_DESC (1 << 29)
#define TX_CHECKSUM_CTL (0x3 << 27) #define TX_CHECKSUM_CTL (0x3 << 27)
#define TX_CHECKSUM_CTL_IP 1 #define TX_CHECKSUM_CTL_IP 1
#define TX_CHECKSUM_CTL_NO_PSE 2 #define TX_CHECKSUM_CTL_NO_PSE 2
#define TX_CHECKSUM_CTL_FULL 3 #define TX_CHECKSUM_CTL_FULL 3
#define TX_CHECKSUM_CTL_SHIFT 27 #define TX_CHECKSUM_CTL_SHIFT 27
#define TX_CRC_CTL (1 << 26) #define TX_CRC_CTL (1 << 26)
#define TX_BUF_SIZE (0xfff << 0) #define TX_BUF_SIZE (0xfff << 0)
#define TX_BUF_SIZE_SHIFT 0 #define TX_BUF_SIZE_SHIFT 0
/* Receive */ /* Receive */
#define RX_INT_CTL (1 << 31) #define RX_INT_CTL (1U << 31)
#define RX_BUF_SIZE (0xfff << 0) #define RX_BUF_SIZE (0xfff << 0)
#define RX_BUF_SIZE_SHIFT 0 #define RX_BUF_SIZE_SHIFT 0
uint32_t addr; uint32_t addr;
uint32_t next; uint32_t next;
} __packed; } __packed;
#endif /* !__IF_AWGREG_H__ */ #endif /* !__IF_AWGREG_H__ */