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head/sys/dev/bhnd/bhndb/bhndb_pcireg.h
| Show First 20 Lines • Show All 178 Lines • ▼ Show 20 Lines | |||||
| #define BHNDB_PCI_V3_BAR0_CCREGS_OFFSET 0x3000 /* bar0 + 12K accesses chipc core registers */ | #define BHNDB_PCI_V3_BAR0_CCREGS_OFFSET 0x3000 /* bar0 + 12K accesses chipc core registers */ | ||||
| #define BHNDB_PCI_V3_BAR0_CCREGS_SIZE 0x1000 | #define BHNDB_PCI_V3_BAR0_CCREGS_SIZE 0x1000 | ||||
| /* BHNDB_PCI_INT_STATUS */ | /* BHNDB_PCI_INT_STATUS */ | ||||
| #define BHNDB_PCI_SBIM_STATUS_SERR 0x4 /* backplane SBErr interrupt status */ | #define BHNDB_PCI_SBIM_STATUS_SERR 0x4 /* backplane SBErr interrupt status */ | ||||
| /* BHNDB_PCI_INT_MASK */ | /* BHNDB_PCI_INT_MASK */ | ||||
| #define BHNDB_PCI_SBIM_SHIFT 8 /* backplane core interrupt mask bits offset */ | #define BHNDB_PCI_SBIM_SHIFT 8 /* backplane core interrupt mask bits offset */ | ||||
| #define BHNDB_PCI_SBIM_COREIDX_MAX 15 /**< maximum representible core index (in 16 bit field) */ | |||||
| #define BHNDB_PCI_SBIM_MASK 0xff00 /* backplane core interrupt mask */ | #define BHNDB_PCI_SBIM_MASK 0xff00 /* backplane core interrupt mask */ | ||||
| #define BHNDB_PCI_SBIM_MASK_SERR 0x4 /* backplane SBErr interrupt mask */ | #define BHNDB_PCI_SBIM_MASK_SERR 0x4 /* backplane SBErr interrupt mask */ | ||||
| /* BHNDB_PCI_SPROM_CONTROL */ | /* BHNDB_PCI_SPROM_CONTROL */ | ||||
| #define BHNDB_PCI_SPROM_SZ_MASK 0x03 /**< sprom size mask */ | #define BHNDB_PCI_SPROM_SZ_MASK 0x03 /**< sprom size mask */ | ||||
| #define BHNDB_PCI_SPROM_SZ_1KB 0x00 /**< 1KB sprom size */ | #define BHNDB_PCI_SPROM_SZ_1KB 0x00 /**< 1KB sprom size */ | ||||
| #define BHNDB_PCI_SPROM_SZ_4KB 0x01 /**< 4KB sprom size */ | #define BHNDB_PCI_SPROM_SZ_4KB 0x01 /**< 4KB sprom size */ | ||||
| #define BHNDB_PCI_SPROM_SZ_16KB 0x02 /**< 16KB sprom size */ | #define BHNDB_PCI_SPROM_SZ_16KB 0x02 /**< 16KB sprom size */ | ||||
| Show All 16 Lines | |||||