Changeset View
Changeset View
Standalone View
Standalone View
lib/libpmc/libpmc.c
Show First 20 Lines • Show All 76 Lines • ▼ Show 20 Lines | |||||
#if defined(__arm__) | #if defined(__arm__) | ||||
#if defined(__XSCALE__) | #if defined(__XSCALE__) | ||||
static int xscale_allocate_pmc(enum pmc_event _pe, char *_ctrspec, | static int xscale_allocate_pmc(enum pmc_event _pe, char *_ctrspec, | ||||
struct pmc_op_pmcallocate *_pmc_config); | struct pmc_op_pmcallocate *_pmc_config); | ||||
#endif | #endif | ||||
static int armv7_allocate_pmc(enum pmc_event _pe, char *_ctrspec, | static int armv7_allocate_pmc(enum pmc_event _pe, char *_ctrspec, | ||||
struct pmc_op_pmcallocate *_pmc_config); | struct pmc_op_pmcallocate *_pmc_config); | ||||
#endif | #endif | ||||
#if defined(__aarch64__) | |||||
bz: Talk to Andy about these; I think it should be an arm version check there these days. | |||||
Done Inline Actions@bz, do you mean something akin to __armv8__? __aarch64__ should sort before __arm__, but i386 above breaks an attempt to sort the full list properly. I'd still put it above. emaste: @bz, do you mean something akin to `__armv8__`?
`__aarch64__` should sort before `__arm__`… | |||||
Done Inline Actions__armv8__ would be spelt __ARM_ARCH == 8, however this is not armv8 code, it's for arm64 so the check is correct, however the functions name should be something like arm64_allocate_pmc. andrew: `__armv8__` would be spelt `__ARM_ARCH == 8`, however this is not armv8 code, it's for arm64 so… | |||||
static int armv8_allocate_pmc(enum pmc_event _pe, char *_ctrspec, | |||||
struct pmc_op_pmcallocate *_pmc_config); | |||||
#endif | |||||
#if defined(__mips__) | #if defined(__mips__) | ||||
static int mips_allocate_pmc(enum pmc_event _pe, char* ctrspec, | static int mips_allocate_pmc(enum pmc_event _pe, char* ctrspec, | ||||
struct pmc_op_pmcallocate *_pmc_config); | struct pmc_op_pmcallocate *_pmc_config); | ||||
#endif /* __mips__ */ | #endif /* __mips__ */ | ||||
static int soft_allocate_pmc(enum pmc_event _pe, char *_ctrspec, | static int soft_allocate_pmc(enum pmc_event _pe, char *_ctrspec, | ||||
struct pmc_op_pmcallocate *_pmc_config); | struct pmc_op_pmcallocate *_pmc_config); | ||||
#if defined(__powerpc__) | #if defined(__powerpc__) | ||||
▲ Show 20 Lines • Show All 60 Lines • ▼ Show 20 Lines | |||||
PMC_CLASSDEP_TABLE(iaf, IAF); | PMC_CLASSDEP_TABLE(iaf, IAF); | ||||
PMC_CLASSDEP_TABLE(k7, K7); | PMC_CLASSDEP_TABLE(k7, K7); | ||||
PMC_CLASSDEP_TABLE(k8, K8); | PMC_CLASSDEP_TABLE(k8, K8); | ||||
PMC_CLASSDEP_TABLE(p4, P4); | PMC_CLASSDEP_TABLE(p4, P4); | ||||
PMC_CLASSDEP_TABLE(p5, P5); | PMC_CLASSDEP_TABLE(p5, P5); | ||||
PMC_CLASSDEP_TABLE(p6, P6); | PMC_CLASSDEP_TABLE(p6, P6); | ||||
PMC_CLASSDEP_TABLE(xscale, XSCALE); | PMC_CLASSDEP_TABLE(xscale, XSCALE); | ||||
PMC_CLASSDEP_TABLE(armv7, ARMV7); | PMC_CLASSDEP_TABLE(armv7, ARMV7); | ||||
PMC_CLASSDEP_TABLE(armv8, ARMV8); | |||||
PMC_CLASSDEP_TABLE(mips24k, MIPS24K); | PMC_CLASSDEP_TABLE(mips24k, MIPS24K); | ||||
PMC_CLASSDEP_TABLE(mips74k, MIPS74K); | PMC_CLASSDEP_TABLE(mips74k, MIPS74K); | ||||
PMC_CLASSDEP_TABLE(octeon, OCTEON); | PMC_CLASSDEP_TABLE(octeon, OCTEON); | ||||
PMC_CLASSDEP_TABLE(ucf, UCF); | PMC_CLASSDEP_TABLE(ucf, UCF); | ||||
PMC_CLASSDEP_TABLE(ppc7450, PPC7450); | PMC_CLASSDEP_TABLE(ppc7450, PPC7450); | ||||
PMC_CLASSDEP_TABLE(ppc970, PPC970); | PMC_CLASSDEP_TABLE(ppc970, PPC970); | ||||
PMC_CLASSDEP_TABLE(e500, E500); | PMC_CLASSDEP_TABLE(e500, E500); | ||||
▲ Show 20 Lines • Show All 89 Lines • ▼ Show 20 Lines | static const struct pmc_event_descr sandybridgeuc_event_table[] = | ||||
__PMC_EV_ALIAS_SANDYBRIDGEUC() | __PMC_EV_ALIAS_SANDYBRIDGEUC() | ||||
}; | }; | ||||
static const struct pmc_event_descr westmereuc_event_table[] = | static const struct pmc_event_descr westmereuc_event_table[] = | ||||
{ | { | ||||
__PMC_EV_ALIAS_WESTMEREUC() | __PMC_EV_ALIAS_WESTMEREUC() | ||||
}; | }; | ||||
static const struct pmc_event_descr cortex_a53_event_table[] = | |||||
{ | |||||
__PMC_EV_ALIAS_ARMV8_CORTEX_A53() | |||||
}; | |||||
static const struct pmc_event_descr cortex_a57_event_table[] = | |||||
{ | |||||
__PMC_EV_ALIAS_ARMV8_CORTEX_A57() | |||||
}; | |||||
/* | /* | ||||
* PMC_MDEP_TABLE(NAME, PRIMARYCLASS, ADDITIONAL_CLASSES...) | * PMC_MDEP_TABLE(NAME, PRIMARYCLASS, ADDITIONAL_CLASSES...) | ||||
* | * | ||||
* Map a CPU to the PMC classes it supports. | * Map a CPU to the PMC classes it supports. | ||||
*/ | */ | ||||
#define PMC_MDEP_TABLE(N,C,...) \ | #define PMC_MDEP_TABLE(N,C,...) \ | ||||
static const enum pmc_class N##_pmc_classes[] = { \ | static const enum pmc_class N##_pmc_classes[] = { \ | ||||
PMC_CLASS_##C, __VA_ARGS__ \ | PMC_CLASS_##C, __VA_ARGS__ \ | ||||
Show All 15 Lines | |||||
PMC_MDEP_TABLE(westmere_ex, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC); | PMC_MDEP_TABLE(westmere_ex, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC); | ||||
PMC_MDEP_TABLE(k7, K7, PMC_CLASS_SOFT, PMC_CLASS_TSC); | PMC_MDEP_TABLE(k7, K7, PMC_CLASS_SOFT, PMC_CLASS_TSC); | ||||
PMC_MDEP_TABLE(k8, K8, PMC_CLASS_SOFT, PMC_CLASS_TSC); | PMC_MDEP_TABLE(k8, K8, PMC_CLASS_SOFT, PMC_CLASS_TSC); | ||||
PMC_MDEP_TABLE(p4, P4, PMC_CLASS_SOFT, PMC_CLASS_TSC); | PMC_MDEP_TABLE(p4, P4, PMC_CLASS_SOFT, PMC_CLASS_TSC); | ||||
PMC_MDEP_TABLE(p5, P5, PMC_CLASS_SOFT, PMC_CLASS_TSC); | PMC_MDEP_TABLE(p5, P5, PMC_CLASS_SOFT, PMC_CLASS_TSC); | ||||
PMC_MDEP_TABLE(p6, P6, PMC_CLASS_SOFT, PMC_CLASS_TSC); | PMC_MDEP_TABLE(p6, P6, PMC_CLASS_SOFT, PMC_CLASS_TSC); | ||||
PMC_MDEP_TABLE(xscale, XSCALE, PMC_CLASS_SOFT, PMC_CLASS_XSCALE); | PMC_MDEP_TABLE(xscale, XSCALE, PMC_CLASS_SOFT, PMC_CLASS_XSCALE); | ||||
PMC_MDEP_TABLE(armv7, ARMV7, PMC_CLASS_SOFT, PMC_CLASS_ARMV7); | PMC_MDEP_TABLE(armv7, ARMV7, PMC_CLASS_SOFT, PMC_CLASS_ARMV7); | ||||
PMC_MDEP_TABLE(cortex_a53, ARMV8, PMC_CLASS_SOFT, PMC_CLASS_ARMV8); | |||||
PMC_MDEP_TABLE(cortex_a57, ARMV8, PMC_CLASS_SOFT, PMC_CLASS_ARMV8); | |||||
PMC_MDEP_TABLE(mips24k, MIPS24K, PMC_CLASS_SOFT, PMC_CLASS_MIPS24K); | PMC_MDEP_TABLE(mips24k, MIPS24K, PMC_CLASS_SOFT, PMC_CLASS_MIPS24K); | ||||
PMC_MDEP_TABLE(mips74k, MIPS74K, PMC_CLASS_SOFT, PMC_CLASS_MIPS74K); | PMC_MDEP_TABLE(mips74k, MIPS74K, PMC_CLASS_SOFT, PMC_CLASS_MIPS74K); | ||||
PMC_MDEP_TABLE(octeon, OCTEON, PMC_CLASS_SOFT, PMC_CLASS_OCTEON); | PMC_MDEP_TABLE(octeon, OCTEON, PMC_CLASS_SOFT, PMC_CLASS_OCTEON); | ||||
PMC_MDEP_TABLE(ppc7450, PPC7450, PMC_CLASS_SOFT, PMC_CLASS_PPC7450, PMC_CLASS_TSC); | PMC_MDEP_TABLE(ppc7450, PPC7450, PMC_CLASS_SOFT, PMC_CLASS_PPC7450, PMC_CLASS_TSC); | ||||
PMC_MDEP_TABLE(ppc970, PPC970, PMC_CLASS_SOFT, PMC_CLASS_PPC970, PMC_CLASS_TSC); | PMC_MDEP_TABLE(ppc970, PPC970, PMC_CLASS_SOFT, PMC_CLASS_PPC970, PMC_CLASS_TSC); | ||||
PMC_MDEP_TABLE(e500, E500, PMC_CLASS_SOFT, PMC_CLASS_E500, PMC_CLASS_TSC); | PMC_MDEP_TABLE(e500, E500, PMC_CLASS_SOFT, PMC_CLASS_E500, PMC_CLASS_TSC); | ||||
PMC_MDEP_TABLE(generic, SOFT, PMC_CLASS_SOFT); | PMC_MDEP_TABLE(generic, SOFT, PMC_CLASS_SOFT); | ||||
▲ Show 20 Lines • Show All 52 Lines • ▼ Show 20 Lines | |||||
PMC_CLASS_TABLE_DESC(tsc, TSC, tsc, tsc); | PMC_CLASS_TABLE_DESC(tsc, TSC, tsc, tsc); | ||||
#endif | #endif | ||||
#if defined(__arm__) | #if defined(__arm__) | ||||
#if defined(__XSCALE__) | #if defined(__XSCALE__) | ||||
PMC_CLASS_TABLE_DESC(xscale, XSCALE, xscale, xscale); | PMC_CLASS_TABLE_DESC(xscale, XSCALE, xscale, xscale); | ||||
#endif | #endif | ||||
PMC_CLASS_TABLE_DESC(armv7, ARMV7, armv7, armv7); | PMC_CLASS_TABLE_DESC(armv7, ARMV7, armv7, armv7); | ||||
#endif | #endif | ||||
#if defined(__aarch64__) | |||||
bzUnsubmitted Done Inline ActionsYeah the #if checks here need changing. And all the way down. Andy! bz: Yeah the #if checks here need changing. And all the way down. Andy! | |||||
andrewUnsubmitted Done Inline ActionsIt depends on if we are checking for 32 vs 64-bit ARM, or for the version of the architecture within 32 or 64-bit. andrew: It depends on if we are checking for 32 vs 64-bit ARM, or for the version of the architecture… | |||||
PMC_CLASS_TABLE_DESC(cortex_a53, ARMV8, cortex_a53, armv8); | |||||
PMC_CLASS_TABLE_DESC(cortex_a57, ARMV8, cortex_a57, armv8); | |||||
#endif | |||||
#if defined(__mips__) | #if defined(__mips__) | ||||
PMC_CLASS_TABLE_DESC(mips24k, MIPS24K, mips24k, mips); | PMC_CLASS_TABLE_DESC(mips24k, MIPS24K, mips24k, mips); | ||||
PMC_CLASS_TABLE_DESC(mips74k, MIPS74K, mips74k, mips); | PMC_CLASS_TABLE_DESC(mips74k, MIPS74K, mips74k, mips); | ||||
PMC_CLASS_TABLE_DESC(octeon, OCTEON, octeon, mips); | PMC_CLASS_TABLE_DESC(octeon, OCTEON, octeon, mips); | ||||
#endif /* __mips__ */ | #endif /* __mips__ */ | ||||
#if defined(__powerpc__) | #if defined(__powerpc__) | ||||
PMC_CLASS_TABLE_DESC(ppc7450, PPC7450, ppc7450, powerpc); | PMC_CLASS_TABLE_DESC(ppc7450, PPC7450, ppc7450, powerpc); | ||||
PMC_CLASS_TABLE_DESC(ppc970, PPC970, ppc970, powerpc); | PMC_CLASS_TABLE_DESC(ppc970, PPC970, ppc970, powerpc); | ||||
▲ Show 20 Lines • Show All 2,051 Lines • ▼ Show 20 Lines | armv7_allocate_pmc(enum pmc_event pe, char *ctrspec __unused, | ||||
default: | default: | ||||
break; | break; | ||||
} | } | ||||
return (0); | return (0); | ||||
} | } | ||||
#endif | #endif | ||||
#if defined(__aarch64__) | |||||
static struct pmc_event_alias cortex_a53_aliases[] = { | |||||
EV_ALIAS(NULL, NULL) | |||||
}; | |||||
static struct pmc_event_alias cortex_a57_aliases[] = { | |||||
EV_ALIAS(NULL, NULL) | |||||
}; | |||||
static int | |||||
armv8_allocate_pmc(enum pmc_event pe, char *ctrspec __unused, | |||||
struct pmc_op_pmcallocate *pmc_config __unused) | |||||
{ | |||||
switch (pe) { | |||||
default: | |||||
break; | |||||
} | |||||
return (0); | |||||
} | |||||
#endif | |||||
#if defined(__mips__) | #if defined(__mips__) | ||||
static struct pmc_event_alias mips24k_aliases[] = { | static struct pmc_event_alias mips24k_aliases[] = { | ||||
EV_ALIAS("instructions", "INSTR_EXECUTED"), | EV_ALIAS("instructions", "INSTR_EXECUTED"), | ||||
EV_ALIAS("branches", "BRANCH_COMPLETED"), | EV_ALIAS("branches", "BRANCH_COMPLETED"), | ||||
EV_ALIAS("branch-mispredicts", "BRANCH_MISPRED"), | EV_ALIAS("branch-mispredicts", "BRANCH_MISPRED"), | ||||
EV_ALIAS(NULL, NULL) | EV_ALIAS(NULL, NULL) | ||||
}; | }; | ||||
▲ Show 20 Lines • Show All 493 Lines • ▼ Show 20 Lines | pmc_event_names_of_class(enum pmc_class cl, const char ***eventnames, | ||||
case PMC_CLASS_XSCALE: | case PMC_CLASS_XSCALE: | ||||
ev = xscale_event_table; | ev = xscale_event_table; | ||||
count = PMC_EVENT_TABLE_SIZE(xscale); | count = PMC_EVENT_TABLE_SIZE(xscale); | ||||
break; | break; | ||||
case PMC_CLASS_ARMV7: | case PMC_CLASS_ARMV7: | ||||
ev = armv7_event_table; | ev = armv7_event_table; | ||||
count = PMC_EVENT_TABLE_SIZE(armv7); | count = PMC_EVENT_TABLE_SIZE(armv7); | ||||
break; | break; | ||||
case PMC_CLASS_ARMV8: | |||||
switch (cpu_info.pm_cputype) { | |||||
default: | |||||
case PMC_CPU_ARMV8_CORTEX_A53: | |||||
ev = cortex_a53_event_table; | |||||
count = PMC_EVENT_TABLE_SIZE(cortex_a53); | |||||
break; | |||||
case PMC_CPU_ARMV8_CORTEX_A57: | |||||
ev = cortex_a57_event_table; | |||||
count = PMC_EVENT_TABLE_SIZE(cortex_a57); | |||||
break; | |||||
} | |||||
break; | |||||
case PMC_CLASS_MIPS24K: | case PMC_CLASS_MIPS24K: | ||||
ev = mips24k_event_table; | ev = mips24k_event_table; | ||||
count = PMC_EVENT_TABLE_SIZE(mips24k); | count = PMC_EVENT_TABLE_SIZE(mips24k); | ||||
break; | break; | ||||
case PMC_CLASS_MIPS74K: | case PMC_CLASS_MIPS74K: | ||||
ev = mips74k_event_table; | ev = mips74k_event_table; | ||||
count = PMC_EVENT_TABLE_SIZE(mips74k); | count = PMC_EVENT_TABLE_SIZE(mips74k); | ||||
break; | break; | ||||
▲ Show 20 Lines • Show All 281 Lines • ▼ Show 20 Lines | case PMC_CPU_INTEL_XSCALE: | ||||
pmc_class_table[n] = &xscale_class_table_descr; | pmc_class_table[n] = &xscale_class_table_descr; | ||||
break; | break; | ||||
#endif | #endif | ||||
case PMC_CPU_ARMV7: | case PMC_CPU_ARMV7: | ||||
PMC_MDEP_INIT(armv7); | PMC_MDEP_INIT(armv7); | ||||
pmc_class_table[n] = &armv7_class_table_descr; | pmc_class_table[n] = &armv7_class_table_descr; | ||||
break; | break; | ||||
#endif | #endif | ||||
#if defined(__aarch64__) | |||||
case PMC_CPU_ARMV8_CORTEX_A53: | |||||
PMC_MDEP_INIT(cortex_a53); | |||||
pmc_class_table[n] = &cortex_a53_class_table_descr; | |||||
break; | |||||
case PMC_CPU_ARMV8_CORTEX_A57: | |||||
PMC_MDEP_INIT(cortex_a57); | |||||
pmc_class_table[n] = &cortex_a57_class_table_descr; | |||||
break; | |||||
#endif | |||||
#if defined(__mips__) | #if defined(__mips__) | ||||
case PMC_CPU_MIPS_24K: | case PMC_CPU_MIPS_24K: | ||||
PMC_MDEP_INIT(mips24k); | PMC_MDEP_INIT(mips24k); | ||||
pmc_class_table[n] = &mips24k_class_table_descr; | pmc_class_table[n] = &mips24k_class_table_descr; | ||||
break; | break; | ||||
case PMC_CPU_MIPS_74K: | case PMC_CPU_MIPS_74K: | ||||
PMC_MDEP_INIT(mips74k); | PMC_MDEP_INIT(mips74k); | ||||
pmc_class_table[n] = &mips74k_class_table_descr; | pmc_class_table[n] = &mips74k_class_table_descr; | ||||
▲ Show 20 Lines • Show All 195 Lines • ▼ Show 20 Lines | if (pe >= PMC_EV_IAF_FIRST && pe <= PMC_EV_IAF_LAST) { | ||||
ev = p6_event_table; | ev = p6_event_table; | ||||
evfence = p6_event_table + PMC_EVENT_TABLE_SIZE(p6); | evfence = p6_event_table + PMC_EVENT_TABLE_SIZE(p6); | ||||
} else if (pe >= PMC_EV_XSCALE_FIRST && pe <= PMC_EV_XSCALE_LAST) { | } else if (pe >= PMC_EV_XSCALE_FIRST && pe <= PMC_EV_XSCALE_LAST) { | ||||
ev = xscale_event_table; | ev = xscale_event_table; | ||||
evfence = xscale_event_table + PMC_EVENT_TABLE_SIZE(xscale); | evfence = xscale_event_table + PMC_EVENT_TABLE_SIZE(xscale); | ||||
} else if (pe >= PMC_EV_ARMV7_FIRST && pe <= PMC_EV_ARMV7_LAST) { | } else if (pe >= PMC_EV_ARMV7_FIRST && pe <= PMC_EV_ARMV7_LAST) { | ||||
ev = armv7_event_table; | ev = armv7_event_table; | ||||
evfence = armv7_event_table + PMC_EVENT_TABLE_SIZE(armv7); | evfence = armv7_event_table + PMC_EVENT_TABLE_SIZE(armv7); | ||||
} else if (pe >= PMC_EV_ARMV8_FIRST && pe <= PMC_EV_ARMV8_LAST) { | |||||
switch (cpu) { | |||||
case PMC_CPU_ARMV8_CORTEX_A53: | |||||
ev = cortex_a53_event_table; | |||||
evfence = cortex_a53_event_table + PMC_EVENT_TABLE_SIZE(cortex_a53); | |||||
break; | |||||
case PMC_CPU_ARMV8_CORTEX_A57: | |||||
ev = cortex_a57_event_table; | |||||
evfence = cortex_a57_event_table + PMC_EVENT_TABLE_SIZE(cortex_a57); | |||||
break; | |||||
default: /* Unknown CPU type. */ | |||||
break; | |||||
} | |||||
} else if (pe >= PMC_EV_MIPS24K_FIRST && pe <= PMC_EV_MIPS24K_LAST) { | } else if (pe >= PMC_EV_MIPS24K_FIRST && pe <= PMC_EV_MIPS24K_LAST) { | ||||
ev = mips24k_event_table; | ev = mips24k_event_table; | ||||
evfence = mips24k_event_table + PMC_EVENT_TABLE_SIZE(mips24k); | evfence = mips24k_event_table + PMC_EVENT_TABLE_SIZE(mips24k); | ||||
} else if (pe >= PMC_EV_MIPS74K_FIRST && pe <= PMC_EV_MIPS74K_LAST) { | } else if (pe >= PMC_EV_MIPS74K_FIRST && pe <= PMC_EV_MIPS74K_LAST) { | ||||
ev = mips74k_event_table; | ev = mips74k_event_table; | ||||
evfence = mips74k_event_table + PMC_EVENT_TABLE_SIZE(mips74k); | evfence = mips74k_event_table + PMC_EVENT_TABLE_SIZE(mips74k); | ||||
} else if (pe >= PMC_EV_OCTEON_FIRST && pe <= PMC_EV_OCTEON_LAST) { | } else if (pe >= PMC_EV_OCTEON_FIRST && pe <= PMC_EV_OCTEON_LAST) { | ||||
ev = octeon_event_table; | ev = octeon_event_table; | ||||
▲ Show 20 Lines • Show All 220 Lines • Show Last 20 Lines |
Talk to Andy about these; I think it should be an arm version check there these days.