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Differential D12843 Diff 34482 sys/arm/allwinner/clkng/ccu_sun8i_r.c

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sys/arm/allwinner/clkng/ccu_sun8i_r.c

Show First 20 Lines • Show All 64 Lines • ▼ Show 20 Linesstatic struct aw_ccung_gate ccu_sun8i_r_gates[] = {
CCU_GATE(CLK_APB0_TIMER, "apb0-timer", "apb0", 0x28, 2) CCU_GATE(CLK_APB0_TIMER, "apb0-timer", "apb0", 0x28, 2)
CCU_GATE(CLK_APB0_RSB, "apb0-rsb", "apb0", 0x28, 3) CCU_GATE(CLK_APB0_RSB, "apb0-rsb", "apb0", 0x28, 3)
CCU_GATE(CLK_APB0_UART, "apb0-uart", "apb0", 0x28, 4) CCU_GATE(CLK_APB0_UART, "apb0-uart", "apb0", 0x28, 4)
CCU_GATE(CLK_APB0_I2C, "apb0-i2c", "apb0", 0x28, 6) CCU_GATE(CLK_APB0_I2C, "apb0-i2c", "apb0", 0x28, 6)
CCU_GATE(CLK_APB0_TWD, "apb0-twd", "apb0", 0x28, 7) CCU_GATE(CLK_APB0_TWD, "apb0-twd", "apb0", 0x28, 7)
}; };
static const char *ar100_parents[] = {"osc32k", "osc24M", "pll_periph0", "iosc"}; static const char *ar100_parents[] = {"osc32k", "osc24M", "pll_periph0", "iosc"};
static const char *a83t_ar100_parents[] = {"osc16M-d512", "osc24M", "pll_periph", "osc16M"};
PREDIV_CLK(ar100_clk, CLK_AR100, /* id */ PREDIV_CLK(ar100_clk, CLK_AR100, /* id */
"ar100", ar100_parents, /* name, parents */ "ar100", ar100_parents, /* name, parents */
0x00, /* offset */ 0x00, /* offset */
16, 2, /* mux */ 16, 2, /* mux */
4, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* div */ 4, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* div */
8, 5, 0, AW_CLK_FACTOR_HAS_COND, /* prediv */ 8, 5, 0, AW_CLK_FACTOR_HAS_COND, /* prediv */
16, 2, 2); /* prediv condition */ 16, 2, 2); /* prediv condition */
PREDIV_CLK(a83t_ar100_clk, CLK_AR100, /* id */
"ar100", a83t_ar100_parents, /* name, parents */
0x00, /* offset */
16, 2, /* mux */
4, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* div */
8, 5, 0, AW_CLK_FACTOR_HAS_COND, /* prediv */
16, 2, 2); /* prediv condition */
static const char *ahb0_parents[] = {"ar100"}; static const char *ahb0_parents[] = {"ar100"};
FIXED_CLK(ahb0_clk, FIXED_CLK(ahb0_clk,
CLK_AHB0, /* id */ CLK_AHB0, /* id */
"ahb0", /* name */ "ahb0", /* name */
ahb0_parents, /* parent */ ahb0_parents, /* parent */
0, /* freq */ 0, /* freq */
1, /* mult */ 1, /* mult */
1, /* div */ 1, /* div */
0); /* flags */ 0); /* flags */
static const char *apb0_parents[] = {"ahb0"}; static const char *apb0_parents[] = {"ahb0"};
DIV_CLK(apb0_clk, DIV_CLK(apb0_clk,
CLK_APB0, /* id */ CLK_APB0, /* id */
"apb0", apb0_parents, /* name, parents */ "apb0", apb0_parents, /* name, parents */
0x0c, /* offset */ 0x0c, /* offset */
0, 2, /* shift, width */ 0, 2, /* shift, width */
0, NULL); /* flags, div table */ 0, NULL); /* flags, div table */
static struct aw_clk_prediv_mux_def *prediv_mux_clks[] = {
&ar100_clk,
};
static struct clk_div_def *div_clks[] = { static struct clk_div_def *div_clks[] = {
&apb0_clk, &apb0_clk,
}; };
static struct clk_fixed_def *fixed_factor_clks[] = { static struct clk_fixed_def *fixed_factor_clks[] = {
&ahb0_clk, &ahb0_clk,
}; };
void void
ccu_sun8i_r_register_clocks(struct aw_ccung_softc *sc) ccu_sun8i_r_register_clocks(struct aw_ccung_softc *sc)
{ {
int i; int i;
sc->resets = ccu_sun8i_r_resets; sc->resets = ccu_sun8i_r_resets;
sc->nresets = nitems(ccu_sun8i_r_resets); sc->nresets = nitems(ccu_sun8i_r_resets);
sc->gates = ccu_sun8i_r_gates; sc->gates = ccu_sun8i_r_gates;
sc->ngates = nitems(ccu_sun8i_r_gates); sc->ngates = nitems(ccu_sun8i_r_gates);
for (i = 0; i < nitems(prediv_mux_clks); i++) /* The ar100 on the a83t has different parents than the others */
aw_clk_prediv_mux_register(sc->clkdom, prediv_mux_clks[i]); if (sc->type == A83T_R_CCU)
aw_clk_prediv_mux_register(sc->clkdom, &a83t_ar100_clk);
else
aw_clk_prediv_mux_register(sc->clkdom, &ar100_clk);
for (i = 0; i < nitems(div_clks); i++) for (i = 0; i < nitems(div_clks); i++)
clknode_div_register(sc->clkdom, div_clks[i]); clknode_div_register(sc->clkdom, div_clks[i]);
for (i = 0; i < nitems(fixed_factor_clks); i++) for (i = 0; i < nitems(fixed_factor_clks); i++)
clknode_fixed_register(sc->clkdom, fixed_factor_clks[i]); clknode_fixed_register(sc->clkdom, fixed_factor_clks[i]);
} }