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sys/dev/ixgbe/ixgbe.h
/****************************************************************************** | /****************************************************************************** | ||||
Copyright (c) 2001-2015, Intel Corporation | Copyright (c) 2001-2017, Intel Corporation | ||||
All rights reserved. | All rights reserved. | ||||
Redistribution and use in source and binary forms, with or without | Redistribution and use in source and binary forms, with or without | ||||
modification, are permitted provided that the following conditions are met: | modification, are permitted provided that the following conditions are met: | ||||
1. Redistributions of source code must retain the above copyright notice, | 1. Redistributions of source code must retain the above copyright notice, | ||||
this list of conditions and the following disclaimer. | this list of conditions and the following disclaimer. | ||||
2. Redistributions in binary form must reproduce the above copyright | 2. Redistributions in binary form must reproduce the above copyright | ||||
notice, this list of conditions and the following disclaimer in the | notice, this list of conditions and the following disclaimer in the | ||||
documentation and/or other materials provided with the distribution. | documentation and/or other materials provided with the distribution. | ||||
3. Neither the name of the Intel Corporation nor the names of its | 3. Neither the name of the Intel Corporation nor the names of its | ||||
contributors may be used to endorse or promote products derived from | contributors may be used to endorse or promote products derived from | ||||
this software without specific prior written permission. | this software without specific prior written permission. | ||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | ||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | ||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | ||||
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE | ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE | ||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | ||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | ||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | ||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN | ||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | ||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE | ||||
POSSIBILITY OF SUCH DAMAGE. | POSSIBILITY OF SUCH DAMAGE. | ||||
******************************************************************************/ | ******************************************************************************/ | ||||
/*$FreeBSD$*/ | /*$FreeBSD$*/ | ||||
#ifndef _IXGBE_H_ | #ifndef _IXGBE_H_ | ||||
#define _IXGBE_H_ | #define _IXGBE_H_ | ||||
#include <sys/param.h> | #include <sys/param.h> | ||||
#include <sys/systm.h> | #include <sys/systm.h> | ||||
#ifndef IXGBE_LEGACY_TX | |||||
#include <sys/buf_ring.h> | #include <sys/buf_ring.h> | ||||
#endif | |||||
#include <sys/mbuf.h> | #include <sys/mbuf.h> | ||||
#include <sys/protosw.h> | #include <sys/protosw.h> | ||||
#include <sys/socket.h> | #include <sys/socket.h> | ||||
#include <sys/malloc.h> | #include <sys/malloc.h> | ||||
#include <sys/kernel.h> | #include <sys/kernel.h> | ||||
#include <sys/module.h> | #include <sys/module.h> | ||||
#include <sys/sockio.h> | #include <sys/sockio.h> | ||||
#include <sys/eventhandler.h> | #include <sys/eventhandler.h> | ||||
Show All 34 Lines | |||||
#include <sys/sysctl.h> | #include <sys/sysctl.h> | ||||
#include <sys/endian.h> | #include <sys/endian.h> | ||||
#include <sys/taskqueue.h> | #include <sys/taskqueue.h> | ||||
#include <sys/pcpu.h> | #include <sys/pcpu.h> | ||||
#include <sys/smp.h> | #include <sys/smp.h> | ||||
#include <machine/smp.h> | #include <machine/smp.h> | ||||
#include <sys/sbuf.h> | #include <sys/sbuf.h> | ||||
#ifdef PCI_IOV | |||||
#include <sys/nv.h> | |||||
#include <sys/iov_schema.h> | |||||
#include <dev/pci/pci_iov.h> | |||||
#endif | |||||
#include "ixgbe_api.h" | #include "ixgbe_api.h" | ||||
#include "ixgbe_common.h" | #include "ixgbe_common.h" | ||||
#include "ixgbe_phy.h" | #include "ixgbe_phy.h" | ||||
#include "ixgbe_vf.h" | #include "ixgbe_vf.h" | ||||
#include "ixgbe_features.h" | |||||
#ifdef PCI_IOV | |||||
#include "ixgbe_common.h" | |||||
#include "ixgbe_mbx.h" | |||||
#endif | |||||
/* Tunables */ | /* Tunables */ | ||||
/* | /* | ||||
* TxDescriptors Valid Range: 64-4096 Default Value: 256 This value is the | * TxDescriptors Valid Range: 64-4096 Default Value: 256 This value is the | ||||
* number of transmit descriptors allocated by the driver. Increasing this | * number of transmit descriptors allocated by the driver. Increasing this | ||||
* value allows the driver to queue more transmits. Each descriptor is 16 | * value allows the driver to queue more transmits. Each descriptor is 16 | ||||
* bytes. Performance tests have show the 2K value to be optimal for top | * bytes. Performance tests have show the 2K value to be optimal for top | ||||
* performance. | * performance. | ||||
*/ | */ | ||||
#define DEFAULT_TXD 1024 | #define DEFAULT_TXD 1024 | ||||
#define PERFORM_TXD 2048 | #define PERFORM_TXD 2048 | ||||
#define MAX_TXD 4096 | #define MAX_TXD 4096 | ||||
#define MIN_TXD 64 | #define MIN_TXD 64 | ||||
/* | /* | ||||
* RxDescriptors Valid Range: 64-4096 Default Value: 256 This value is the | * RxDescriptors Valid Range: 64-4096 Default Value: 256 This value is the | ||||
* number of receive descriptors allocated for each RX queue. Increasing this | * number of receive descriptors allocated for each RX queue. Increasing this | ||||
* value allows the driver to buffer more incoming packets. Each descriptor | * value allows the driver to buffer more incoming packets. Each descriptor | ||||
* is 16 bytes. A receive buffer is also allocated for each descriptor. | * is 16 bytes. A receive buffer is also allocated for each descriptor. | ||||
* | * | ||||
* Note: with 8 rings and a dual port card, it is possible to bump up | * Note: with 8 rings and a dual port card, it is possible to bump up | ||||
* against the system mbuf pool limit, you can tune nmbclusters | * against the system mbuf pool limit, you can tune nmbclusters | ||||
* to adjust for this. | * to adjust for this. | ||||
*/ | */ | ||||
#define DEFAULT_RXD 1024 | #define DEFAULT_RXD 1024 | ||||
#define PERFORM_RXD 2048 | #define PERFORM_RXD 2048 | ||||
#define MAX_RXD 4096 | #define MAX_RXD 4096 | ||||
#define MIN_RXD 64 | #define MIN_RXD 64 | ||||
/* Alignment for rings */ | /* Alignment for rings */ | ||||
#define DBA_ALIGN 128 | #define DBA_ALIGN 128 | ||||
/* | /* | ||||
* This is the max watchdog interval, ie. the time that can | * This is the max watchdog interval, ie. the time that can | ||||
* pass between any two TX clean operations, such only happening | * pass between any two TX clean operations, such only happening | ||||
* when the TX hardware is functioning. | * when the TX hardware is functioning. | ||||
*/ | */ | ||||
#define IXGBE_WATCHDOG (10 * hz) | #define IXGBE_WATCHDOG (10 * hz) | ||||
/* | /* | ||||
* This parameters control when the driver calls the routine to reclaim | * This parameters control when the driver calls the routine to reclaim | ||||
* transmit descriptors. | * transmit descriptors. | ||||
*/ | */ | ||||
#define IXGBE_TX_CLEANUP_THRESHOLD (adapter->num_tx_desc / 8) | #define IXGBE_TX_CLEANUP_THRESHOLD(_a) ((_a)->num_tx_desc / 8) | ||||
#define IXGBE_TX_OP_THRESHOLD (adapter->num_tx_desc / 32) | #define IXGBE_TX_OP_THRESHOLD(_a) ((_a)->num_tx_desc / 32) | ||||
/* These defines are used in MTU calculations */ | /* These defines are used in MTU calculations */ | ||||
#define IXGBE_MAX_FRAME_SIZE 9728 | #define IXGBE_MAX_FRAME_SIZE 9728 | ||||
#define IXGBE_MTU_HDR (ETHER_HDR_LEN + ETHER_CRC_LEN) | #define IXGBE_MTU_HDR (ETHER_HDR_LEN + ETHER_CRC_LEN) | ||||
#define IXGBE_MTU_HDR_VLAN (ETHER_HDR_LEN + ETHER_CRC_LEN + \ | #define IXGBE_MTU_HDR_VLAN (ETHER_HDR_LEN + ETHER_CRC_LEN + \ | ||||
ETHER_VLAN_ENCAP_LEN) | ETHER_VLAN_ENCAP_LEN) | ||||
#define IXGBE_MAX_MTU (IXGBE_MAX_FRAME_SIZE - IXGBE_MTU_HDR) | #define IXGBE_MAX_MTU (IXGBE_MAX_FRAME_SIZE - IXGBE_MTU_HDR) | ||||
#define IXGBE_MAX_MTU_VLAN (IXGBE_MAX_FRAME_SIZE - IXGBE_MTU_HDR_VLAN) | #define IXGBE_MAX_MTU_VLAN (IXGBE_MAX_FRAME_SIZE - IXGBE_MTU_HDR_VLAN) | ||||
/* Flow control constants */ | /* Flow control constants */ | ||||
#define IXGBE_FC_PAUSE 0xFFFF | #define IXGBE_FC_PAUSE 0xFFFF | ||||
#define IXGBE_FC_HI 0x20000 | #define IXGBE_FC_HI 0x20000 | ||||
#define IXGBE_FC_LO 0x10000 | #define IXGBE_FC_LO 0x10000 | ||||
/* | /* | ||||
* Used for optimizing small rx mbufs. Effort is made to keep the copy | * Used for optimizing small rx mbufs. Effort is made to keep the copy | ||||
* small and aligned for the CPU L1 cache. | * small and aligned for the CPU L1 cache. | ||||
* | * | ||||
* MHLEN is typically 168 bytes, giving us 8-byte alignment. Getting | * MHLEN is typically 168 bytes, giving us 8-byte alignment. Getting | ||||
* 32 byte alignment needed for the fast bcopy results in 8 bytes being | * 32 byte alignment needed for the fast bcopy results in 8 bytes being | ||||
* wasted. Getting 64 byte alignment, which _should_ be ideal for | * wasted. Getting 64 byte alignment, which _should_ be ideal for | ||||
* modern Intel CPUs, results in 40 bytes wasted and a significant drop | * modern Intel CPUs, results in 40 bytes wasted and a significant drop | ||||
* in observed efficiency of the optimization, 97.9% -> 81.8%. | * in observed efficiency of the optimization, 97.9% -> 81.8%. | ||||
*/ | */ | ||||
#if __FreeBSD_version < 1002000 | #if __FreeBSD_version < 1002000 | ||||
#define MPKTHSIZE (sizeof(struct m_hdr) + sizeof(struct pkthdr)) | #define MPKTHSIZE (sizeof(struct m_hdr) + sizeof(struct pkthdr)) | ||||
#endif | #endif | ||||
#define IXGBE_RX_COPY_HDR_PADDED ((((MPKTHSIZE - 1) / 32) + 1) * 32) | #define IXGBE_RX_COPY_HDR_PADDED ((((MPKTHSIZE - 1) / 32) + 1) * 32) | ||||
#define IXGBE_RX_COPY_LEN (MSIZE - IXGBE_RX_COPY_HDR_PADDED) | #define IXGBE_RX_COPY_LEN (MSIZE - IXGBE_RX_COPY_HDR_PADDED) | ||||
#define IXGBE_RX_COPY_ALIGN (IXGBE_RX_COPY_HDR_PADDED - MPKTHSIZE) | #define IXGBE_RX_COPY_ALIGN (IXGBE_RX_COPY_HDR_PADDED - MPKTHSIZE) | ||||
/* Keep older OS drivers building... */ | /* Keep older OS drivers building... */ | ||||
#if !defined(SYSCTL_ADD_UQUAD) | #if !defined(SYSCTL_ADD_UQUAD) | ||||
#define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD | #define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD | ||||
#endif | #endif | ||||
/* Defines for printing debug information */ | /* Defines for printing debug information */ | ||||
#define DEBUG_INIT 0 | #define DEBUG_INIT 0 | ||||
#define DEBUG_IOCTL 0 | #define DEBUG_IOCTL 0 | ||||
#define DEBUG_HW 0 | #define DEBUG_HW 0 | ||||
#define INIT_DEBUGOUT(S) if (DEBUG_INIT) printf(S "\n") | #define INIT_DEBUGOUT(S) if (DEBUG_INIT) printf(S "\n") | ||||
#define INIT_DEBUGOUT1(S, A) if (DEBUG_INIT) printf(S "\n", A) | #define INIT_DEBUGOUT1(S, A) if (DEBUG_INIT) printf(S "\n", A) | ||||
#define INIT_DEBUGOUT2(S, A, B) if (DEBUG_INIT) printf(S "\n", A, B) | #define INIT_DEBUGOUT2(S, A, B) if (DEBUG_INIT) printf(S "\n", A, B) | ||||
#define IOCTL_DEBUGOUT(S) if (DEBUG_IOCTL) printf(S "\n") | #define IOCTL_DEBUGOUT(S) if (DEBUG_IOCTL) printf(S "\n") | ||||
#define IOCTL_DEBUGOUT1(S, A) if (DEBUG_IOCTL) printf(S "\n", A) | #define IOCTL_DEBUGOUT1(S, A) if (DEBUG_IOCTL) printf(S "\n", A) | ||||
#define IOCTL_DEBUGOUT2(S, A, B) if (DEBUG_IOCTL) printf(S "\n", A, B) | #define IOCTL_DEBUGOUT2(S, A, B) if (DEBUG_IOCTL) printf(S "\n", A, B) | ||||
#define HW_DEBUGOUT(S) if (DEBUG_HW) printf(S "\n") | #define HW_DEBUGOUT(S) if (DEBUG_HW) printf(S "\n") | ||||
#define HW_DEBUGOUT1(S, A) if (DEBUG_HW) printf(S "\n", A) | #define HW_DEBUGOUT1(S, A) if (DEBUG_HW) printf(S "\n", A) | ||||
#define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) printf(S "\n", A, B) | #define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) printf(S "\n", A, B) | ||||
#define MAX_NUM_MULTICAST_ADDRESSES 128 | #define MAX_NUM_MULTICAST_ADDRESSES 128 | ||||
#define IXGBE_82598_SCATTER 100 | #define IXGBE_82598_SCATTER 100 | ||||
#define IXGBE_82599_SCATTER 32 | #define IXGBE_82599_SCATTER 32 | ||||
#define MSIX_82598_BAR 3 | #define MSIX_82598_BAR 3 | ||||
#define MSIX_82599_BAR 4 | #define MSIX_82599_BAR 4 | ||||
#define IXGBE_TSO_SIZE 262140 | #define IXGBE_TSO_SIZE 262140 | ||||
#define IXGBE_RX_HDR 128 | #define IXGBE_RX_HDR 128 | ||||
#define IXGBE_VFTA_SIZE 128 | #define IXGBE_VFTA_SIZE 128 | ||||
#define IXGBE_BR_SIZE 4096 | #define IXGBE_BR_SIZE 4096 | ||||
#define IXGBE_QUEUE_MIN_FREE 32 | #define IXGBE_QUEUE_MIN_FREE 32 | ||||
#define IXGBE_MAX_TX_BUSY 10 | #define IXGBE_MAX_TX_BUSY 10 | ||||
#define IXGBE_QUEUE_HUNG 0x80000000 | #define IXGBE_QUEUE_HUNG 0x80000000 | ||||
#define IXV_EITR_DEFAULT 128 | #define IXGBE_EITR_DEFAULT 128 | ||||
/* Supported offload bits in mbuf flag */ | /* Supported offload bits in mbuf flag */ | ||||
#if __FreeBSD_version >= 1000000 | #if __FreeBSD_version >= 1000000 | ||||
#define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \ | #define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \ | ||||
CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \ | CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \ | ||||
CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP) | CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP) | ||||
#elif __FreeBSD_version >= 800000 | #elif __FreeBSD_version >= 800000 | ||||
#define CSUM_OFFLOAD (CSUM_IP|CSUM_TCP|CSUM_UDP|CSUM_SCTP) | #define CSUM_OFFLOAD (CSUM_IP|CSUM_TCP|CSUM_UDP|CSUM_SCTP) | ||||
#else | #else | ||||
#define CSUM_OFFLOAD (CSUM_IP|CSUM_TCP|CSUM_UDP) | #define CSUM_OFFLOAD (CSUM_IP|CSUM_TCP|CSUM_UDP) | ||||
#endif | #endif | ||||
/* Backward compatibility items for very old versions */ | /* Backward compatibility items for very old versions */ | ||||
#ifndef pci_find_cap | #ifndef pci_find_cap | ||||
#define pci_find_cap pci_find_extcap | #define pci_find_cap pci_find_extcap | ||||
#endif | #endif | ||||
#ifndef DEVMETHOD_END | #ifndef DEVMETHOD_END | ||||
#define DEVMETHOD_END { NULL, NULL } | #define DEVMETHOD_END { NULL, NULL } | ||||
#endif | #endif | ||||
/* | /* | ||||
* Interrupt Moderation parameters | * Interrupt Moderation parameters | ||||
*/ | */ | ||||
#define IXGBE_LOW_LATENCY 128 | #define IXGBE_LOW_LATENCY 128 | ||||
#define IXGBE_AVE_LATENCY 400 | #define IXGBE_AVE_LATENCY 400 | ||||
#define IXGBE_BULK_LATENCY 1200 | #define IXGBE_BULK_LATENCY 1200 | ||||
/* Using 1FF (the max value), the interval is ~1.05ms */ | /* Using 1FF (the max value), the interval is ~1.05ms */ | ||||
#define IXGBE_LINK_ITR_QUANTA 0x1FF | #define IXGBE_LINK_ITR_QUANTA 0x1FF | ||||
#define IXGBE_LINK_ITR ((IXGBE_LINK_ITR_QUANTA << 3) & \ | #define IXGBE_LINK_ITR ((IXGBE_LINK_ITR_QUANTA << 3) & \ | ||||
IXGBE_EITR_ITR_INT_MASK) | IXGBE_EITR_ITR_INT_MASK) | ||||
/* MAC type macros */ | |||||
#define IXGBE_IS_X550VF(_adapter) \ | |||||
((_adapter->hw.mac.type == ixgbe_mac_X550_vf) || \ | |||||
(_adapter->hw.mac.type == ixgbe_mac_X550EM_x_vf)) | |||||
#define IXGBE_IS_VF(_adapter) \ | |||||
(IXGBE_IS_X550VF(_adapter) || \ | |||||
(_adapter->hw.mac.type == ixgbe_mac_X540_vf) || \ | |||||
(_adapter->hw.mac.type == ixgbe_mac_82599_vf)) | |||||
#ifdef PCI_IOV | /************************************************************************ | ||||
#define IXGBE_VF_INDEX(vmdq) ((vmdq) / 32) | |||||
#define IXGBE_VF_BIT(vmdq) (1 << ((vmdq) % 32)) | |||||
#define IXGBE_VT_MSG_MASK 0xFFFF | |||||
#define IXGBE_VT_MSGINFO(msg) \ | |||||
(((msg) & IXGBE_VT_MSGINFO_MASK) >> IXGBE_VT_MSGINFO_SHIFT) | |||||
#define IXGBE_VF_GET_QUEUES_RESP_LEN 5 | |||||
#define IXGBE_API_VER_1_0 0 | |||||
#define IXGBE_API_VER_2_0 1 /* Solaris API. Not supported. */ | |||||
#define IXGBE_API_VER_1_1 2 | |||||
#define IXGBE_API_VER_UNKNOWN UINT16_MAX | |||||
enum ixgbe_iov_mode { | |||||
IXGBE_64_VM, | |||||
IXGBE_32_VM, | |||||
IXGBE_NO_VM | |||||
}; | |||||
#endif /* PCI_IOV */ | |||||
/* | |||||
***************************************************************************** | |||||
* vendor_info_array | * vendor_info_array | ||||
* | * | ||||
* This array contains the list of Subvendor/Subdevice IDs on which the driver | * Contains the list of Subvendor/Subdevice IDs on | ||||
* should load. | * which the driver should load. | ||||
* | ************************************************************************/ | ||||
***************************************************************************** | |||||
*/ | |||||
typedef struct _ixgbe_vendor_info_t { | typedef struct _ixgbe_vendor_info_t { | ||||
unsigned int vendor_id; | unsigned int vendor_id; | ||||
unsigned int device_id; | unsigned int device_id; | ||||
unsigned int subvendor_id; | unsigned int subvendor_id; | ||||
unsigned int subdevice_id; | unsigned int subdevice_id; | ||||
unsigned int index; | unsigned int index; | ||||
} ixgbe_vendor_info_t; | } ixgbe_vendor_info_t; | ||||
struct ixgbe_bp_data { | |||||
u32 low; | |||||
u32 high; | |||||
u32 log; | |||||
}; | |||||
struct ixgbe_tx_buf { | struct ixgbe_tx_buf { | ||||
union ixgbe_adv_tx_desc *eop; | union ixgbe_adv_tx_desc *eop; | ||||
struct mbuf *m_head; | struct mbuf *m_head; | ||||
bus_dmamap_t map; | bus_dmamap_t map; | ||||
}; | }; | ||||
struct ixgbe_rx_buf { | struct ixgbe_rx_buf { | ||||
struct mbuf *buf; | struct mbuf *buf; | ||||
struct mbuf *fmp; | struct mbuf *fmp; | ||||
bus_dmamap_t pmap; | bus_dmamap_t pmap; | ||||
u_int flags; | u_int flags; | ||||
#define IXGBE_RX_COPY 0x01 | #define IXGBE_RX_COPY 0x01 | ||||
uint64_t addr; | uint64_t addr; | ||||
}; | }; | ||||
/* | /* | ||||
* Bus dma allocation structure used by ixgbe_dma_malloc and ixgbe_dma_free. | * Bus dma allocation structure used by ixgbe_dma_malloc and ixgbe_dma_free | ||||
*/ | */ | ||||
struct ixgbe_dma_alloc { | struct ixgbe_dma_alloc { | ||||
bus_addr_t dma_paddr; | bus_addr_t dma_paddr; | ||||
caddr_t dma_vaddr; | caddr_t dma_vaddr; | ||||
bus_dma_tag_t dma_tag; | bus_dma_tag_t dma_tag; | ||||
bus_dmamap_t dma_map; | bus_dmamap_t dma_map; | ||||
bus_dma_segment_t dma_seg; | bus_dma_segment_t dma_seg; | ||||
bus_size_t dma_size; | bus_size_t dma_size; | ||||
int dma_nseg; | int dma_nseg; | ||||
}; | }; | ||||
struct ixgbe_mc_addr { | struct ixgbe_mc_addr { | ||||
u8 addr[IXGBE_ETH_LENGTH_OF_ADDRESS]; | u8 addr[IXGBE_ETH_LENGTH_OF_ADDRESS]; | ||||
u32 vmdq; | u32 vmdq; | ||||
}; | }; | ||||
/* | /* | ||||
** Driver queue struct: this is the interrupt container | * Driver queue struct: this is the interrupt container | ||||
** for the associated tx and rx ring. | * for the associated tx and rx ring. | ||||
*/ | */ | ||||
struct ix_queue { | struct ix_queue { | ||||
struct adapter *adapter; | struct adapter *adapter; | ||||
u32 msix; /* This queue's MSIX vector */ | u32 msix; /* This queue's MSI-X vector */ | ||||
u32 eims; /* This queue's EIMS bit */ | u32 eims; /* This queue's EIMS bit */ | ||||
u32 eitr_setting; | u32 eitr_setting; | ||||
u32 me; | u32 me; | ||||
struct resource *res; | struct resource *res; | ||||
void *tag; | void *tag; | ||||
int busy; | int busy; | ||||
struct tx_ring *txr; | struct tx_ring *txr; | ||||
struct rx_ring *rxr; | struct rx_ring *rxr; | ||||
struct task que_task; | struct task que_task; | ||||
struct taskqueue *tq; | struct taskqueue *tq; | ||||
u64 irqs; | u64 irqs; | ||||
}; | }; | ||||
/* | /* | ||||
* The transmit ring, one per queue | * The transmit ring, one per queue | ||||
*/ | */ | ||||
struct tx_ring { | struct tx_ring { | ||||
struct adapter *adapter; | struct adapter *adapter; | ||||
struct mtx tx_mtx; | struct mtx tx_mtx; | ||||
u32 me; | u32 me; | ||||
u32 tail; | u32 tail; | ||||
int busy; | int busy; | ||||
union ixgbe_adv_tx_desc *tx_base; | union ixgbe_adv_tx_desc *tx_base; | ||||
struct ixgbe_tx_buf *tx_buffers; | struct ixgbe_tx_buf *tx_buffers; | ||||
struct ixgbe_dma_alloc txdma; | struct ixgbe_dma_alloc txdma; | ||||
volatile u16 tx_avail; | volatile u16 tx_avail; | ||||
u16 next_avail_desc; | u16 next_avail_desc; | ||||
u16 next_to_clean; | u16 next_to_clean; | ||||
u16 num_desc; | u16 num_desc; | ||||
u32 txd_cmd; | u32 txd_cmd; | ||||
bus_dma_tag_t txtag; | bus_dma_tag_t txtag; | ||||
char mtx_name[16]; | char mtx_name[16]; | ||||
#ifndef IXGBE_LEGACY_TX | |||||
struct buf_ring *br; | struct buf_ring *br; | ||||
struct task txq_task; | struct task txq_task; | ||||
#endif | |||||
#ifdef IXGBE_FDIR | /* Flow Director */ | ||||
u16 atr_sample; | u16 atr_sample; | ||||
u16 atr_count; | u16 atr_count; | ||||
#endif | |||||
u32 bytes; /* used for AIM */ | u32 bytes; /* used for AIM */ | ||||
u32 packets; | u32 packets; | ||||
/* Soft Stats */ | /* Soft Stats */ | ||||
unsigned long tso_tx; | u64 tso_tx; | ||||
unsigned long no_tx_map_avail; | u64 no_tx_map_avail; | ||||
unsigned long no_tx_dma_setup; | u64 no_tx_dma_setup; | ||||
u64 no_desc_avail; | u64 no_desc_avail; | ||||
u64 total_packets; | u64 total_packets; | ||||
}; | }; | ||||
/* | /* | ||||
* The Receive ring, one per rx queue | * The Receive ring, one per rx queue | ||||
*/ | */ | ||||
struct rx_ring { | struct rx_ring { | ||||
struct adapter *adapter; | struct adapter *adapter; | ||||
struct mtx rx_mtx; | struct mtx rx_mtx; | ||||
u32 me; | u32 me; | ||||
u32 tail; | u32 tail; | ||||
union ixgbe_adv_rx_desc *rx_base; | union ixgbe_adv_rx_desc *rx_base; | ||||
struct ixgbe_dma_alloc rxdma; | struct ixgbe_dma_alloc rxdma; | ||||
struct lro_ctrl lro; | struct lro_ctrl lro; | ||||
bool lro_enabled; | bool lro_enabled; | ||||
bool hw_rsc; | bool hw_rsc; | ||||
bool vtag_strip; | bool vtag_strip; | ||||
u16 next_to_refresh; | u16 next_to_refresh; | ||||
u16 next_to_check; | u16 next_to_check; | ||||
u16 num_desc; | u16 num_desc; | ||||
u16 mbuf_sz; | u16 mbuf_sz; | ||||
char mtx_name[16]; | char mtx_name[16]; | ||||
struct ixgbe_rx_buf *rx_buffers; | struct ixgbe_rx_buf *rx_buffers; | ||||
bus_dma_tag_t ptag; | bus_dma_tag_t ptag; | ||||
u32 bytes; /* Used for AIM calc */ | u32 bytes; /* Used for AIM calc */ | ||||
u32 packets; | u32 packets; | ||||
/* Soft stats */ | /* Soft stats */ | ||||
u64 rx_irq; | u64 rx_irq; | ||||
u64 rx_copies; | u64 rx_copies; | ||||
u64 rx_packets; | u64 rx_packets; | ||||
u64 rx_bytes; | u64 rx_bytes; | ||||
u64 rx_discarded; | u64 rx_discarded; | ||||
u64 rsc_num; | u64 rsc_num; | ||||
#ifdef IXGBE_FDIR | |||||
/* Flow Director */ | |||||
u64 flm; | u64 flm; | ||||
#endif | |||||
}; | }; | ||||
#ifdef PCI_IOV | |||||
#define IXGBE_VF_CTS (1 << 0) /* VF is clear to send. */ | |||||
#define IXGBE_VF_CAP_MAC (1 << 1) /* VF is permitted to change MAC. */ | |||||
#define IXGBE_VF_CAP_VLAN (1 << 2) /* VF is permitted to join vlans. */ | |||||
#define IXGBE_VF_ACTIVE (1 << 3) /* VF is active. */ | |||||
#define IXGBE_MAX_VF_MC 30 /* Max number of multicast entries */ | #define IXGBE_MAX_VF_MC 30 /* Max number of multicast entries */ | ||||
struct ixgbe_vf { | struct ixgbe_vf { | ||||
u_int pool; | u_int pool; | ||||
u_int rar_index; | u_int rar_index; | ||||
u_int max_frame_size; | u_int max_frame_size; | ||||
uint32_t flags; | uint32_t flags; | ||||
uint8_t ether_addr[ETHER_ADDR_LEN]; | uint8_t ether_addr[ETHER_ADDR_LEN]; | ||||
uint16_t mc_hash[IXGBE_MAX_VF_MC]; | uint16_t mc_hash[IXGBE_MAX_VF_MC]; | ||||
uint16_t num_mc_hashes; | uint16_t num_mc_hashes; | ||||
uint16_t default_vlan; | uint16_t default_vlan; | ||||
uint16_t vlan_tag; | uint16_t vlan_tag; | ||||
uint16_t api_ver; | uint16_t api_ver; | ||||
}; | }; | ||||
#endif /* PCI_IOV */ | |||||
/* Our adapter structure */ | /* Our adapter structure */ | ||||
struct adapter { | struct adapter { | ||||
struct ixgbe_hw hw; | struct ixgbe_hw hw; | ||||
struct ixgbe_osdep osdep; | struct ixgbe_osdep osdep; | ||||
device_t dev; | device_t dev; | ||||
struct ifnet *ifp; | struct ifnet *ifp; | ||||
struct resource *pci_mem; | struct resource *pci_mem; | ||||
struct resource *msix_mem; | struct resource *msix_mem; | ||||
/* | /* | ||||
* Interrupt resources: this set is | * Interrupt resources: this set is | ||||
* either used for legacy, or for Link | * either used for legacy, or for Link | ||||
* when doing MSIX | * when doing MSI-X | ||||
*/ | */ | ||||
void *tag; | void *tag; | ||||
struct resource *res; | struct resource *res; | ||||
struct ifmedia media; | struct ifmedia media; | ||||
struct callout timer; | struct callout timer; | ||||
int msix; | int link_rid; | ||||
int if_flags; | int if_flags; | ||||
struct mtx core_mtx; | struct mtx core_mtx; | ||||
eventhandler_tag vlan_attach; | eventhandler_tag vlan_attach; | ||||
eventhandler_tag vlan_detach; | eventhandler_tag vlan_detach; | ||||
u16 num_vlans; | u16 num_vlans; | ||||
u16 num_queues; | u16 num_queues; | ||||
/* | /* | ||||
** Shadow VFTA table, this is needed because | * Shadow VFTA table, this is needed because | ||||
** the real vlan filter table gets cleared during | * the real vlan filter table gets cleared during | ||||
** a soft reset and the driver needs to be able | * a soft reset and the driver needs to be able | ||||
** to repopulate it. | * to repopulate it. | ||||
*/ | */ | ||||
u32 shadow_vfta[IXGBE_VFTA_SIZE]; | u32 shadow_vfta[IXGBE_VFTA_SIZE]; | ||||
/* Info about the interface */ | /* Info about the interface */ | ||||
u32 optics; | |||||
u32 fc; /* local flow ctrl setting */ | |||||
int advertise; /* link speeds */ | int advertise; /* link speeds */ | ||||
bool enable_aim; /* adaptive interrupt moderation */ | int enable_aim; /* adaptive interrupt moderation */ | ||||
bool link_active; | bool link_active; | ||||
u16 max_frame_size; | u16 max_frame_size; | ||||
u16 num_segs; | u16 num_segs; | ||||
u32 link_speed; | u32 link_speed; | ||||
bool link_up; | bool link_up; | ||||
u32 vector; | u32 vector; | ||||
u16 dmac; | u16 dmac; | ||||
bool eee_enabled; | |||||
u32 phy_layer; | u32 phy_layer; | ||||
/* Power management-related */ | /* Power management-related */ | ||||
bool wol_support; | bool wol_support; | ||||
u32 wufc; | u32 wufc; | ||||
/* Mbuf cluster size */ | /* Mbuf cluster size */ | ||||
u32 rx_mbuf_sz; | u32 rx_mbuf_sz; | ||||
/* Support for pluggable optics */ | /* Support for pluggable optics */ | ||||
bool sfp_probe; | bool sfp_probe; | ||||
struct task link_task; /* Link tasklet */ | struct task link_task; /* Link tasklet */ | ||||
struct task mod_task; /* SFP tasklet */ | struct task mod_task; /* SFP tasklet */ | ||||
struct task msf_task; /* Multispeed Fiber */ | struct task msf_task; /* Multispeed Fiber */ | ||||
#ifdef PCI_IOV | |||||
struct task mbx_task; /* VF -> PF mailbox interrupt */ | struct task mbx_task; /* VF -> PF mailbox interrupt */ | ||||
#endif /* PCI_IOV */ | |||||
#ifdef IXGBE_FDIR | /* Flow Director */ | ||||
int fdir_reinit; | int fdir_reinit; | ||||
struct task fdir_task; | struct task fdir_task; | ||||
#endif | |||||
struct task phy_task; /* PHY intr tasklet */ | struct task phy_task; /* PHY intr tasklet */ | ||||
struct taskqueue *tq; | struct taskqueue *tq; | ||||
/* | /* | ||||
** Queues: | * Queues: | ||||
** This is the irq holder, it has | * This is the irq holder, it has | ||||
** and RX/TX pair or rings associated | * and RX/TX pair or rings associated | ||||
** with it. | * with it. | ||||
*/ | */ | ||||
struct ix_queue *queues; | struct ix_queue *queues; | ||||
/* | /* | ||||
* Transmit rings: | * Transmit rings | ||||
* Allocated at run time, an array of rings. | * Allocated at run time, an array of rings | ||||
*/ | */ | ||||
struct tx_ring *tx_rings; | struct tx_ring *tx_rings; | ||||
u32 num_tx_desc; | u32 num_tx_desc; | ||||
u32 tx_process_limit; | u32 tx_process_limit; | ||||
/* | /* | ||||
* Receive rings: | * Receive rings | ||||
* Allocated at run time, an array of rings. | * Allocated at run time, an array of rings | ||||
*/ | */ | ||||
struct rx_ring *rx_rings; | struct rx_ring *rx_rings; | ||||
u64 active_queues; | u64 active_queues; | ||||
u32 num_rx_desc; | u32 num_rx_desc; | ||||
u32 rx_process_limit; | u32 rx_process_limit; | ||||
/* Multicast array memory */ | /* Multicast array memory */ | ||||
struct ixgbe_mc_addr *mta; | struct ixgbe_mc_addr *mta; | ||||
/* SR-IOV */ | |||||
int iov_mode; | |||||
int num_vfs; | int num_vfs; | ||||
int pool; | int pool; | ||||
#ifdef PCI_IOV | |||||
struct ixgbe_vf *vfs; | struct ixgbe_vf *vfs; | ||||
#endif | |||||
#ifdef DEV_NETMAP | /* Bypass */ | ||||
struct ixgbe_bp_data bypass; | |||||
/* Netmap */ | |||||
void (*init_locked)(struct adapter *); | void (*init_locked)(struct adapter *); | ||||
void (*stop_locked)(void *); | void (*stop_locked)(void *); | ||||
#endif | |||||
/* Misc stats maintained by the driver */ | /* Misc stats maintained by the driver */ | ||||
unsigned long dropped_pkts; | unsigned long dropped_pkts; | ||||
unsigned long mbuf_defrag_failed; | unsigned long mbuf_defrag_failed; | ||||
unsigned long mbuf_header_failed; | unsigned long mbuf_header_failed; | ||||
unsigned long mbuf_packet_failed; | unsigned long mbuf_packet_failed; | ||||
unsigned long watchdog_events; | unsigned long watchdog_events; | ||||
unsigned long link_irq; | unsigned long link_irq; | ||||
union { | union { | ||||
struct ixgbe_hw_stats pf; | struct ixgbe_hw_stats pf; | ||||
struct ixgbevf_hw_stats vf; | struct ixgbevf_hw_stats vf; | ||||
} stats; | } stats; | ||||
#if __FreeBSD_version >= 1100036 | #if __FreeBSD_version >= 1100036 | ||||
/* counter(9) stats */ | /* counter(9) stats */ | ||||
u64 ipackets; | u64 ipackets; | ||||
u64 ierrors; | u64 ierrors; | ||||
u64 opackets; | u64 opackets; | ||||
u64 oerrors; | u64 oerrors; | ||||
u64 ibytes; | u64 ibytes; | ||||
u64 obytes; | u64 obytes; | ||||
u64 imcasts; | u64 imcasts; | ||||
u64 omcasts; | u64 omcasts; | ||||
u64 iqdrops; | u64 iqdrops; | ||||
u64 noproto; | u64 noproto; | ||||
#endif | #endif | ||||
/* Feature capable/enabled flags. See ixgbe_features.h */ | |||||
u32 feat_cap; | |||||
u32 feat_en; | |||||
}; | }; | ||||
/* Precision Time Sync (IEEE 1588) defines */ | /* Precision Time Sync (IEEE 1588) defines */ | ||||
#define ETHERTYPE_IEEE1588 0x88F7 | #define ETHERTYPE_IEEE1588 0x88F7 | ||||
#define PICOSECS_PER_TICK 20833 | #define PICOSECS_PER_TICK 20833 | ||||
#define TSYNC_UDP_PORT 319 /* UDP port for the protocol */ | #define TSYNC_UDP_PORT 319 /* UDP port for the protocol */ | ||||
#define IXGBE_ADVTXD_TSTAMP 0x00080000 | #define IXGBE_ADVTXD_TSTAMP 0x00080000 | ||||
#define IXGBE_CORE_LOCK_INIT(_sc, _name) \ | #define IXGBE_CORE_LOCK_INIT(_sc, _name) \ | ||||
mtx_init(&(_sc)->core_mtx, _name, "IXGBE Core Lock", MTX_DEF) | mtx_init(&(_sc)->core_mtx, _name, "IXGBE Core Lock", MTX_DEF) | ||||
#define IXGBE_CORE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->core_mtx) | #define IXGBE_CORE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->core_mtx) | ||||
#define IXGBE_TX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->tx_mtx) | #define IXGBE_TX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->tx_mtx) | ||||
#define IXGBE_RX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->rx_mtx) | #define IXGBE_RX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->rx_mtx) | ||||
#define IXGBE_CORE_LOCK(_sc) mtx_lock(&(_sc)->core_mtx) | #define IXGBE_CORE_LOCK(_sc) mtx_lock(&(_sc)->core_mtx) | ||||
Show All 32 Lines | |||||
#define IXGBE_SET_IBYTES(sc, count) (sc)->ifp->if_ibytes = (count) | #define IXGBE_SET_IBYTES(sc, count) (sc)->ifp->if_ibytes = (count) | ||||
#define IXGBE_SET_OBYTES(sc, count) (sc)->ifp->if_obytes = (count) | #define IXGBE_SET_OBYTES(sc, count) (sc)->ifp->if_obytes = (count) | ||||
#define IXGBE_SET_IMCASTS(sc, count) (sc)->ifp->if_imcasts = (count) | #define IXGBE_SET_IMCASTS(sc, count) (sc)->ifp->if_imcasts = (count) | ||||
#define IXGBE_SET_OMCASTS(sc, count) (sc)->ifp->if_omcasts = (count) | #define IXGBE_SET_OMCASTS(sc, count) (sc)->ifp->if_omcasts = (count) | ||||
#define IXGBE_SET_IQDROPS(sc, count) (sc)->ifp->if_iqdrops = (count) | #define IXGBE_SET_IQDROPS(sc, count) (sc)->ifp->if_iqdrops = (count) | ||||
#endif | #endif | ||||
/* External PHY register addresses */ | /* External PHY register addresses */ | ||||
#define IXGBE_PHY_CURRENT_TEMP 0xC820 | #define IXGBE_PHY_CURRENT_TEMP 0xC820 | ||||
#define IXGBE_PHY_OVERTEMP_STATUS 0xC830 | #define IXGBE_PHY_OVERTEMP_STATUS 0xC830 | ||||
/* Sysctl help messages; displayed with sysctl -d */ | /* Sysctl help messages; displayed with sysctl -d */ | ||||
#define IXGBE_SYSCTL_DESC_ADV_SPEED \ | #define IXGBE_SYSCTL_DESC_ADV_SPEED \ | ||||
"\nControl advertised link speed using these flags:\n" \ | "\nControl advertised link speed using these flags:\n" \ | ||||
"\t0x1 - advertise 100M\n" \ | "\t0x1 - advertise 100M\n" \ | ||||
"\t0x2 - advertise 1G\n" \ | "\t0x2 - advertise 1G\n" \ | ||||
"\t0x4 - advertise 10G\n\n" \ | "\t0x4 - advertise 10G\n" \ | ||||
"\t100M is only supported on certain 10GBaseT adapters.\n" | "\t0x8 - advertise 10M\n\n" \ | ||||
"\t100M and 10M are only supported on certain adapters.\n" | |||||
#define IXGBE_SYSCTL_DESC_SET_FC \ | #define IXGBE_SYSCTL_DESC_SET_FC \ | ||||
"\nSet flow control mode using these values:\n" \ | "\nSet flow control mode using these values:\n" \ | ||||
"\t0 - off\n" \ | "\t0 - off\n" \ | ||||
"\t1 - rx pause\n" \ | "\t1 - rx pause\n" \ | ||||
"\t2 - tx pause\n" \ | "\t2 - tx pause\n" \ | ||||
"\t3 - tx and rx pause" | "\t3 - tx and rx pause" | ||||
static inline bool | |||||
ixgbe_is_sfp(struct ixgbe_hw *hw) | |||||
{ | |||||
switch (hw->phy.type) { | |||||
case ixgbe_phy_sfp_avago: | |||||
case ixgbe_phy_sfp_ftl: | |||||
case ixgbe_phy_sfp_intel: | |||||
case ixgbe_phy_sfp_unknown: | |||||
case ixgbe_phy_sfp_passive_tyco: | |||||
case ixgbe_phy_sfp_passive_unknown: | |||||
case ixgbe_phy_qsfp_passive_unknown: | |||||
case ixgbe_phy_qsfp_active_unknown: | |||||
case ixgbe_phy_qsfp_intel: | |||||
case ixgbe_phy_qsfp_unknown: | |||||
return TRUE; | |||||
default: | |||||
return FALSE; | |||||
} | |||||
} | |||||
/* Workaround to make 8.0 buildable */ | /* Workaround to make 8.0 buildable */ | ||||
#if __FreeBSD_version >= 800000 && __FreeBSD_version < 800504 | #if __FreeBSD_version >= 800000 && __FreeBSD_version < 800504 | ||||
static __inline int | static __inline int | ||||
drbr_needs_enqueue(struct ifnet *ifp, struct buf_ring *br) | drbr_needs_enqueue(struct ifnet *ifp, struct buf_ring *br) | ||||
{ | { | ||||
#ifdef ALTQ | #ifdef ALTQ | ||||
if (ALTQ_IS_ENABLED(&ifp->if_snd)) | if (ALTQ_IS_ENABLED(&ifp->if_snd)) | ||||
return (1); | return (1); | ||||
#endif | #endif | ||||
return (!buf_ring_empty(br)); | return (!buf_ring_empty(br)); | ||||
} | } | ||||
#endif | #endif | ||||
/* | /* | ||||
** Find the number of unrefreshed RX descriptors | * Find the number of unrefreshed RX descriptors | ||||
*/ | */ | ||||
static inline u16 | static inline u16 | ||||
ixgbe_rx_unrefreshed(struct rx_ring *rxr) | ixgbe_rx_unrefreshed(struct rx_ring *rxr) | ||||
{ | { | ||||
if (rxr->next_to_check > rxr->next_to_refresh) | if (rxr->next_to_check > rxr->next_to_refresh) | ||||
return (rxr->next_to_check - rxr->next_to_refresh - 1); | return (rxr->next_to_check - rxr->next_to_refresh - 1); | ||||
else | else | ||||
return ((rxr->num_desc + rxr->next_to_check) - | return ((rxr->num_desc + rxr->next_to_check) - | ||||
rxr->next_to_refresh - 1); | rxr->next_to_refresh - 1); | ||||
} | } | ||||
static inline int | |||||
ixgbe_legacy_ring_empty(struct ifnet *ifp, struct buf_ring *dummy) | |||||
{ | |||||
UNREFERENCED_1PARAMETER(dummy); | |||||
return IFQ_DRV_IS_EMPTY(&ifp->if_snd); | |||||
} | |||||
/* | /* | ||||
** This checks for a zero mac addr, something that will be likely | * This checks for a zero mac addr, something that will be likely | ||||
** unless the Admin on the Host has created one. | * unless the Admin on the Host has created one. | ||||
*/ | */ | ||||
static inline bool | static inline bool | ||||
ixv_check_ether_addr(u8 *addr) | ixv_check_ether_addr(u8 *addr) | ||||
{ | { | ||||
bool status = TRUE; | bool status = TRUE; | ||||
if ((addr[0] == 0 && addr[1]== 0 && addr[2] == 0 && | if ((addr[0] == 0 && addr[1]== 0 && addr[2] == 0 && | ||||
addr[3] == 0 && addr[4]== 0 && addr[5] == 0)) | addr[3] == 0 && addr[4]== 0 && addr[5] == 0)) | ||||
status = FALSE; | status = FALSE; | ||||
return (status); | return (status); | ||||
} | } | ||||
/* Shared Prototypes */ | /* Shared Prototypes */ | ||||
void ixgbe_legacy_start(struct ifnet *); | |||||
#ifdef IXGBE_LEGACY_TX | int ixgbe_legacy_start_locked(struct ifnet *, struct tx_ring *); | ||||
void ixgbe_start(struct ifnet *); | |||||
void ixgbe_start_locked(struct tx_ring *, struct ifnet *); | |||||
#else /* ! IXGBE_LEGACY_TX */ | |||||
int ixgbe_mq_start(struct ifnet *, struct mbuf *); | int ixgbe_mq_start(struct ifnet *, struct mbuf *); | ||||
int ixgbe_mq_start_locked(struct ifnet *, struct tx_ring *); | int ixgbe_mq_start_locked(struct ifnet *, struct tx_ring *); | ||||
void ixgbe_qflush(struct ifnet *); | void ixgbe_qflush(struct ifnet *); | ||||
void ixgbe_deferred_mq_start(void *, int); | void ixgbe_deferred_mq_start(void *, int); | ||||
#endif /* IXGBE_LEGACY_TX */ | |||||
int ixgbe_allocate_queues(struct adapter *); | int ixgbe_allocate_queues(struct adapter *); | ||||
int ixgbe_allocate_transmit_buffers(struct tx_ring *); | |||||
int ixgbe_setup_transmit_structures(struct adapter *); | int ixgbe_setup_transmit_structures(struct adapter *); | ||||
void ixgbe_free_transmit_structures(struct adapter *); | void ixgbe_free_transmit_structures(struct adapter *); | ||||
int ixgbe_allocate_receive_buffers(struct rx_ring *); | |||||
int ixgbe_setup_receive_structures(struct adapter *); | int ixgbe_setup_receive_structures(struct adapter *); | ||||
void ixgbe_free_receive_structures(struct adapter *); | void ixgbe_free_receive_structures(struct adapter *); | ||||
void ixgbe_txeof(struct tx_ring *); | void ixgbe_txeof(struct tx_ring *); | ||||
bool ixgbe_rxeof(struct ix_queue *); | bool ixgbe_rxeof(struct ix_queue *); | ||||
int ixgbe_dma_malloc(struct adapter *, | #include "ixgbe_bypass.h" | ||||
bus_size_t, struct ixgbe_dma_alloc *, int); | #include "ixgbe_sriov.h" | ||||
void ixgbe_dma_free(struct adapter *, struct ixgbe_dma_alloc *); | #include "ixgbe_fdir.h" | ||||
#include "ixgbe_rss.h" | |||||
#ifdef PCI_IOV | #include "ixgbe_netmap.h" | ||||
static inline boolean_t | |||||
ixgbe_vf_mac_changed(struct ixgbe_vf *vf, const uint8_t *mac) | |||||
{ | |||||
return (bcmp(mac, vf->ether_addr, ETHER_ADDR_LEN) != 0); | |||||
} | |||||
static inline void | |||||
ixgbe_send_vf_msg(struct adapter *adapter, struct ixgbe_vf *vf, u32 msg) | |||||
{ | |||||
if (vf->flags & IXGBE_VF_CTS) | |||||
msg |= IXGBE_VT_MSGTYPE_CTS; | |||||
ixgbe_write_mbx(&adapter->hw, &msg, 1, vf->pool); | |||||
} | |||||
static inline void | |||||
ixgbe_send_vf_ack(struct adapter *adapter, struct ixgbe_vf *vf, u32 msg) | |||||
{ | |||||
msg &= IXGBE_VT_MSG_MASK; | |||||
ixgbe_send_vf_msg(adapter, vf, msg | IXGBE_VT_MSGTYPE_ACK); | |||||
} | |||||
static inline void | |||||
ixgbe_send_vf_nack(struct adapter *adapter, struct ixgbe_vf *vf, u32 msg) | |||||
{ | |||||
msg &= IXGBE_VT_MSG_MASK; | |||||
ixgbe_send_vf_msg(adapter, vf, msg | IXGBE_VT_MSGTYPE_NACK); | |||||
} | |||||
static inline void | |||||
ixgbe_process_vf_ack(struct adapter *adapter, struct ixgbe_vf *vf) | |||||
{ | |||||
if (!(vf->flags & IXGBE_VF_CTS)) | |||||
ixgbe_send_vf_nack(adapter, vf, 0); | |||||
} | |||||
static inline enum ixgbe_iov_mode | |||||
ixgbe_get_iov_mode(struct adapter *adapter) | |||||
{ | |||||
if (adapter->num_vfs == 0) | |||||
return (IXGBE_NO_VM); | |||||
if (adapter->num_queues <= 2) | |||||
return (IXGBE_64_VM); | |||||
else if (adapter->num_queues <= 4) | |||||
return (IXGBE_32_VM); | |||||
else | |||||
return (IXGBE_NO_VM); | |||||
} | |||||
static inline u16 | |||||
ixgbe_max_vfs(enum ixgbe_iov_mode mode) | |||||
{ | |||||
/* | |||||
* We return odd numbers below because we | |||||
* reserve 1 VM's worth of queues for the PF. | |||||
*/ | |||||
switch (mode) { | |||||
case IXGBE_64_VM: | |||||
return (63); | |||||
case IXGBE_32_VM: | |||||
return (31); | |||||
case IXGBE_NO_VM: | |||||
default: | |||||
return (0); | |||||
} | |||||
} | |||||
static inline int | |||||
ixgbe_vf_queues(enum ixgbe_iov_mode mode) | |||||
{ | |||||
switch (mode) { | |||||
case IXGBE_64_VM: | |||||
return (2); | |||||
case IXGBE_32_VM: | |||||
return (4); | |||||
case IXGBE_NO_VM: | |||||
default: | |||||
return (0); | |||||
} | |||||
} | |||||
static inline int | |||||
ixgbe_vf_que_index(enum ixgbe_iov_mode mode, u32 vfnum, int num) | |||||
{ | |||||
return ((vfnum * ixgbe_vf_queues(mode)) + num); | |||||
} | |||||
static inline int | |||||
ixgbe_pf_que_index(enum ixgbe_iov_mode mode, int num) | |||||
{ | |||||
return (ixgbe_vf_que_index(mode, ixgbe_max_vfs(mode), num)); | |||||
} | |||||
static inline void | |||||
ixgbe_update_max_frame(struct adapter * adapter, int max_frame) | |||||
{ | |||||
if (adapter->max_frame_size < max_frame) | |||||
adapter->max_frame_size = max_frame; | |||||
} | |||||
static inline u32 | |||||
ixgbe_get_mrqc(enum ixgbe_iov_mode mode) | |||||
{ | |||||
u32 mrqc = 0; | |||||
switch (mode) { | |||||
case IXGBE_64_VM: | |||||
mrqc = IXGBE_MRQC_VMDQRSS64EN; | |||||
break; | |||||
case IXGBE_32_VM: | |||||
mrqc = IXGBE_MRQC_VMDQRSS32EN; | |||||
break; | |||||
case IXGBE_NO_VM: | |||||
mrqc = 0; | |||||
break; | |||||
default: | |||||
panic("Unexpected SR-IOV mode %d", mode); | |||||
} | |||||
return(mrqc); | |||||
} | |||||
static inline u32 | |||||
ixgbe_get_mtqc(enum ixgbe_iov_mode mode) | |||||
{ | |||||
uint32_t mtqc = 0; | |||||
switch (mode) { | |||||
case IXGBE_64_VM: | |||||
mtqc |= IXGBE_MTQC_64VF | IXGBE_MTQC_VT_ENA; | |||||
break; | |||||
case IXGBE_32_VM: | |||||
mtqc |= IXGBE_MTQC_32VF | IXGBE_MTQC_VT_ENA; | |||||
break; | |||||
case IXGBE_NO_VM: | |||||
mtqc = IXGBE_MTQC_64Q_1PB; | |||||
break; | |||||
default: | |||||
panic("Unexpected SR-IOV mode %d", mode); | |||||
} | |||||
return(mtqc); | |||||
} | |||||
#endif /* PCI_IOV */ | |||||
#endif /* _IXGBE_H_ */ | #endif /* _IXGBE_H_ */ |