Differential D11232 Diff 29693 sys/dev/ixgbe/ixgbe_api.c

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sys/dev/ixgbe/ixgbe_api.c

/******************************************************************************		/******************************************************************************

Copyright (c) 2001-2015, Intel Corporation		Copyright (c) 2001-2017, Intel Corporation
All rights reserved.		All rights reserved.

Redistribution and use in source and binary forms, with or without		Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:		modification, are permitted provided that the following conditions are met:

1. Redistributions of source code must retain the above copyright notice,		1. Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.		this list of conditions and the following disclaimer.

2. Redistributions in binary form must reproduce the above copyright		2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the		notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.		documentation and/or other materials provided with the distribution.

3. Neither the name of the Intel Corporation nor the names of its		3. Neither the name of the Intel Corporation nor the names of its
contributors may be used to endorse or promote products derived from		contributors may be used to endorse or promote products derived from
this software without specific prior written permission.		this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"		THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE		AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE		IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE		ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR		LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF		CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS		SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN		INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE		ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.		POSSIBILITY OF SUCH DAMAGE.

******************************************************************************/		******************************************************************************/
/$FreeBSD$/		/$FreeBSD$/

#include "ixgbe_api.h"		#include "ixgbe_api.h"
#include "ixgbe_common.h"		#include "ixgbe_common.h"
Show All 11 Lines
static const u32 ixgbe_mvals_X550[IXGBE_MVALS_IDX_LIMIT] = {		static const u32 ixgbe_mvals_X550[IXGBE_MVALS_IDX_LIMIT] = {
IXGBE_MVALS_INIT(_X550)		IXGBE_MVALS_INIT(_X550)
};		};

static const u32 ixgbe_mvals_X550EM_x[IXGBE_MVALS_IDX_LIMIT] = {		static const u32 ixgbe_mvals_X550EM_x[IXGBE_MVALS_IDX_LIMIT] = {
IXGBE_MVALS_INIT(_X550EM_x)		IXGBE_MVALS_INIT(_X550EM_x)
};		};

		static const u32 ixgbe_mvals_X550EM_a[IXGBE_MVALS_IDX_LIMIT] = {
		IXGBE_MVALS_INIT(_X550EM_a)
		};

/**		/**
* ixgbe_dcb_get_rtrup2tc - read rtrup2tc reg		* ixgbe_dcb_get_rtrup2tc - read rtrup2tc reg
* @hw: pointer to hardware structure		* @hw: pointer to hardware structure
* @map: pointer to u8 arr for returning map		* @map: pointer to u8 arr for returning map
*		*
* Read the rtrup2tc HW register and resolve its content into map		* Read the rtrup2tc HW register and resolve its content into map
**/		**/
void ixgbe_dcb_get_rtrup2tc(struct ixgbe_hw hw, u8 map)		void ixgbe_dcb_get_rtrup2tc(struct ixgbe_hw hw, u8 map)
Show All 34 Lines	case ixgbe_mac_82599EB:
break;		break;
case ixgbe_mac_X540:		case ixgbe_mac_X540:
status = ixgbe_init_ops_X540(hw);		status = ixgbe_init_ops_X540(hw);
break;		break;
case ixgbe_mac_X550:		case ixgbe_mac_X550:
status = ixgbe_init_ops_X550(hw);		status = ixgbe_init_ops_X550(hw);
break;		break;
case ixgbe_mac_X550EM_x:		case ixgbe_mac_X550EM_x:
status = ixgbe_init_ops_X550EM(hw);		status = ixgbe_init_ops_X550EM_x(hw);
break;		break;
case ixgbe_mac_82599_vf:		case ixgbe_mac_X550EM_a:
case ixgbe_mac_X540_vf:		status = ixgbe_init_ops_X550EM_a(hw);
case ixgbe_mac_X550_vf:
case ixgbe_mac_X550EM_x_vf:
status = ixgbe_init_ops_vf(hw);
break;		break;
default:		default:
status = IXGBE_ERR_DEVICE_NOT_SUPPORTED;		status = IXGBE_ERR_DEVICE_NOT_SUPPORTED;
break;		break;
}		}
hw->mac.max_link_up_time = IXGBE_LINK_UP_TIME;		hw->mac.max_link_up_time = IXGBE_LINK_UP_TIME;

return status;		return status;
▲ Show 20 Lines • Show All 48 Lines • ▼ Show 20 Lines	s32 ixgbe_set_mac_type(struct ixgbe_hw *hw)
case IXGBE_DEV_ID_82599_SFP_SF_QP:		case IXGBE_DEV_ID_82599_SFP_SF_QP:
case IXGBE_DEV_ID_82599_QSFP_SF_QP:		case IXGBE_DEV_ID_82599_QSFP_SF_QP:
case IXGBE_DEV_ID_82599EN_SFP:		case IXGBE_DEV_ID_82599EN_SFP:
case IXGBE_DEV_ID_82599_CX4:		case IXGBE_DEV_ID_82599_CX4:
case IXGBE_DEV_ID_82599_BYPASS:		case IXGBE_DEV_ID_82599_BYPASS:
case IXGBE_DEV_ID_82599_T3_LOM:		case IXGBE_DEV_ID_82599_T3_LOM:
hw->mac.type = ixgbe_mac_82599EB;		hw->mac.type = ixgbe_mac_82599EB;
break;		break;
case IXGBE_DEV_ID_82599_VF:
case IXGBE_DEV_ID_82599_VF_HV:
hw->mac.type = ixgbe_mac_82599_vf;
break;
case IXGBE_DEV_ID_X540_VF:
case IXGBE_DEV_ID_X540_VF_HV:
hw->mac.type = ixgbe_mac_X540_vf;
hw->mvals = ixgbe_mvals_X540;
break;
case IXGBE_DEV_ID_X540T:		case IXGBE_DEV_ID_X540T:
case IXGBE_DEV_ID_X540T1:		case IXGBE_DEV_ID_X540T1:
case IXGBE_DEV_ID_X540_BYPASS:		case IXGBE_DEV_ID_X540_BYPASS:
hw->mac.type = ixgbe_mac_X540;		hw->mac.type = ixgbe_mac_X540;
hw->mvals = ixgbe_mvals_X540;		hw->mvals = ixgbe_mvals_X540;
break;		break;
case IXGBE_DEV_ID_X550T:		case IXGBE_DEV_ID_X550T:
case IXGBE_DEV_ID_X550T1:		case IXGBE_DEV_ID_X550T1:
hw->mac.type = ixgbe_mac_X550;		hw->mac.type = ixgbe_mac_X550;
hw->mvals = ixgbe_mvals_X550;		hw->mvals = ixgbe_mvals_X550;
break;		break;
case IXGBE_DEV_ID_X550EM_X_KX4:		case IXGBE_DEV_ID_X550EM_X_KX4:
case IXGBE_DEV_ID_X550EM_X_KR:		case IXGBE_DEV_ID_X550EM_X_KR:
case IXGBE_DEV_ID_X550EM_X_10G_T:		case IXGBE_DEV_ID_X550EM_X_10G_T:
case IXGBE_DEV_ID_X550EM_X_1G_T:		case IXGBE_DEV_ID_X550EM_X_1G_T:
case IXGBE_DEV_ID_X550EM_X_SFP:		case IXGBE_DEV_ID_X550EM_X_SFP:
		case IXGBE_DEV_ID_X550EM_X_XFI:
hw->mac.type = ixgbe_mac_X550EM_x;		hw->mac.type = ixgbe_mac_X550EM_x;
hw->mvals = ixgbe_mvals_X550EM_x;		hw->mvals = ixgbe_mvals_X550EM_x;
break;		break;
case IXGBE_DEV_ID_X550_VF:		case IXGBE_DEV_ID_X550EM_A_KR:
case IXGBE_DEV_ID_X550_VF_HV:		case IXGBE_DEV_ID_X550EM_A_KR_L:
hw->mac.type = ixgbe_mac_X550_vf;		case IXGBE_DEV_ID_X550EM_A_SFP_N:
hw->mvals = ixgbe_mvals_X550;		case IXGBE_DEV_ID_X550EM_A_SGMII:
		case IXGBE_DEV_ID_X550EM_A_SGMII_L:
		case IXGBE_DEV_ID_X550EM_A_1G_T:
		case IXGBE_DEV_ID_X550EM_A_1G_T_L:
		case IXGBE_DEV_ID_X550EM_A_10G_T:
		case IXGBE_DEV_ID_X550EM_A_QSFP:
		case IXGBE_DEV_ID_X550EM_A_QSFP_N:
		case IXGBE_DEV_ID_X550EM_A_SFP:
		hw->mac.type = ixgbe_mac_X550EM_a;
		hw->mvals = ixgbe_mvals_X550EM_a;
break;		break;
case IXGBE_DEV_ID_X550EM_X_VF:
case IXGBE_DEV_ID_X550EM_X_VF_HV:
hw->mac.type = ixgbe_mac_X550EM_x_vf;
hw->mvals = ixgbe_mvals_X550EM_x;
break;
default:		default:
ret_val = IXGBE_ERR_DEVICE_NOT_SUPPORTED;		ret_val = IXGBE_ERR_DEVICE_NOT_SUPPORTED;
ERROR_REPORT2(IXGBE_ERROR_UNSUPPORTED,		ERROR_REPORT2(IXGBE_ERROR_UNSUPPORTED,
"Unsupported device id: %x",		"Unsupported device id: %x",
hw->device_id);		hw->device_id);
break;		break;
}		}

▲ Show 20 Lines • Show All 829 Lines • ▼ Show 20 Lines	s32 ixgbe_clear_vfta(struct ixgbe_hw *hw)
return ixgbe_call_func(hw, hw->mac.ops.clear_vfta, (hw),		return ixgbe_call_func(hw, hw->mac.ops.clear_vfta, (hw),
IXGBE_NOT_IMPLEMENTED);		IXGBE_NOT_IMPLEMENTED);
}		}

/**		/**
* ixgbe_set_vfta - Set VLAN filter table		* ixgbe_set_vfta - Set VLAN filter table
* @hw: pointer to hardware structure		* @hw: pointer to hardware structure
* @vlan: VLAN id to write to VLAN filter		* @vlan: VLAN id to write to VLAN filter
* @vind: VMDq output index that maps queue to VLAN id in VFTA		* @vind: VMDq output index that maps queue to VLAN id in VLVFB
* @vlan_on: boolean flag to turn on/off VLAN in VFTA		* @vlan_on: boolean flag to turn on/off VLAN
		* @vlvf_bypass: boolean flag indicating updating the default pool is okay
*		*
* Turn on/off specified VLAN in the VLAN filter table.		* Turn on/off specified VLAN in the VLAN filter table.
**/		**/
s32 ixgbe_set_vfta(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on)		s32 ixgbe_set_vfta(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on,
		bool vlvf_bypass)
{		{
return ixgbe_call_func(hw, hw->mac.ops.set_vfta, (hw, vlan, vind,		return ixgbe_call_func(hw, hw->mac.ops.set_vfta, (hw, vlan, vind,
vlan_on), IXGBE_NOT_IMPLEMENTED);		vlan_on, vlvf_bypass), IXGBE_NOT_IMPLEMENTED);
}		}

/**		/**
* ixgbe_set_vlvf - Set VLAN Pool Filter		* ixgbe_set_vlvf - Set VLAN Pool Filter
* @hw: pointer to hardware structure		* @hw: pointer to hardware structure
* @vlan: VLAN id to write to VLAN filter		* @vlan: VLAN id to write to VLAN filter
* @vind: VMDq output index that maps queue to VLAN id in VFVFB		* @vind: VMDq output index that maps queue to VLAN id in VLVFB
* @vlan_on: boolean flag to turn on/off VLAN in VFVF		* @vlan_on: boolean flag to turn on/off VLAN in VLVF
* @vfta_changed: pointer to boolean flag which indicates whether VFTA		* @vfta_delta: pointer to the difference between the current value of VFTA
* should be changed		* and the desired value
		* @vfta: the desired value of the VFTA
		* @vlvf_bypass: boolean flag indicating updating the default pool is okay
*		*
* Turn on/off specified bit in VLVF table.		* Turn on/off specified bit in VLVF table.
**/		**/
s32 ixgbe_set_vlvf(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on,		s32 ixgbe_set_vlvf(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on,
bool *vfta_changed)		u32 *vfta_delta, u32 vfta, bool vlvf_bypass)
{		{
return ixgbe_call_func(hw, hw->mac.ops.set_vlvf, (hw, vlan, vind,		return ixgbe_call_func(hw, hw->mac.ops.set_vlvf, (hw, vlan, vind,
vlan_on, vfta_changed), IXGBE_NOT_IMPLEMENTED);		vlan_on, vfta_delta, vfta, vlvf_bypass),
		IXGBE_NOT_IMPLEMENTED);
}		}

/**		/**
* ixgbe_fc_enable - Enable flow control		* ixgbe_fc_enable - Enable flow control
* @hw: pointer to hardware structure		* @hw: pointer to hardware structure
*		*
* Configures the flow control settings based on SW configuration.		* Configures the flow control settings based on SW configuration.
**/		**/
Show All 17 Lines

/**		/**
* ixgbe_set_fw_drv_ver - Try to send the driver version number FW		* ixgbe_set_fw_drv_ver - Try to send the driver version number FW
* @hw: pointer to hardware structure		* @hw: pointer to hardware structure
* @maj: driver major number to be sent to firmware		* @maj: driver major number to be sent to firmware
* @min: driver minor number to be sent to firmware		* @min: driver minor number to be sent to firmware
* @build: driver build number to be sent to firmware		* @build: driver build number to be sent to firmware
* @ver: driver version number to be sent to firmware		* @ver: driver version number to be sent to firmware
		* @len: length of driver_ver string
		* @driver_ver: driver string
**/		**/
s32 ixgbe_set_fw_drv_ver(struct ixgbe_hw *hw, u8 maj, u8 min, u8 build,		s32 ixgbe_set_fw_drv_ver(struct ixgbe_hw *hw, u8 maj, u8 min, u8 build,
u8 ver)		u8 ver, u16 len, char *driver_ver)
{		{
return ixgbe_call_func(hw, hw->mac.ops.set_fw_drv_ver, (hw, maj, min,		return ixgbe_call_func(hw, hw->mac.ops.set_fw_drv_ver, (hw, maj, min,
build, ver), IXGBE_NOT_IMPLEMENTED);		build, ver, len, driver_ver),
		IXGBE_NOT_IMPLEMENTED);
}		}



/**		/**
* ixgbe_dmac_config - Configure DMA Coalescing registers.		* ixgbe_dmac_config - Configure DMA Coalescing registers.
* @hw: pointer to hardware structure		* @hw: pointer to hardware structure
*		*
▲ Show 20 Lines • Show All 178 Lines • ▼ Show 20 Lines
*/		*/
s32 ixgbe_handle_lasi(struct ixgbe_hw *hw)		s32 ixgbe_handle_lasi(struct ixgbe_hw *hw)
{		{
return ixgbe_call_func(hw, hw->phy.ops.handle_lasi, (hw),		return ixgbe_call_func(hw, hw->phy.ops.handle_lasi, (hw),
IXGBE_NOT_IMPLEMENTED);		IXGBE_NOT_IMPLEMENTED);
}		}

/**		/**
		* ixgbe_bypass_rw - Bit bang data into by_pass FW
		* @hw: pointer to hardware structure
		* @cmd: Command we send to the FW
		* @status: The reply from the FW
		*
		* Bit-bangs the cmd to the by_pass FW status points to what is returned.
		**/
		s32 ixgbe_bypass_rw(struct ixgbe_hw hw, u32 cmd, u32 status)
		{
		return ixgbe_call_func(hw, hw->mac.ops.bypass_rw, (hw, cmd, status),
		IXGBE_NOT_IMPLEMENTED);
		}

		/**
		* ixgbe_bypass_valid_rd - Verify valid return from bit-bang.
		*
		* If we send a write we can't be sure it took until we can read back
		* that same register. It can be a problem as some of the feilds may
		* for valid reasons change inbetween the time wrote the register and
		* we read it again to verify. So this function check everything we
		* can check and then assumes it worked.
		*
		* @u32 in_reg - The register cmd for the bit-bang read.
		* @u32 out_reg - The register returned from a bit-bang read.
		**/
		bool ixgbe_bypass_valid_rd(struct ixgbe_hw *hw, u32 in_reg, u32 out_reg)
		{
		return ixgbe_call_func(hw, hw->mac.ops.bypass_valid_rd,
		(in_reg, out_reg), IXGBE_NOT_IMPLEMENTED);
		}

		/**
		* ixgbe_bypass_set - Set a bypass field in the FW CTRL Regiter.
		* @hw: pointer to hardware structure
		* @cmd: The control word we are setting.
		* @event: The event we are setting in the FW. This also happens to
		* be the mask for the event we are setting (handy)
		* @action: The action we set the event to in the FW. This is in a
		* bit field that happens to be what we want to put in
		* the event spot (also handy)
		*
		* Writes to the cmd control the bits in actions.
		**/
		s32 ixgbe_bypass_set(struct ixgbe_hw *hw, u32 cmd, u32 event, u32 action)
		{
		return ixgbe_call_func(hw, hw->mac.ops.bypass_set,
		(hw, cmd, event, action),
		IXGBE_NOT_IMPLEMENTED);
		}

		/**
		* ixgbe_bypass_rd_eep - Read the bypass FW eeprom address
		* @hw: pointer to hardware structure
		* @addr: The bypass eeprom address to read.
		* @value: The 8b of data at the address above.
		**/
		s32 ixgbe_bypass_rd_eep(struct ixgbe_hw hw, u32 addr, u8 value)
		{
		return ixgbe_call_func(hw, hw->mac.ops.bypass_rd_eep,
		(hw, addr, value), IXGBE_NOT_IMPLEMENTED);
		}

		/**
* ixgbe_read_analog_reg8 - Reads 8 bit analog register		* ixgbe_read_analog_reg8 - Reads 8 bit analog register
* @hw: pointer to hardware structure		* @hw: pointer to hardware structure
* @reg: analog register to read		* @reg: analog register to read
* @val: read value		* @val: read value
*		*
* Performs write operation to analog register specified.		* Performs write operation to analog register specified.
**/		**/
s32 ixgbe_read_analog_reg8(struct ixgbe_hw hw, u32 reg, u8 val)		s32 ixgbe_read_analog_reg8(struct ixgbe_hw hw, u32 reg, u8 val)
▲ Show 20 Lines • Show All 58 Lines • ▼ Show 20 Lines	s32 ixgbe_read_i2c_byte_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
u8 dev_addr, u8 *data)		u8 dev_addr, u8 *data)
{		{
return ixgbe_call_func(hw, hw->phy.ops.read_i2c_byte_unlocked,		return ixgbe_call_func(hw, hw->phy.ops.read_i2c_byte_unlocked,
(hw, byte_offset, dev_addr, data),		(hw, byte_offset, dev_addr, data),
IXGBE_NOT_IMPLEMENTED);		IXGBE_NOT_IMPLEMENTED);
}		}

/**		/**
* ixgbe_read_i2c_combined - Perform I2C read combined operation		* ixgbe_read_link - Perform read operation on link device
* @hw: pointer to the hardware structure		* @hw: pointer to the hardware structure
* @addr: I2C bus address to read from		* @addr: bus address to read from
* @reg: I2C device register to read from		* @reg: device register to read from
* @val: pointer to location to receive read value		* @val: pointer to location to receive read value
*		*
* Returns an error code on error.		* Returns an error code on error.
*/		*/
s32 ixgbe_read_i2c_combined(struct ixgbe_hw hw, u8 addr, u16 reg, u16 val)		s32 ixgbe_read_link(struct ixgbe_hw hw, u8 addr, u16 reg, u16 val)
{		{
return ixgbe_call_func(hw, hw->phy.ops.read_i2c_combined, (hw, addr,		return ixgbe_call_func(hw, hw->link.ops.read_link, (hw, addr,
reg, val), IXGBE_NOT_IMPLEMENTED);		reg, val), IXGBE_NOT_IMPLEMENTED);
}		}

/**		/**
* ixgbe_read_i2c_combined_unlocked - Perform I2C read combined operation		* ixgbe_read_link_unlocked - Perform read operation on link device
* @hw: pointer to the hardware structure		* @hw: pointer to the hardware structure
* @addr: I2C bus address to read from		* @addr: bus address to read from
* @reg: I2C device register to read from		* @reg: device register to read from
* @val: pointer to location to receive read value		* @val: pointer to location to receive read value
*		*
* Returns an error code on error.		* Returns an error code on error.
**/		**/
s32 ixgbe_read_i2c_combined_unlocked(struct ixgbe_hw *hw, u8 addr, u16 reg,		s32 ixgbe_read_link_unlocked(struct ixgbe_hw hw, u8 addr, u16 reg, u16 val)
u16 *val)
{		{
return ixgbe_call_func(hw, hw->phy.ops.read_i2c_combined_unlocked,		return ixgbe_call_func(hw, hw->link.ops.read_link_unlocked,
(hw, addr, reg, val),		(hw, addr, reg, val), IXGBE_NOT_IMPLEMENTED);
IXGBE_NOT_IMPLEMENTED);
}		}

/**		/**
* ixgbe_write_i2c_byte - Writes 8 bit word over I2C		* ixgbe_write_i2c_byte - Writes 8 bit word over I2C
* @hw: pointer to hardware structure		* @hw: pointer to hardware structure
* @byte_offset: byte offset to write		* @byte_offset: byte offset to write
* @dev_addr: I2C bus address to write to		* @dev_addr: I2C bus address to write to
* @data: value to write		* @data: value to write
Show All 22 Lines	s32 ixgbe_write_i2c_byte_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
u8 dev_addr, u8 data)		u8 dev_addr, u8 data)
{		{
return ixgbe_call_func(hw, hw->phy.ops.write_i2c_byte_unlocked,		return ixgbe_call_func(hw, hw->phy.ops.write_i2c_byte_unlocked,
(hw, byte_offset, dev_addr, data),		(hw, byte_offset, dev_addr, data),
IXGBE_NOT_IMPLEMENTED);		IXGBE_NOT_IMPLEMENTED);
}		}

/**		/**
* ixgbe_write_i2c_combined - Perform I2C write combined operation		* ixgbe_write_link - Perform write operation on link device
* @hw: pointer to the hardware structure		* @hw: pointer to the hardware structure
* @addr: I2C bus address to write to		* @addr: bus address to write to
* @reg: I2C device register to write to		* @reg: device register to write to
* @val: value to write		* @val: value to write
*		*
* Returns an error code on error.		* Returns an error code on error.
*/		*/
s32 ixgbe_write_i2c_combined(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 val)		s32 ixgbe_write_link(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 val)
{		{
return ixgbe_call_func(hw, hw->phy.ops.write_i2c_combined, (hw, addr,		return ixgbe_call_func(hw, hw->link.ops.write_link,
reg, val), IXGBE_NOT_IMPLEMENTED);		(hw, addr, reg, val), IXGBE_NOT_IMPLEMENTED);
}		}

/**		/**
* ixgbe_write_i2c_combined_unlocked - Perform I2C write combined operation		* ixgbe_write_link_unlocked - Perform write operation on link device
* @hw: pointer to the hardware structure		* @hw: pointer to the hardware structure
* @addr: I2C bus address to write to		* @addr: bus address to write to
* @reg: I2C device register to write to		* @reg: device register to write to
* @val: value to write		* @val: value to write
*		*
* Returns an error code on error.		* Returns an error code on error.
**/		**/
s32 ixgbe_write_i2c_combined_unlocked(struct ixgbe_hw *hw, u8 addr, u16 reg,		s32 ixgbe_write_link_unlocked(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 val)
u16 val)
{		{
return ixgbe_call_func(hw, hw->phy.ops.write_i2c_combined_unlocked,		return ixgbe_call_func(hw, hw->link.ops.write_link_unlocked,
(hw, addr, reg, val), IXGBE_NOT_IMPLEMENTED);		(hw, addr, reg, val), IXGBE_NOT_IMPLEMENTED);
}		}

/**		/**
* ixgbe_write_i2c_eeprom - Writes 8 bit EEPROM word over I2C interface		* ixgbe_write_i2c_eeprom - Writes 8 bit EEPROM word over I2C interface
* @hw: pointer to hardware structure		* @hw: pointer to hardware structure
* @byte_offset: EEPROM byte offset to write		* @byte_offset: EEPROM byte offset to write
* @eeprom_data: value to write		* @eeprom_data: value to write
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}		}

/**		/**
* ixgbe_get_supported_physical_layer - Returns physical layer type		* ixgbe_get_supported_physical_layer - Returns physical layer type
* @hw: pointer to hardware structure		* @hw: pointer to hardware structure
*		*
* Determines physical layer capabilities of the current configuration.		* Determines physical layer capabilities of the current configuration.
**/		**/
u32 ixgbe_get_supported_physical_layer(struct ixgbe_hw *hw)		u64 ixgbe_get_supported_physical_layer(struct ixgbe_hw *hw)
{		{
return ixgbe_call_func(hw, hw->mac.ops.get_supported_physical_layer,		return ixgbe_call_func(hw, hw->mac.ops.get_supported_physical_layer,
(hw), IXGBE_PHYSICAL_LAYER_UNKNOWN);		(hw), IXGBE_PHYSICAL_LAYER_UNKNOWN);
}		}

/**		/**
* ixgbe_enable_rx_dma - Enables Rx DMA unit, dependent on device specifics		* ixgbe_enable_rx_dma - Enables Rx DMA unit, dependent on device specifics
* @hw: pointer to hardware structure		* @hw: pointer to hardware structure
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*		*
* Releases the SWFW semaphore through SW_FW_SYNC register for the specified		* Releases the SWFW semaphore through SW_FW_SYNC register for the specified
* function (CSR, PHY0, PHY1, EEPROM, Flash)		* function (CSR, PHY0, PHY1, EEPROM, Flash)
**/		**/
void ixgbe_release_swfw_semaphore(struct ixgbe_hw *hw, u32 mask)		void ixgbe_release_swfw_semaphore(struct ixgbe_hw *hw, u32 mask)
{		{
if (hw->mac.ops.release_swfw_sync)		if (hw->mac.ops.release_swfw_sync)
hw->mac.ops.release_swfw_sync(hw, mask);		hw->mac.ops.release_swfw_sync(hw, mask);
		}

		/**
		* ixgbe_init_swfw_semaphore - Clean up SWFW semaphore
		* @hw: pointer to hardware structure
		*
		* Attempts to acquire the SWFW semaphore through SW_FW_SYNC register.
		* Regardless of whether is succeeds or not it then release the semaphore.
		* This is function is called to recover from catastrophic failures that
		* may have left the semaphore locked.
		**/
		void ixgbe_init_swfw_semaphore(struct ixgbe_hw *hw)
		{
		if (hw->mac.ops.init_swfw_sync)
		hw->mac.ops.init_swfw_sync(hw);
}		}


void ixgbe_disable_rx(struct ixgbe_hw *hw)		void ixgbe_disable_rx(struct ixgbe_hw *hw)
{		{
if (hw->mac.ops.disable_rx)		if (hw->mac.ops.disable_rx)
hw->mac.ops.disable_rx(hw);		hw->mac.ops.disable_rx(hw);
}		}
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