Differential D10156 Diff 29485 head/sys/sparc64/sparc64/intr_machdep.c

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head/sys/sparc64/sparc64/intr_machdep.c

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#endif		#endif

static int intr_assign_cpu(void *arg, int cpu);		static int intr_assign_cpu(void *arg, int cpu);
static void intr_execute_handlers(void *);		static void intr_execute_handlers(void *);
static void intr_stray_level(struct trapframe *);		static void intr_stray_level(struct trapframe *);
static void intr_stray_vector(void *);		static void intr_stray_vector(void *);
static int intrcnt_setname(const char *, int);		static int intrcnt_setname(const char *, int);
static void intrcnt_updatename(int, const char *, int);		static void intrcnt_updatename(int, const char *, int);
		void counter_intr_inc(void);

static void		static void
intrcnt_updatename(int vec, const char *name, int ispil)		intrcnt_updatename(int vec, const char *name, int ispil)
{		{
static int intrcnt_index, stray_pil_index, stray_vec_index;		static int intrcnt_index, stray_pil_index, stray_vec_index;
int name_index;		int name_index;

mtx_lock_spin(&intrcnt_lock);		mtx_lock_spin(&intrcnt_lock);
▲ Show 20 Lines • Show All 310 Lines • ▼ Show 20 Lines	intr_describe(int vec, void ih, const char descr)
error = intr_event_describe_handler(iv->iv_event, ih, descr);		error = intr_event_describe_handler(iv->iv_event, ih, descr);
if (error) {		if (error) {
sx_xunlock(&intr_table_lock);		sx_xunlock(&intr_table_lock);
return (error);		return (error);
}		}
intrcnt_updatename(vec, iv->iv_event->ie_fullname, 0);		intrcnt_updatename(vec, iv->iv_event->ie_fullname, 0);
sx_xunlock(&intr_table_lock);		sx_xunlock(&intr_table_lock);
return (error);		return (error);
		}

		/*
		* Do VM_CNT_INC(intr), being in the interrupt context already. This is
		* called from assembly.
		* To avoid counter_enter() and appropriate assertion, unwrap VM_CNT_INC()
		* and hardcode the actual increment.
		*/
		void
		counter_intr_inc(void)
		{

		(uint64_t )zpcpu_get(vm_cnt.v_intr) += 1;
}		}

#ifdef SMP		#ifdef SMP
/*		/*
* Support for balancing interrupt sources across CPUs. For now we just		* Support for balancing interrupt sources across CPUs. For now we just
* allocate CPUs round-robin.		* allocate CPUs round-robin.
*/		*/

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