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sys/dev/ixl/ixl.h
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#ifndef _IXL_H_ | #ifndef _IXL_H_ | ||||
#define _IXL_H_ | #define _IXL_H_ | ||||
#include "opt_inet.h" | #include "opt_inet.h" | ||||
#include "opt_inet6.h" | #include "opt_inet6.h" | ||||
#include "opt_rss.h" | #include "opt_rss.h" | ||||
#include "opt_ixl.h" | |||||
#include <sys/param.h> | #include <sys/param.h> | ||||
#include <sys/systm.h> | #include <sys/systm.h> | ||||
#include <sys/buf_ring.h> | #include <sys/buf_ring.h> | ||||
#include <sys/mbuf.h> | #include <sys/mbuf.h> | ||||
#include <sys/protosw.h> | #include <sys/protosw.h> | ||||
#include <sys/socket.h> | #include <sys/socket.h> | ||||
#include <sys/malloc.h> | #include <sys/malloc.h> | ||||
#include <sys/kernel.h> | #include <sys/kernel.h> | ||||
#include <sys/module.h> | #include <sys/module.h> | ||||
#include <sys/sockio.h> | #include <sys/sockio.h> | ||||
#include <sys/eventhandler.h> | #include <sys/eventhandler.h> | ||||
#include <sys/syslog.h> | |||||
#include <net/if.h> | #include <net/if.h> | ||||
#include <net/if_var.h> | #include <net/if_var.h> | ||||
#include <net/if_arp.h> | #include <net/if_arp.h> | ||||
#include <net/bpf.h> | #include <net/bpf.h> | ||||
#include <net/ethernet.h> | #include <net/ethernet.h> | ||||
#include <net/if_dl.h> | #include <net/if_dl.h> | ||||
#include <net/if_media.h> | #include <net/if_media.h> | ||||
▲ Show 20 Lines • Show All 103 Lines • ▼ Show 20 Lines | enum ixl_dbg_mask { | ||||
IXL_DBG_IOCTL_ALL = 0x00000030, | IXL_DBG_IOCTL_ALL = 0x00000030, | ||||
I40E_DEBUG_RSS = 0x00000100, | I40E_DEBUG_RSS = 0x00000100, | ||||
IXL_DBG_IOV = 0x00001000, | IXL_DBG_IOV = 0x00001000, | ||||
IXL_DBG_IOV_VC = 0x00002000, | IXL_DBG_IOV_VC = 0x00002000, | ||||
IXL_DBG_SWITCH_INFO = 0x00010000, | IXL_DBG_SWITCH_INFO = 0x00010000, | ||||
IXL_DBG_I2C = 0x00020000, | |||||
IXL_DBG_ALL = 0xFFFFFFFF | IXL_DBG_ALL = 0xFFFFFFFF | ||||
}; | }; | ||||
/* Tunables */ | /* Tunables */ | ||||
/* | /* | ||||
* Ring Descriptors Valid Range: 32-4096 Default Value: 1024 This value is the | * Ring Descriptors Valid Range: 32-4096 Default Value: 1024 This value is the | ||||
* number of tx/rx descriptors allocated by the driver. Increasing this | * number of tx/rx descriptors allocated by the driver. Increasing this | ||||
* value allows the driver to queue more operations. | * value allows the driver to queue more operations. | ||||
* | * | ||||
* Tx descriptors are always 16 bytes, but Rx descriptors can be 32 bytes. | * Tx descriptors are always 16 bytes, but Rx descriptors can be 32 bytes. | ||||
* The driver currently always uses 32 byte Rx descriptors. | * The driver currently always uses 32 byte Rx descriptors. | ||||
*/ | */ | ||||
#define DEFAULT_RING 1024 | #define IXL_DEFAULT_RING 1024 | ||||
#define IXL_MAX_RING 8160 | #define IXL_MAX_RING 8160 | ||||
#define IXL_MIN_RING 32 | #define IXL_MIN_RING 32 | ||||
#define IXL_RING_INCREMENT 32 | #define IXL_RING_INCREMENT 32 | ||||
#define IXL_AQ_LEN 256 | #define IXL_AQ_LEN 256 | ||||
#define IXL_AQ_LEN_MAX 1024 | #define IXL_AQ_LEN_MAX 1024 | ||||
/* | /* | ||||
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* This parameters control when the driver calls the routine to reclaim | * This parameters control when the driver calls the routine to reclaim | ||||
* transmit descriptors. | * transmit descriptors. | ||||
*/ | */ | ||||
#define IXL_TX_CLEANUP_THRESHOLD (que->num_desc / 8) | #define IXL_TX_CLEANUP_THRESHOLD (que->num_desc / 8) | ||||
#define IXL_TX_OP_THRESHOLD (que->num_desc / 32) | #define IXL_TX_OP_THRESHOLD (que->num_desc / 32) | ||||
#define MAX_MULTICAST_ADDR 128 | #define MAX_MULTICAST_ADDR 128 | ||||
#define IXL_BAR 3 | #define IXL_MSIX_BAR 3 | ||||
#define IXL_ADM_LIMIT 2 | #define IXL_ADM_LIMIT 2 | ||||
#define IXL_TSO_SIZE 65535 | #define IXL_TSO_SIZE 65535 | ||||
#define IXL_AQ_BUF_SZ ((u32) 4096) | #define IXL_AQ_BUF_SZ ((u32) 4096) | ||||
#define IXL_RX_HDR 128 | #define IXL_RX_HDR 128 | ||||
#define IXL_RX_LIMIT 512 | #define IXL_RX_LIMIT 512 | ||||
#define IXL_RX_ITR 0 | #define IXL_RX_ITR 0 | ||||
#define IXL_TX_ITR 1 | #define IXL_TX_ITR 1 | ||||
#define IXL_ITR_NONE 3 | #define IXL_ITR_NONE 3 | ||||
#define IXL_QUEUE_EOL 0x7FF | #define IXL_QUEUE_EOL 0x7FF | ||||
#define IXL_MAX_FRAME 9728 | #define IXL_MAX_FRAME 9728 | ||||
#define IXL_MAX_TX_SEGS 8 | #define IXL_MAX_TX_SEGS 8 | ||||
#define IXL_MAX_TSO_SEGS 128 | #define IXL_MAX_TSO_SEGS 128 | ||||
#define IXL_SPARSE_CHAIN 6 | #define IXL_SPARSE_CHAIN 6 | ||||
#define IXL_QUEUE_HUNG 0x80000000 | #define IXL_QUEUE_HUNG 0x80000000 | ||||
#define IXL_MIN_TSO_MSS 64 | |||||
#define IXL_RSS_KEY_SIZE_REG 13 | #define IXL_RSS_KEY_SIZE_REG 13 | ||||
#define IXL_RSS_KEY_SIZE (IXL_RSS_KEY_SIZE_REG * 4) | #define IXL_RSS_KEY_SIZE (IXL_RSS_KEY_SIZE_REG * 4) | ||||
#define IXL_RSS_VSI_LUT_SIZE 64 /* X722 -> VSI, X710 -> VF */ | #define IXL_RSS_VSI_LUT_SIZE 64 /* X722 -> VSI, X710 -> VF */ | ||||
#define IXL_RSS_VSI_LUT_ENTRY_MASK 0x3F | #define IXL_RSS_VSI_LUT_ENTRY_MASK 0x3F | ||||
#define IXL_RSS_VF_LUT_ENTRY_MASK 0xF | #define IXL_RSS_VF_LUT_ENTRY_MASK 0xF | ||||
#define IXL_VF_MAX_BUFFER 0x3F80 | #define IXL_VF_MAX_BUFFER 0x3F80 | ||||
#define IXL_VF_MAX_HDR_BUFFER 0x840 | #define IXL_VF_MAX_HDR_BUFFER 0x840 | ||||
#define IXL_VF_MAX_FRAME 0x3FFF | #define IXL_VF_MAX_FRAME 0x3FFF | ||||
/* ERJ: hardware can support ~2k (SW5+) filters between all functions */ | /* ERJ: hardware can support ~2k (SW5+) filters between all functions */ | ||||
#define IXL_MAX_FILTERS 256 | #define IXL_MAX_FILTERS 256 | ||||
#define IXL_MAX_TX_BUSY 10 | #define IXL_MAX_TX_BUSY 10 | ||||
#define IXL_NVM_VERSION_LO_SHIFT 0 | #define IXL_NVM_VERSION_LO_SHIFT 0 | ||||
#define IXL_NVM_VERSION_LO_MASK (0xff << IXL_NVM_VERSION_LO_SHIFT) | #define IXL_NVM_VERSION_LO_MASK (0xff << IXL_NVM_VERSION_LO_SHIFT) | ||||
#define IXL_NVM_VERSION_HI_SHIFT 12 | #define IXL_NVM_VERSION_HI_SHIFT 12 | ||||
#define IXL_NVM_VERSION_HI_MASK (0xf << IXL_NVM_VERSION_HI_SHIFT) | #define IXL_NVM_VERSION_HI_MASK (0xf << IXL_NVM_VERSION_HI_SHIFT) | ||||
/* | /* | ||||
* Interrupt Moderation parameters | * Interrupt Moderation parameters | ||||
* Multiply ITR values by 2 for real ITR value | |||||
*/ | */ | ||||
#define IXL_MAX_ITR 0x07FF | #define IXL_MAX_ITR 0x0FF0 | ||||
#define IXL_ITR_100K 0x0005 | #define IXL_ITR_100K 0x0005 | ||||
#define IXL_ITR_20K 0x0019 | #define IXL_ITR_20K 0x0019 | ||||
#define IXL_ITR_8K 0x003E | #define IXL_ITR_8K 0x003E | ||||
#define IXL_ITR_4K 0x007A | #define IXL_ITR_4K 0x007A | ||||
#define IXL_ITR_1K 0x01F4 | |||||
#define IXL_ITR_DYNAMIC 0x8000 | #define IXL_ITR_DYNAMIC 0x8000 | ||||
#define IXL_LOW_LATENCY 0 | #define IXL_LOW_LATENCY 0 | ||||
#define IXL_AVE_LATENCY 1 | #define IXL_AVE_LATENCY 1 | ||||
#define IXL_BULK_LATENCY 2 | #define IXL_BULK_LATENCY 2 | ||||
/* MacVlan Flags */ | /* MacVlan Flags */ | ||||
#define IXL_FILTER_USED (u16)(1 << 0) | #define IXL_FILTER_USED (u16)(1 << 0) | ||||
#define IXL_FILTER_VLAN (u16)(1 << 1) | #define IXL_FILTER_VLAN (u16)(1 << 1) | ||||
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#define IXL_GLGEN_VFLRSTAT_INDEX(glb_vf) ((glb_vf) / 32) | #define IXL_GLGEN_VFLRSTAT_INDEX(glb_vf) ((glb_vf) / 32) | ||||
#define IXL_GLGEN_VFLRSTAT_MASK(glb_vf) (1 << ((glb_vf) % 32)) | #define IXL_GLGEN_VFLRSTAT_MASK(glb_vf) (1 << ((glb_vf) % 32)) | ||||
#define IXL_MAX_ITR_IDX 3 | #define IXL_MAX_ITR_IDX 3 | ||||
#define IXL_END_OF_INTR_LNKLST 0x7FF | #define IXL_END_OF_INTR_LNKLST 0x7FF | ||||
#define IXL_DEFAULT_RSS_HENA (\ | #define IXL_DEFAULT_RSS_HENA_BASE (\ | ||||
BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_UDP) | \ | BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_UDP) | \ | ||||
BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_TCP) | \ | BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_TCP) | \ | ||||
BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_SCTP) | \ | BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_SCTP) | \ | ||||
BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_OTHER) | \ | BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_OTHER) | \ | ||||
BIT_ULL(I40E_FILTER_PCTYPE_FRAG_IPV4) | \ | BIT_ULL(I40E_FILTER_PCTYPE_FRAG_IPV4) | \ | ||||
BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_UDP) | \ | BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_UDP) | \ | ||||
BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_TCP) | \ | BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_TCP) | \ | ||||
BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_SCTP) | \ | BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_SCTP) | \ | ||||
BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_OTHER) | \ | BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_OTHER) | \ | ||||
BIT_ULL(I40E_FILTER_PCTYPE_FRAG_IPV6) | \ | BIT_ULL(I40E_FILTER_PCTYPE_FRAG_IPV6) | \ | ||||
BIT_ULL(I40E_FILTER_PCTYPE_L2_PAYLOAD)) | BIT_ULL(I40E_FILTER_PCTYPE_L2_PAYLOAD)) | ||||
#define IXL_DEFAULT_RSS_HENA_XL710 IXL_DEFAULT_RSS_HENA_BASE | |||||
#define IXL_DEFAULT_RSS_HENA_X722 (\ | |||||
IXL_DEFAULT_RSS_HENA_BASE | \ | |||||
BIT_ULL(I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) | \ | |||||
BIT_ULL(I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP) | \ | |||||
BIT_ULL(I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) | \ | |||||
BIT_ULL(I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP) | \ | |||||
BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK) | \ | |||||
BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK)) | |||||
#define IXL_TX_LOCK(_sc) mtx_lock(&(_sc)->mtx) | #define IXL_TX_LOCK(_sc) mtx_lock(&(_sc)->mtx) | ||||
#define IXL_TX_UNLOCK(_sc) mtx_unlock(&(_sc)->mtx) | #define IXL_TX_UNLOCK(_sc) mtx_unlock(&(_sc)->mtx) | ||||
#define IXL_TX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->mtx) | #define IXL_TX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->mtx) | ||||
#define IXL_TX_TRYLOCK(_sc) mtx_trylock(&(_sc)->mtx) | #define IXL_TX_TRYLOCK(_sc) mtx_trylock(&(_sc)->mtx) | ||||
#define IXL_TX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->mtx, MA_OWNED) | #define IXL_TX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->mtx, MA_OWNED) | ||||
#define IXL_RX_LOCK(_sc) mtx_lock(&(_sc)->mtx) | #define IXL_RX_LOCK(_sc) mtx_lock(&(_sc)->mtx) | ||||
#define IXL_RX_UNLOCK(_sc) mtx_unlock(&(_sc)->mtx) | #define IXL_RX_UNLOCK(_sc) mtx_unlock(&(_sc)->mtx) | ||||
▲ Show 20 Lines • Show All 89 Lines • ▼ Show 20 Lines | struct tx_ring { | ||||
u32 latency; | u32 latency; | ||||
struct ixl_tx_buf *buffers; | struct ixl_tx_buf *buffers; | ||||
volatile u16 avail; | volatile u16 avail; | ||||
u32 cmd; | u32 cmd; | ||||
bus_dma_tag_t tx_tag; | bus_dma_tag_t tx_tag; | ||||
bus_dma_tag_t tso_tag; | bus_dma_tag_t tso_tag; | ||||
char mtx_name[16]; | char mtx_name[16]; | ||||
struct buf_ring *br; | struct buf_ring *br; | ||||
s32 watchdog_timer; | |||||
/* Used for Dynamic ITR calculation */ | /* Used for Dynamic ITR calculation */ | ||||
u32 packets; | u32 packets; | ||||
u32 bytes; | u32 bytes; | ||||
/* Soft Stats */ | /* Soft Stats */ | ||||
u64 tx_bytes; | u64 tx_bytes; | ||||
u64 no_desc; | u64 no_desc; | ||||
▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Lines | |||||
struct ixl_queue { | struct ixl_queue { | ||||
struct ixl_vsi *vsi; | struct ixl_vsi *vsi; | ||||
u32 me; | u32 me; | ||||
u32 msix; /* This queue's MSIX vector */ | u32 msix; /* This queue's MSIX vector */ | ||||
u32 eims; /* This queue's EIMS bit */ | u32 eims; /* This queue's EIMS bit */ | ||||
struct resource *res; | struct resource *res; | ||||
void *tag; | void *tag; | ||||
int num_desc; /* both tx and rx */ | int num_desc; /* both tx and rx */ | ||||
int busy; | |||||
struct tx_ring txr; | struct tx_ring txr; | ||||
struct rx_ring rxr; | struct rx_ring rxr; | ||||
struct task task; | struct task task; | ||||
struct task tx_task; | struct task tx_task; | ||||
struct taskqueue *tq; | struct taskqueue *tq; | ||||
/* Queue stats */ | /* Queue stats */ | ||||
u64 irqs; | u64 irqs; | ||||
u64 tso; | u64 tso; | ||||
u64 mbuf_defrag_failed; | u64 mbuf_defrag_failed; | ||||
u64 mbuf_hdr_failed; | u64 mbuf_hdr_failed; | ||||
u64 mbuf_pkt_failed; | u64 mbuf_pkt_failed; | ||||
u64 tx_dmamap_failed; | u64 tx_dmamap_failed; | ||||
u64 dropped_pkts; | u64 dropped_pkts; | ||||
u64 mss_too_small; | |||||
}; | }; | ||||
/* | /* | ||||
** Virtual Station Interface | ** Virtual Station Interface | ||||
*/ | */ | ||||
SLIST_HEAD(ixl_ftl_head, ixl_mac_filter); | SLIST_HEAD(ixl_ftl_head, ixl_mac_filter); | ||||
struct ixl_vsi { | struct ixl_vsi { | ||||
void *back; | void *back; | ||||
▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Lines | struct ixl_vsi { | ||||
u64 oqdrops; | u64 oqdrops; | ||||
u64 noproto; | u64 noproto; | ||||
/* Driver statistics */ | /* Driver statistics */ | ||||
u64 hw_filters_del; | u64 hw_filters_del; | ||||
u64 hw_filters_add; | u64 hw_filters_add; | ||||
/* Misc. */ | /* Misc. */ | ||||
u64 active_queues; | |||||
u64 flags; | u64 flags; | ||||
struct sysctl_oid *vsi_node; | struct sysctl_oid *vsi_node; | ||||
}; | }; | ||||
/* | /* | ||||
** Find the number of unrefreshed RX descriptors | ** Find the number of unrefreshed RX descriptors | ||||
*/ | */ | ||||
static inline u16 | static inline u16 | ||||
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