Differential D9227 Diff 24163 sys/dev/ixl/i40e_common.c

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sys/dev/ixl/i40e_common.c

Show First 20 Lines • Show All 72 Lines • ▼ Show 20 Lines	if (hw->vendor_id == I40E_INTEL_VENDOR_ID) {
case I40E_DEV_ID_QSFP_X722:		case I40E_DEV_ID_QSFP_X722:
case I40E_DEV_ID_SFP_X722:		case I40E_DEV_ID_SFP_X722:
case I40E_DEV_ID_1G_BASE_T_X722:		case I40E_DEV_ID_1G_BASE_T_X722:
case I40E_DEV_ID_10G_BASE_T_X722:		case I40E_DEV_ID_10G_BASE_T_X722:
case I40E_DEV_ID_SFP_I_X722:		case I40E_DEV_ID_SFP_I_X722:
hw->mac.type = I40E_MAC_X722;		hw->mac.type = I40E_MAC_X722;
break;		break;
case I40E_DEV_ID_X722_VF:		case I40E_DEV_ID_X722_VF:
case I40E_DEV_ID_X722_VF_HV:
case I40E_DEV_ID_X722_A0_VF:		case I40E_DEV_ID_X722_A0_VF:
hw->mac.type = I40E_MAC_X722_VF;		hw->mac.type = I40E_MAC_X722_VF;
break;		break;
case I40E_DEV_ID_VF:		case I40E_DEV_ID_VF:
case I40E_DEV_ID_VF_HV:		case I40E_DEV_ID_VF_HV:
hw->mac.type = I40E_MAC_VF;		hw->mac.type = I40E_MAC_VF;
break;		break;
default:		default:
▲ Show 20 Lines • Show All 993 Lines • ▼ Show 20 Lines
{		{
struct i40e_aqc_mac_address_read_data addrs;		struct i40e_aqc_mac_address_read_data addrs;
enum i40e_status_code status;		enum i40e_status_code status;
u16 flags = 0;		u16 flags = 0;

status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);		status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);

if (flags & I40E_AQC_LAN_ADDR_VALID)		if (flags & I40E_AQC_LAN_ADDR_VALID)
memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac));		i40e_memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac),
		I40E_NONDMA_TO_NONDMA);

return status;		return status;
}		}

/**		/**
* i40e_get_port_mac_addr - get Port MAC address		* i40e_get_port_mac_addr - get Port MAC address
* @hw: pointer to the HW structure		* @hw: pointer to the HW structure
* @mac_addr: pointer to Port MAC address		* @mac_addr: pointer to Port MAC address
*		*
* Reads the adapter's Port MAC address		* Reads the adapter's Port MAC address
**/		**/
enum i40e_status_code i40e_get_port_mac_addr(struct i40e_hw hw, u8 mac_addr)		enum i40e_status_code i40e_get_port_mac_addr(struct i40e_hw hw, u8 mac_addr)
{		{
struct i40e_aqc_mac_address_read_data addrs;		struct i40e_aqc_mac_address_read_data addrs;
enum i40e_status_code status;		enum i40e_status_code status;
u16 flags = 0;		u16 flags = 0;

status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);		status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
if (status)		if (status)
return status;		return status;

if (flags & I40E_AQC_PORT_ADDR_VALID)		if (flags & I40E_AQC_PORT_ADDR_VALID)
memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac));		i40e_memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac),
		I40E_NONDMA_TO_NONDMA);
else		else
status = I40E_ERR_INVALID_MAC_ADDR;		status = I40E_ERR_INVALID_MAC_ADDR;

return status;		return status;
}		}

/**		/**
* i40e_pre_tx_queue_cfg - pre tx queue configure		* i40e_pre_tx_queue_cfg - pre tx queue configure
▲ Show 20 Lines • Show All 96 Lines • ▼ Show 20 Lines	static enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)

switch (hw->phy.link_info.phy_type) {		switch (hw->phy.link_info.phy_type) {
case I40E_PHY_TYPE_10GBASE_SR:		case I40E_PHY_TYPE_10GBASE_SR:
case I40E_PHY_TYPE_10GBASE_LR:		case I40E_PHY_TYPE_10GBASE_LR:
case I40E_PHY_TYPE_1000BASE_SX:		case I40E_PHY_TYPE_1000BASE_SX:
case I40E_PHY_TYPE_1000BASE_LX:		case I40E_PHY_TYPE_1000BASE_LX:
case I40E_PHY_TYPE_40GBASE_SR4:		case I40E_PHY_TYPE_40GBASE_SR4:
case I40E_PHY_TYPE_40GBASE_LR4:		case I40E_PHY_TYPE_40GBASE_LR4:
		case I40E_PHY_TYPE_25GBASE_LR:
		case I40E_PHY_TYPE_25GBASE_SR:
media = I40E_MEDIA_TYPE_FIBER;		media = I40E_MEDIA_TYPE_FIBER;
break;		break;
case I40E_PHY_TYPE_100BASE_TX:		case I40E_PHY_TYPE_100BASE_TX:
case I40E_PHY_TYPE_1000BASE_T:		case I40E_PHY_TYPE_1000BASE_T:
case I40E_PHY_TYPE_10GBASE_T:		case I40E_PHY_TYPE_10GBASE_T:
media = I40E_MEDIA_TYPE_BASET;		media = I40E_MEDIA_TYPE_BASET;
break;		break;
case I40E_PHY_TYPE_10GBASE_CR1_CU:		case I40E_PHY_TYPE_10GBASE_CR1_CU:
case I40E_PHY_TYPE_40GBASE_CR4_CU:		case I40E_PHY_TYPE_40GBASE_CR4_CU:
case I40E_PHY_TYPE_10GBASE_CR1:		case I40E_PHY_TYPE_10GBASE_CR1:
case I40E_PHY_TYPE_40GBASE_CR4:		case I40E_PHY_TYPE_40GBASE_CR4:
case I40E_PHY_TYPE_10GBASE_SFPP_CU:		case I40E_PHY_TYPE_10GBASE_SFPP_CU:
case I40E_PHY_TYPE_40GBASE_AOC:		case I40E_PHY_TYPE_40GBASE_AOC:
case I40E_PHY_TYPE_10GBASE_AOC:		case I40E_PHY_TYPE_10GBASE_AOC:
		case I40E_PHY_TYPE_25GBASE_CR:
media = I40E_MEDIA_TYPE_DA;		media = I40E_MEDIA_TYPE_DA;
break;		break;
case I40E_PHY_TYPE_1000BASE_KX:		case I40E_PHY_TYPE_1000BASE_KX:
case I40E_PHY_TYPE_10GBASE_KX4:		case I40E_PHY_TYPE_10GBASE_KX4:
case I40E_PHY_TYPE_10GBASE_KR:		case I40E_PHY_TYPE_10GBASE_KR:
case I40E_PHY_TYPE_40GBASE_KR4:		case I40E_PHY_TYPE_40GBASE_KR4:
case I40E_PHY_TYPE_20GBASE_KR2:		case I40E_PHY_TYPE_20GBASE_KR2:
		case I40E_PHY_TYPE_25GBASE_KR:
media = I40E_MEDIA_TYPE_BACKPLANE;		media = I40E_MEDIA_TYPE_BACKPLANE;
break;		break;
case I40E_PHY_TYPE_SGMII:		case I40E_PHY_TYPE_SGMII:
case I40E_PHY_TYPE_XAUI:		case I40E_PHY_TYPE_XAUI:
case I40E_PHY_TYPE_XFI:		case I40E_PHY_TYPE_XFI:
case I40E_PHY_TYPE_XLAUI:		case I40E_PHY_TYPE_XLAUI:
case I40E_PHY_TYPE_XLPPI:		case I40E_PHY_TYPE_XLPPI:
default:		default:
▲ Show 20 Lines • Show All 464 Lines • ▼ Show 20 Lines	enum i40e_status_code i40e_set_fc(struct i40e_hw hw, u8 aq_failures,
config.abilities \|= pause_mask;		config.abilities \|= pause_mask;
/* If the abilities have changed, then set the new config */		/* If the abilities have changed, then set the new config */
if (config.abilities != abilities.abilities) {		if (config.abilities != abilities.abilities) {
/* Auto restart link so settings take effect */		/* Auto restart link so settings take effect */
if (atomic_restart)		if (atomic_restart)
config.abilities \|= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;		config.abilities \|= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
/* Copy over all the old settings */		/* Copy over all the old settings */
config.phy_type = abilities.phy_type;		config.phy_type = abilities.phy_type;
		config.phy_type_ext = abilities.phy_type_ext;
config.link_speed = abilities.link_speed;		config.link_speed = abilities.link_speed;
config.eee_capability = abilities.eee_capability;		config.eee_capability = abilities.eee_capability;
config.eeer = abilities.eeer_val;		config.eeer = abilities.eeer_val;
config.low_power_ctrl = abilities.d3_lpan;		config.low_power_ctrl = abilities.d3_lpan;
		config.fec_config = abilities.fec_cfg_curr_mod_ext_info &
		I40E_AQ_PHY_FEC_CONFIG_MASK;
status = i40e_aq_set_phy_config(hw, &config, NULL);		status = i40e_aq_set_phy_config(hw, &config, NULL);

if (status)		if (status)
*aq_failures \|= I40E_SET_FC_AQ_FAIL_SET;		*aq_failures \|= I40E_SET_FC_AQ_FAIL_SET;
}		}
/* Update the link info */		/* Update the link info */
status = i40e_update_link_info(hw);		status = i40e_update_link_info(hw);
if (status) {		if (status) {
▲ Show 20 Lines • Show All 143 Lines • ▼ Show 20 Lines	i40e_memcpy(&hw->phy.link_info_old, hw_link_info,
sizeof(*hw_link_info), I40E_NONDMA_TO_NONDMA);		sizeof(*hw_link_info), I40E_NONDMA_TO_NONDMA);

/* update link status */		/* update link status */
hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;		hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
hw->phy.media_type = i40e_get_media_type(hw);		hw->phy.media_type = i40e_get_media_type(hw);
hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;		hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
hw_link_info->link_info = resp->link_info;		hw_link_info->link_info = resp->link_info;
hw_link_info->an_info = resp->an_info;		hw_link_info->an_info = resp->an_info;
		hw_link_info->fec_info = resp->config & (I40E_AQ_CONFIG_FEC_KR_ENA \|
		I40E_AQ_CONFIG_FEC_RS_ENA);
hw_link_info->ext_info = resp->ext_info;		hw_link_info->ext_info = resp->ext_info;
hw_link_info->loopback = resp->loopback;		hw_link_info->loopback = resp->loopback;
hw_link_info->max_frame_size = LE16_TO_CPU(resp->max_frame_size);		hw_link_info->max_frame_size = LE16_TO_CPU(resp->max_frame_size);
hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;		hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;

/* update fc info */		/* update fc info */
tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);		tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);		rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
if (tx_pause & rx_pause)		if (tx_pause & rx_pause)
hw->fc.current_mode = I40E_FC_FULL;		hw->fc.current_mode = I40E_FC_FULL;
else if (tx_pause)		else if (tx_pause)
hw->fc.current_mode = I40E_FC_TX_PAUSE;		hw->fc.current_mode = I40E_FC_TX_PAUSE;
else if (rx_pause)		else if (rx_pause)
hw->fc.current_mode = I40E_FC_RX_PAUSE;		hw->fc.current_mode = I40E_FC_RX_PAUSE;
else		else
hw->fc.current_mode = I40E_FC_NONE;		hw->fc.current_mode = I40E_FC_NONE;

if (resp->config & I40E_AQ_CONFIG_CRC_ENA)		if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
hw_link_info->crc_enable = TRUE;		hw_link_info->crc_enable = TRUE;
else		else
hw_link_info->crc_enable = FALSE;		hw_link_info->crc_enable = FALSE;

if (resp->command_flags & CPU_TO_LE16(I40E_AQ_LSE_ENABLE))		if (resp->command_flags & CPU_TO_LE16(I40E_AQ_LSE_IS_ENABLED))
hw_link_info->lse_enable = TRUE;		hw_link_info->lse_enable = TRUE;
else		else
hw_link_info->lse_enable = FALSE;		hw_link_info->lse_enable = FALSE;

if ((hw->aq.fw_maj_ver < 4 \|\| (hw->aq.fw_maj_ver == 4 &&		if ((hw->mac.type == I40E_MAC_XL710) &&
		(hw->aq.fw_maj_ver < 4 \|\| (hw->aq.fw_maj_ver == 4 &&
hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)		hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)
hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;		hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;

/* save link status information */		/* save link status information */
if (link)		if (link)
i40e_memcpy(link, hw_link_info, sizeof(*hw_link_info),		i40e_memcpy(link, hw_link_info, sizeof(*hw_link_info),
I40E_NONDMA_TO_NONDMA);		I40E_NONDMA_TO_NONDMA);

▲ Show 20 Lines • Show All 348 Lines • ▼ Show 20 Lines	enum i40e_status_code i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,

cmd->seid = CPU_TO_LE16(seid);		cmd->seid = CPU_TO_LE16(seid);
status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);		status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);

return status;		return status;
}		}

/**		/**
		* i40e_aq_set_vsi_full_promiscuous
		* @hw: pointer to the hw struct
		* @seid: VSI number
		* @set: set promiscuous enable/disable
		* @cmd_details: pointer to command details structure or NULL
		**/
		enum i40e_status_code i40e_aq_set_vsi_full_promiscuous(struct i40e_hw *hw,
		u16 seid, bool set,
		struct i40e_asq_cmd_details *cmd_details)
		{
		struct i40e_aq_desc desc;
		struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
		(struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
		enum i40e_status_code status;
		u16 flags = 0;

		i40e_fill_default_direct_cmd_desc(&desc,
		i40e_aqc_opc_set_vsi_promiscuous_modes);

		if (set)
		flags = I40E_AQC_SET_VSI_PROMISC_UNICAST \|
		I40E_AQC_SET_VSI_PROMISC_MULTICAST \|
		I40E_AQC_SET_VSI_PROMISC_BROADCAST;

		cmd->promiscuous_flags = CPU_TO_LE16(flags);

		cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST \|
		I40E_AQC_SET_VSI_PROMISC_MULTICAST \|
		I40E_AQC_SET_VSI_PROMISC_BROADCAST);

		cmd->seid = CPU_TO_LE16(seid);
		status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);

		return status;
		}

		/**
* i40e_aq_set_vsi_mc_promisc_on_vlan		* i40e_aq_set_vsi_mc_promisc_on_vlan
* @hw: pointer to the hw struct		* @hw: pointer to the hw struct
* @seid: vsi number		* @seid: vsi number
* @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN		* @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
* @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag		* @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag
* @cmd_details: pointer to command details structure or NULL		* @cmd_details: pointer to command details structure or NULL
**/		**/
enum i40e_status_code i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw,		enum i40e_status_code i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw,
▲ Show 20 Lines • Show All 52 Lines • ▼ Show 20 Lines	enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw,
cmd->vlan_tag = CPU_TO_LE16(vid \| I40E_AQC_SET_VSI_VLAN_VALID);		cmd->vlan_tag = CPU_TO_LE16(vid \| I40E_AQC_SET_VSI_VLAN_VALID);

status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);		status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);

return status;		return status;
}		}

/**		/**
		* i40e_aq_set_vsi_bc_promisc_on_vlan
		* @hw: pointer to the hw struct
		* @seid: vsi number
		* @enable: set broadcast promiscuous enable/disable for a given VLAN
		* @vid: The VLAN tag filter - capture any broadcast packet with this VLAN tag
		* @cmd_details: pointer to command details structure or NULL
		**/
		enum i40e_status_code i40e_aq_set_vsi_bc_promisc_on_vlan(struct i40e_hw *hw,
		u16 seid, bool enable, u16 vid,
		struct i40e_asq_cmd_details *cmd_details)
		{
		struct i40e_aq_desc desc;
		struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
		(struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
		enum i40e_status_code status;
		u16 flags = 0;

		i40e_fill_default_direct_cmd_desc(&desc,
		i40e_aqc_opc_set_vsi_promiscuous_modes);

		if (enable)
		flags \|= I40E_AQC_SET_VSI_PROMISC_BROADCAST;

		cmd->promiscuous_flags = CPU_TO_LE16(flags);
		cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
		cmd->seid = CPU_TO_LE16(seid);
		cmd->vlan_tag = CPU_TO_LE16(vid \| I40E_AQC_SET_VSI_VLAN_VALID);

		status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);

		return status;
		}

		/**
* i40e_aq_set_vsi_broadcast		* i40e_aq_set_vsi_broadcast
* @hw: pointer to the hw struct		* @hw: pointer to the hw struct
* @seid: vsi number		* @seid: vsi number
* @set_filter: TRUE to set filter, FALSE to clear filter		* @set_filter: TRUE to set filter, FALSE to clear filter
* @cmd_details: pointer to command details structure or NULL		* @cmd_details: pointer to command details structure or NULL
*		*
* Set or clear the broadcast promiscuous flag (filter) for a given VSI.		* Set or clear the broadcast promiscuous flag (filter) for a given VSI.
**/		**/
▲ Show 20 Lines • Show All 316 Lines • ▼ Show 20 Lines
{		{
struct i40e_aq_get_phy_abilities_resp abilities;		struct i40e_aq_get_phy_abilities_resp abilities;
enum i40e_status_code status = I40E_SUCCESS;		enum i40e_status_code status = I40E_SUCCESS;

status = i40e_aq_get_link_info(hw, TRUE, NULL, NULL);		status = i40e_aq_get_link_info(hw, TRUE, NULL, NULL);
if (status)		if (status)
return status;		return status;

if (hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) {		/* extra checking needed to ensure link info to user is timely */
		if ((hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) &&
		((hw->phy.link_info.link_info & I40E_AQ_LINK_UP) \|\|
		!(hw->phy.link_info_old.link_info & I40E_AQ_LINK_UP))) {
status = i40e_aq_get_phy_capabilities(hw, FALSE, false,		status = i40e_aq_get_phy_capabilities(hw, FALSE, false,
&abilities, NULL);		&abilities, NULL);
if (status)		if (status)
return status;		return status;

memcpy(hw->phy.link_info.module_type, &abilities.module_type,		i40e_memcpy(hw->phy.link_info.module_type, &abilities.module_type,
sizeof(hw->phy.link_info.module_type));		sizeof(hw->phy.link_info.module_type), I40E_NONDMA_TO_NONDMA);
}		}
return status;		return status;
}		}


/**		/**
* i40e_get_link_speed		* i40e_get_link_speed
* @hw: pointer to the hw struct		* @hw: pointer to the hw struct
▲ Show 20 Lines • Show All 833 Lines • ▼ Show 20 Lines	for (i = 0; i < cap_count; i++, cap++) {
case I40E_AQ_CAP_ID_SWITCH_MODE:		case I40E_AQ_CAP_ID_SWITCH_MODE:
p->switch_mode = number;		p->switch_mode = number;
i40e_debug(hw, I40E_DEBUG_INIT,		i40e_debug(hw, I40E_DEBUG_INIT,
"HW Capability: Switch mode = %d\n",		"HW Capability: Switch mode = %d\n",
p->switch_mode);		p->switch_mode);
break;		break;
case I40E_AQ_CAP_ID_MNG_MODE:		case I40E_AQ_CAP_ID_MNG_MODE:
p->management_mode = number;		p->management_mode = number;
		if (major_rev > 1) {
		p->mng_protocols_over_mctp = logical_id;
i40e_debug(hw, I40E_DEBUG_INIT,		i40e_debug(hw, I40E_DEBUG_INIT,
		"HW Capability: Protocols over MCTP = %d\n",
		p->mng_protocols_over_mctp);
		} else {
		p->mng_protocols_over_mctp = 0;
		}
		i40e_debug(hw, I40E_DEBUG_INIT,
"HW Capability: Management Mode = %d\n",		"HW Capability: Management Mode = %d\n",
p->management_mode);		p->management_mode);
break;		break;
case I40E_AQ_CAP_ID_NPAR_ACTIVE:		case I40E_AQ_CAP_ID_NPAR_ACTIVE:
p->npar_enable = number;		p->npar_enable = number;
i40e_debug(hw, I40E_DEBUG_INIT,		i40e_debug(hw, I40E_DEBUG_INIT,
"HW Capability: NPAR enable = %d\n",		"HW Capability: NPAR enable = %d\n",
p->npar_enable);		p->npar_enable);
▲ Show 20 Lines • Show All 211 Lines • ▼ Show 20 Lines	case I40E_AQ_CAP_ID_WOL_AND_PROXY:
hw->num_wol_proxy_filters = (u16)number;		hw->num_wol_proxy_filters = (u16)number;
hw->wol_proxy_vsi_seid = (u16)logical_id;		hw->wol_proxy_vsi_seid = (u16)logical_id;
p->apm_wol_support = phys_id & I40E_WOL_SUPPORT_MASK;		p->apm_wol_support = phys_id & I40E_WOL_SUPPORT_MASK;
if (phys_id & I40E_ACPI_PROGRAMMING_METHOD_MASK)		if (phys_id & I40E_ACPI_PROGRAMMING_METHOD_MASK)
p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_AQC_FPK;		p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_AQC_FPK;
else		else
p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_HW_FVL;		p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_HW_FVL;
p->proxy_support = (phys_id & I40E_PROXY_SUPPORT_MASK) ? 1 : 0;		p->proxy_support = (phys_id & I40E_PROXY_SUPPORT_MASK) ? 1 : 0;
p->proxy_support = p->proxy_support;
i40e_debug(hw, I40E_DEBUG_INIT,		i40e_debug(hw, I40E_DEBUG_INIT,
"HW Capability: WOL proxy filters = %d\n",		"HW Capability: WOL proxy filters = %d\n",
hw->num_wol_proxy_filters);		hw->num_wol_proxy_filters);
break;		break;
default:		default:
break;		break;
}		}
}		}
Show All 24 Lines	while (valid_functions) {
if (valid_functions & 1)		if (valid_functions & 1)
num_functions++;		num_functions++;
valid_functions >>= 1;		valid_functions >>= 1;
}		}

/* partition id is 1-based, and functions are evenly spread		/* partition id is 1-based, and functions are evenly spread
* across the ports as partitions		* across the ports as partitions
*/		*/
		if (hw->num_ports != 0) {
hw->partition_id = (hw->pf_id / hw->num_ports) + 1;		hw->partition_id = (hw->pf_id / hw->num_ports) + 1;
hw->num_partitions = num_functions / hw->num_ports;		hw->num_partitions = num_functions / hw->num_ports;
		}

/* additional HW specific goodies that might		/* additional HW specific goodies that might
* someday be HW version specific		* someday be HW version specific
*/		*/
p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;		p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
}		}

/**		/**
▲ Show 20 Lines • Show All 468 Lines • ▼ Show 20 Lines	enum i40e_status_code i40e_aq_start_stop_dcbx(struct i40e_hw *hw,
status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);		status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);

return status;		return status;
}		}

/**		/**
* i40e_aq_add_udp_tunnel		* i40e_aq_add_udp_tunnel
* @hw: pointer to the hw struct		* @hw: pointer to the hw struct
* @udp_port: the UDP port to add		* @udp_port: the UDP port to add in Host byte order
* @header_len: length of the tunneling header length in DWords		* @header_len: length of the tunneling header length in DWords
* @protocol_index: protocol index type		* @protocol_index: protocol index type
* @filter_index: pointer to filter index		* @filter_index: pointer to filter index
* @cmd_details: pointer to command details structure or NULL		* @cmd_details: pointer to command details structure or NULL
		*
		* Note: Firmware expects the udp_port value to be in Little Endian format,
		* and this function will call CPU_TO_LE16 to convert from Host byte order to
		* Little Endian order.
**/		**/
enum i40e_status_code i40e_aq_add_udp_tunnel(struct i40e_hw *hw,		enum i40e_status_code i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
u16 udp_port, u8 protocol_index,		u16 udp_port, u8 protocol_index,
u8 *filter_index,		u8 *filter_index,
struct i40e_asq_cmd_details *cmd_details)		struct i40e_asq_cmd_details *cmd_details)
{		{
struct i40e_aq_desc desc;		struct i40e_aq_desc desc;
struct i40e_aqc_add_udp_tunnel *cmd =		struct i40e_aqc_add_udp_tunnel *cmd =
▲ Show 20 Lines • Show All 1,592 Lines • ▼ Show 20 Lines	enum i40e_status_code i40e_aq_configure_partition_bw(struct i40e_hw *hw,

i40e_fill_default_direct_cmd_desc(&desc,		i40e_fill_default_direct_cmd_desc(&desc,
i40e_aqc_opc_configure_partition_bw);		i40e_aqc_opc_configure_partition_bw);

/* Indirect command */		/* Indirect command */
desc.flags \|= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);		desc.flags \|= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
desc.flags \|= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);		desc.flags \|= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);

if (bwd_size > I40E_AQ_LARGE_BUF)
desc.flags \|= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);

desc.datalen = CPU_TO_LE16(bwd_size);		desc.datalen = CPU_TO_LE16(bwd_size);

status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, cmd_details);		status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, cmd_details);

return status;		return status;
}		}

/**		/**
* i40e_read_phy_register		* i40e_read_phy_register_clause22
* @hw: pointer to the HW structure		* @hw: pointer to the HW structure
		* @reg: register address in the page
		* @phy_adr: PHY address on MDIO interface
		* @value: PHY register value
		*
		* Reads specified PHY register value
		**/
		enum i40e_status_code i40e_read_phy_register_clause22(struct i40e_hw *hw,
		u16 reg, u8 phy_addr, u16 *value)
		{
		enum i40e_status_code status = I40E_ERR_TIMEOUT;
		u8 port_num = (u8)hw->func_caps.mdio_port_num;
		u32 command = 0;
		u16 retry = 1000;

		command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) \|
		(phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) \|
		(I40E_MDIO_CLAUSE22_OPCODE_READ_MASK) \|
		(I40E_MDIO_CLAUSE22_STCODE_MASK) \|
		(I40E_GLGEN_MSCA_MDICMD_MASK);
		wr32(hw, I40E_GLGEN_MSCA(port_num), command);
		do {
		command = rd32(hw, I40E_GLGEN_MSCA(port_num));
		if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
		status = I40E_SUCCESS;
		break;
		}
		i40e_usec_delay(10);
		retry--;
		} while (retry);

		if (status) {
		i40e_debug(hw, I40E_DEBUG_PHY,
		"PHY: Can't write command to external PHY.\n");
		} else {
		command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
		*value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
		I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
		}

		return status;
		}

		/**
		* i40e_write_phy_register_clause22
		* @hw: pointer to the HW structure
		* @reg: register address in the page
		* @phy_adr: PHY address on MDIO interface
		* @value: PHY register value
		*
		* Writes specified PHY register value
		**/
		enum i40e_status_code i40e_write_phy_register_clause22(struct i40e_hw *hw,
		u16 reg, u8 phy_addr, u16 value)
		{
		enum i40e_status_code status = I40E_ERR_TIMEOUT;
		u8 port_num = (u8)hw->func_caps.mdio_port_num;
		u32 command = 0;
		u16 retry = 1000;

		command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
		wr32(hw, I40E_GLGEN_MSRWD(port_num), command);

		command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) \|
		(phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) \|
		(I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK) \|
		(I40E_MDIO_CLAUSE22_STCODE_MASK) \|
		(I40E_GLGEN_MSCA_MDICMD_MASK);

		wr32(hw, I40E_GLGEN_MSCA(port_num), command);
		do {
		command = rd32(hw, I40E_GLGEN_MSCA(port_num));
		if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
		status = I40E_SUCCESS;
		break;
		}
		i40e_usec_delay(10);
		retry--;
		} while (retry);

		return status;
		}

		/**
		* i40e_read_phy_register_clause45
		* @hw: pointer to the HW structure
* @page: registers page number		* @page: registers page number
* @reg: register address in the page		* @reg: register address in the page
* @phy_adr: PHY address on MDIO interface		* @phy_adr: PHY address on MDIO interface
* @value: PHY register value		* @value: PHY register value
*		*
* Reads specified PHY register value		* Reads specified PHY register value
**/		**/
enum i40e_status_code i40e_read_phy_register(struct i40e_hw *hw,		enum i40e_status_code i40e_read_phy_register_clause45(struct i40e_hw *hw,
u8 page, u16 reg, u8 phy_addr,		u8 page, u16 reg, u8 phy_addr, u16 *value)
u16 *value)
{		{
enum i40e_status_code status = I40E_ERR_TIMEOUT;		enum i40e_status_code status = I40E_ERR_TIMEOUT;
u32 command = 0;		u32 command = 0;
u16 retry = 1000;		u16 retry = 1000;
u8 port_num = (u8)hw->func_caps.mdio_port_num;		u8 port_num = (u8)hw->func_caps.mdio_port_num;

command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) \|		command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) \|
(page << I40E_GLGEN_MSCA_DEVADD_SHIFT) \|		(page << I40E_GLGEN_MSCA_DEVADD_SHIFT) \|
(phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) \|		(phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) \|
(I40E_MDIO_OPCODE_ADDRESS) \|		(I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) \|
(I40E_MDIO_STCODE) \|		(I40E_MDIO_CLAUSE45_STCODE_MASK) \|
(I40E_GLGEN_MSCA_MDICMD_MASK) \|		(I40E_GLGEN_MSCA_MDICMD_MASK) \|
(I40E_GLGEN_MSCA_MDIINPROGEN_MASK);		(I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
wr32(hw, I40E_GLGEN_MSCA(port_num), command);		wr32(hw, I40E_GLGEN_MSCA(port_num), command);
do {		do {
command = rd32(hw, I40E_GLGEN_MSCA(port_num));		command = rd32(hw, I40E_GLGEN_MSCA(port_num));
if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {		if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
status = I40E_SUCCESS;		status = I40E_SUCCESS;
break;		break;
}		}
i40e_usec_delay(10);		i40e_usec_delay(10);
retry--;		retry--;
} while (retry);		} while (retry);

if (status) {		if (status) {
i40e_debug(hw, I40E_DEBUG_PHY,		i40e_debug(hw, I40E_DEBUG_PHY,
"PHY: Can't write command to external PHY.\n");		"PHY: Can't write command to external PHY.\n");
goto phy_read_end;		goto phy_read_end;
}		}

command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) \|		command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) \|
(phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) \|		(phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) \|
(I40E_MDIO_OPCODE_READ) \|		(I40E_MDIO_CLAUSE45_OPCODE_READ_MASK) \|
(I40E_MDIO_STCODE) \|		(I40E_MDIO_CLAUSE45_STCODE_MASK) \|
(I40E_GLGEN_MSCA_MDICMD_MASK) \|		(I40E_GLGEN_MSCA_MDICMD_MASK) \|
(I40E_GLGEN_MSCA_MDIINPROGEN_MASK);		(I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
status = I40E_ERR_TIMEOUT;		status = I40E_ERR_TIMEOUT;
retry = 1000;		retry = 1000;
wr32(hw, I40E_GLGEN_MSCA(port_num), command);		wr32(hw, I40E_GLGEN_MSCA(port_num), command);
do {		do {
command = rd32(hw, I40E_GLGEN_MSCA(port_num));		command = rd32(hw, I40E_GLGEN_MSCA(port_num));
if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {		if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
Show All 13 Lines	i40e_debug(hw, I40E_DEBUG_PHY,
"PHY: Can't read register value from external PHY.\n");		"PHY: Can't read register value from external PHY.\n");
}		}

phy_read_end:		phy_read_end:
return status;		return status;
}		}

/**		/**
* i40e_write_phy_register		* i40e_write_phy_register_clause45
* @hw: pointer to the HW structure		* @hw: pointer to the HW structure
* @page: registers page number		* @page: registers page number
* @reg: register address in the page		* @reg: register address in the page
* @phy_adr: PHY address on MDIO interface		* @phy_adr: PHY address on MDIO interface
* @value: PHY register value		* @value: PHY register value
*		*
* Writes value to specified PHY register		* Writes value to specified PHY register
**/		**/
enum i40e_status_code i40e_write_phy_register(struct i40e_hw *hw,		enum i40e_status_code i40e_write_phy_register_clause45(struct i40e_hw *hw,
u8 page, u16 reg, u8 phy_addr,		u8 page, u16 reg, u8 phy_addr, u16 value)
u16 value)
{		{
enum i40e_status_code status = I40E_ERR_TIMEOUT;		enum i40e_status_code status = I40E_ERR_TIMEOUT;
u32 command = 0;		u32 command = 0;
u16 retry = 1000;		u16 retry = 1000;
u8 port_num = (u8)hw->func_caps.mdio_port_num;		u8 port_num = (u8)hw->func_caps.mdio_port_num;

command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) \|		command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) \|
(page << I40E_GLGEN_MSCA_DEVADD_SHIFT) \|		(page << I40E_GLGEN_MSCA_DEVADD_SHIFT) \|
(phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) \|		(phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) \|
(I40E_MDIO_OPCODE_ADDRESS) \|		(I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) \|
(I40E_MDIO_STCODE) \|		(I40E_MDIO_CLAUSE45_STCODE_MASK) \|
(I40E_GLGEN_MSCA_MDICMD_MASK) \|		(I40E_GLGEN_MSCA_MDICMD_MASK) \|
(I40E_GLGEN_MSCA_MDIINPROGEN_MASK);		(I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
wr32(hw, I40E_GLGEN_MSCA(port_num), command);		wr32(hw, I40E_GLGEN_MSCA(port_num), command);
do {		do {
command = rd32(hw, I40E_GLGEN_MSCA(port_num));		command = rd32(hw, I40E_GLGEN_MSCA(port_num));
if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {		if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
status = I40E_SUCCESS;		status = I40E_SUCCESS;
break;		break;
}		}
i40e_usec_delay(10);		i40e_usec_delay(10);
retry--;		retry--;
} while (retry);		} while (retry);
if (status) {		if (status) {
i40e_debug(hw, I40E_DEBUG_PHY,		i40e_debug(hw, I40E_DEBUG_PHY,
"PHY: Can't write command to external PHY.\n");		"PHY: Can't write command to external PHY.\n");
goto phy_write_end;		goto phy_write_end;
}		}

command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;		command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
wr32(hw, I40E_GLGEN_MSRWD(port_num), command);		wr32(hw, I40E_GLGEN_MSRWD(port_num), command);

command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) \|		command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) \|
(phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) \|		(phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) \|
(I40E_MDIO_OPCODE_WRITE) \|		(I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK) \|
(I40E_MDIO_STCODE) \|		(I40E_MDIO_CLAUSE45_STCODE_MASK) \|
(I40E_GLGEN_MSCA_MDICMD_MASK) \|		(I40E_GLGEN_MSCA_MDICMD_MASK) \|
(I40E_GLGEN_MSCA_MDIINPROGEN_MASK);		(I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
status = I40E_ERR_TIMEOUT;		status = I40E_ERR_TIMEOUT;
retry = 1000;		retry = 1000;
wr32(hw, I40E_GLGEN_MSCA(port_num), command);		wr32(hw, I40E_GLGEN_MSCA(port_num), command);
do {		do {
command = rd32(hw, I40E_GLGEN_MSCA(port_num));		command = rd32(hw, I40E_GLGEN_MSCA(port_num));
if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {		if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
status = I40E_SUCCESS;		status = I40E_SUCCESS;
break;		break;
}		}
i40e_usec_delay(10);		i40e_usec_delay(10);
retry--;		retry--;
} while (retry);		} while (retry);

phy_write_end:		phy_write_end:
return status;		return status;
}		}

/**		/**
		* i40e_write_phy_register
		* @hw: pointer to the HW structure
		* @page: registers page number
		* @reg: register address in the page
		* @phy_adr: PHY address on MDIO interface
		* @value: PHY register value
		*
		* Writes value to specified PHY register
		**/
		enum i40e_status_code i40e_write_phy_register(struct i40e_hw *hw,
		u8 page, u16 reg, u8 phy_addr, u16 value)
		{
		enum i40e_status_code status;

		switch (hw->device_id) {
		case I40E_DEV_ID_1G_BASE_T_X722:
		status = i40e_write_phy_register_clause22(hw,
		reg, phy_addr, value);
		break;
		case I40E_DEV_ID_10G_BASE_T:
		case I40E_DEV_ID_10G_BASE_T4:
		case I40E_DEV_ID_10G_BASE_T_X722:
		case I40E_DEV_ID_25G_B:
		case I40E_DEV_ID_25G_SFP28:
		status = i40e_write_phy_register_clause45(hw,
		page, reg, phy_addr, value);
		break;
		default:
		status = I40E_ERR_UNKNOWN_PHY;
		break;
		}

		return status;
		}

		/**
		* i40e_read_phy_register
		* @hw: pointer to the HW structure
		* @page: registers page number
		* @reg: register address in the page
		* @phy_adr: PHY address on MDIO interface
		* @value: PHY register value
		*
		* Reads specified PHY register value
		**/
		enum i40e_status_code i40e_read_phy_register(struct i40e_hw *hw,
		u8 page, u16 reg, u8 phy_addr, u16 *value)
		{
		enum i40e_status_code status;

		switch (hw->device_id) {
		case I40E_DEV_ID_1G_BASE_T_X722:
		status = i40e_read_phy_register_clause22(hw, reg, phy_addr,
		value);
		break;
		case I40E_DEV_ID_10G_BASE_T:
		case I40E_DEV_ID_10G_BASE_T4:
		case I40E_DEV_ID_10G_BASE_T_X722:
		case I40E_DEV_ID_25G_B:
		case I40E_DEV_ID_25G_SFP28:
		status = i40e_read_phy_register_clause45(hw, page, reg,
		phy_addr, value);
		break;
		default:
		status = I40E_ERR_UNKNOWN_PHY;
		break;
		}

		return status;
		}

		/**
* i40e_get_phy_address		* i40e_get_phy_address
* @hw: pointer to the HW structure		* @hw: pointer to the HW structure
* @dev_num: PHY port num that address we want		* @dev_num: PHY port num that address we want
* @phy_addr: Returned PHY address		* @phy_addr: Returned PHY address
*		*
* Gets PHY address for current port		* Gets PHY address for current port
**/		**/
u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num)		u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num)
Show All 25 Lines	enum i40e_status_code i40e_blink_phy_link_led(struct i40e_hw *hw,
u8 port_num;		u8 port_num;

i = rd32(hw, I40E_PFGEN_PORTNUM);		i = rd32(hw, I40E_PFGEN_PORTNUM);
port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);		port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
phy_addr = i40e_get_phy_address(hw, port_num);		phy_addr = i40e_get_phy_address(hw, port_num);

for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,		for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
led_addr++) {		led_addr++) {
status = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE,		status = i40e_read_phy_register_clause45(hw,
led_addr, phy_addr, &led_reg);		I40E_PHY_COM_REG_PAGE,
		led_addr, phy_addr,
		&led_reg);
if (status)		if (status)
goto phy_blinking_end;		goto phy_blinking_end;
led_ctl = led_reg;		led_ctl = led_reg;
if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {		if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
led_reg = 0;		led_reg = 0;
status = i40e_write_phy_register(hw,		status = i40e_write_phy_register_clause45(hw,
I40E_PHY_COM_REG_PAGE,		I40E_PHY_COM_REG_PAGE,
led_addr, phy_addr,		led_addr, phy_addr,
led_reg);		led_reg);
if (status)		if (status)
goto phy_blinking_end;		goto phy_blinking_end;
break;		break;
}		}
}		}

if (time > 0 && interval > 0) {		if (time > 0 && interval > 0) {
for (i = 0; i < time * 1000; i += interval) {		for (i = 0; i < time * 1000; i += interval) {
status = i40e_read_phy_register(hw,		status = i40e_read_phy_register_clause45(hw,
I40E_PHY_COM_REG_PAGE,		I40E_PHY_COM_REG_PAGE,
led_addr, phy_addr,		led_addr, phy_addr, &led_reg);
&led_reg);
if (status)		if (status)
goto restore_config;		goto restore_config;
if (led_reg & I40E_PHY_LED_MANUAL_ON)		if (led_reg & I40E_PHY_LED_MANUAL_ON)
led_reg = 0;		led_reg = 0;
else		else
led_reg = I40E_PHY_LED_MANUAL_ON;		led_reg = I40E_PHY_LED_MANUAL_ON;
status = i40e_write_phy_register(hw,		status = i40e_write_phy_register_clause45(hw,
I40E_PHY_COM_REG_PAGE,		I40E_PHY_COM_REG_PAGE,
led_addr, phy_addr,		led_addr, phy_addr, led_reg);
led_reg);
if (status)		if (status)
goto restore_config;		goto restore_config;
i40e_msec_delay(interval);		i40e_msec_delay(interval);
}		}
}		}

restore_config:		restore_config:
status = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE, led_addr,		status = i40e_write_phy_register_clause45(hw,
phy_addr, led_ctl);		I40E_PHY_COM_REG_PAGE,
		led_addr, phy_addr, led_ctl);

phy_blinking_end:		phy_blinking_end:
return status;		return status;
}		}

/**		/**
* i40e_led_get_phy - return current on/off mode		* i40e_led_get_phy - return current on/off mode
* @hw: pointer to the hw struct		* @hw: pointer to the hw struct
Show All 14 Lines	enum i40e_status_code i40e_led_get_phy(struct i40e_hw hw, u16 led_addr,

temp_addr = I40E_PHY_LED_PROV_REG_1;		temp_addr = I40E_PHY_LED_PROV_REG_1;
i = rd32(hw, I40E_PFGEN_PORTNUM);		i = rd32(hw, I40E_PFGEN_PORTNUM);
port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);		port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
phy_addr = i40e_get_phy_address(hw, port_num);		phy_addr = i40e_get_phy_address(hw, port_num);

for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,		for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
temp_addr++) {		temp_addr++) {
status = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE,		status = i40e_read_phy_register_clause45(hw,
temp_addr, phy_addr, &reg_val);		I40E_PHY_COM_REG_PAGE,
		temp_addr, phy_addr,
		&reg_val);
if (status)		if (status)
return status;		return status;
*val = reg_val;		*val = reg_val;
if (reg_val & I40E_PHY_LED_LINK_MODE_MASK) {		if (reg_val & I40E_PHY_LED_LINK_MODE_MASK) {
*led_addr = temp_addr;		*led_addr = temp_addr;
break;		break;
}		}
}		}
Show All 16 Lines	enum i40e_status_code i40e_led_set_phy(struct i40e_hw *hw, bool on,
u16 led_reg = 0;		u16 led_reg = 0;
u8 phy_addr = 0;		u8 phy_addr = 0;
u8 port_num;		u8 port_num;
u32 i;		u32 i;

i = rd32(hw, I40E_PFGEN_PORTNUM);		i = rd32(hw, I40E_PFGEN_PORTNUM);
port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);		port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
phy_addr = i40e_get_phy_address(hw, port_num);		phy_addr = i40e_get_phy_address(hw, port_num);
		status = i40e_read_phy_register_clause45(hw, I40E_PHY_COM_REG_PAGE,
status = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE, led_addr,		led_addr, phy_addr, &led_reg);
phy_addr, &led_reg);
if (status)		if (status)
return status;		return status;
led_ctl = led_reg;		led_ctl = led_reg;
if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {		if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
led_reg = 0;		led_reg = 0;
status = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE,		status = i40e_write_phy_register_clause45(hw,
led_addr, phy_addr, led_reg);		I40E_PHY_COM_REG_PAGE,
		led_addr, phy_addr,
		led_reg);
if (status)		if (status)
return status;		return status;
}		}
status = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE,		status = i40e_read_phy_register_clause45(hw, I40E_PHY_COM_REG_PAGE,
led_addr, phy_addr, &led_reg);		led_addr, phy_addr, &led_reg);
if (status)		if (status)
goto restore_config;		goto restore_config;
if (on)		if (on)
led_reg = I40E_PHY_LED_MANUAL_ON;		led_reg = I40E_PHY_LED_MANUAL_ON;
else		else
led_reg = 0;		led_reg = 0;
status = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE,		status = i40e_write_phy_register_clause45(hw, I40E_PHY_COM_REG_PAGE,
led_addr, phy_addr, led_reg);		led_addr, phy_addr, led_reg);
if (status)		if (status)
goto restore_config;		goto restore_config;
if (mode & I40E_PHY_LED_MODE_ORIG) {		if (mode & I40E_PHY_LED_MODE_ORIG) {
led_ctl = (mode & I40E_PHY_LED_MODE_MASK);		led_ctl = (mode & I40E_PHY_LED_MODE_MASK);
status = i40e_write_phy_register(hw,		status = i40e_write_phy_register_clause45(hw,
I40E_PHY_COM_REG_PAGE,		I40E_PHY_COM_REG_PAGE,
led_addr, phy_addr, led_ctl);		led_addr, phy_addr, led_ctl);
}		}
return status;		return status;
restore_config:		restore_config:
status = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE, led_addr,		status = i40e_write_phy_register_clause45(hw, I40E_PHY_COM_REG_PAGE,
phy_addr, led_ctl);		led_addr, phy_addr, led_ctl);
return status;		return status;
}		}

/**		/**
* i40e_aq_rx_ctl_read_register - use FW to read from an Rx control register		* i40e_aq_rx_ctl_read_register - use FW to read from an Rx control register
* @hw: pointer to the hw struct		* @hw: pointer to the hw struct
* @reg_addr: register address		* @reg_addr: register address
* @reg_val: ptr to register value		* @reg_val: ptr to register value
▲ Show 20 Lines • Show All 228 Lines • ▼ Show 20 Lines	enum i40e_status_code i40e_aq_set_arp_proxy_config(struct i40e_hw *hw,
struct i40e_aq_desc desc;		struct i40e_aq_desc desc;
enum i40e_status_code status;		enum i40e_status_code status;

if (!proxy_config)		if (!proxy_config)
return I40E_ERR_PARAM;		return I40E_ERR_PARAM;

i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_proxy_config);		i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_proxy_config);

		desc.flags \|= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
		desc.flags \|= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
desc.params.external.addr_high =		desc.params.external.addr_high =
CPU_TO_LE32(I40E_HI_DWORD((u64)proxy_config));		CPU_TO_LE32(I40E_HI_DWORD((u64)proxy_config));
desc.params.external.addr_low =		desc.params.external.addr_low =
CPU_TO_LE32(I40E_LO_DWORD((u64)proxy_config));		CPU_TO_LE32(I40E_LO_DWORD((u64)proxy_config));
		desc.datalen = CPU_TO_LE16(sizeof(struct i40e_aqc_arp_proxy_data));

status = i40e_asq_send_command(hw, &desc, proxy_config,		status = i40e_asq_send_command(hw, &desc, proxy_config,
sizeof(struct i40e_aqc_arp_proxy_data),		sizeof(struct i40e_aqc_arp_proxy_data),
cmd_details);		cmd_details);

return status;		return status;
}		}

Show All 14 Lines	enum i40e_status_code i40e_aq_set_ns_proxy_table_entry(struct i40e_hw *hw,
enum i40e_status_code status;		enum i40e_status_code status;

if (!ns_proxy_table_entry)		if (!ns_proxy_table_entry)
return I40E_ERR_PARAM;		return I40E_ERR_PARAM;

i40e_fill_default_direct_cmd_desc(&desc,		i40e_fill_default_direct_cmd_desc(&desc,
i40e_aqc_opc_set_ns_proxy_table_entry);		i40e_aqc_opc_set_ns_proxy_table_entry);

		desc.flags \|= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
		desc.flags \|= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
desc.params.external.addr_high =		desc.params.external.addr_high =
CPU_TO_LE32(I40E_HI_DWORD((u64)ns_proxy_table_entry));		CPU_TO_LE32(I40E_HI_DWORD((u64)ns_proxy_table_entry));
desc.params.external.addr_low =		desc.params.external.addr_low =
CPU_TO_LE32(I40E_LO_DWORD((u64)ns_proxy_table_entry));		CPU_TO_LE32(I40E_LO_DWORD((u64)ns_proxy_table_entry));
		desc.datalen = CPU_TO_LE16(sizeof(struct i40e_aqc_ns_proxy_data));

status = i40e_asq_send_command(hw, &desc, ns_proxy_table_entry,		status = i40e_asq_send_command(hw, &desc, ns_proxy_table_entry,
sizeof(struct i40e_aqc_ns_proxy_data),		sizeof(struct i40e_aqc_ns_proxy_data),
cmd_details);		cmd_details);

return status;		return status;
}		}

Show All 30 Lines	enum i40e_status_code i40e_aq_set_clear_wol_filter(struct i40e_hw *hw,

if (filter_index >= I40E_AQC_MAX_NUM_WOL_FILTERS)		if (filter_index >= I40E_AQC_MAX_NUM_WOL_FILTERS)
return I40E_ERR_PARAM;		return I40E_ERR_PARAM;
cmd->filter_index = CPU_TO_LE16(filter_index);		cmd->filter_index = CPU_TO_LE16(filter_index);

if (set_filter) {		if (set_filter) {
if (!filter)		if (!filter)
return I40E_ERR_PARAM;		return I40E_ERR_PARAM;

cmd_flags \|= I40E_AQC_SET_WOL_FILTER;		cmd_flags \|= I40E_AQC_SET_WOL_FILTER;
buff_len = sizeof(*filter);		cmd_flags \|= I40E_AQC_SET_WOL_FILTER_WOL_PRESERVE_ON_PFR;
}		}

if (no_wol_tco)		if (no_wol_tco)
cmd_flags \|= I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL;		cmd_flags \|= I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL;
cmd->cmd_flags = CPU_TO_LE16(cmd_flags);		cmd->cmd_flags = CPU_TO_LE16(cmd_flags);

if (filter_valid)		if (filter_valid)
valid_flags \|= I40E_AQC_SET_WOL_FILTER_ACTION_VALID;		valid_flags \|= I40E_AQC_SET_WOL_FILTER_ACTION_VALID;
if (no_wol_tco_valid)		if (no_wol_tco_valid)
valid_flags \|= I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID;		valid_flags \|= I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID;
cmd->valid_flags = CPU_TO_LE16(valid_flags);		cmd->valid_flags = CPU_TO_LE16(valid_flags);

		buff_len = sizeof(*filter);
		desc.datalen = CPU_TO_LE16(buff_len);

		desc.flags \|= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
		desc.flags \|= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);

cmd->address_high = CPU_TO_LE32(I40E_HI_DWORD((u64)filter));		cmd->address_high = CPU_TO_LE32(I40E_HI_DWORD((u64)filter));
cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((u64)filter));		cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((u64)filter));

status = i40e_asq_send_command(hw, &desc, filter,		status = i40e_asq_send_command(hw, &desc, filter,
buff_len, cmd_details);		buff_len, cmd_details);

return status;		return status;
}		}
Show All 16 Lines	enum i40e_status_code i40e_aq_get_wake_event_reason(struct i40e_hw *hw,
enum i40e_status_code status;		enum i40e_status_code status;

i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_wake_reason);		i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_wake_reason);

status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);		status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);

if (status == I40E_SUCCESS)		if (status == I40E_SUCCESS)
*wake_reason = LE16_TO_CPU(resp->wake_reason);		*wake_reason = LE16_TO_CPU(resp->wake_reason);

		return status;
		}

		/**
		* i40e_aq_clear_all_wol_filters
		* @hw: pointer to the hw struct
		* @cmd_details: pointer to command details structure or NULL
		*
		* Get information for the reason of a Wake Up event
		**/
		enum i40e_status_code i40e_aq_clear_all_wol_filters(struct i40e_hw *hw,
		struct i40e_asq_cmd_details *cmd_details)
		{
		struct i40e_aq_desc desc;
		enum i40e_status_code status;

		i40e_fill_default_direct_cmd_desc(&desc,
		i40e_aqc_opc_clear_all_wol_filters);

		status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);

return status;		return status;
}		}