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sys/dev/ixl/ixl_pf_iov.c
Show All 36 Lines | |||||
/* Private functions */ | /* Private functions */ | ||||
static void ixl_vf_map_vsi_queue(struct i40e_hw *hw, struct ixl_vf *vf, int qnum, uint32_t val); | static void ixl_vf_map_vsi_queue(struct i40e_hw *hw, struct ixl_vf *vf, int qnum, uint32_t val); | ||||
static void ixl_vf_disable_queue_intr(struct i40e_hw *hw, uint32_t vfint_reg); | static void ixl_vf_disable_queue_intr(struct i40e_hw *hw, uint32_t vfint_reg); | ||||
static void ixl_vf_unregister_intr(struct i40e_hw *hw, uint32_t vpint_reg); | static void ixl_vf_unregister_intr(struct i40e_hw *hw, uint32_t vpint_reg); | ||||
static bool ixl_zero_mac(const uint8_t *addr); | static bool ixl_zero_mac(const uint8_t *addr); | ||||
static bool ixl_bcast_mac(const uint8_t *addr); | static bool ixl_bcast_mac(const uint8_t *addr); | ||||
static const char * ixl_vc_opcode_str(uint16_t op); | |||||
static int ixl_vc_opcode_level(uint16_t opcode); | static int ixl_vc_opcode_level(uint16_t opcode); | ||||
static int ixl_vf_mac_valid(struct ixl_vf *vf, const uint8_t *addr); | static int ixl_vf_mac_valid(struct ixl_vf *vf, const uint8_t *addr); | ||||
static int ixl_vf_alloc_vsi(struct ixl_pf *pf, struct ixl_vf *vf); | static int ixl_vf_alloc_vsi(struct ixl_pf *pf, struct ixl_vf *vf); | ||||
static int ixl_vf_setup_vsi(struct ixl_pf *pf, struct ixl_vf *vf); | static int ixl_vf_setup_vsi(struct ixl_pf *pf, struct ixl_vf *vf); | ||||
static void ixl_vf_map_queues(struct ixl_pf *pf, struct ixl_vf *vf); | static void ixl_vf_map_queues(struct ixl_pf *pf, struct ixl_vf *vf); | ||||
static void ixl_vf_vsi_release(struct ixl_pf *pf, struct ixl_vsi *vsi); | static void ixl_vf_vsi_release(struct ixl_pf *pf, struct ixl_vsi *vsi); | ||||
▲ Show 20 Lines • Show All 362 Lines • ▼ Show 20 Lines | ixl_reinit_vf(struct ixl_pf *pf, struct ixl_vf *vf) | ||||
ixl_vf_release_resources(pf, vf); | ixl_vf_release_resources(pf, vf); | ||||
ixl_vf_setup_vsi(pf, vf); | ixl_vf_setup_vsi(pf, vf); | ||||
ixl_vf_map_queues(pf, vf); | ixl_vf_map_queues(pf, vf); | ||||
wr32(hw, I40E_VFGEN_RSTAT1(vf->vf_num), I40E_VFR_VFACTIVE); | wr32(hw, I40E_VFGEN_RSTAT1(vf->vf_num), I40E_VFR_VFACTIVE); | ||||
ixl_flush(hw); | ixl_flush(hw); | ||||
} | } | ||||
static const char * | |||||
ixl_vc_opcode_str(uint16_t op) | |||||
{ | |||||
switch (op) { | |||||
case I40E_VIRTCHNL_OP_VERSION: | |||||
return ("VERSION"); | |||||
case I40E_VIRTCHNL_OP_RESET_VF: | |||||
return ("RESET_VF"); | |||||
case I40E_VIRTCHNL_OP_GET_VF_RESOURCES: | |||||
return ("GET_VF_RESOURCES"); | |||||
case I40E_VIRTCHNL_OP_CONFIG_TX_QUEUE: | |||||
return ("CONFIG_TX_QUEUE"); | |||||
case I40E_VIRTCHNL_OP_CONFIG_RX_QUEUE: | |||||
return ("CONFIG_RX_QUEUE"); | |||||
case I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES: | |||||
return ("CONFIG_VSI_QUEUES"); | |||||
case I40E_VIRTCHNL_OP_CONFIG_IRQ_MAP: | |||||
return ("CONFIG_IRQ_MAP"); | |||||
case I40E_VIRTCHNL_OP_ENABLE_QUEUES: | |||||
return ("ENABLE_QUEUES"); | |||||
case I40E_VIRTCHNL_OP_DISABLE_QUEUES: | |||||
return ("DISABLE_QUEUES"); | |||||
case I40E_VIRTCHNL_OP_ADD_ETHER_ADDRESS: | |||||
return ("ADD_ETHER_ADDRESS"); | |||||
case I40E_VIRTCHNL_OP_DEL_ETHER_ADDRESS: | |||||
return ("DEL_ETHER_ADDRESS"); | |||||
case I40E_VIRTCHNL_OP_ADD_VLAN: | |||||
return ("ADD_VLAN"); | |||||
case I40E_VIRTCHNL_OP_DEL_VLAN: | |||||
return ("DEL_VLAN"); | |||||
case I40E_VIRTCHNL_OP_CONFIG_PROMISCUOUS_MODE: | |||||
return ("CONFIG_PROMISCUOUS_MODE"); | |||||
case I40E_VIRTCHNL_OP_GET_STATS: | |||||
return ("GET_STATS"); | |||||
case I40E_VIRTCHNL_OP_FCOE: | |||||
return ("FCOE"); | |||||
case I40E_VIRTCHNL_OP_EVENT: | |||||
return ("EVENT"); | |||||
case I40E_VIRTCHNL_OP_CONFIG_RSS_KEY: | |||||
return ("CONFIG_RSS_KEY"); | |||||
case I40E_VIRTCHNL_OP_CONFIG_RSS_LUT: | |||||
return ("CONFIG_RSS_LUT"); | |||||
case I40E_VIRTCHNL_OP_GET_RSS_HENA_CAPS: | |||||
return ("GET_RSS_HENA_CAPS"); | |||||
case I40E_VIRTCHNL_OP_SET_RSS_HENA: | |||||
return ("SET_RSS_HENA"); | |||||
default: | |||||
return ("UNKNOWN"); | |||||
} | |||||
} | |||||
static int | static int | ||||
ixl_vc_opcode_level(uint16_t opcode) | ixl_vc_opcode_level(uint16_t opcode) | ||||
{ | { | ||||
switch (opcode) { | switch (opcode) { | ||||
case I40E_VIRTCHNL_OP_GET_STATS: | case I40E_VIRTCHNL_OP_GET_STATS: | ||||
return (10); | return (10); | ||||
default: | default: | ||||
return (5); | return (5); | ||||
▲ Show 20 Lines • Show All 970 Lines • ▼ Show 20 Lines | if (status) { | ||||
device_printf(pf->dev, "i40e_aq_set_rss_key status %s, error %s\n", | device_printf(pf->dev, "i40e_aq_set_rss_key status %s, error %s\n", | ||||
i40e_stat_str(hw, status), i40e_aq_str(hw, hw->aq.asq_last_status)); | i40e_stat_str(hw, status), i40e_aq_str(hw, hw->aq.asq_last_status)); | ||||
i40e_send_vf_nack(pf, vf, I40E_VIRTCHNL_OP_CONFIG_RSS_KEY, | i40e_send_vf_nack(pf, vf, I40E_VIRTCHNL_OP_CONFIG_RSS_KEY, | ||||
I40E_ERR_ADMIN_QUEUE_ERROR); | I40E_ERR_ADMIN_QUEUE_ERROR); | ||||
return; | return; | ||||
} | } | ||||
} else { | } else { | ||||
for (int i = 0; i < (key->key_len / 4); i++) | for (int i = 0; i < (key->key_len / 4); i++) | ||||
i40e_write_rx_ctl(hw, I40E_VFQF_HKEY1(i, vf->vf_num), ((u32 *)key->key)[i]); | i40e_write_rx_ctl(hw, I40E_VFQF_HKEY1(i, IXL_GLOBAL_VF_NUM(hw, vf)), ((u32 *)key->key)[i]); | ||||
} | } | ||||
DDPRINTF(pf->dev, "VF %d: Programmed key starting with 0x%x ok!", | DDPRINTF(pf->dev, "VF %d: Programmed key starting with 0x%x ok!", | ||||
vf->vf_num, key->key[0]); | vf->vf_num, key->key[0]); | ||||
ixl_send_vf_ack(pf, vf, I40E_VIRTCHNL_OP_CONFIG_RSS_KEY); | ixl_send_vf_ack(pf, vf, I40E_VIRTCHNL_OP_CONFIG_RSS_KEY); | ||||
} | } | ||||
Show All 38 Lines | if (status) { | ||||
device_printf(pf->dev, "i40e_aq_set_rss_lut status %s, error %s\n", | device_printf(pf->dev, "i40e_aq_set_rss_lut status %s, error %s\n", | ||||
i40e_stat_str(hw, status), i40e_aq_str(hw, hw->aq.asq_last_status)); | i40e_stat_str(hw, status), i40e_aq_str(hw, hw->aq.asq_last_status)); | ||||
i40e_send_vf_nack(pf, vf, I40E_VIRTCHNL_OP_CONFIG_RSS_LUT, | i40e_send_vf_nack(pf, vf, I40E_VIRTCHNL_OP_CONFIG_RSS_LUT, | ||||
I40E_ERR_ADMIN_QUEUE_ERROR); | I40E_ERR_ADMIN_QUEUE_ERROR); | ||||
return; | return; | ||||
} | } | ||||
} else { | } else { | ||||
for (int i = 0; i < (lut->lut_entries / 4); i++) | for (int i = 0; i < (lut->lut_entries / 4); i++) | ||||
i40e_write_rx_ctl(hw, I40E_VFQF_HLUT1(i, vf->vf_num), ((u32 *)lut->lut)[i]); | i40e_write_rx_ctl(hw, I40E_VFQF_HLUT1(i, IXL_GLOBAL_VF_NUM(hw, vf)), ((u32 *)lut->lut)[i]); | ||||
} | } | ||||
DDPRINTF(pf->dev, "VF %d: Programmed LUT starting with 0x%x and length %d ok!", | DDPRINTF(pf->dev, "VF %d: Programmed LUT starting with 0x%x and length %d ok!", | ||||
vf->vf_num, lut->lut[0], lut->lut_entries); | vf->vf_num, lut->lut[0], lut->lut_entries); | ||||
ixl_send_vf_ack(pf, vf, I40E_VIRTCHNL_OP_CONFIG_RSS_LUT); | ixl_send_vf_ack(pf, vf, I40E_VIRTCHNL_OP_CONFIG_RSS_LUT); | ||||
} | } | ||||
Show All 10 Lines | if (msg_size < sizeof(*hena)) { | ||||
i40e_send_vf_nack(pf, vf, I40E_VIRTCHNL_OP_SET_RSS_HENA, | i40e_send_vf_nack(pf, vf, I40E_VIRTCHNL_OP_SET_RSS_HENA, | ||||
I40E_ERR_PARAM); | I40E_ERR_PARAM); | ||||
return; | return; | ||||
} | } | ||||
hena = msg; | hena = msg; | ||||
/* Set HENA */ | /* Set HENA */ | ||||
i40e_write_rx_ctl(hw, I40E_VFQF_HENA1(0, vf->vf_num), (u32)hena->hena); | i40e_write_rx_ctl(hw, I40E_VFQF_HENA1(0, IXL_GLOBAL_VF_NUM(hw, vf)), (u32)hena->hena); | ||||
i40e_write_rx_ctl(hw, I40E_VFQF_HENA1(1, vf->vf_num), (u32)(hena->hena >> 32)); | i40e_write_rx_ctl(hw, I40E_VFQF_HENA1(1, IXL_GLOBAL_VF_NUM(hw, vf)), (u32)(hena->hena >> 32)); | ||||
DDPRINTF(pf->dev, "VF %d: Programmed HENA with 0x%016lx", | DDPRINTF(pf->dev, "VF %d: Programmed HENA with 0x%016lx", | ||||
vf->vf_num, hena->hena); | vf->vf_num, hena->hena); | ||||
ixl_send_vf_ack(pf, vf, I40E_VIRTCHNL_OP_SET_RSS_HENA); | ixl_send_vf_ack(pf, vf, I40E_VIRTCHNL_OP_SET_RSS_HENA); | ||||
} | } | ||||
void | void | ||||
▲ Show 20 Lines • Show All 209 Lines • ▼ Show 20 Lines | ret = i40e_aq_add_veb(hw, pf_vsi->uplink_seid, pf_vsi->seid, | ||||
1, FALSE, &pf->veb_seid, FALSE, NULL); | 1, FALSE, &pf->veb_seid, FALSE, NULL); | ||||
if (ret != I40E_SUCCESS) { | if (ret != I40E_SUCCESS) { | ||||
error = ixl_adminq_err_to_errno(hw->aq.asq_last_status); | error = ixl_adminq_err_to_errno(hw->aq.asq_last_status); | ||||
device_printf(dev, "add_veb failed; code=%d error=%d", ret, | device_printf(dev, "add_veb failed; code=%d error=%d", ret, | ||||
error); | error); | ||||
goto fail; | goto fail; | ||||
} | } | ||||
ixl_enable_adminq(hw); | |||||
pf->num_vfs = num_vfs; | pf->num_vfs = num_vfs; | ||||
IXL_PF_UNLOCK(pf); | IXL_PF_UNLOCK(pf); | ||||
return (0); | return (0); | ||||
fail: | fail: | ||||
free(pf->vfs, M_IXL); | free(pf->vfs, M_IXL); | ||||
pf->vfs = NULL; | pf->vfs = NULL; | ||||
IXL_PF_UNLOCK(pf); | IXL_PF_UNLOCK(pf); | ||||
Show All 23 Lines | for (i = 0; i < pf->num_vfs; i++) { | ||||
DDPRINTF(dev, "VF %d: %d released\n", | DDPRINTF(dev, "VF %d: %d released\n", | ||||
i, pf->vfs[i].qtag.num_allocated); | i, pf->vfs[i].qtag.num_allocated); | ||||
DDPRINTF(dev, "Unallocated total: %d\n", ixl_pf_qmgr_get_num_free(&pf->qmgr)); | DDPRINTF(dev, "Unallocated total: %d\n", ixl_pf_qmgr_get_num_free(&pf->qmgr)); | ||||
} | } | ||||
if (pf->veb_seid != 0) { | if (pf->veb_seid != 0) { | ||||
i40e_aq_delete_element(hw, pf->veb_seid, NULL); | i40e_aq_delete_element(hw, pf->veb_seid, NULL); | ||||
pf->veb_seid = 0; | pf->veb_seid = 0; | ||||
} | |||||
if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) { | |||||
ixl_disable_intr(vsi); | |||||
ixl_flush(hw); | |||||
} | } | ||||
vfs = pf->vfs; | vfs = pf->vfs; | ||||
num_vfs = pf->num_vfs; | num_vfs = pf->num_vfs; | ||||
pf->vfs = NULL; | pf->vfs = NULL; | ||||
pf->num_vfs = 0; | pf->num_vfs = 0; | ||||
IXL_PF_UNLOCK(pf); | IXL_PF_UNLOCK(pf); | ||||
▲ Show 20 Lines • Show All 101 Lines • Show Last 20 Lines |