Differential D9227 Diff 24141 sys/dev/ixl/i40e_type.h

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sys/dev/ixl/i40e_type.h

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#define I40E_PCI_LINK_WIDTH_2 0x20		#define I40E_PCI_LINK_WIDTH_2 0x20
#define I40E_PCI_LINK_WIDTH_4 0x40		#define I40E_PCI_LINK_WIDTH_4 0x40
#define I40E_PCI_LINK_WIDTH_8 0x80		#define I40E_PCI_LINK_WIDTH_8 0x80
#define I40E_PCI_LINK_SPEED 0xF		#define I40E_PCI_LINK_SPEED 0xF
#define I40E_PCI_LINK_SPEED_2500 0x1		#define I40E_PCI_LINK_SPEED_2500 0x1
#define I40E_PCI_LINK_SPEED_5000 0x2		#define I40E_PCI_LINK_SPEED_5000 0x2
#define I40E_PCI_LINK_SPEED_8000 0x3		#define I40E_PCI_LINK_SPEED_8000 0x3

#define I40E_MDIO_STCODE I40E_MASK(0, \		#define I40E_MDIO_CLAUSE22_STCODE_MASK I40E_MASK(1, \
I40E_GLGEN_MSCA_STCODE_SHIFT)		I40E_GLGEN_MSCA_STCODE_SHIFT)
#define I40E_MDIO_OPCODE_ADDRESS I40E_MASK(0, \		#define I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK I40E_MASK(1, \
I40E_GLGEN_MSCA_OPCODE_SHIFT)		I40E_GLGEN_MSCA_OPCODE_SHIFT)
#define I40E_MDIO_OPCODE_WRITE I40E_MASK(1, \		#define I40E_MDIO_CLAUSE22_OPCODE_READ_MASK I40E_MASK(2, \
I40E_GLGEN_MSCA_OPCODE_SHIFT)		I40E_GLGEN_MSCA_OPCODE_SHIFT)
#define I40E_MDIO_OPCODE_READ_INC_ADDR I40E_MASK(2, \
		#define I40E_MDIO_CLAUSE45_STCODE_MASK I40E_MASK(0, \
		I40E_GLGEN_MSCA_STCODE_SHIFT)
		#define I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK I40E_MASK(0, \
I40E_GLGEN_MSCA_OPCODE_SHIFT)		I40E_GLGEN_MSCA_OPCODE_SHIFT)
#define I40E_MDIO_OPCODE_READ I40E_MASK(3, \		#define I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK I40E_MASK(1, \
I40E_GLGEN_MSCA_OPCODE_SHIFT)		I40E_GLGEN_MSCA_OPCODE_SHIFT)
		#define I40E_MDIO_CLAUSE45_OPCODE_READ_INC_ADDR_MASK I40E_MASK(2, \
		I40E_GLGEN_MSCA_OPCODE_SHIFT)
		#define I40E_MDIO_CLAUSE45_OPCODE_READ_MASK I40E_MASK(3, \
		I40E_GLGEN_MSCA_OPCODE_SHIFT)

#define I40E_PHY_COM_REG_PAGE 0x1E		#define I40E_PHY_COM_REG_PAGE 0x1E
#define I40E_PHY_LED_LINK_MODE_MASK 0xF0		#define I40E_PHY_LED_LINK_MODE_MASK 0xF0
#define I40E_PHY_LED_MANUAL_ON 0x100		#define I40E_PHY_LED_MANUAL_ON 0x100
#define I40E_PHY_LED_PROV_REG_1 0xC430		#define I40E_PHY_LED_PROV_REG_1 0xC430
#define I40E_PHY_LED_MODE_MASK 0xFFFF		#define I40E_PHY_LED_MODE_MASK 0xFFFF
#define I40E_PHY_LED_MODE_ORIG 0x80000000		#define I40E_PHY_LED_MODE_ORIG 0x80000000

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* know for sure exactly which hardware we're working with. This gives us the		* know for sure exactly which hardware we're working with. This gives us the
* flexibility of using the same main driver code but adapting to slightly		* flexibility of using the same main driver code but adapting to slightly
* different hardware needs as new parts are developed. For this architecture,		* different hardware needs as new parts are developed. For this architecture,
* the Firmware and AdminQ are intended to insulate the driver from most of the		* the Firmware and AdminQ are intended to insulate the driver from most of the
* future changes, but these structures will also do part of the job.		* future changes, but these structures will also do part of the job.
*/		*/
enum i40e_mac_type {		enum i40e_mac_type {
I40E_MAC_UNKNOWN = 0,		I40E_MAC_UNKNOWN = 0,
I40E_MAC_X710,
I40E_MAC_XL710,		I40E_MAC_XL710,
I40E_MAC_VF,		I40E_MAC_VF,
I40E_MAC_X722,		I40E_MAC_X722,
I40E_MAC_X722_VF,		I40E_MAC_X722_VF,
I40E_MAC_GENERIC,		I40E_MAC_GENERIC,
};		};

enum i40e_media_type {		enum i40e_media_type {
▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Lines	enum i40e_queue_type {
I40E_QUEUE_TYPE_UNKNOWN		I40E_QUEUE_TYPE_UNKNOWN
};		};

struct i40e_link_status {		struct i40e_link_status {
enum i40e_aq_phy_type phy_type;		enum i40e_aq_phy_type phy_type;
enum i40e_aq_link_speed link_speed;		enum i40e_aq_link_speed link_speed;
u8 link_info;		u8 link_info;
u8 an_info;		u8 an_info;
		u8 fec_info;
u8 ext_info;		u8 ext_info;
u8 loopback;		u8 loopback;
/* is Link Status Event notification to SW enabled */		/* is Link Status Event notification to SW enabled */
bool lse_enable;		bool lse_enable;
u16 max_frame_size;		u16 max_frame_size;
bool crc_enable;		bool crc_enable;
u8 pacing;		u8 pacing;
u8 requested_speeds;		u8 requested_speeds;
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#define I40E_CAP_PHY_TYPE_40GBASE_CR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4)		#define I40E_CAP_PHY_TYPE_40GBASE_CR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4)
#define I40E_CAP_PHY_TYPE_40GBASE_SR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_SR4)		#define I40E_CAP_PHY_TYPE_40GBASE_SR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_SR4)
#define I40E_CAP_PHY_TYPE_40GBASE_LR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_LR4)		#define I40E_CAP_PHY_TYPE_40GBASE_LR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_LR4)
#define I40E_CAP_PHY_TYPE_1000BASE_SX BIT_ULL(I40E_PHY_TYPE_1000BASE_SX)		#define I40E_CAP_PHY_TYPE_1000BASE_SX BIT_ULL(I40E_PHY_TYPE_1000BASE_SX)
#define I40E_CAP_PHY_TYPE_1000BASE_LX BIT_ULL(I40E_PHY_TYPE_1000BASE_LX)		#define I40E_CAP_PHY_TYPE_1000BASE_LX BIT_ULL(I40E_PHY_TYPE_1000BASE_LX)
#define I40E_CAP_PHY_TYPE_1000BASE_T_OPTICAL \		#define I40E_CAP_PHY_TYPE_1000BASE_T_OPTICAL \
BIT_ULL(I40E_PHY_TYPE_1000BASE_T_OPTICAL)		BIT_ULL(I40E_PHY_TYPE_1000BASE_T_OPTICAL)
#define I40E_CAP_PHY_TYPE_20GBASE_KR2 BIT_ULL(I40E_PHY_TYPE_20GBASE_KR2)		#define I40E_CAP_PHY_TYPE_20GBASE_KR2 BIT_ULL(I40E_PHY_TYPE_20GBASE_KR2)
#define I40E_CAP_PHY_TYPE_25GBASE_KR BIT_ULL(I40E_AQ_PHY_TYPE_EXT_25G_KR + 32)		/*
#define I40E_CAP_PHY_TYPE_25GBASE_CR BIT_ULL(I40E_AQ_PHY_TYPE_EXT_25G_CR + 32)		* Defining the macro I40E_TYPE_OFFSET to implement a bit shift for some
#define I40E_CAP_PHY_TYPE_25GBASE_SR BIT_ULL(I40E_AQ_PHY_TYPE_EXT_25G_SR + 32)		* PHY types. There is an unused bit (31) in the I40E_CAP_PHY_TYPE_* bit
#define I40E_CAP_PHY_TYPE_25GBASE_LR BIT_ULL(I40E_AQ_PHY_TYPE_EXT_25G_LR + 32)		* fields but no corresponding gap in the i40e_aq_phy_type enumeration. So,
		* a shift is needed to adjust for this with values larger than 31. The
		* only affected values are I40E_PHY_TYPE_25GBASE_*.
		*/
		#define I40E_PHY_TYPE_OFFSET 1
		#define I40E_CAP_PHY_TYPE_25GBASE_KR BIT_ULL(I40E_PHY_TYPE_25GBASE_KR + \
		I40E_PHY_TYPE_OFFSET)
		#define I40E_CAP_PHY_TYPE_25GBASE_CR BIT_ULL(I40E_PHY_TYPE_25GBASE_CR + \
		I40E_PHY_TYPE_OFFSET)
		#define I40E_CAP_PHY_TYPE_25GBASE_SR BIT_ULL(I40E_PHY_TYPE_25GBASE_SR + \
		I40E_PHY_TYPE_OFFSET)
		#define I40E_CAP_PHY_TYPE_25GBASE_LR BIT_ULL(I40E_PHY_TYPE_25GBASE_LR + \
		I40E_PHY_TYPE_OFFSET)
#define I40E_HW_CAP_MAX_GPIO 30		#define I40E_HW_CAP_MAX_GPIO 30
#define I40E_HW_CAP_MDIO_PORT_MODE_MDIO 0		#define I40E_HW_CAP_MDIO_PORT_MODE_MDIO 0
#define I40E_HW_CAP_MDIO_PORT_MODE_I2C 1		#define I40E_HW_CAP_MDIO_PORT_MODE_I2C 1

enum i40e_acpi_programming_method {		enum i40e_acpi_programming_method {
I40E_ACPI_PROGRAMMING_METHOD_HW_FVL = 0,		I40E_ACPI_PROGRAMMING_METHOD_HW_FVL = 0,
I40E_ACPI_PROGRAMMING_METHOD_AQC_FPK = 1		I40E_ACPI_PROGRAMMING_METHOD_AQC_FPK = 1
};		};

#define I40E_WOL_SUPPORT_MASK 1		#define I40E_WOL_SUPPORT_MASK 0x1
#define I40E_ACPI_PROGRAMMING_METHOD_MASK (1 << 1)		#define I40E_ACPI_PROGRAMMING_METHOD_MASK 0x2
#define I40E_PROXY_SUPPORT_MASK (1 << 2)		#define I40E_PROXY_SUPPORT_MASK 0x4

/* Capabilities of a PF or a VF or the whole device */		/* Capabilities of a PF or a VF or the whole device */
struct i40e_hw_capabilities {		struct i40e_hw_capabilities {
u32 switch_mode;		u32 switch_mode;
#define I40E_NVM_IMAGE_TYPE_EVB 0x0		#define I40E_NVM_IMAGE_TYPE_EVB 0x0
#define I40E_NVM_IMAGE_TYPE_CLOUD 0x2		#define I40E_NVM_IMAGE_TYPE_CLOUD 0x2
#define I40E_NVM_IMAGE_TYPE_UDP_CLOUD 0x3		#define I40E_NVM_IMAGE_TYPE_UDP_CLOUD 0x3

u32 management_mode;		u32 management_mode;
		u32 mng_protocols_over_mctp;
		#define I40E_MNG_PROTOCOL_PLDM 0x2
		#define I40E_MNG_PROTOCOL_OEM_COMMANDS 0x4
		#define I40E_MNG_PROTOCOL_NCSI 0x8
u32 npar_enable;		u32 npar_enable;
u32 os2bmc;		u32 os2bmc;
u32 valid_functions;		u32 valid_functions;
bool sr_iov_1_1;		bool sr_iov_1_1;
bool vmdq;		bool vmdq;
bool evb_802_1_qbg; /* Edge Virtual Bridging */		bool evb_802_1_qbg; /* Edge Virtual Bridging */
bool evb_802_1_qbh; /* Bridge Port Extension */		bool evb_802_1_qbh; /* Bridge Port Extension */
bool dcb;		bool dcb;
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};		};

enum i40e_nvmupd_state {		enum i40e_nvmupd_state {
I40E_NVMUPD_STATE_INIT,		I40E_NVMUPD_STATE_INIT,
I40E_NVMUPD_STATE_READING,		I40E_NVMUPD_STATE_READING,
I40E_NVMUPD_STATE_WRITING,		I40E_NVMUPD_STATE_WRITING,
I40E_NVMUPD_STATE_INIT_WAIT,		I40E_NVMUPD_STATE_INIT_WAIT,
I40E_NVMUPD_STATE_WRITE_WAIT,		I40E_NVMUPD_STATE_WRITE_WAIT,
		I40E_NVMUPD_STATE_ERROR
};		};

/* nvm_access definition and its masks/shifts need to be accessible to		/* nvm_access definition and its masks/shifts need to be accessible to
* application, core driver, and shared code. Where is the right file?		* application, core driver, and shared code. Where is the right file?
*/		*/
#define I40E_NVM_READ 0xB		#define I40E_NVM_READ 0xB
#define I40E_NVM_WRITE 0xC		#define I40E_NVM_WRITE 0xC

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struct i40e_bus_info {		struct i40e_bus_info {
enum i40e_bus_speed speed;		enum i40e_bus_speed speed;
enum i40e_bus_width width;		enum i40e_bus_width width;
enum i40e_bus_type type;		enum i40e_bus_type type;

u16 func;		u16 func;
u16 device;		u16 device;
u16 lan_id;		u16 lan_id;
		u16 bus_id;
};		};

/* Flow control (FC) parameters */		/* Flow control (FC) parameters */
struct i40e_fc_info {		struct i40e_fc_info {
enum i40e_fc_mode current_mode; /* FC mode in effect */		enum i40e_fc_mode current_mode; /* FC mode in effect */
enum i40e_fc_mode requested_mode; /* FC mode requested by caller */		enum i40e_fc_mode requested_mode; /* FC mode requested by caller */
};		};

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#define I40E_SR_PXE_CONFIG_CUST_OPTIONS_PTR 0x31		#define I40E_SR_PXE_CONFIG_CUST_OPTIONS_PTR 0x31
#define I40E_SR_NVM_ORIGINAL_EETRACK_LO 0x34		#define I40E_SR_NVM_ORIGINAL_EETRACK_LO 0x34
#define I40E_SR_NVM_ORIGINAL_EETRACK_HI 0x35		#define I40E_SR_NVM_ORIGINAL_EETRACK_HI 0x35
#define I40E_SR_SW_ETHERNET_MAC_ADDRESS_PTR 0x37		#define I40E_SR_SW_ETHERNET_MAC_ADDRESS_PTR 0x37
#define I40E_SR_POR_REGS_AUTO_LOAD_PTR 0x38		#define I40E_SR_POR_REGS_AUTO_LOAD_PTR 0x38
#define I40E_SR_EMPR_REGS_AUTO_LOAD_PTR 0x3A		#define I40E_SR_EMPR_REGS_AUTO_LOAD_PTR 0x3A
#define I40E_SR_GLOBR_REGS_AUTO_LOAD_PTR 0x3B		#define I40E_SR_GLOBR_REGS_AUTO_LOAD_PTR 0x3B
#define I40E_SR_CORER_REGS_AUTO_LOAD_PTR 0x3C		#define I40E_SR_CORER_REGS_AUTO_LOAD_PTR 0x3C
		#define I40E_SR_PHY_ACTIVITY_LIST_PTR 0x3D
#define I40E_SR_PCIE_ALT_AUTO_LOAD_PTR 0x3E		#define I40E_SR_PCIE_ALT_AUTO_LOAD_PTR 0x3E
#define I40E_SR_SW_CHECKSUM_WORD 0x3F		#define I40E_SR_SW_CHECKSUM_WORD 0x3F
#define I40E_SR_1ST_FREE_PROVISION_AREA_PTR 0x40		#define I40E_SR_1ST_FREE_PROVISION_AREA_PTR 0x40
#define I40E_SR_4TH_FREE_PROVISION_AREA_PTR 0x42		#define I40E_SR_4TH_FREE_PROVISION_AREA_PTR 0x42
#define I40E_SR_3RD_FREE_PROVISION_AREA_PTR 0x44		#define I40E_SR_3RD_FREE_PROVISION_AREA_PTR 0x44
#define I40E_SR_2ND_FREE_PROVISION_AREA_PTR 0x46		#define I40E_SR_2ND_FREE_PROVISION_AREA_PTR 0x46
#define I40E_SR_EMP_SR_SETTINGS_PTR 0x48		#define I40E_SR_EMP_SR_SETTINGS_PTR 0x48
#define I40E_SR_FEATURE_CONFIGURATION_PTR 0x49		#define I40E_SR_FEATURE_CONFIGURATION_PTR 0x49
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