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head/sys/arm/include/sysreg.h
| Show First 20 Lines • Show All 134 Lines • ▼ Show 20 Lines | |||||
| #if __ARM_ARCH >= 6 | #if __ARM_ARCH >= 6 | ||||
| /* From ARMv6k: */ | /* From ARMv6k: */ | ||||
| #define CP15_IFAR(rr) p15, 0, rr, c6, c0, 2 /* Instruction Fault Address Register */ | #define CP15_IFAR(rr) p15, 0, rr, c6, c0, 2 /* Instruction Fault Address Register */ | ||||
| #endif | #endif | ||||
| /* | /* | ||||
| * CP15 C7 registers | * CP15 C7 registers | ||||
| */ | */ | ||||
| #if __ARM_ARCH >= 7 && defined(SMP) | #if __ARM_ARCH >= 7 | ||||
| /* From ARMv7: */ | /* From ARMv7: */ | ||||
| #define CP15_ICIALLUIS p15, 0, r0, c7, c1, 0 /* Instruction cache invalidate all PoU, IS */ | #define CP15_ICIALLUIS p15, 0, r0, c7, c1, 0 /* Instruction cache invalidate all PoU, IS */ | ||||
| #define CP15_BPIALLIS p15, 0, r0, c7, c1, 6 /* Branch predictor invalidate all IS */ | #define CP15_BPIALLIS p15, 0, r0, c7, c1, 6 /* Branch predictor invalidate all IS */ | ||||
| #endif | #endif | ||||
| #define CP15_PAR(rr) p15, 0, rr, c7, c4, 0 /* Physical Address Register */ | #define CP15_PAR(rr) p15, 0, rr, c7, c4, 0 /* Physical Address Register */ | ||||
| #define CP15_ICIALLU p15, 0, r0, c7, c5, 0 /* Instruction cache invalidate all PoU */ | #define CP15_ICIALLU p15, 0, r0, c7, c5, 0 /* Instruction cache invalidate all PoU */ | ||||
| ▲ Show 20 Lines • Show All 48 Lines • ▼ Show 20 Lines | |||||
| #define CP15_DCCIALL p15, 0, r0, c7, c14, 0 /* Data cache clean and invalidate all */ | #define CP15_DCCIALL p15, 0, r0, c7, c14, 0 /* Data cache clean and invalidate all */ | ||||
| #endif | #endif | ||||
| #define CP15_DCCIMVAC(rr) p15, 0, rr, c7, c14, 1 /* Data cache clean and invalidate by MVA PoC */ | #define CP15_DCCIMVAC(rr) p15, 0, rr, c7, c14, 1 /* Data cache clean and invalidate by MVA PoC */ | ||||
| #define CP15_DCCISW(rr) p15, 0, rr, c7, c14, 2 /* Data cache clean and invalidate by set/way */ | #define CP15_DCCISW(rr) p15, 0, rr, c7, c14, 2 /* Data cache clean and invalidate by set/way */ | ||||
| /* | /* | ||||
| * CP15 C8 registers | * CP15 C8 registers | ||||
| */ | */ | ||||
| #if __ARM_ARCH >= 7 && defined(SMP) | #if __ARM_ARCH >= 7 | ||||
| /* From ARMv7: */ | /* From ARMv7: */ | ||||
| #define CP15_TLBIALLIS p15, 0, r0, c8, c3, 0 /* Invalidate entire unified TLB IS */ | #define CP15_TLBIALLIS p15, 0, r0, c8, c3, 0 /* Invalidate entire unified TLB IS */ | ||||
| #define CP15_TLBIMVAIS(rr) p15, 0, rr, c8, c3, 1 /* Invalidate unified TLB by MVA IS */ | #define CP15_TLBIMVAIS(rr) p15, 0, rr, c8, c3, 1 /* Invalidate unified TLB by MVA IS */ | ||||
| #define CP15_TLBIASIDIS(rr) p15, 0, rr, c8, c3, 2 /* Invalidate unified TLB by ASID IS */ | #define CP15_TLBIASIDIS(rr) p15, 0, rr, c8, c3, 2 /* Invalidate unified TLB by ASID IS */ | ||||
| #define CP15_TLBIMVAAIS(rr) p15, 0, rr, c8, c3, 3 /* Invalidate unified TLB by MVA, all ASID IS */ | #define CP15_TLBIMVAAIS(rr) p15, 0, rr, c8, c3, 3 /* Invalidate unified TLB by MVA, all ASID IS */ | ||||
| #endif | #endif | ||||
| #define CP15_TLBIALL p15, 0, r0, c8, c7, 0 /* Invalidate entire unified TLB */ | #define CP15_TLBIALL p15, 0, r0, c8, c7, 0 /* Invalidate entire unified TLB */ | ||||
| ▲ Show 20 Lines • Show All 89 Lines • Show Last 20 Lines | |||||