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Show First 20 Lines • Show All 494 Lines • ▼ Show 20 Lines	for (i = 0; i < 8; i++) {
nmrr \|= inner << (i * 2);		nmrr \|= inner << (i * 2);
nmrr \|= outer << (i * 2 + 16);		nmrr \|= outer << (i * 2 + 16);
}		}
/* Add shareable bits for device memory. */		/* Add shareable bits for device memory. */
prrr \|= PRRR_DS0 \| PRRR_DS1;		prrr \|= PRRR_DS0 \| PRRR_DS1;

/* Add shareable bits for normal memory in SMP case. */		/* Add shareable bits for normal memory in SMP case. */
#ifdef SMP		#ifdef SMP
		if (ARM_USE_MP_EXTENSIONS)
prrr \|= PRRR_NS1;		prrr \|= PRRR_NS1;
#endif		#endif
cp15_prrr_set(prrr);		cp15_prrr_set(prrr);
cp15_nmrr_set(nmrr);		cp15_nmrr_set(nmrr);

/* Caches are disabled, so full TLB flush should be enough. */		/* Caches are disabled, so full TLB flush should be enough. */
tlb_flush_all_local();		tlb_flush_all_local();
}		}

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