Differential D7552 Diff 19462 sys/mips/broadcom/bcm_machdep.c

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sys/mips/broadcom/bcm_machdep.c

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#include <dev/bhnd/siba/sibareg.h>		#include <dev/bhnd/siba/sibareg.h>
#include <dev/bhnd/siba/sibavar.h>		#include <dev/bhnd/siba/sibavar.h>

#include <dev/bhnd/cores/chipc/chipcreg.h>		#include <dev/bhnd/cores/chipc/chipcreg.h>
#include <dev/bhnd/cores/pmu/bhnd_pmureg.h>		#include <dev/bhnd/cores/pmu/bhnd_pmureg.h>

#include "bcm_machdep.h"		#include "bcm_machdep.h"
#include "bcm_mips_exts.h"		#include "bcm_mips_exts.h"
#include "bcm_socinfo.h"

#ifdef CFE		#ifdef CFE
#include <dev/cfe/cfe_api.h>		#include <dev/cfe/cfe_api.h>
#endif		#endif

#if 0		#if 0
#define BCM_TRACE(_fmt, ...) printf(_fmt, ##__VA_ARGS__)		#define BCM_TRACE(_fmt, ...) printf(_fmt, ##__VA_ARGS__)
#else		#else
▲ Show 20 Lines • Show All 136 Lines • ▼ Show 20 Lines	if (pmu && aob) {
pdata->pmu_addr = pdata->cc_addr;		pdata->pmu_addr = pdata->cc_addr;
pdata->pmu_id = pdata->cc_id;		pdata->pmu_id = pdata->cc_id;
} else {		} else {
/* No PMU */		/* No PMU */
pdata->pmu_addr = 0x0;		pdata->pmu_addr = 0x0;
memset(&pdata->pmu_id, 0, sizeof(pdata->pmu_id));		memset(&pdata->pmu_id, 0, sizeof(pdata->pmu_id));
}		}

		if (pmu) {
		error = bhnd_pmu_query_init(&pdata->pmu, NULL, pdata->id,
		&bcm_pmu_soc_io, pdata);
		if (error) {
		printf("%s: bhnd_pmu_query_init() failed: %d\n",
		__FUNCTION__, error);
		return (error);
		}
		}

bcm_platform_data_avail = true;		bcm_platform_data_avail = true;
return (0);		return (0);
}		}

void		void
platform_cpu_init()		platform_cpu_init()
{		{
/* Nothing special */		/* Nothing special */
▲ Show 20 Lines • Show All 64 Lines • ▼ Show 20 Lines	#ifdef KDB
if (boothowto & RB_KDB)		if (boothowto & RB_KDB)
kdb_enter(KDB_WHY_BOOTFLAGS, "Boot flags requested debugger");		kdb_enter(KDB_WHY_BOOTFLAGS, "Boot flags requested debugger");
#endif		#endif
}		}

void		void
platform_reset(void)		platform_reset(void)
{		{
		struct bcm_platform *bp;
bool bcm4785war;		bool bcm4785war;

printf("bcm::platform_reset()\n");		printf("bcm::platform_reset()\n");
intr_disable();		intr_disable();

#ifdef CFE		#ifdef CFE
/* Fall back on CFE if reset requested during platform		/* Fall back on CFE if reset requested during platform
* data initialization */		* data initialization */
if (!bcm_platform_data_avail) {		if (!bcm_platform_data_avail) {
cfe_exit(0, 0);		cfe_exit(0, 0);
while (1);		while (1);
}		}
#endif		#endif

/* Handle BCM4785-specific behavior */		bp = bcm_get_platform();
bcm4785war = false;		bcm4785war = false;
if (bcm_get_platform()->id.chip_id == BHND_CHIPID_BCM4785) {
		/* Handle BCM4785-specific behavior */
		if (bp->id.chip_id == BHND_CHIPID_BCM4785) {
bcm4785war = true;		bcm4785war = true;

/* Switch to async mode */		/* Switch to async mode */
bcm_mips_wr_pllcfg3(MIPS_BCMCFG_PLLCFG3_SM);		bcm_mips_wr_pllcfg3(MIPS_BCMCFG_PLLCFG3_SM);
}		}

/* Set watchdog (PMU or ChipCommon) */		/* Set watchdog (PMU or ChipCommon) */
if (bcm_get_platform()->pmu_addr != 0x0) {		if (bp->pmu_addr != 0x0) {
BCM_CHIPC_WRITE_4(BHND_PMU_WATCHDOG, 1);		BCM_PMU_WRITE_4(bp, BHND_PMU_WATCHDOG, 1);
} else		} else
BCM_CHIPC_WRITE_4(CHIPC_WATCHDOG, 1);		BCM_CHIPC_WRITE_4(bp, CHIPC_WATCHDOG, 1);

/* BCM4785 */		/* BCM4785 */
if (bcm4785war) {		if (bcm4785war) {
mips_sync();		mips_sync();
__asm __volatile("wait");		__asm __volatile("wait");
}		}

while (1);		while (1);
}		}

void		void
platform_start(__register_t a0, __register_t a1, __register_t a2,		platform_start(__register_t a0, __register_t a1, __register_t a2,
__register_t a3)		__register_t a3)
{		{
vm_offset_t kernend;		vm_offset_t kernend;
uint64_t platform_counter_freq;		uint64_t platform_counter_freq;
struct bcm_socinfo *socinfo;
int error;		int error;

/* clear the BSS and SBSS segments */		/* clear the BSS and SBSS segments */
kernend = (vm_offset_t)&end;		kernend = (vm_offset_t)&end;
memset(&edata, 0, kernend - (vm_offset_t)(&edata));		memset(&edata, 0, kernend - (vm_offset_t)(&edata));

mips_postboot_fixup();		mips_postboot_fixup();

Show All 14 Lines	#ifdef CFE
if (a3 == CFE_EPTSEAL)		if (a3 == CFE_EPTSEAL)
cfe_init(a0, a2);		cfe_init(a0, a2);
#endif		#endif

/* Init BCM platform data */		/* Init BCM platform data */
if ((error = bcm_init_platform_data(&bcm_platform_data)))		if ((error = bcm_init_platform_data(&bcm_platform_data)))
panic("bcm_init_platform_data() failed: %d", error);		panic("bcm_init_platform_data() failed: %d", error);

socinfo = bcm_get_socinfo();		platform_counter_freq = bcm_get_cpufreq(bcm_get_platform());
platform_counter_freq = socinfo->cpurate * 1000 * 1000; /* BCM4718 is 480MHz */

mips_timer_early_init(platform_counter_freq);		/* CP0 ticks every two cycles */
		mips_timer_early_init(platform_counter_freq / 2);

cninit();		cninit();

mips_init();		mips_init();

mips_timer_init_params(platform_counter_freq, socinfo->double_count);		mips_timer_init_params(platform_counter_freq, 1);
}		}

/*		/*
* CFE-based EARLY_PRINTF support. To use, add the following to the kernel		* CFE-based EARLY_PRINTF support. To use, add the following to the kernel
* config:		* config:
* option EARLY_PRINTF		* option EARLY_PRINTF
* option CFE		* option CFE
* device cfe		* device cfe
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