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sys/dev/bhnd/cores/chipc/chipcreg.h
| Show All 25 Lines | |||||
| #define _BHND_CORES_CHIPC_CHIPCREG_H_ | #define _BHND_CORES_CHIPC_CHIPCREG_H_ | ||||
| #define CHIPC_CHIPID_SIZE 0x100 /**< size of the register block | #define CHIPC_CHIPID_SIZE 0x100 /**< size of the register block | ||||
| containing the chip | containing the chip | ||||
| identification registers | identification registers | ||||
| required during bus | required during bus | ||||
| enumeration */ | enumeration */ | ||||
| /** Evaluates to true if the given ChipCommon core revision supports | |||||
| * the CHIPC_CORECTRL register */ | |||||
| #define CHIPC_HWREV_HAS_CORECTRL(hwrev) ((hwrev) >= 1) | |||||
| /** Evaluates to true if the given ChipCommon core revision provides | /** Evaluates to true if the given ChipCommon core revision provides | ||||
| * the core count via the chip identification register. */ | * the core count via the chip identification register. */ | ||||
| #define CHIPC_NCORES_MIN_HWREV(hwrev) ((hwrev) == 4 || (hwrev) >= 6) | #define CHIPC_NCORES_MIN_HWREV(hwrev) ((hwrev) == 4 || (hwrev) >= 6) | ||||
| /** Evaluates to true if the given ChipCommon core revision supports | /** Evaluates to true if the given ChipCommon core revision supports | ||||
| * the CHIPC_CAPABILITIES_EXT register */ | * the CHIPC_CAPABILITIES_EXT register */ | ||||
| #define CHIPC_HWREV_HAS_CAP_EXT(hwrev) ((hwrev) >= 35) | #define CHIPC_HWREV_HAS_CAP_EXT(hwrev) ((hwrev) >= 35) | ||||
| ▲ Show 20 Lines • Show All 231 Lines • ▼ Show 20 Lines | #define CHIPC_CST_SPROM_OTP_SEL_R23_MASK 0x000000c0 /**< chipstatus OTP/SPROM SEL value (revs 23-31) | ||||
| * | * | ||||
| * it is unknown whether this is supported on | * it is unknown whether this is supported on | ||||
| * any CC revs >= 32 that also vend CHIPC_CAP_* | * any CC revs >= 32 that also vend CHIPC_CAP_* | ||||
| * constants for OTP/SPROM/NVRAM availability. | * constants for OTP/SPROM/NVRAM availability. | ||||
| */ | */ | ||||
| #define CHIPC_CST_SPROM_OTP_SEL_R23_SHIFT 6 | #define CHIPC_CST_SPROM_OTP_SEL_R23_SHIFT 6 | ||||
| /* PLL type */ | /* PLL type */ | ||||
| #define CHIPC_PLL_NONE 0x00 | #define CHIPC_PLL_NONE 0x0 | ||||
| #define CHIPC_PLL_TYPE1 0x10 /* 48MHz base, 3 dividers */ | #define CHIPC_PLL_TYPE1 0x2 /* 48MHz base, 3 dividers */ | ||||
| #define CHIPC_PLL_TYPE2 0x20 /* 48MHz, 4 dividers */ | #define CHIPC_PLL_TYPE2 0x4 /* 48MHz, 4 dividers */ | ||||
| #define CHIPC_PLL_TYPE3 0x30 /* 25MHz, 2 dividers */ | #define CHIPC_PLL_TYPE3 0x6 /* 25MHz, 2 dividers */ | ||||
| #define CHIPC_PLL_TYPE4 0x08 /* 48MHz, 4 dividers */ | #define CHIPC_PLL_TYPE4 0x8 /* 48MHz, 4 dividers */ | ||||
| #define CHIPC_PLL_TYPE5 0x18 /* 25MHz, 4 dividers */ | #define CHIPC_PLL_TYPE5 0x3 /* 25MHz, 4 dividers */ | ||||
| #define CHIPC_PLL_TYPE6 0x28 /* 100/200 or 120/240 only */ | #define CHIPC_PLL_TYPE6 0x5 /* 100/200 or 120/240 only */ | ||||
| #define CHIPC_PLL_TYPE7 0x38 /* 25MHz, 4 dividers */ | #define CHIPC_PLL_TYPE7 0x7 /* 25MHz, 4 dividers */ | ||||
| /* dynamic clock control defines */ | /* dynamic clock control defines */ | ||||
| #define CHIPC_LPOMINFREQ 25000 /* low power oscillator min */ | #define CHIPC_LPOMINFREQ 25000 /* low power oscillator min */ | ||||
| #define CHIPC_LPOMAXFREQ 43000 /* low power oscillator max */ | #define CHIPC_LPOMAXFREQ 43000 /* low power oscillator max */ | ||||
| #define CHIPC_XTALMINFREQ 19800000 /* 20 MHz - 1% */ | #define CHIPC_XTALMINFREQ 19800000 /* 20 MHz - 1% */ | ||||
| #define CHIPC_XTALMAXFREQ 20200000 /* 20 MHz + 1% */ | #define CHIPC_XTALMAXFREQ 20200000 /* 20 MHz + 1% */ | ||||
| #define CHIPC_PCIMINFREQ 25000000 /* 25 MHz */ | #define CHIPC_PCIMINFREQ 25000000 /* 25 MHz */ | ||||
| #define CHIPC_PCIMAXFREQ 34000000 /* 33 MHz + fudge */ | #define CHIPC_PCIMAXFREQ 34000000 /* 33 MHz + fudge */ | ||||
| ▲ Show 20 Lines • Show All 666 Lines • Show Last 20 Lines | |||||