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head/sys/dev/bhnd/cores/chipc/chipcreg.h
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| #define CHIPC_CAP_UARTGPIO 0x00000020 /* UARTs own GPIOs 15:12 */ | #define CHIPC_CAP_UARTGPIO 0x00000020 /* UARTs own GPIOs 15:12 */ | ||||
| #define CHIPC_CAP_EXTBUS_MASK 0x000000c0 /* External bus mask */ | #define CHIPC_CAP_EXTBUS_MASK 0x000000c0 /* External bus mask */ | ||||
| #define CHIPC_CAP_EXTBUS_SHIFT 6 | #define CHIPC_CAP_EXTBUS_SHIFT 6 | ||||
| #define CHIPC_CAP_EXTBUS_NONE 0x0 /* No ExtBus present */ | #define CHIPC_CAP_EXTBUS_NONE 0x0 /* No ExtBus present */ | ||||
| #define CHIPC_CAP_EXTBUS_FULL 0x1 /* ExtBus: PCMCIA, IDE & Prog */ | #define CHIPC_CAP_EXTBUS_FULL 0x1 /* ExtBus: PCMCIA, IDE & Prog */ | ||||
| #define CHIPC_CAP_EXTBUS_PROG 0x2 /* ExtBus: ProgIf only */ | #define CHIPC_CAP_EXTBUS_PROG 0x2 /* ExtBus: ProgIf only */ | ||||
| #define CHIPC_CAP_FLASH_MASK 0x00000700 /* Type of flash */ | #define CHIPC_CAP_FLASH_MASK 0x00000700 /* Type of flash */ | ||||
| #define CHIPC_CAP_FLASH_SHIFT 8 | #define CHIPC_CAP_FLASH_SHIFT 8 | ||||
| #define CHIPC_CAP_FLASH_NONE 0x000 /* No flash */ | #define CHIPC_CAP_FLASH_NONE 0x0 /* No flash */ | ||||
| #define CHIPC_CAP_SFLASH_ST 0x100 /* ST serial flash */ | #define CHIPC_CAP_SFLASH_ST 0x1 /* ST serial flash */ | ||||
| #define CHIPC_CAP_SFLASH_AT 0x200 /* Atmel serial flash */ | #define CHIPC_CAP_SFLASH_AT 0x2 /* Atmel serial flash */ | ||||
| #define CHIPC_CAP_NFLASH 0x300 /* NAND flash */ | #define CHIPC_CAP_NFLASH 0x3 /* NAND flash */ | ||||
| #define CHIPC_CAP_PFLASH 0x700 /* Parallel flash */ | #define CHIPC_CAP_PFLASH 0x7 /* Parallel flash */ | ||||
| #define CHIPC_CAP_PLL_MASK 0x00038000 /* Type of PLL */ | #define CHIPC_CAP_PLL_MASK 0x00038000 /* Type of PLL */ | ||||
| #define CHIPC_CAP_PLL_SHIFT 15 | #define CHIPC_CAP_PLL_SHIFT 15 | ||||
| #define CHIPC_CAP_PWR_CTL 0x00040000 /* Power control */ | #define CHIPC_CAP_PWR_CTL 0x00040000 /* Power control */ | ||||
| #define CHIPC_CAP_OTP_SIZE_MASK 0x00380000 /* OTP Size (0 = none) */ | #define CHIPC_CAP_OTP_SIZE_MASK 0x00380000 /* OTP Size (0 = none) */ | ||||
| #define CHIPC_CAP_OTP_SIZE_SHIFT 19 /* OTP Size shift */ | #define CHIPC_CAP_OTP_SIZE_SHIFT 19 /* OTP Size shift */ | ||||
| #define CHIPC_CAP_OTP_SIZE_BASE 5 /* OTP Size base */ | #define CHIPC_CAP_OTP_SIZE_BASE 5 /* OTP Size base */ | ||||
| #define CHIPC_CAP_JTAGP 0x00400000 /* JTAG Master Present */ | #define CHIPC_CAP_JTAGP 0x00400000 /* JTAG Master Present */ | ||||
| #define CHIPC_CAP_ROM 0x00800000 /* Internal boot rom active */ | #define CHIPC_CAP_ROM 0x00800000 /* Internal boot rom active */ | ||||
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