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head/sys/dev/mpr/mpi/mpi2_cnfg.h
| /*- | /*- | ||||
| * Copyright (c) 2012-2015 LSI Corp. | * Copyright (c) 2012-2015 LSI Corp. | ||||
| * Copyright (c) 2013-2015 Avago Technologies | * Copyright (c) 2013-2016 Avago Technologies | ||||
| * All rights reserved. | * All rights reserved. | ||||
| * | * | ||||
| * Redistribution and use in source and binary forms, with or without | * Redistribution and use in source and binary forms, with or without | ||||
| * modification, are permitted provided that the following conditions | * modification, are permitted provided that the following conditions | ||||
| * are met: | * are met: | ||||
| * 1. Redistributions of source code must retain the above copyright | * 1. Redistributions of source code must retain the above copyright | ||||
| * notice, this list of conditions and the following disclaimer. | * notice, this list of conditions and the following disclaimer. | ||||
| * 2. Redistributions in binary form must reproduce the above copyright | * 2. Redistributions in binary form must reproduce the above copyright | ||||
| Show All 17 Lines | |||||
| * | * | ||||
| * Avago Technologies (LSI) MPT-Fusion Host Adapter FreeBSD | * Avago Technologies (LSI) MPT-Fusion Host Adapter FreeBSD | ||||
| * | * | ||||
| * $FreeBSD$ | * $FreeBSD$ | ||||
| */ | */ | ||||
| /* | /* | ||||
| * Copyright (c) 2000-2015 LSI Corporation. | * Copyright (c) 2000-2015 LSI Corporation. | ||||
| * Copyright (c) 2013-2015 Avago Technologies | * Copyright (c) 2013-2016 Avago Technologies | ||||
| * All rights reserved. | |||||
| * | * | ||||
| * | * | ||||
| * Name: mpi2_cnfg.h | * Name: mpi2_cnfg.h | ||||
| * Title: MPI Configuration messages and pages | * Title: MPI Configuration messages and pages | ||||
| * Creation Date: November 10, 2006 | * Creation Date: November 10, 2006 | ||||
| * | * | ||||
| * mpi2_cnfg.h Version: 02.00.27 | * mpi2_cnfg.h Version: 02.00.35 | ||||
| * | * | ||||
| * NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25 | * NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25 | ||||
| * prefix are for use only on MPI v2.5 products, and must not be used | * prefix are for use only on MPI v2.5 products, and must not be used | ||||
| * with MPI v2.0 products. Unless otherwise noted, names beginning with | * with MPI v2.0 products. Unless otherwise noted, names beginning with | ||||
| * MPI2 or Mpi2 are for use with both MPI v2.0 and MPI v2.5 products. | * MPI2 or Mpi2 are for use with both MPI v2.0 and MPI v2.5 products. | ||||
| * | * | ||||
| * Version History | * Version History | ||||
| * --------------- | * --------------- | ||||
| ▲ Show 20 Lines • Show All 152 Lines • ▼ Show 20 Lines | |||||
| * Added EnclosureLevel and ConnectorName fields to | * Added EnclosureLevel and ConnectorName fields to | ||||
| * MPI2_CONFIG_PAGE_SAS_DEV_0. | * MPI2_CONFIG_PAGE_SAS_DEV_0. | ||||
| * Added MPI2_SAS_DEVICE0_FLAGS_ENCL_LEVEL_VALID for | * Added MPI2_SAS_DEVICE0_FLAGS_ENCL_LEVEL_VALID for | ||||
| * MPI2_CONFIG_PAGE_SAS_DEV_0. | * MPI2_CONFIG_PAGE_SAS_DEV_0. | ||||
| * Added EnclosureLevel field to | * Added EnclosureLevel field to | ||||
| * MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0. | * MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0. | ||||
| * Added MPI2_SAS_ENCLS0_FLAGS_ENCL_LEVEL_VALID for | * Added MPI2_SAS_ENCLS0_FLAGS_ENCL_LEVEL_VALID for | ||||
| * MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0. | * MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0. | ||||
| * 01-08-14 02.00.28 Added more defines for the BiosOptions field of | |||||
| * MPI2_CONFIG_PAGE_BIOS_1. | |||||
| * 06-13-14 02.00.29 Added SSUTimeout field to MPI2_CONFIG_PAGE_BIOS_1, and | |||||
| * more defines for the BiosOptions field. | |||||
| * 11-18-14 02.00.30 Updated copyright information. | |||||
| * Added MPI2_BIOSPAGE1_OPTIONS_ADVANCED_CONFIG. | |||||
| * Added AdapterOrderAux fields to BIOS Page 3. | |||||
| * 03-16-15 02.00.31 Updated for MPI v2.6. | |||||
| * Added BoardPowerRequirement, PCISlotPowerAllocation, and | |||||
| * Flags field to IO Unit Page 7. | |||||
| * Added IO Unit Page 11. | |||||
| * Added new SAS Phy Event codes | |||||
| * 05-25-15 02.00.33 Added more defines for the BiosOptions field of | |||||
| * MPI2_CONFIG_PAGE_BIOS_1. | |||||
| * 12-18-15 02.00.35 Added SATADeviceWaitTime to SAS IO Unit Page 4. | |||||
| * -------------------------------------------------------------------------- | * -------------------------------------------------------------------------- | ||||
| */ | */ | ||||
| #ifndef MPI2_CNFG_H | #ifndef MPI2_CNFG_H | ||||
| #define MPI2_CNFG_H | #define MPI2_CNFG_H | ||||
| /***************************************************************************** | /***************************************************************************** | ||||
| * Configuration Page Header and defines | * Configuration Page Header and defines | ||||
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| /* Ethernet PageAddress format */ | /* Ethernet PageAddress format */ | ||||
| #define MPI2_ETHERNET_PGAD_FORM_MASK (0xF0000000) | #define MPI2_ETHERNET_PGAD_FORM_MASK (0xF0000000) | ||||
| #define MPI2_ETHERNET_PGAD_FORM_IF_NUM (0x00000000) | #define MPI2_ETHERNET_PGAD_FORM_IF_NUM (0x00000000) | ||||
| #define MPI2_ETHERNET_PGAD_IF_NUMBER_MASK (0x000000FF) | #define MPI2_ETHERNET_PGAD_IF_NUMBER_MASK (0x000000FF) | ||||
| /**************************************************************************** | /**************************************************************************** | ||||
| * Configuration messages | * Configuration messages | ||||
| ****************************************************************************/ | ****************************************************************************/ | ||||
| /* Configuration Request Message */ | /* Configuration Request Message */ | ||||
| typedef struct _MPI2_CONFIG_REQUEST | typedef struct _MPI2_CONFIG_REQUEST | ||||
| { | { | ||||
| U8 Action; /* 0x00 */ | U8 Action; /* 0x00 */ | ||||
| ▲ Show 20 Lines • Show All 87 Lines • ▼ Show 20 Lines | |||||
| /* MPI v2.5 SAS products */ | /* MPI v2.5 SAS products */ | ||||
| #define MPI25_MFGPAGE_DEVID_SAS3004 (0x0096) | #define MPI25_MFGPAGE_DEVID_SAS3004 (0x0096) | ||||
| #define MPI25_MFGPAGE_DEVID_SAS3008 (0x0097) | #define MPI25_MFGPAGE_DEVID_SAS3008 (0x0097) | ||||
| #define MPI25_MFGPAGE_DEVID_SAS3108_1 (0x0090) | #define MPI25_MFGPAGE_DEVID_SAS3108_1 (0x0090) | ||||
| #define MPI25_MFGPAGE_DEVID_SAS3108_2 (0x0091) | #define MPI25_MFGPAGE_DEVID_SAS3108_2 (0x0091) | ||||
| #define MPI25_MFGPAGE_DEVID_SAS3108_5 (0x0094) | #define MPI25_MFGPAGE_DEVID_SAS3108_5 (0x0094) | ||||
| #define MPI25_MFGPAGE_DEVID_SAS3108_6 (0x0095) | #define MPI25_MFGPAGE_DEVID_SAS3108_6 (0x0095) | ||||
| /* MPI v2.6 SAS Products */ | |||||
| #define MPI26_MFGPAGE_DEVID_SAS3216 (0x00C9) | |||||
| #define MPI26_MFGPAGE_DEVID_SAS3224 (0x00C4) | |||||
| #define MPI26_MFGPAGE_DEVID_SAS3316_1 (0x00C5) | |||||
| #define MPI26_MFGPAGE_DEVID_SAS3316_2 (0x00C6) | |||||
| #define MPI26_MFGPAGE_DEVID_SAS3316_3 (0x00C7) | |||||
| #define MPI26_MFGPAGE_DEVID_SAS3316_4 (0x00C8) | |||||
| #define MPI26_MFGPAGE_DEVID_SAS3324_1 (0x00C0) | |||||
| #define MPI26_MFGPAGE_DEVID_SAS3324_2 (0x00C1) | |||||
| #define MPI26_MFGPAGE_DEVID_SAS3324_3 (0x00C2) | |||||
| #define MPI26_MFGPAGE_DEVID_SAS3324_4 (0x00C3) | |||||
| /* Manufacturing Page 0 */ | /* Manufacturing Page 0 */ | ||||
| typedef struct _MPI2_CONFIG_PAGE_MAN_0 | typedef struct _MPI2_CONFIG_PAGE_MAN_0 | ||||
| { | { | ||||
| MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ | MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ | ||||
| U8 ChipName[16]; /* 0x04 */ | U8 ChipName[16]; /* 0x04 */ | ||||
| U8 ChipRevision[8]; /* 0x14 */ | U8 ChipRevision[8]; /* 0x14 */ | ||||
| U8 BoardName[16]; /* 0x1C */ | U8 BoardName[16]; /* 0x1C */ | ||||
| ▲ Show 20 Lines • Show All 452 Lines • ▼ Show 20 Lines | typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_7 | ||||
| U32 ProcessorState; /* 0x08 */ | U32 ProcessorState; /* 0x08 */ | ||||
| U32 PowerManagementCapabilities; /* 0x0C */ | U32 PowerManagementCapabilities; /* 0x0C */ | ||||
| U16 IOCTemperature; /* 0x10 */ | U16 IOCTemperature; /* 0x10 */ | ||||
| U8 IOCTemperatureUnits; /* 0x12 */ | U8 IOCTemperatureUnits; /* 0x12 */ | ||||
| U8 IOCSpeed; /* 0x13 */ | U8 IOCSpeed; /* 0x13 */ | ||||
| U16 BoardTemperature; /* 0x14 */ | U16 BoardTemperature; /* 0x14 */ | ||||
| U8 BoardTemperatureUnits; /* 0x16 */ | U8 BoardTemperatureUnits; /* 0x16 */ | ||||
| U8 Reserved3; /* 0x17 */ | U8 Reserved3; /* 0x17 */ | ||||
| U32 Reserved4; /* 0x18 */ | U32 BoardPowerRequirement; /* 0x18 */ /* reserved prior to MPI v2.6 */ | ||||
| U32 Reserved5; /* 0x1C */ | U32 PCISlotPowerAllocation; /* 0x1C */ /* reserved prior to MPI v2.6 */ | ||||
| U32 Reserved6; /* 0x20 */ | U8 Flags; /* 0x20 */ /* reserved prior to MPI v2.6 */ | ||||
| U32 Reserved7; /* 0x24 */ | U8 Reserved6; /* 0x21 */ | ||||
| U16 Reserved7; /* 0x22 */ | |||||
| U32 Reserved8; /* 0x24 */ | |||||
| } MPI2_CONFIG_PAGE_IO_UNIT_7, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_7, | } MPI2_CONFIG_PAGE_IO_UNIT_7, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_7, | ||||
| Mpi2IOUnitPage7_t, MPI2_POINTER pMpi2IOUnitPage7_t; | Mpi2IOUnitPage7_t, MPI2_POINTER pMpi2IOUnitPage7_t; | ||||
| #define MPI2_IOUNITPAGE7_PAGEVERSION (0x04) | #define MPI2_IOUNITPAGE7_PAGEVERSION (0x05) | ||||
| /* defines for IO Unit Page 7 CurrentPowerMode and PreviousPowerMode fields */ | /* defines for IO Unit Page 7 CurrentPowerMode and PreviousPowerMode fields */ | ||||
| #define MPI25_IOUNITPAGE7_PM_INIT_MASK (0xC0) | #define MPI25_IOUNITPAGE7_PM_INIT_MASK (0xC0) | ||||
| #define MPI25_IOUNITPAGE7_PM_INIT_UNAVAILABLE (0x00) | #define MPI25_IOUNITPAGE7_PM_INIT_UNAVAILABLE (0x00) | ||||
| #define MPI25_IOUNITPAGE7_PM_INIT_HOST (0x40) | #define MPI25_IOUNITPAGE7_PM_INIT_HOST (0x40) | ||||
| #define MPI25_IOUNITPAGE7_PM_INIT_IO_UNIT (0x80) | #define MPI25_IOUNITPAGE7_PM_INIT_IO_UNIT (0x80) | ||||
| #define MPI25_IOUNITPAGE7_PM_INIT_PCIE_DPA (0xC0) | #define MPI25_IOUNITPAGE7_PM_INIT_PCIE_DPA (0xC0) | ||||
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| #define MPI2_IOUNITPAGE7_IOC_SPEED_QUARTER (0x04) | #define MPI2_IOUNITPAGE7_IOC_SPEED_QUARTER (0x04) | ||||
| #define MPI2_IOUNITPAGE7_IOC_SPEED_EIGHTH (0x08) | #define MPI2_IOUNITPAGE7_IOC_SPEED_EIGHTH (0x08) | ||||
| /* defines for IO Unit Page 7 BoardTemperatureUnits field */ | /* defines for IO Unit Page 7 BoardTemperatureUnits field */ | ||||
| #define MPI2_IOUNITPAGE7_BOARD_TEMP_NOT_PRESENT (0x00) | #define MPI2_IOUNITPAGE7_BOARD_TEMP_NOT_PRESENT (0x00) | ||||
| #define MPI2_IOUNITPAGE7_BOARD_TEMP_FAHRENHEIT (0x01) | #define MPI2_IOUNITPAGE7_BOARD_TEMP_FAHRENHEIT (0x01) | ||||
| #define MPI2_IOUNITPAGE7_BOARD_TEMP_CELSIUS (0x02) | #define MPI2_IOUNITPAGE7_BOARD_TEMP_CELSIUS (0x02) | ||||
| /* defines for IO Unit Page 7 Flags field */ | |||||
| #define MPI2_IOUNITPAGE7_FLAG_CABLE_POWER_EXC (0x01) | |||||
| /* IO Unit Page 8 */ | /* IO Unit Page 8 */ | ||||
| #define MPI2_IOUNIT8_NUM_THRESHOLDS (4) | #define MPI2_IOUNIT8_NUM_THRESHOLDS (4) | ||||
| typedef struct _MPI2_IOUNIT8_SENSOR | typedef struct _MPI2_IOUNIT8_SENSOR | ||||
| { | { | ||||
| U16 Flags; /* 0x00 */ | U16 Flags; /* 0x00 */ | ||||
| ▲ Show 20 Lines • Show All 102 Lines • ▼ Show 20 Lines | typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_10 | ||||
| U32 Reserved4; /* 0x0C */ | U32 Reserved4; /* 0x0C */ | ||||
| MPI2_IOUNIT10_FUNCTION Function[MPI2_IOUNITPAGE10_FUNCTION_ENTRIES]; /* 0x10 */ | MPI2_IOUNIT10_FUNCTION Function[MPI2_IOUNITPAGE10_FUNCTION_ENTRIES]; /* 0x10 */ | ||||
| } MPI2_CONFIG_PAGE_IO_UNIT_10, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_10, | } MPI2_CONFIG_PAGE_IO_UNIT_10, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_10, | ||||
| Mpi2IOUnitPage10_t, MPI2_POINTER pMpi2IOUnitPage10_t; | Mpi2IOUnitPage10_t, MPI2_POINTER pMpi2IOUnitPage10_t; | ||||
| #define MPI2_IOUNITPAGE10_PAGEVERSION (0x01) | #define MPI2_IOUNITPAGE10_PAGEVERSION (0x01) | ||||
| /* IO Unit Page 11 (for MPI v2.6 and later) */ | |||||
| typedef struct _MPI26_IOUNIT11_SPINUP_GROUP | |||||
| { | |||||
| U8 MaxTargetSpinup; /* 0x00 */ | |||||
| U8 SpinupDelay; /* 0x01 */ | |||||
| U8 SpinupFlags; /* 0x02 */ | |||||
| U8 Reserved1; /* 0x03 */ | |||||
| } MPI26_IOUNIT11_SPINUP_GROUP, MPI2_POINTER PTR_MPI26_IOUNIT11_SPINUP_GROUP, | |||||
| Mpi26IOUnit11SpinupGroup_t, MPI2_POINTER pMpi26IOUnit11SpinupGroup_t; | |||||
| /* defines for IO Unit Page 11 SpinupFlags */ | |||||
| #define MPI26_IOUNITPAGE11_SPINUP_DISABLE_FLAG (0x01) | |||||
| /* | |||||
| * Host code (drivers, BIOS, utilities, etc.) should leave this define set to | |||||
| * four and check the value returned for NumPhys at runtime. | |||||
| */ | |||||
| #ifndef MPI26_IOUNITPAGE11_PHY_MAX | |||||
| #define MPI26_IOUNITPAGE11_PHY_MAX (4) | |||||
| #endif | |||||
| typedef struct _MPI26_CONFIG_PAGE_IO_UNIT_11 | |||||
| { | |||||
| MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ | |||||
| U32 Reserved1; /* 0x04 */ | |||||
| MPI26_IOUNIT11_SPINUP_GROUP SpinupGroupParameters[4]; /* 0x08 */ | |||||
| U32 Reserved2; /* 0x18 */ | |||||
| U32 Reserved3; /* 0x1C */ | |||||
| U32 Reserved4; /* 0x20 */ | |||||
| U8 BootDeviceWaitTime; /* 0x24 */ | |||||
| U8 Reserved5; /* 0x25 */ | |||||
| U16 Reserved6; /* 0x26 */ | |||||
| U8 NumPhys; /* 0x28 */ | |||||
| U8 PEInitialSpinupDelay; /* 0x29 */ | |||||
| U8 PEReplyDelay; /* 0x2A */ | |||||
| U8 Flags; /* 0x2B */ | |||||
| U8 PHY[MPI26_IOUNITPAGE11_PHY_MAX];/* 0x2C */ | |||||
| } MPI26_CONFIG_PAGE_IO_UNIT_11, | |||||
| MPI2_POINTER PTR_MPI26_CONFIG_PAGE_IO_UNIT_11, | |||||
| Mpi26IOUnitPage11_t, MPI2_POINTER pMpi26IOUnitPage11_t; | |||||
| #define MPI26_IOUNITPAGE11_PAGEVERSION (0x00) | |||||
| /* defines for Flags field */ | |||||
| #define MPI26_IOUNITPAGE11_FLAGS_AUTO_PORTENABLE (0x01) | |||||
| /* defines for PHY field */ | |||||
| #define MPI26_IOUNITPAGE11_PHY_SPINUP_GROUP_MASK (0x03) | |||||
| /**************************************************************************** | /**************************************************************************** | ||||
| * IOC Config Pages | * IOC Config Pages | ||||
| ****************************************************************************/ | ****************************************************************************/ | ||||
| /* IOC Page 0 */ | /* IOC Page 0 */ | ||||
| typedef struct _MPI2_CONFIG_PAGE_IOC_0 | typedef struct _MPI2_CONFIG_PAGE_IOC_0 | ||||
| { | { | ||||
| ▲ Show 20 Lines • Show All 146 Lines • ▼ Show 20 Lines | |||||
| /* BIOS Page 1 */ | /* BIOS Page 1 */ | ||||
| typedef struct _MPI2_CONFIG_PAGE_BIOS_1 | typedef struct _MPI2_CONFIG_PAGE_BIOS_1 | ||||
| { | { | ||||
| MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ | MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ | ||||
| U32 BiosOptions; /* 0x04 */ | U32 BiosOptions; /* 0x04 */ | ||||
| U32 IOCSettings; /* 0x08 */ | U32 IOCSettings; /* 0x08 */ | ||||
| U32 Reserved1; /* 0x0C */ | U8 SSUTimeout; /* 0x0C */ | ||||
| U8 Reserved1; /* 0x0D */ | |||||
| U16 Reserved2; /* 0x0E */ | |||||
| U32 DeviceSettings; /* 0x10 */ | U32 DeviceSettings; /* 0x10 */ | ||||
| U16 NumberOfDevices; /* 0x14 */ | U16 NumberOfDevices; /* 0x14 */ | ||||
| U16 UEFIVersion; /* 0x16 */ | U16 UEFIVersion; /* 0x16 */ | ||||
| U16 IOTimeoutBlockDevicesNonRM; /* 0x18 */ | U16 IOTimeoutBlockDevicesNonRM; /* 0x18 */ | ||||
| U16 IOTimeoutSequential; /* 0x1A */ | U16 IOTimeoutSequential; /* 0x1A */ | ||||
| U16 IOTimeoutOther; /* 0x1C */ | U16 IOTimeoutOther; /* 0x1C */ | ||||
| U16 IOTimeoutBlockDevicesRM; /* 0x1E */ | U16 IOTimeoutBlockDevicesRM; /* 0x1E */ | ||||
| } MPI2_CONFIG_PAGE_BIOS_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_1, | } MPI2_CONFIG_PAGE_BIOS_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_1, | ||||
| Mpi2BiosPage1_t, MPI2_POINTER pMpi2BiosPage1_t; | Mpi2BiosPage1_t, MPI2_POINTER pMpi2BiosPage1_t; | ||||
| #define MPI2_BIOSPAGE1_PAGEVERSION (0x05) | #define MPI2_BIOSPAGE1_PAGEVERSION (0x07) | ||||
| /* values for BIOS Page 1 BiosOptions field */ | /* values for BIOS Page 1 BiosOptions field */ | ||||
| #define MPI2_BIOSPAGE1_OPTIONS_BOOT_LIST_ADD_ALT_BOOT_DEVICE (0x00008000) | |||||
| #define MPI2_BIOSPAGE1_OPTIONS_ADVANCED_CONFIG (0x00004000) | |||||
| #define MPI2_BIOSPAGE1_OPTIONS_PNS_MASK (0x00003800) | |||||
| #define MPI2_BIOSPAGE1_OPTIONS_PNS_PBDHL (0x00000000) | |||||
| #define MPI2_BIOSPAGE1_OPTIONS_PNS_ENCSLOSURE (0x00000800) | |||||
| #define MPI2_BIOSPAGE1_OPTIONS_PNS_LWWID (0x00001000) | |||||
| #define MPI2_BIOSPAGE1_OPTIONS_PNS_PSENS (0x00001800) | |||||
| #define MPI2_BIOSPAGE1_OPTIONS_PNS_ESPHY (0x00002000) | |||||
| #define MPI2_BIOSPAGE1_OPTIONS_X86_DISABLE_BIOS (0x00000400) | |||||
| #define MPI2_BIOSPAGE1_OPTIONS_MASK_REGISTRATION_UEFI_BSD (0x00000300) | |||||
| #define MPI2_BIOSPAGE1_OPTIONS_USE_BIT0_REGISTRATION_UEFI_BSD (0x00000000) | |||||
| #define MPI2_BIOSPAGE1_OPTIONS_FULL_REGISTRATION_UEFI_BSD (0x00000100) | |||||
| #define MPI2_BIOSPAGE1_OPTIONS_ADAPTER_REGISTRATION_UEFI_BSD (0x00000200) | |||||
| #define MPI2_BIOSPAGE1_OPTIONS_DISABLE_REGISTRATION_UEFI_BSD (0x00000300) | |||||
| #define MPI2_BIOSPAGE1_OPTIONS_MASK_OEM_ID (0x000000F0) | #define MPI2_BIOSPAGE1_OPTIONS_MASK_OEM_ID (0x000000F0) | ||||
| #define MPI2_BIOSPAGE1_OPTIONS_LSI_OEM_ID (0x00000000) | #define MPI2_BIOSPAGE1_OPTIONS_LSI_OEM_ID (0x00000000) | ||||
| #define MPI2_BIOSPAGE1_OPTIONS_MASK_UEFI_HII_REGISTRATION (0x00000006) | #define MPI2_BIOSPAGE1_OPTIONS_MASK_UEFI_HII_REGISTRATION (0x00000006) | ||||
| #define MPI2_BIOSPAGE1_OPTIONS_ENABLE_UEFI_HII (0x00000000) | #define MPI2_BIOSPAGE1_OPTIONS_ENABLE_UEFI_HII (0x00000000) | ||||
| #define MPI2_BIOSPAGE1_OPTIONS_DISABLE_UEFI_HII (0x00000002) | #define MPI2_BIOSPAGE1_OPTIONS_DISABLE_UEFI_HII (0x00000002) | ||||
| #define MPI2_BIOSPAGE1_OPTIONS_VERSION_CHECK_UEFI_HII (0x00000004) | #define MPI2_BIOSPAGE1_OPTIONS_VERSION_CHECK_UEFI_HII (0x00000004) | ||||
| #define MPI2_BIOSPAGE1_OPTIONS_DISABLE_BIOS (0x00000001) | #define MPI2_BIOSPAGE1_OPTIONS_DISABLE_BIOS (0x00000001) | ||||
| /* values for BIOS Page 1 IOCSettings field */ | /* values for BIOS Page 1 IOCSettings field */ | ||||
| #define MPI2_BIOSPAGE1_IOCSET_MASK_BOOT_PREFERENCE (0x00030000) | #define MPI2_BIOSPAGE1_IOCSET_MASK_BOOT_PREFERENCE (0x00030000) | ||||
| #define MPI2_BIOSPAGE1_IOCSET_ENCLOSURE_SLOT_BOOT (0x00000000) | #define MPI2_BIOSPAGE1_IOCSET_ENCLOSURE_SLOT_BOOT (0x00000000) | ||||
| #define MPI2_BIOSPAGE1_IOCSET_SAS_ADDRESS_BOOT (0x00010000) | #define MPI2_BIOSPAGE1_IOCSET_SAS_ADDRESS_BOOT (0x00010000) | ||||
| #define MPI2_BIOSPAGE1_IOCSET_MASK_RM_SETTING (0x000000C0) | #define MPI2_BIOSPAGE1_IOCSET_MASK_RM_SETTING (0x000000C0) | ||||
| #define MPI2_BIOSPAGE1_IOCSET_NONE_RM_SETTING (0x00000000) | #define MPI2_BIOSPAGE1_IOCSET_NONE_RM_SETTING (0x00000000) | ||||
| ▲ Show 20 Lines • Show All 107 Lines • ▼ Show 20 Lines | |||||
| #define MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED (0x00) | #define MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED (0x00) | ||||
| #define MPI2_BIOSPAGE2_FORM_SAS_WWID (0x05) | #define MPI2_BIOSPAGE2_FORM_SAS_WWID (0x05) | ||||
| #define MPI2_BIOSPAGE2_FORM_ENCLOSURE_SLOT (0x06) | #define MPI2_BIOSPAGE2_FORM_ENCLOSURE_SLOT (0x06) | ||||
| #define MPI2_BIOSPAGE2_FORM_DEVICE_NAME (0x07) | #define MPI2_BIOSPAGE2_FORM_DEVICE_NAME (0x07) | ||||
| /* BIOS Page 3 */ | /* BIOS Page 3 */ | ||||
| #define MPI2_BIOSPAGE3_NUM_ADAPTER (4) | |||||
| typedef struct _MPI2_ADAPTER_INFO | typedef struct _MPI2_ADAPTER_INFO | ||||
| { | { | ||||
| U8 PciBusNumber; /* 0x00 */ | U8 PciBusNumber; /* 0x00 */ | ||||
| U8 PciDeviceAndFunctionNumber; /* 0x01 */ | U8 PciDeviceAndFunctionNumber; /* 0x01 */ | ||||
| U16 AdapterFlags; /* 0x02 */ | U16 AdapterFlags; /* 0x02 */ | ||||
| } MPI2_ADAPTER_INFO, MPI2_POINTER PTR_MPI2_ADAPTER_INFO, | } MPI2_ADAPTER_INFO, MPI2_POINTER PTR_MPI2_ADAPTER_INFO, | ||||
| Mpi2AdapterInfo_t, MPI2_POINTER pMpi2AdapterInfo_t; | Mpi2AdapterInfo_t, MPI2_POINTER pMpi2AdapterInfo_t; | ||||
| #define MPI2_ADAPTER_INFO_FLAGS_EMBEDDED (0x0001) | #define MPI2_ADAPTER_INFO_FLAGS_EMBEDDED (0x0001) | ||||
| #define MPI2_ADAPTER_INFO_FLAGS_INIT_STATUS (0x0002) | #define MPI2_ADAPTER_INFO_FLAGS_INIT_STATUS (0x0002) | ||||
| typedef struct _MPI2_ADAPTER_ORDER_AUX | |||||
| { | |||||
| U64 WWID; /* 0x00 */ | |||||
| U32 Reserved1; /* 0x08 */ | |||||
| U32 Reserved2; /* 0x0C */ | |||||
| } MPI2_ADAPTER_ORDER_AUX, MPI2_POINTER PTR_MPI2_ADAPTER_ORDER_AUX, | |||||
| Mpi2AdapterOrderAux_t, MPI2_POINTER pMpi2AdapterOrderAux_t; | |||||
| typedef struct _MPI2_CONFIG_PAGE_BIOS_3 | typedef struct _MPI2_CONFIG_PAGE_BIOS_3 | ||||
| { | { | ||||
| MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ | MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ | ||||
| U32 GlobalFlags; /* 0x04 */ | U32 GlobalFlags; /* 0x04 */ | ||||
| U32 BiosVersion; /* 0x08 */ | U32 BiosVersion; /* 0x08 */ | ||||
| MPI2_ADAPTER_INFO AdapterOrder[4]; /* 0x0C */ | MPI2_ADAPTER_INFO AdapterOrder[MPI2_BIOSPAGE3_NUM_ADAPTER]; /* 0x0C */ | ||||
| U32 Reserved1; /* 0x1C */ | U32 Reserved1; /* 0x1C */ | ||||
| MPI2_ADAPTER_ORDER_AUX AdapterOrderAux[MPI2_BIOSPAGE3_NUM_ADAPTER]; /* 0x20 */ /* MPI v2.5 and newer */ | |||||
| } MPI2_CONFIG_PAGE_BIOS_3, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_3, | } MPI2_CONFIG_PAGE_BIOS_3, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_3, | ||||
| Mpi2BiosPage3_t, MPI2_POINTER pMpi2BiosPage3_t; | Mpi2BiosPage3_t, MPI2_POINTER pMpi2BiosPage3_t; | ||||
| #define MPI2_BIOSPAGE3_PAGEVERSION (0x00) | #define MPI2_BIOSPAGE3_PAGEVERSION (0x01) | ||||
| /* values for BIOS Page 3 GlobalFlags */ | /* values for BIOS Page 3 GlobalFlags */ | ||||
| #define MPI2_BIOSPAGE3_FLAGS_PAUSE_ON_ERROR (0x00000002) | #define MPI2_BIOSPAGE3_FLAGS_PAUSE_ON_ERROR (0x00000002) | ||||
| #define MPI2_BIOSPAGE3_FLAGS_VERBOSE_ENABLE (0x00000004) | #define MPI2_BIOSPAGE3_FLAGS_VERBOSE_ENABLE (0x00000004) | ||||
| #define MPI2_BIOSPAGE3_FLAGS_HOOK_INT_40_DISABLE (0x00000010) | #define MPI2_BIOSPAGE3_FLAGS_HOOK_INT_40_DISABLE (0x00000010) | ||||
| #define MPI2_BIOSPAGE3_FLAGS_DEV_LIST_DISPLAY_MASK (0x000000E0) | #define MPI2_BIOSPAGE3_FLAGS_DEV_LIST_DISPLAY_MASK (0x000000E0) | ||||
| #define MPI2_BIOSPAGE3_FLAGS_INSTALLED_DEV_DISPLAY (0x00000000) | #define MPI2_BIOSPAGE3_FLAGS_INSTALLED_DEV_DISPLAY (0x00000000) | ||||
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| #define MPI2_SASIOUNITPAGE0_PAGEVERSION (0x05) | #define MPI2_SASIOUNITPAGE0_PAGEVERSION (0x05) | ||||
| /* values for SAS IO Unit Page 0 PortFlags */ | /* values for SAS IO Unit Page 0 PortFlags */ | ||||
| #define MPI2_SASIOUNIT0_PORTFLAGS_DISCOVERY_IN_PROGRESS (0x08) | #define MPI2_SASIOUNIT0_PORTFLAGS_DISCOVERY_IN_PROGRESS (0x08) | ||||
| #define MPI2_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG (0x01) | #define MPI2_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG (0x01) | ||||
| /* values for SAS IO Unit Page 0 PhyFlags */ | /* values for SAS IO Unit Page 0 PhyFlags */ | ||||
| #define MPI2_SASIOUNIT0_PHYFLAGS_INIT_PERSIST_CONNECT (0x40) | |||||
| #define MPI2_SASIOUNIT0_PHYFLAGS_TARG_PERSIST_CONNECT (0x20) | |||||
| #define MPI2_SASIOUNIT0_PHYFLAGS_ZONING_ENABLED (0x10) | #define MPI2_SASIOUNIT0_PHYFLAGS_ZONING_ENABLED (0x10) | ||||
| #define MPI2_SASIOUNIT0_PHYFLAGS_PHY_DISABLED (0x08) | #define MPI2_SASIOUNIT0_PHYFLAGS_PHY_DISABLED (0x08) | ||||
| /* use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */ | /* use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */ | ||||
| /* see mpi2_sas.h for values for SAS IO Unit Page 0 ControllerPhyDeviceInfo values */ | /* see mpi2_sas.h for values for SAS IO Unit Page 0 ControllerPhyDeviceInfo values */ | ||||
| /* values for SAS IO Unit Page 0 DiscoveryStatus */ | /* values for SAS IO Unit Page 0 DiscoveryStatus */ | ||||
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| #define MPI2_SASIOUNIT1_CONTROL_SATA_NCQ_REQUIRED (0x0020) | #define MPI2_SASIOUNIT1_CONTROL_SATA_NCQ_REQUIRED (0x0020) | ||||
| #define MPI2_SASIOUNIT1_CONTROL_SATA_FUA_REQUIRED (0x0010) | #define MPI2_SASIOUNIT1_CONTROL_SATA_FUA_REQUIRED (0x0010) | ||||
| #define MPI2_SASIOUNIT1_CONTROL_TABLE_SUBTRACTIVE_ILLEGAL (0x0008) | #define MPI2_SASIOUNIT1_CONTROL_TABLE_SUBTRACTIVE_ILLEGAL (0x0008) | ||||
| #define MPI2_SASIOUNIT1_CONTROL_SUBTRACTIVE_ILLEGAL (0x0004) | #define MPI2_SASIOUNIT1_CONTROL_SUBTRACTIVE_ILLEGAL (0x0004) | ||||
| #define MPI2_SASIOUNIT1_CONTROL_FIRST_LVL_DISC_ONLY (0x0002) | #define MPI2_SASIOUNIT1_CONTROL_FIRST_LVL_DISC_ONLY (0x0002) | ||||
| #define MPI2_SASIOUNIT1_CONTROL_CLEAR_AFFILIATION (0x0001) /* MPI v2.0 only. Obsolete in MPI v2.5 and later. */ | #define MPI2_SASIOUNIT1_CONTROL_CLEAR_AFFILIATION (0x0001) /* MPI v2.0 only. Obsolete in MPI v2.5 and later. */ | ||||
| /* values for SAS IO Unit Page 1 AdditionalControlFlags */ | /* values for SAS IO Unit Page 1 AdditionalControlFlags */ | ||||
| #define MPI2_SASIOUNIT1_ACONTROL_DA_PERSIST_CONNECT (0x0100) | |||||
| #define MPI2_SASIOUNIT1_ACONTROL_MULTI_PORT_DOMAIN_ILLEGAL (0x0080) | #define MPI2_SASIOUNIT1_ACONTROL_MULTI_PORT_DOMAIN_ILLEGAL (0x0080) | ||||
| #define MPI2_SASIOUNIT1_ACONTROL_SATA_ASYNCHROUNOUS_NOTIFICATION (0x0040) | #define MPI2_SASIOUNIT1_ACONTROL_SATA_ASYNCHROUNOUS_NOTIFICATION (0x0040) | ||||
| #define MPI2_SASIOUNIT1_ACONTROL_INVALID_TOPOLOGY_CORRECTION (0x0020) | #define MPI2_SASIOUNIT1_ACONTROL_INVALID_TOPOLOGY_CORRECTION (0x0020) | ||||
| #define MPI2_SASIOUNIT1_ACONTROL_PORT_ENABLE_ONLY_SATA_LINK_RESET (0x0010) | #define MPI2_SASIOUNIT1_ACONTROL_PORT_ENABLE_ONLY_SATA_LINK_RESET (0x0010) | ||||
| #define MPI2_SASIOUNIT1_ACONTROL_OTHER_AFFILIATION_SATA_LINK_RESET (0x0008) | #define MPI2_SASIOUNIT1_ACONTROL_OTHER_AFFILIATION_SATA_LINK_RESET (0x0008) | ||||
| #define MPI2_SASIOUNIT1_ACONTROL_SELF_AFFILIATION_SATA_LINK_RESET (0x0004) | #define MPI2_SASIOUNIT1_ACONTROL_SELF_AFFILIATION_SATA_LINK_RESET (0x0004) | ||||
| #define MPI2_SASIOUNIT1_ACONTROL_NO_AFFILIATION_SATA_LINK_RESET (0x0002) | #define MPI2_SASIOUNIT1_ACONTROL_NO_AFFILIATION_SATA_LINK_RESET (0x0002) | ||||
| #define MPI2_SASIOUNIT1_ACONTROL_ALLOW_TABLE_TO_TABLE (0x0001) | #define MPI2_SASIOUNIT1_ACONTROL_ALLOW_TABLE_TO_TABLE (0x0001) | ||||
| /* defines for SAS IO Unit Page 1 ReportDeviceMissingDelay */ | /* defines for SAS IO Unit Page 1 ReportDeviceMissingDelay */ | ||||
| #define MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK (0x7F) | #define MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK (0x7F) | ||||
| #define MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16 (0x80) | #define MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16 (0x80) | ||||
| /* values for SAS IO Unit Page 1 PortFlags */ | /* values for SAS IO Unit Page 1 PortFlags */ | ||||
| #define MPI2_SASIOUNIT1_PORT_FLAGS_AUTO_PORT_CONFIG (0x01) | #define MPI2_SASIOUNIT1_PORT_FLAGS_AUTO_PORT_CONFIG (0x01) | ||||
| /* values for SAS IO Unit Page 1 PhyFlags */ | /* values for SAS IO Unit Page 1 PhyFlags */ | ||||
| #define MPI2_SASIOUNIT1_PHYFLAGS_INIT_PERSIST_CONNECT (0x40) | |||||
| #define MPI2_SASIOUNIT1_PHYFLAGS_TARG_PERSIST_CONNECT (0x20) | |||||
| #define MPI2_SASIOUNIT1_PHYFLAGS_ZONING_ENABLE (0x10) | #define MPI2_SASIOUNIT1_PHYFLAGS_ZONING_ENABLE (0x10) | ||||
| #define MPI2_SASIOUNIT1_PHYFLAGS_PHY_DISABLE (0x08) | #define MPI2_SASIOUNIT1_PHYFLAGS_PHY_DISABLE (0x08) | ||||
| /* values for SAS IO Unit Page 1 MaxMinLinkRate */ | /* values for SAS IO Unit Page 1 MaxMinLinkRate */ | ||||
| #define MPI2_SASIOUNIT1_MAX_RATE_MASK (0xF0) | #define MPI2_SASIOUNIT1_MAX_RATE_MASK (0xF0) | ||||
| #define MPI2_SASIOUNIT1_MAX_RATE_1_5 (0x80) | #define MPI2_SASIOUNIT1_MAX_RATE_1_5 (0x80) | ||||
| #define MPI2_SASIOUNIT1_MAX_RATE_3_0 (0x90) | #define MPI2_SASIOUNIT1_MAX_RATE_3_0 (0x90) | ||||
| #define MPI2_SASIOUNIT1_MAX_RATE_6_0 (0xA0) | #define MPI2_SASIOUNIT1_MAX_RATE_6_0 (0xA0) | ||||
| #define MPI25_SASIOUNIT1_MAX_RATE_12_0 (0xB0) | #define MPI25_SASIOUNIT1_MAX_RATE_12_0 (0xB0) | ||||
| #define MPI2_SASIOUNIT1_MIN_RATE_MASK (0x0F) | #define MPI2_SASIOUNIT1_MIN_RATE_MASK (0x0F) | ||||
| #define MPI2_SASIOUNIT1_MIN_RATE_1_5 (0x08) | #define MPI2_SASIOUNIT1_MIN_RATE_1_5 (0x08) | ||||
| #define MPI2_SASIOUNIT1_MIN_RATE_3_0 (0x09) | #define MPI2_SASIOUNIT1_MIN_RATE_3_0 (0x09) | ||||
| #define MPI2_SASIOUNIT1_MIN_RATE_6_0 (0x0A) | #define MPI2_SASIOUNIT1_MIN_RATE_6_0 (0x0A) | ||||
| #define MPI25_SASIOUNIT1_MIN_RATE_12_0 (0x0B) | #define MPI25_SASIOUNIT1_MIN_RATE_12_0 (0x0B) | ||||
| /* see mpi2_sas.h for values for SAS IO Unit Page 1 ControllerPhyDeviceInfo values */ | /* see mpi2_sas.h for values for SAS IO Unit Page 1 ControllerPhyDeviceInfo values */ | ||||
| /* SAS IO Unit Page 4 */ | /* SAS IO Unit Page 4 (for MPI v2.5 and earlier) */ | ||||
| typedef struct _MPI2_SAS_IOUNIT4_SPINUP_GROUP | typedef struct _MPI2_SAS_IOUNIT4_SPINUP_GROUP | ||||
| { | { | ||||
| U8 MaxTargetSpinup; /* 0x00 */ | U8 MaxTargetSpinup; /* 0x00 */ | ||||
| U8 SpinupDelay; /* 0x01 */ | U8 SpinupDelay; /* 0x01 */ | ||||
| U8 SpinupFlags; /* 0x02 */ | U8 SpinupFlags; /* 0x02 */ | ||||
| U8 Reserved1; /* 0x03 */ | U8 Reserved1; /* 0x03 */ | ||||
| } MPI2_SAS_IOUNIT4_SPINUP_GROUP, MPI2_POINTER PTR_MPI2_SAS_IOUNIT4_SPINUP_GROUP, | } MPI2_SAS_IOUNIT4_SPINUP_GROUP, MPI2_POINTER PTR_MPI2_SAS_IOUNIT4_SPINUP_GROUP, | ||||
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| typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_4 | typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_4 | ||||
| { | { | ||||
| MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ | MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ | ||||
| MPI2_SAS_IOUNIT4_SPINUP_GROUP SpinupGroupParameters[4]; /* 0x08 */ | MPI2_SAS_IOUNIT4_SPINUP_GROUP SpinupGroupParameters[4]; /* 0x08 */ | ||||
| U32 Reserved1; /* 0x18 */ | U32 Reserved1; /* 0x18 */ | ||||
| U32 Reserved2; /* 0x1C */ | U32 Reserved2; /* 0x1C */ | ||||
| U32 Reserved3; /* 0x20 */ | U32 Reserved3; /* 0x20 */ | ||||
| U8 BootDeviceWaitTime; /* 0x24 */ | U8 BootDeviceWaitTime; /* 0x24 */ | ||||
| U8 Reserved4; /* 0x25 */ | U8 SATADeviceWaitTime; /* 0x25 */ | ||||
| U16 Reserved5; /* 0x26 */ | U16 Reserved5; /* 0x26 */ | ||||
| U8 NumPhys; /* 0x28 */ | U8 NumPhys; /* 0x28 */ | ||||
| U8 PEInitialSpinupDelay; /* 0x29 */ | U8 PEInitialSpinupDelay; /* 0x29 */ | ||||
| U8 PEReplyDelay; /* 0x2A */ | U8 PEReplyDelay; /* 0x2A */ | ||||
| U8 Flags; /* 0x2B */ | U8 Flags; /* 0x2B */ | ||||
| U8 PHY[MPI2_SAS_IOUNIT4_PHY_MAX]; /* 0x2C */ | U8 PHY[MPI2_SAS_IOUNIT4_PHY_MAX]; /* 0x2C */ | ||||
| } MPI2_CONFIG_PAGE_SASIOUNIT_4, | } MPI2_CONFIG_PAGE_SASIOUNIT_4, | ||||
| MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_4, | MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_4, | ||||
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| #define MPI2_SAS_DEVICE0_FLAGS_SATA_ASYNCHRONOUS_NOTIFY (0x0400) | #define MPI2_SAS_DEVICE0_FLAGS_SATA_ASYNCHRONOUS_NOTIFY (0x0400) | ||||
| #define MPI2_SAS_DEVICE0_FLAGS_SATA_SW_PRESERVE (0x0200) | #define MPI2_SAS_DEVICE0_FLAGS_SATA_SW_PRESERVE (0x0200) | ||||
| #define MPI2_SAS_DEVICE0_FLAGS_UNSUPPORTED_DEVICE (0x0100) | #define MPI2_SAS_DEVICE0_FLAGS_UNSUPPORTED_DEVICE (0x0100) | ||||
| #define MPI2_SAS_DEVICE0_FLAGS_SATA_48BIT_LBA_SUPPORTED (0x0080) | #define MPI2_SAS_DEVICE0_FLAGS_SATA_48BIT_LBA_SUPPORTED (0x0080) | ||||
| #define MPI2_SAS_DEVICE0_FLAGS_SATA_SMART_SUPPORTED (0x0040) | #define MPI2_SAS_DEVICE0_FLAGS_SATA_SMART_SUPPORTED (0x0040) | ||||
| #define MPI2_SAS_DEVICE0_FLAGS_SATA_NCQ_SUPPORTED (0x0020) | #define MPI2_SAS_DEVICE0_FLAGS_SATA_NCQ_SUPPORTED (0x0020) | ||||
| #define MPI2_SAS_DEVICE0_FLAGS_SATA_FUA_SUPPORTED (0x0010) | #define MPI2_SAS_DEVICE0_FLAGS_SATA_FUA_SUPPORTED (0x0010) | ||||
| #define MPI2_SAS_DEVICE0_FLAGS_PORT_SELECTOR_ATTACH (0x0008) | #define MPI2_SAS_DEVICE0_FLAGS_PORT_SELECTOR_ATTACH (0x0008) | ||||
| #define MPI2_SAS_DEVICE0_FLAGS_PERSIST_CAPABLE (0x0004) | |||||
| #define MPI2_SAS_DEVICE0_FLAGS_ENCL_LEVEL_VALID (0x0002) | #define MPI2_SAS_DEVICE0_FLAGS_ENCL_LEVEL_VALID (0x0002) | ||||
| #define MPI2_SAS_DEVICE0_FLAGS_DEVICE_PRESENT (0x0001) | #define MPI2_SAS_DEVICE0_FLAGS_DEVICE_PRESENT (0x0001) | ||||
| /* SAS Device Page 1 */ | /* SAS Device Page 1 */ | ||||
| typedef struct _MPI2_CONFIG_PAGE_SAS_DEV_1 | typedef struct _MPI2_CONFIG_PAGE_SAS_DEV_1 | ||||
| { | { | ||||
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| #define MPI2_SASPHY3_EVENT_CODE_RX_SATA_FRAMES (0x51) | #define MPI2_SASPHY3_EVENT_CODE_RX_SATA_FRAMES (0x51) | ||||
| #define MPI2_SASPHY3_EVENT_CODE_SATA_OVERFLOW (0x52) | #define MPI2_SASPHY3_EVENT_CODE_SATA_OVERFLOW (0x52) | ||||
| #define MPI2_SASPHY3_EVENT_CODE_TX_SMP_FRAMES (0x60) | #define MPI2_SASPHY3_EVENT_CODE_TX_SMP_FRAMES (0x60) | ||||
| #define MPI2_SASPHY3_EVENT_CODE_RX_SMP_FRAMES (0x61) | #define MPI2_SASPHY3_EVENT_CODE_RX_SMP_FRAMES (0x61) | ||||
| #define MPI2_SASPHY3_EVENT_CODE_RX_SMP_ERROR_FRAMES (0x63) | #define MPI2_SASPHY3_EVENT_CODE_RX_SMP_ERROR_FRAMES (0x63) | ||||
| #define MPI2_SASPHY3_EVENT_CODE_HOTPLUG_TIMEOUT (0xD0) | #define MPI2_SASPHY3_EVENT_CODE_HOTPLUG_TIMEOUT (0xD0) | ||||
| #define MPI2_SASPHY3_EVENT_CODE_MISALIGNED_MUX_PRIMITIVE (0xD1) | #define MPI2_SASPHY3_EVENT_CODE_MISALIGNED_MUX_PRIMITIVE (0xD1) | ||||
| #define MPI2_SASPHY3_EVENT_CODE_RX_AIP (0xD2) | #define MPI2_SASPHY3_EVENT_CODE_RX_AIP (0xD2) | ||||
| /* Following codes are product specific and in MPI v2.6 and later */ | |||||
| #define MPI2_SASPHY3_EVENT_CODE_LCARB_WAIT_TIME (0xD3) | |||||
| #define MPI2_SASPHY3_EVENT_CODE_RCVD_CONN_RESP_WAIT_TIME (0xD4) | |||||
| #define MPI2_SASPHY3_EVENT_CODE_LCCONN_TIME (0xD5) | |||||
| #define MPI2_SASPHY3_EVENT_CODE_SSP_TX_START_TRANSMIT (0xD6) | |||||
| #define MPI2_SASPHY3_EVENT_CODE_SATA_TX_START (0xD7) | |||||
| #define MPI2_SASPHY3_EVENT_CODE_SMP_TX_START_TRANSMT (0xD8) | |||||
| #define MPI2_SASPHY3_EVENT_CODE_TX_SMP_BREAK_CONN (0xD9) | |||||
| #define MPI2_SASPHY3_EVENT_CODE_SSP_RX_START_RECEIVE (0xDA) | |||||
| #define MPI2_SASPHY3_EVENT_CODE_SATA_RX_START_RECEIVE (0xDB) | |||||
| #define MPI2_SASPHY3_EVENT_CODE_SMP_RX_START_RECEIVE (0xDC) | |||||
| /* values for the CounterType field */ | /* values for the CounterType field */ | ||||
| #define MPI2_SASPHY3_COUNTER_TYPE_WRAPPING (0x00) | #define MPI2_SASPHY3_COUNTER_TYPE_WRAPPING (0x00) | ||||
| #define MPI2_SASPHY3_COUNTER_TYPE_SATURATING (0x01) | #define MPI2_SASPHY3_COUNTER_TYPE_SATURATING (0x01) | ||||
| #define MPI2_SASPHY3_COUNTER_TYPE_PEAK_VALUE (0x02) | #define MPI2_SASPHY3_COUNTER_TYPE_PEAK_VALUE (0x02) | ||||
| /* values for the TimeUnits field */ | /* values for the TimeUnits field */ | ||||
| #define MPI2_SASPHY3_TIME_UNITS_10_MICROSECONDS (0x00) | #define MPI2_SASPHY3_TIME_UNITS_10_MICROSECONDS (0x00) | ||||
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