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sys/dev/mpr/mpi/mpi2.h
/*- | /*- | ||||
* Copyright (c) 2012-2015 LSI Corp. | * Copyright (c) 2012-2015 LSI Corp. | ||||
* Copyright (c) 2013-2015 Avago Technologies | * Copyright (c) 2013-2016 Avago Technologies | ||||
* All rights reserved. | * All rights reserved. | ||||
* | * | ||||
* Redistribution and use in source and binary forms, with or without | * Redistribution and use in source and binary forms, with or without | ||||
* modification, are permitted provided that the following conditions | * modification, are permitted provided that the following conditions | ||||
* are met: | * are met: | ||||
* 1. Redistributions of source code must retain the above copyright | * 1. Redistributions of source code must retain the above copyright | ||||
* notice, this list of conditions and the following disclaimer. | * notice, this list of conditions and the following disclaimer. | ||||
* 2. Redistributions in binary form must reproduce the above copyright | * 2. Redistributions in binary form must reproduce the above copyright | ||||
Show All 17 Lines | |||||
* | * | ||||
* Avago Technologies (LSI) MPT-Fusion Host Adapter FreeBSD | * Avago Technologies (LSI) MPT-Fusion Host Adapter FreeBSD | ||||
* | * | ||||
* $FreeBSD$ | * $FreeBSD$ | ||||
*/ | */ | ||||
/* | /* | ||||
* Copyright (c) 2000-2015 LSI Corporation. | * Copyright (c) 2000-2015 LSI Corporation. | ||||
* Copyright (c) 2013-2015 Avago Technologies | * Copyright (c) 2013-2016 Avago Technologies | ||||
* All rights reserved. | |||||
* | * | ||||
* | * | ||||
* Name: mpi2.h | * Name: mpi2.h | ||||
* Title: MPI Message independent structures and definitions | * Title: MPI Message independent structures and definitions | ||||
* including System Interface Register Set and | * including System Interface Register Set and | ||||
* scatter/gather formats. | * scatter/gather formats. | ||||
* Creation Date: June 21, 2006 | * Creation Date: June 21, 2006 | ||||
* | * | ||||
* mpi2.h Version: 02.00.33 | * mpi2.h Version: 02.00.42 | ||||
* | * | ||||
* NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25 | * NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25 | ||||
* prefix are for use only on MPI v2.5 products, and must not be used | * prefix are for use only on MPI v2.5 products, and must not be used | ||||
* with MPI v2.0 products. Unless otherwise noted, names beginning with | * with MPI v2.0 products. Unless otherwise noted, names beginning with | ||||
* MPI2 or Mpi2 are for use with both MPI v2.0 and MPI v2.5 products. | * MPI2 or Mpi2 are for use with both MPI v2.0 and MPI v2.5 products. | ||||
* | * | ||||
* Version History | * Version History | ||||
* --------------- | * --------------- | ||||
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* 07-26-12 02.00.27 Bumped MPI2_HEADER_VERSION_UNIT. | * 07-26-12 02.00.27 Bumped MPI2_HEADER_VERSION_UNIT. | ||||
* 11-27-12 02.00.28 Bumped MPI2_HEADER_VERSION_UNIT. | * 11-27-12 02.00.28 Bumped MPI2_HEADER_VERSION_UNIT. | ||||
* 12-20-12 02.00.29 Bumped MPI2_HEADER_VERSION_UNIT. | * 12-20-12 02.00.29 Bumped MPI2_HEADER_VERSION_UNIT. | ||||
* Added MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET. | * Added MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET. | ||||
* 04-09-13 02.00.30 Bumped MPI2_HEADER_VERSION_UNIT. | * 04-09-13 02.00.30 Bumped MPI2_HEADER_VERSION_UNIT. | ||||
* 04-17-13 02.00.31 Bumped MPI2_HEADER_VERSION_UNIT. | * 04-17-13 02.00.31 Bumped MPI2_HEADER_VERSION_UNIT. | ||||
* 08-19-13 02.00.32 Bumped MPI2_HEADER_VERSION_UNIT. | * 08-19-13 02.00.32 Bumped MPI2_HEADER_VERSION_UNIT. | ||||
* 12-05-13 02.00.33 Bumped MPI2_HEADER_VERSION_UNIT. | * 12-05-13 02.00.33 Bumped MPI2_HEADER_VERSION_UNIT. | ||||
* 01-08-14 02.00.34 Bumped MPI2_HEADER_VERSION_UNIT. | |||||
* 06-13-14 02.00.35 Bumped MPI2_HEADER_VERSION_UNIT. | |||||
* 11-18-14 02.00.36 Updated copyright information. | |||||
* Bumped MPI2_HEADER_VERSION_UNIT. | |||||
* 03-16-15 02.00.37 Updated for MPI v2.6. | |||||
* Bumped MPI2_HEADER_VERSION_UNIT. | |||||
* Added Scratchpad registers to | |||||
* MPI2_SYSTEM_INTERFACE_REGS. | |||||
* Added MPI2_DIAG_SBR_RELOAD. | |||||
* Added MPI2_IOCSTATUS_INSUFFICIENT_POWER. | |||||
* 03-19-15 02.00.38 Bumped MPI2_HEADER_VERSION_UNIT. | |||||
* 05-25-15 02.00.39 Bumped MPI2_HEADER_VERSION_UNIT | |||||
* 08-25-15 02.00.40 Bumped MPI2_HEADER_VERSION_UNIT. | |||||
* Added V7 HostDiagnostic register defines | |||||
* 12-15-15 02.00.41 Bumped MPI_HEADER_VERSION_UNIT | |||||
* 01-01-16 02.00.42 Bumped MPI_HEADER_VERSION_UNIT | |||||
* -------------------------------------------------------------------------- | * -------------------------------------------------------------------------- | ||||
*/ | */ | ||||
#ifndef MPI2_H | #ifndef MPI2_H | ||||
#define MPI2_H | #define MPI2_H | ||||
/***************************************************************************** | /***************************************************************************** | ||||
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/* minor version for MPI v2.5 compatible products */ | /* minor version for MPI v2.5 compatible products */ | ||||
#define MPI25_VERSION_MINOR (0x05) | #define MPI25_VERSION_MINOR (0x05) | ||||
#define MPI25_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \ | #define MPI25_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \ | ||||
MPI25_VERSION_MINOR) | MPI25_VERSION_MINOR) | ||||
#define MPI2_VERSION_02_05 (0x0205) | #define MPI2_VERSION_02_05 (0x0205) | ||||
/* minor version for MPI v2.6 compatible products */ | |||||
#define MPI26_VERSION_MINOR (0x06) | |||||
#define MPI26_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \ | |||||
MPI26_VERSION_MINOR) | |||||
#define MPI2_VERSION_02_06 (0x0206) | |||||
/* Unit and Dev versioning for this MPI header set */ | /* Unit and Dev versioning for this MPI header set */ | ||||
#define MPI2_HEADER_VERSION_UNIT (0x21) | #define MPI2_HEADER_VERSION_UNIT (0x2A) | ||||
#define MPI2_HEADER_VERSION_DEV (0x00) | #define MPI2_HEADER_VERSION_DEV (0x00) | ||||
#define MPI2_HEADER_VERSION_UNIT_MASK (0xFF00) | #define MPI2_HEADER_VERSION_UNIT_MASK (0xFF00) | ||||
#define MPI2_HEADER_VERSION_UNIT_SHIFT (8) | #define MPI2_HEADER_VERSION_UNIT_SHIFT (8) | ||||
#define MPI2_HEADER_VERSION_DEV_MASK (0x00FF) | #define MPI2_HEADER_VERSION_DEV_MASK (0x00FF) | ||||
#define MPI2_HEADER_VERSION_DEV_SHIFT (0) | #define MPI2_HEADER_VERSION_DEV_SHIFT (0) | ||||
#define MPI2_HEADER_VERSION ((MPI2_HEADER_VERSION_UNIT << 8) | MPI2_HEADER_VERSION_DEV) | #define MPI2_HEADER_VERSION ((MPI2_HEADER_VERSION_UNIT << 8) | MPI2_HEADER_VERSION_DEV) | ||||
Show All 39 Lines | typedef volatile struct _MPI2_SYSTEM_INTERFACE_REGS | ||||
U32 Reserved3[2]; /* 0x40 */ | U32 Reserved3[2]; /* 0x40 */ | ||||
U32 ReplyFreeHostIndex; /* 0x48 */ | U32 ReplyFreeHostIndex; /* 0x48 */ | ||||
U32 Reserved4[8]; /* 0x4C */ | U32 Reserved4[8]; /* 0x4C */ | ||||
U32 ReplyPostHostIndex; /* 0x6C */ | U32 ReplyPostHostIndex; /* 0x6C */ | ||||
U32 Reserved5; /* 0x70 */ | U32 Reserved5; /* 0x70 */ | ||||
U32 HCBSize; /* 0x74 */ | U32 HCBSize; /* 0x74 */ | ||||
U32 HCBAddressLow; /* 0x78 */ | U32 HCBAddressLow; /* 0x78 */ | ||||
U32 HCBAddressHigh; /* 0x7C */ | U32 HCBAddressHigh; /* 0x7C */ | ||||
U32 Reserved6[16]; /* 0x80 */ | U32 Reserved6[12]; /* 0x80 */ | ||||
U32 Scratchpad[4]; /* 0xB0 */ | |||||
U32 RequestDescriptorPostLow; /* 0xC0 */ | U32 RequestDescriptorPostLow; /* 0xC0 */ | ||||
U32 RequestDescriptorPostHigh; /* 0xC4 */ | U32 RequestDescriptorPostHigh; /* 0xC4 */ | ||||
U32 Reserved7[14]; /* 0xC8 */ | U32 Reserved7[14]; /* 0xC8 */ | ||||
} MPI2_SYSTEM_INTERFACE_REGS, MPI2_POINTER PTR_MPI2_SYSTEM_INTERFACE_REGS, | } MPI2_SYSTEM_INTERFACE_REGS, MPI2_POINTER PTR_MPI2_SYSTEM_INTERFACE_REGS, | ||||
Mpi2SystemInterfaceRegs_t, MPI2_POINTER pMpi2SystemInterfaceRegs_t; | Mpi2SystemInterfaceRegs_t, MPI2_POINTER pMpi2SystemInterfaceRegs_t; | ||||
/* | /* | ||||
* Defines for working with the Doorbell register. | * Defines for working with the Doorbell register. | ||||
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#define MPI2_WRSEQ_5TH_KEY_VALUE (0x7) | #define MPI2_WRSEQ_5TH_KEY_VALUE (0x7) | ||||
#define MPI2_WRSEQ_6TH_KEY_VALUE (0xD) | #define MPI2_WRSEQ_6TH_KEY_VALUE (0xD) | ||||
/* | /* | ||||
* Defines for the HostDiagnostic register | * Defines for the HostDiagnostic register | ||||
*/ | */ | ||||
#define MPI2_HOST_DIAGNOSTIC_OFFSET (0x00000008) | #define MPI2_HOST_DIAGNOSTIC_OFFSET (0x00000008) | ||||
#define MPI2_DIAG_SBR_RELOAD (0x00002000) | |||||
#define MPI2_DIAG_BOOT_DEVICE_SELECT_MASK (0x00001800) | #define MPI2_DIAG_BOOT_DEVICE_SELECT_MASK (0x00001800) | ||||
#define MPI2_DIAG_BOOT_DEVICE_SELECT_DEFAULT (0x00000000) | #define MPI2_DIAG_BOOT_DEVICE_SELECT_DEFAULT (0x00000000) | ||||
#define MPI2_DIAG_BOOT_DEVICE_SELECT_HCDW (0x00000800) | #define MPI2_DIAG_BOOT_DEVICE_SELECT_HCDW (0x00000800) | ||||
/* Defines for V7A/V7R HostDiagnostic Register */ | |||||
#define MPI26_DIAG_BOOT_DEVICE_SELECT_FLASH64 (0x00000000) | |||||
#define MPI26_DIAG_BOOT_DEVICE_SELECT_HCDW64 (0x00000800) | |||||
#define MPI26_DIAG_BOOT_DEVICE_SELECT_FLASH32 (0x00001000) | |||||
#define MPI26_DIAG_BOOT_DEVICE_SELECT_HCDW32 (0x00001800) | |||||
#define MPI2_DIAG_CLEAR_FLASH_BAD_SIG (0x00000400) | #define MPI2_DIAG_CLEAR_FLASH_BAD_SIG (0x00000400) | ||||
#define MPI2_DIAG_FORCE_HCB_ON_RESET (0x00000200) | #define MPI2_DIAG_FORCE_HCB_ON_RESET (0x00000200) | ||||
#define MPI2_DIAG_HCB_MODE (0x00000100) | #define MPI2_DIAG_HCB_MODE (0x00000100) | ||||
#define MPI2_DIAG_DIAG_WRITE_ENABLE (0x00000080) | #define MPI2_DIAG_DIAG_WRITE_ENABLE (0x00000080) | ||||
#define MPI2_DIAG_FLASH_BAD_SIG (0x00000040) | #define MPI2_DIAG_FLASH_BAD_SIG (0x00000040) | ||||
#define MPI2_DIAG_RESET_HISTORY (0x00000020) | #define MPI2_DIAG_RESET_HISTORY (0x00000020) | ||||
#define MPI2_DIAG_DIAG_RW_ENABLE (0x00000010) | #define MPI2_DIAG_DIAG_RW_ENABLE (0x00000010) | ||||
#define MPI2_DIAG_RESET_ADAPTER (0x00000004) | #define MPI2_DIAG_RESET_ADAPTER (0x00000004) | ||||
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#define MPI2_HCB_SIZE_OFFSET (0x00000074) | #define MPI2_HCB_SIZE_OFFSET (0x00000074) | ||||
#define MPI2_HCB_SIZE_SIZE_MASK (0xFFFFF000) | #define MPI2_HCB_SIZE_SIZE_MASK (0xFFFFF000) | ||||
#define MPI2_HCB_SIZE_HCB_ENABLE (0x00000001) | #define MPI2_HCB_SIZE_HCB_ENABLE (0x00000001) | ||||
#define MPI2_HCB_ADDRESS_LOW_OFFSET (0x00000078) | #define MPI2_HCB_ADDRESS_LOW_OFFSET (0x00000078) | ||||
#define MPI2_HCB_ADDRESS_HIGH_OFFSET (0x0000007C) | #define MPI2_HCB_ADDRESS_HIGH_OFFSET (0x0000007C) | ||||
/* | /* | ||||
* Offsets for the Request Queue | * Offsets for the Scratchpad registers | ||||
*/ | */ | ||||
#define MPI26_SCRATCHPAD0_OFFSET (0x000000B0) | |||||
#define MPI26_SCRATCHPAD1_OFFSET (0x000000B4) | |||||
#define MPI26_SCRATCHPAD2_OFFSET (0x000000B8) | |||||
#define MPI26_SCRATCHPAD3_OFFSET (0x000000BC) | |||||
/* | |||||
* Offsets for the Request Descriptor Post Queue | |||||
*/ | |||||
#define MPI2_REQUEST_DESCRIPTOR_POST_LOW_OFFSET (0x000000C0) | #define MPI2_REQUEST_DESCRIPTOR_POST_LOW_OFFSET (0x000000C0) | ||||
#define MPI2_REQUEST_DESCRIPTOR_POST_HIGH_OFFSET (0x000000C4) | #define MPI2_REQUEST_DESCRIPTOR_POST_HIGH_OFFSET (0x000000C4) | ||||
/* Hard Reset delay timings */ | /* Hard Reset delay timings */ | ||||
#define MPI2_HARD_RESET_PCIE_FIRST_READ_DELAY_MICRO_SEC (50000) | #define MPI2_HARD_RESET_PCIE_FIRST_READ_DELAY_MICRO_SEC (50000) | ||||
#define MPI2_HARD_RESET_PCIE_RESET_READ_WINDOW_MICRO_SEC (255000) | #define MPI2_HARD_RESET_PCIE_RESET_READ_WINDOW_MICRO_SEC (255000) | ||||
#define MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC (256000) | #define MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC (256000) | ||||
Show All 14 Lines | typedef struct _MPI2_DEFAULT_REQUEST_DESCRIPTOR | ||||
U16 SMID; /* 0x02 */ | U16 SMID; /* 0x02 */ | ||||
U16 LMID; /* 0x04 */ | U16 LMID; /* 0x04 */ | ||||
U16 DescriptorTypeDependent; /* 0x06 */ | U16 DescriptorTypeDependent; /* 0x06 */ | ||||
} MPI2_DEFAULT_REQUEST_DESCRIPTOR, | } MPI2_DEFAULT_REQUEST_DESCRIPTOR, | ||||
MPI2_POINTER PTR_MPI2_DEFAULT_REQUEST_DESCRIPTOR, | MPI2_POINTER PTR_MPI2_DEFAULT_REQUEST_DESCRIPTOR, | ||||
Mpi2DefaultRequestDescriptor_t, MPI2_POINTER pMpi2DefaultRequestDescriptor_t; | Mpi2DefaultRequestDescriptor_t, MPI2_POINTER pMpi2DefaultRequestDescriptor_t; | ||||
/* defines for the RequestFlags field */ | /* defines for the RequestFlags field */ | ||||
#define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK (0x0E) | #define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK (0x1E) | ||||
#define MPI2_REQ_DESCRIPT_FLAGS_TYPE_RSHIFT (1) /* use carefully; values below are pre-shifted left */ | |||||
#define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO (0x00) | #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO (0x00) | ||||
#define MPI2_REQ_DESCRIPT_FLAGS_SCSI_TARGET (0x02) | #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_TARGET (0x02) | ||||
#define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY (0x06) | #define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY (0x06) | ||||
#define MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE (0x08) | #define MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE (0x08) | ||||
#define MPI2_REQ_DESCRIPT_FLAGS_RAID_ACCELERATOR (0x0A) | #define MPI2_REQ_DESCRIPT_FLAGS_RAID_ACCELERATOR (0x0A) | ||||
#define MPI25_REQ_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO (0x0C) | #define MPI25_REQ_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO (0x0C) | ||||
#define MPI2_REQ_DESCRIPT_FLAGS_IOC_FIFO_MARKER (0x01) | #define MPI2_REQ_DESCRIPT_FLAGS_IOC_FIFO_MARKER (0x01) | ||||
▲ Show 20 Lines • Show All 71 Lines • ▼ Show 20 Lines | typedef union _MPI2_REQUEST_DESCRIPTOR_UNION | ||||
MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR SCSITarget; | MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR SCSITarget; | ||||
MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR RAIDAccelerator; | MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR RAIDAccelerator; | ||||
MPI25_FP_SCSI_IO_REQUEST_DESCRIPTOR FastPathSCSIIO; | MPI25_FP_SCSI_IO_REQUEST_DESCRIPTOR FastPathSCSIIO; | ||||
U64 Words; | U64 Words; | ||||
} MPI2_REQUEST_DESCRIPTOR_UNION, MPI2_POINTER PTR_MPI2_REQUEST_DESCRIPTOR_UNION, | } MPI2_REQUEST_DESCRIPTOR_UNION, MPI2_POINTER PTR_MPI2_REQUEST_DESCRIPTOR_UNION, | ||||
Mpi2RequestDescriptorUnion_t, MPI2_POINTER pMpi2RequestDescriptorUnion_t; | Mpi2RequestDescriptorUnion_t, MPI2_POINTER pMpi2RequestDescriptorUnion_t; | ||||
/* for the RequestFlags field, use the same defines as MPI2_DEFAULT_REQUEST_DESCRIPTOR */ | |||||
/* Reply Descriptors */ | /* Reply Descriptors */ | ||||
/* Default Reply Descriptor */ | /* Default Reply Descriptor */ | ||||
typedef struct _MPI2_DEFAULT_REPLY_DESCRIPTOR | typedef struct _MPI2_DEFAULT_REPLY_DESCRIPTOR | ||||
{ | { | ||||
U8 ReplyFlags; /* 0x00 */ | U8 ReplyFlags; /* 0x00 */ | ||||
U8 MSIxIndex; /* 0x01 */ | U8 MSIxIndex; /* 0x01 */ | ||||
U16 DescriptorTypeDependent1; /* 0x02 */ | U16 DescriptorTypeDependent1; /* 0x02 */ | ||||
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#define MPI2_FUNCTION_TARGET_STATUS_SEND (0x0C) /* Target Status Send */ | #define MPI2_FUNCTION_TARGET_STATUS_SEND (0x0C) /* Target Status Send */ | ||||
#define MPI2_FUNCTION_TARGET_MODE_ABORT (0x0D) /* Target Mode Abort */ | #define MPI2_FUNCTION_TARGET_MODE_ABORT (0x0D) /* Target Mode Abort */ | ||||
#define MPI2_FUNCTION_FW_UPLOAD (0x12) /* FW Upload */ | #define MPI2_FUNCTION_FW_UPLOAD (0x12) /* FW Upload */ | ||||
#define MPI2_FUNCTION_RAID_ACTION (0x15) /* RAID Action */ | #define MPI2_FUNCTION_RAID_ACTION (0x15) /* RAID Action */ | ||||
#define MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH (0x16) /* SCSI IO RAID Passthrough */ | #define MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH (0x16) /* SCSI IO RAID Passthrough */ | ||||
#define MPI2_FUNCTION_TOOLBOX (0x17) /* Toolbox */ | #define MPI2_FUNCTION_TOOLBOX (0x17) /* Toolbox */ | ||||
#define MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR (0x18) /* SCSI Enclosure Processor */ | #define MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR (0x18) /* SCSI Enclosure Processor */ | ||||
#define MPI2_FUNCTION_SMP_PASSTHROUGH (0x1A) /* SMP Passthrough */ | #define MPI2_FUNCTION_SMP_PASSTHROUGH (0x1A) /* SMP Passthrough */ | ||||
#define MPI2_FUNCTION_SAS_IO_UNIT_CONTROL (0x1B) /* SAS IO Unit Control */ | #define MPI2_FUNCTION_SAS_IO_UNIT_CONTROL (0x1B) /* SAS IO Unit Control */ /* for MPI v2.5 and earlier */ | ||||
asomers: Exceeds 80 chars per line here and several other places. | |||||
scottlUnsubmitted Not Done Inline ActionsSince this is common platform header code, I don't think that we should be too concerned about style compliance, especially since the existing style is established and the additions do not alter it. scottl: Since this is common platform header code, I don't think that we should be too concerned about… | |||||
slmAuthorUnsubmitted Not Done Inline ActionsI agree with Scott on this. These headers are used in all of our drivers, apps, FW, etc. I'd like to keep them as close as possible to our actual released headers that we keep internally. The FreeBSD driver headers are modified a little bit from the released versions. Some licensing stuff is added and some newer items are removed to keep them from getting out into the public too soon. Other than that, these are the actual header files. I can remove that dup'ed line however. slm: I agree with Scott on this. These headers are used in all of our drivers, apps, FW, etc. I'd… | |||||
#define MPI2_FUNCTION_IO_UNIT_CONTROL (0x1B) /* IO Unit Control */ /* for MPI v2.6 and later */ | |||||
#define MPI2_FUNCTION_SATA_PASSTHROUGH (0x1C) /* SATA Passthrough */ | #define MPI2_FUNCTION_SATA_PASSTHROUGH (0x1C) /* SATA Passthrough */ | ||||
#define MPI2_FUNCTION_DIAG_BUFFER_POST (0x1D) /* Diagnostic Buffer Post */ | #define MPI2_FUNCTION_DIAG_BUFFER_POST (0x1D) /* Diagnostic Buffer Post */ | ||||
#define MPI2_FUNCTION_DIAG_RELEASE (0x1E) /* Diagnostic Release */ | #define MPI2_FUNCTION_DIAG_RELEASE (0x1E) /* Diagnostic Release */ | ||||
#define MPI2_FUNCTION_TARGET_CMD_BUF_BASE_POST (0x24) /* Target Command Buffer Post Base */ | #define MPI2_FUNCTION_TARGET_CMD_BUF_BASE_POST (0x24) /* Target Command Buffer Post Base */ | ||||
#define MPI2_FUNCTION_TARGET_CMD_BUF_LIST_POST (0x25) /* Target Command Buffer Post List */ | #define MPI2_FUNCTION_TARGET_CMD_BUF_LIST_POST (0x25) /* Target Command Buffer Post List */ | ||||
#define MPI2_FUNCTION_RAID_ACCELERATOR (0x2C) /* RAID Accelerator */ | #define MPI2_FUNCTION_RAID_ACCELERATOR (0x2C) /* RAID Accelerator */ | ||||
#define MPI2_FUNCTION_HOST_BASED_DISCOVERY_ACTION (0x2F) /* Host Based Discovery Action */ | #define MPI2_FUNCTION_HOST_BASED_DISCOVERY_ACTION (0x2F) /* Host Based Discovery Action */ | ||||
#define MPI2_FUNCTION_PWR_MGMT_CONTROL (0x30) /* Power Management Control */ | #define MPI2_FUNCTION_PWR_MGMT_CONTROL (0x30) /* Power Management Control */ | ||||
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#define MPI2_IOCSTATUS_BUSY (0x0002) | #define MPI2_IOCSTATUS_BUSY (0x0002) | ||||
#define MPI2_IOCSTATUS_INVALID_SGL (0x0003) | #define MPI2_IOCSTATUS_INVALID_SGL (0x0003) | ||||
#define MPI2_IOCSTATUS_INTERNAL_ERROR (0x0004) | #define MPI2_IOCSTATUS_INTERNAL_ERROR (0x0004) | ||||
#define MPI2_IOCSTATUS_INVALID_VPID (0x0005) | #define MPI2_IOCSTATUS_INVALID_VPID (0x0005) | ||||
#define MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES (0x0006) | #define MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES (0x0006) | ||||
#define MPI2_IOCSTATUS_INVALID_FIELD (0x0007) | #define MPI2_IOCSTATUS_INVALID_FIELD (0x0007) | ||||
#define MPI2_IOCSTATUS_INVALID_STATE (0x0008) | #define MPI2_IOCSTATUS_INVALID_STATE (0x0008) | ||||
#define MPI2_IOCSTATUS_OP_STATE_NOT_SUPPORTED (0x0009) | #define MPI2_IOCSTATUS_OP_STATE_NOT_SUPPORTED (0x0009) | ||||
#define MPI2_IOCSTATUS_INSUFFICIENT_POWER (0x000A) /* MPI v2.6 and later */ | |||||
/**************************************************************************** | /**************************************************************************** | ||||
* Config IOCStatus values | * Config IOCStatus values | ||||
****************************************************************************/ | ****************************************************************************/ | ||||
#define MPI2_IOCSTATUS_CONFIG_INVALID_ACTION (0x0020) | #define MPI2_IOCSTATUS_CONFIG_INVALID_ACTION (0x0020) | ||||
#define MPI2_IOCSTATUS_CONFIG_INVALID_TYPE (0x0021) | #define MPI2_IOCSTATUS_CONFIG_INVALID_TYPE (0x0021) | ||||
#define MPI2_IOCSTATUS_CONFIG_INVALID_PAGE (0x0022) | #define MPI2_IOCSTATUS_CONFIG_INVALID_PAGE (0x0022) | ||||
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typedef union _MPI2_IEEE_SGE_CHAIN_UNION | typedef union _MPI2_IEEE_SGE_CHAIN_UNION | ||||
{ | { | ||||
MPI2_IEEE_SGE_CHAIN32 Chain32; | MPI2_IEEE_SGE_CHAIN32 Chain32; | ||||
MPI2_IEEE_SGE_CHAIN64 Chain64; | MPI2_IEEE_SGE_CHAIN64 Chain64; | ||||
} MPI2_IEEE_SGE_CHAIN_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_CHAIN_UNION, | } MPI2_IEEE_SGE_CHAIN_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_CHAIN_UNION, | ||||
Mpi2IeeeSgeChainUnion_t, MPI2_POINTER pMpi2IeeeSgeChainUnion_t; | Mpi2IeeeSgeChainUnion_t, MPI2_POINTER pMpi2IeeeSgeChainUnion_t; | ||||
/* MPI25_IEEE_SGE_CHAIN64 is for MPI v2.5 products only */ | /* MPI25_IEEE_SGE_CHAIN64 is for MPI v2.5 and later */ | ||||
typedef struct _MPI25_IEEE_SGE_CHAIN64 | typedef struct _MPI25_IEEE_SGE_CHAIN64 | ||||
{ | { | ||||
U64 Address; | U64 Address; | ||||
U32 Length; | U32 Length; | ||||
U16 Reserved1; | U16 Reserved1; | ||||
U8 NextChainOffset; | U8 NextChainOffset; | ||||
U8 Flags; | U8 Flags; | ||||
} MPI25_IEEE_SGE_CHAIN64, MPI2_POINTER PTR_MPI25_IEEE_SGE_CHAIN64, | } MPI25_IEEE_SGE_CHAIN64, MPI2_POINTER PTR_MPI25_IEEE_SGE_CHAIN64, | ||||
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#define MPI2_IEEE32_SGE_LENGTH_MASK (0x00FFFFFF) | #define MPI2_IEEE32_SGE_LENGTH_MASK (0x00FFFFFF) | ||||
/* Element Type */ | /* Element Type */ | ||||
#define MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT (0x00) | #define MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT (0x00) | ||||
#define MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT (0x80) | #define MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT (0x80) | ||||
/* Next Segment Format */ | |||||
#define MPI26_IEEE_SGE_FLAGS_NSF_MASK (0x1C) | |||||
#define MPI26_IEEE_SGE_FLAGS_NSF_MPI_IEEE (0x00) | |||||
/* Data Location Address Space */ | /* Data Location Address Space */ | ||||
#define MPI2_IEEE_SGE_FLAGS_ADDR_MASK (0x03) | #define MPI2_IEEE_SGE_FLAGS_ADDR_MASK (0x03) | ||||
#define MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR (0x00) /* for MPI v2.0, use in IEEE Simple Element only; for MPI v2.5, use in IEEE Simple or Chain element */ | #define MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR (0x00) /* for MPI v2.0, use in IEEE Simple Element only; for MPI v2.5 and later, use in IEEE Simple or Chain element */ | ||||
#define MPI2_IEEE_SGE_FLAGS_IOCDDR_ADDR (0x01) /* use in IEEE Simple Element only */ | #define MPI2_IEEE_SGE_FLAGS_IOCDDR_ADDR (0x01) /* use in IEEE Simple Element only */ | ||||
#define MPI2_IEEE_SGE_FLAGS_IOCPLB_ADDR (0x02) | #define MPI2_IEEE_SGE_FLAGS_IOCPLB_ADDR (0x02) | ||||
#define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03) /* for MPI v2.0, use in IEEE Simple Element only; for MPI v2.5, use in IEEE Simple or Chain element */ | #define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03) /* for MPI v2.0, use in IEEE Simple Element only; for MPI v2.5, use in IEEE Simple or Chain element */ | ||||
#define MPI2_IEEE_SGE_FLAGS_SYSTEMPLBPCI_ADDR (0x03) /* use in MPI v2.0 IEEE Chain Element only */ | #define MPI2_IEEE_SGE_FLAGS_SYSTEMPLBPCI_ADDR (0x03) /* use in MPI v2.0 IEEE Chain Element only */ | ||||
#define MPI2_IEEE_SGE_FLAGS_SYSTEMPLBCPI_ADDR (MPI2_IEEE_SGE_FLAGS_SYSTEMPLBPCI_ADDR) /* typo in name */ | #define MPI2_IEEE_SGE_FLAGS_SYSTEMPLBCPI_ADDR (MPI2_IEEE_SGE_FLAGS_SYSTEMPLBPCI_ADDR) /* typo in name */ | ||||
#define MPI26_IEEE_SGE_FLAGS_IOCCTL_ADDR (0x02) /* for MPI v2.6 only */ | |||||
/**************************************************************************** | /**************************************************************************** | ||||
* IEEE SGE operation Macros | * IEEE SGE operation Macros | ||||
****************************************************************************/ | ****************************************************************************/ | ||||
/* SIMPLE FlagsLength manipulations... */ | /* SIMPLE FlagsLength manipulations... */ | ||||
#define MPI2_IEEE32_SGE_SET_FLAGS(f) ((U32)(f) << MPI2_IEEE32_SGE_FLAGS_SHIFT) | #define MPI2_IEEE32_SGE_SET_FLAGS(f) ((U32)(f) << MPI2_IEEE32_SGE_FLAGS_SHIFT) | ||||
#define MPI2_IEEE32_SGE_GET_FLAGS(f) (((f) & ~MPI2_IEEE32_SGE_LENGTH_MASK) >> MPI2_IEEE32_SGE_FLAGS_SHIFT) | #define MPI2_IEEE32_SGE_GET_FLAGS(f) (((f) & ~MPI2_IEEE32_SGE_LENGTH_MASK) >> MPI2_IEEE32_SGE_FLAGS_SHIFT) | ||||
#define MPI2_IEEE32_SGE_LENGTH(f) ((f) & MPI2_IEEE32_SGE_LENGTH_MASK) | #define MPI2_IEEE32_SGE_LENGTH(f) ((f) & MPI2_IEEE32_SGE_LENGTH_MASK) | ||||
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* Values for SGLFlags field, used in many request messages with an SGL | * Values for SGLFlags field, used in many request messages with an SGL | ||||
* | * | ||||
****************************************************************************/ | ****************************************************************************/ | ||||
/* values for MPI SGL Data Location Address Space subfield */ | /* values for MPI SGL Data Location Address Space subfield */ | ||||
#define MPI2_SGLFLAGS_ADDRESS_SPACE_MASK (0x0C) | #define MPI2_SGLFLAGS_ADDRESS_SPACE_MASK (0x0C) | ||||
#define MPI2_SGLFLAGS_SYSTEM_ADDRESS_SPACE (0x00) | #define MPI2_SGLFLAGS_SYSTEM_ADDRESS_SPACE (0x00) | ||||
#define MPI2_SGLFLAGS_IOCDDR_ADDRESS_SPACE (0x04) | #define MPI2_SGLFLAGS_IOCDDR_ADDRESS_SPACE (0x04) | ||||
#define MPI2_SGLFLAGS_IOCPLB_ADDRESS_SPACE (0x08) | #define MPI2_SGLFLAGS_IOCPLB_ADDRESS_SPACE (0x08) /* only for MPI v2.5 and earlier */ | ||||
#define MPI2_SGLFLAGS_IOCPLBNTA_ADDRESS_SPACE (0x0C) | #define MPI26_SGLFLAGS_IOCPLB_ADDRESS_SPACE (0x08) /* only for MPI v2.6 */ | ||||
#define MPI2_SGLFLAGS_IOCPLBNTA_ADDRESS_SPACE (0x0C) /* only for MPI v2.5 and earlier */ | |||||
/* values for SGL Type subfield */ | /* values for SGL Type subfield */ | ||||
#define MPI2_SGLFLAGS_SGL_TYPE_MASK (0x03) | #define MPI2_SGLFLAGS_SGL_TYPE_MASK (0x03) | ||||
#define MPI2_SGLFLAGS_SGL_TYPE_MPI (0x00) | #define MPI2_SGLFLAGS_SGL_TYPE_MPI (0x00) | ||||
#define MPI2_SGLFLAGS_SGL_TYPE_IEEE32 (0x01) /* MPI v2.0 products only */ | #define MPI2_SGLFLAGS_SGL_TYPE_IEEE32 (0x01) /* MPI v2.0 products only */ | ||||
#define MPI2_SGLFLAGS_SGL_TYPE_IEEE64 (0x02) | #define MPI2_SGLFLAGS_SGL_TYPE_IEEE64 (0x02) | ||||
#endif | #endif | ||||
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