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head/sys/dev/rt/if_rtvar.h
| Show First 20 Lines • Show All 109 Lines • ▼ Show 20 Lines | |||||
| #define TXDSCR_DST_PORT_CPU 0x00 | #define TXDSCR_DST_PORT_CPU 0x00 | ||||
| #define TXDSCR_DST_PORT_GDMA1 0x01 | #define TXDSCR_DST_PORT_GDMA1 0x01 | ||||
| #define TXDSCR_DST_PORT_GDMA2 0x02 | #define TXDSCR_DST_PORT_GDMA2 0x02 | ||||
| #define TXDSCR_DST_PORT_PPE 0x06 | #define TXDSCR_DST_PORT_PPE 0x06 | ||||
| #define TXDSCR_DST_PORT_DISC 0x07 | #define TXDSCR_DST_PORT_DISC 0x07 | ||||
| } __packed; | } __packed; | ||||
| #define RT_RXDESC_SDL0_DDONE (1 << 15) | #define RT_RXDESC_SDL0_DDONE (1 << 15) | ||||
| #define RT305X_RXD_SRC_L4_CSUM_FAIL (1 << 28) | |||||
| #define RT305X_RXD_SRC_IP_CSUM_FAIL (1 << 29) | |||||
| #define MT7620_RXD_SRC_L4_CSUM_FAIL (1 << 22) | |||||
| #define MT7620_RXD_SRC_IP_CSUM_FAIL (1 << 25) | |||||
| #define MT7621_RXD_SRC_L4_CSUM_FAIL (1 << 23) | |||||
| #define MT7621_RXD_SRC_IP_CSUM_FAIL (1 << 26) | |||||
| struct rt_rxdesc | struct rt_rxdesc | ||||
| { | { | ||||
| uint32_t sdp0; | uint32_t sdp0; | ||||
| uint16_t sdl1; | uint16_t sdl1; | ||||
| uint16_t sdl0; | uint16_t sdl0; | ||||
| uint32_t sdp1; | uint32_t sdp1; | ||||
| #if 0 | |||||
| uint16_t foe; | uint16_t foe; | ||||
| #define RXDSXR_FOE_ENTRY_VALID 0x40 | #define RXDSXR_FOE_ENTRY_VALID 0x40 | ||||
| #define RXDSXR_FOE_ENTRY_MASK 0x3f | #define RXDSXR_FOE_ENTRY_MASK 0x3f | ||||
| uint8_t ai; | uint8_t ai; | ||||
| #define RXDSXR_AI_COU_REASON 0xff | #define RXDSXR_AI_COU_REASON 0xff | ||||
| #define RXDSXR_AI_PARSER_RSLT_MASK 0xff | #define RXDSXR_AI_PARSER_RSLT_MASK 0xff | ||||
| uint8_t src; | uint8_t src; | ||||
| #define RXDSXR_SRC_IPFVLD 0x80 | #define RXDSXR_SRC_IPFVLD 0x80 | ||||
| #define RXDSXR_SRC_L4FVLD 0x40 | #define RXDSXR_SRC_L4FVLD 0x40 | ||||
| #define RXDSXR_SRC_IP_CSUM_FAIL 0x20 | #define RXDSXR_SRC_IP_CSUM_FAIL 0x20 | ||||
| #define RXDSXR_SRC_L4_CSUM_FAIL 0x10 | #define RXDSXR_SRC_L4_CSUM_FAIL 0x10 | ||||
| #define RXDSXR_SRC_AIS 0x08 | #define RXDSXR_SRC_AIS 0x08 | ||||
| #define RXDSXR_SRC_PORT_MASK 0x07 | #define RXDSXR_SRC_PORT_MASK 0x07 | ||||
| #endif | |||||
| uint32_t word3; | |||||
| } __packed; | } __packed; | ||||
| struct rt_softc_rx_data | struct rt_softc_rx_data | ||||
| { | { | ||||
| bus_dmamap_t dma_map; | bus_dmamap_t dma_map; | ||||
| struct mbuf *m; | struct mbuf *m; | ||||
| }; | }; | ||||
| ▲ Show 20 Lines • Show All 113 Lines • ▼ Show 20 Lines | |||||
| #ifdef IF_RT_DEBUG | #ifdef IF_RT_DEBUG | ||||
| int debug; | int debug; | ||||
| #endif | #endif | ||||
| uint32_t rt_chipid; | uint32_t rt_chipid; | ||||
| /* chip specific registers config */ | /* chip specific registers config */ | ||||
| int rx_ring_count; | int rx_ring_count; | ||||
| uint32_t csum_fail_l4; | |||||
| uint32_t csum_fail_ip; | |||||
| uint32_t int_rx_done_mask; | uint32_t int_rx_done_mask; | ||||
| uint32_t int_tx_done_mask; | uint32_t int_tx_done_mask; | ||||
| uint32_t delay_int_cfg; | uint32_t delay_int_cfg; | ||||
| uint32_t fe_int_status; | uint32_t fe_int_status; | ||||
| uint32_t fe_int_enable; | uint32_t fe_int_enable; | ||||
| uint32_t pdma_glo_cfg; | uint32_t pdma_glo_cfg; | ||||
| uint32_t pdma_rst_idx; | uint32_t pdma_rst_idx; | ||||
| uint32_t tx_base_ptr[RT_SOFTC_TX_RING_COUNT]; | uint32_t tx_base_ptr[RT_SOFTC_TX_RING_COUNT]; | ||||
| Show All 30 Lines | |||||