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Differential D5467 Diff 13957 head/sys/arm/allwinner/a31/a31_clk.h

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head/sys/arm/allwinner/a31/a31_clk.h

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#define A31_CCM_CLK_OUTA 0x0300 #define A31_CCM_CLK_OUTA 0x0300
#define A31_CCM_CLK_OUTB 0x0304 #define A31_CCM_CLK_OUTB 0x0304
#define A31_CCM_CLK_OUTC 0x0308 #define A31_CCM_CLK_OUTC 0x0308
/* PLL6_CFG_REG */ /* PLL6_CFG_REG */
#define A31_CCM_PLL6_CFG_REG_LOCK (1 << 28) #define A31_CCM_PLL6_CFG_REG_LOCK (1 << 28)
/* AHB_GATING_REG0 */ /* AHB_GATING_REG0 */
#define A31_CCM_AHB_GATING_SDMMC0 (1 << 8) #define A31_CCM_AHB_GATING_OHCI2 (1 << 31)
#define A31_CCM_AHB_GATING_OHCI1 (1 << 30)
#define A31_CCM_AHB_GATING_OHCI0 (1 << 29)
#define A31_CCM_AHB_GATING_EHCI1 (1 << 27)
#define A31_CCM_AHB_GATING_EHCI0 (1 << 26)
#define A31_CCM_AHB_GATING_USBDRD (1 << 24)
#define A31_CCM_AHB_GATING_GMAC (1 << 17) #define A31_CCM_AHB_GATING_GMAC (1 << 17)
#define A31_CCM_AHB_GATING_SDMMC0 (1 << 8)
#define A31_CCM_PLL_CFG_ENABLE (1U << 31) #define A31_CCM_PLL_CFG_ENABLE (1U << 31)
#define A31_CCM_PLL_CFG_BYPASS (1U << 30) #define A31_CCM_PLL_CFG_BYPASS (1U << 30)
#define A31_CCM_PLL_CFG_PLL5 (1U << 25) #define A31_CCM_PLL_CFG_PLL5 (1U << 25)
#define A31_CCM_PLL_CFG_PLL6 (1U << 24) #define A31_CCM_PLL_CFG_PLL6 (1U << 24)
#define A31_CCM_PLL_CFG_FACTOR_N 0x1f00 #define A31_CCM_PLL_CFG_FACTOR_N 0x1f00
#define A31_CCM_PLL_CFG_FACTOR_N_SHIFT 8 #define A31_CCM_PLL_CFG_FACTOR_N_SHIFT 8
#define A31_CCM_PLL_CFG_FACTOR_K 0x30 #define A31_CCM_PLL_CFG_FACTOR_K 0x30
#define A31_CCM_PLL_CFG_FACTOR_K_SHIFT 4 #define A31_CCM_PLL_CFG_FACTOR_K_SHIFT 4
#define A31_CCM_PLL_CFG_FACTOR_M 0x3 #define A31_CCM_PLL_CFG_FACTOR_M 0x3
/* APB2_GATING */ /* APB2_GATING */
#define A31_CCM_APB2_GATING_TWI (1 << 0) #define A31_CCM_APB2_GATING_TWI (1 << 0)
/* AHB1_RST_REG0 */ /* AHB1_RST_REG0 */
#define A31_CCM_AHB1_RST_REG0_OHCI2 (1 << 31)
#define A31_CCM_AHB1_RST_REG0_OHCI1 (1 << 30)
#define A31_CCM_AHB1_RST_REG0_OHCI0 (1 << 29)
#define A31_CCM_AHB1_RST_REG0_EHCI1 (1 << 27)
#define A31_CCM_AHB1_RST_REG0_EHCI0 (1 << 26)
#define A31_CCM_AHB1_RST_REG0_GMAC (1 << 17) #define A31_CCM_AHB1_RST_REG0_GMAC (1 << 17)
#define A31_CCM_AHB1_RST_REG0_SDMMC (1 << 8) #define A31_CCM_AHB1_RST_REG0_SDMMC (1 << 8)
/* APB2_RST_REG */ /* APB2_RST_REG */
#define A31_CCM_APB2_RST_TWI (1 << 0) #define A31_CCM_APB2_RST_TWI (1 << 0)
/* GMAC */ /* GMAC */
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#define A31_CCM_SD_CLK_PHASE_CTR 0x700000 #define A31_CCM_SD_CLK_PHASE_CTR 0x700000
#define A31_CCM_SD_CLK_PHASE_CTR_SHIFT 20 #define A31_CCM_SD_CLK_PHASE_CTR_SHIFT 20
#define A31_CCM_SD_CLK_DIV_RATIO_N 0x30000 #define A31_CCM_SD_CLK_DIV_RATIO_N 0x30000
#define A31_CCM_SD_CLK_DIV_RATIO_N_SHIFT 16 #define A31_CCM_SD_CLK_DIV_RATIO_N_SHIFT 16
#define A31_CCM_SD_CLK_OPHASE_CTR 0x700 #define A31_CCM_SD_CLK_OPHASE_CTR 0x700
#define A31_CCM_SD_CLK_OPHASE_CTR_SHIFT 8 #define A31_CCM_SD_CLK_OPHASE_CTR_SHIFT 8
#define A31_CCM_SD_CLK_DIV_RATIO_M 0xf #define A31_CCM_SD_CLK_DIV_RATIO_M 0xf
/* USB */
#define A31_CCM_USBPHY_CLK_GATING_OHCI2 (1 << 18)
#define A31_CCM_USBPHY_CLK_GATING_OHCI1 (1 << 17)
#define A31_CCM_USBPHY_CLK_GATING_OHCI0 (1 << 16)
#define A31_CCM_USBPHY_CLK_GATING_USBPHY2 (1 << 10)
#define A31_CCM_USBPHY_CLK_GATING_USBPHY1 (1 << 9)
#define A31_CCM_USBPHY_CLK_GATING_USBPHY0 (1 << 8)
#define A31_CCM_USBPHY_CLK_USBPHY2_RST (1 << 2)
#define A31_CCM_USBPHY_CLK_USBPHY1_RST (1 << 1)
#define A31_CCM_USBPHY_CLK_USBPHY0_RST (1 << 0)
#define A31_CCM_CLK_REF_FREQ 24000000U #define A31_CCM_CLK_REF_FREQ 24000000U
int a31_clk_gmac_activate(phandle_t); int a31_clk_gmac_activate(phandle_t);
int a31_clk_mmc_activate(int); int a31_clk_mmc_activate(int);
int a31_clk_mmc_cfg(int, int); int a31_clk_mmc_cfg(int, int);
int a31_clk_i2c_activate(int); int a31_clk_i2c_activate(int);
int a31_clk_ehci_activate(void);
int a31_clk_ehci_deactivate(void);
#endif /* _A31_CLK_H_ */ #endif /* _A31_CLK_H_ */