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	#define ICC_IAR1_EL1_SPUR (0x03ff)			#define ICC_IAR1_EL1_SPUR (0x03ff)

	/* ICC_IGRPEN0_EL1 */			/* ICC_IGRPEN0_EL1 */
	#define ICC_IGRPEN0_EL1_EN (1U << 0)			#define ICC_IGRPEN0_EL1_EN (1U << 0)

	/* ICC_PMR_EL1 */			/* ICC_PMR_EL1 */
	#define ICC_PMR_EL1_PRIO_MASK (0xFFUL)			#define ICC_PMR_EL1_PRIO_MASK (0xFFUL)

				/* ICC_SGI1R_EL1 */
				#define ICC_SGI1R_EL1_TL_MASK 0xffffUL
				#define ICC_SGI1R_EL1_AFF1_SHIFT 16
				#define ICC_SGI1R_EL1_SGIID_SHIFT 24
				#define ICC_SGI1R_EL1_AFF2_SHIFT 32
				#define ICC_SGI1R_EL1_AFF3_SHIFT 48
				#define ICC_SGI1R_EL1_SGIID_MASK 0xfUL
				#define ICC_SGI1R_EL1_IRM (0x1UL << 40)

	/* ICC_SRE_EL1 */			/* ICC_SRE_EL1 */
	#define ICC_SRE_EL1_SRE (1U << 0)			#define ICC_SRE_EL1_SRE (1U << 0)

	/* ICC_SRE_EL2 */			/* ICC_SRE_EL2 */
	#define ICC_SRE_EL2_EN (1U << 3)			#define ICC_SRE_EL2_EN (1U << 3)

	/* ID_AA64DFR0_EL1 */			/* ID_AA64DFR0_EL1 */
	#define ID_AA64DFR0_MASK 0xf0f0ffff			#define ID_AA64DFR0_MASK 0xf0f0ffff
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