Differential D35247 Diff 106166 sys/arm64/include/armreg.h

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sys/arm64/include/armreg.h

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	#define DBGPRCR_EL1_op0 2			#define DBGPRCR_EL1_op0 2
	#define DBGPRCR_EL1_op1 0			#define DBGPRCR_EL1_op1 0
	#define DBGPRCR_EL1_CRn 1			#define DBGPRCR_EL1_CRn 1
	#define DBGPRCR_EL1_CRm 4			#define DBGPRCR_EL1_CRm 4
	#define DBGPRCR_EL1_op2 4			#define DBGPRCR_EL1_op2 4

	/* ESR_ELx */			/* ESR_ELx */
	#define ESR_ELx_ISS_MASK 0x01ffffff			#define ESR_ELx_ISS_MASK 0x01ffffff
				#define ISS_FP_TFV_SHIFT 23
				#define ISS_FP_TFV (0x01 << ISS_FP_TFV_SHIFT)
				#define ISS_FP_IOF 0x01
				#define ISS_FP_DZF 0x02
				#define ISS_FP_OFF 0x04
				#define ISS_FP_UFF 0x08
				#define ISS_FP_IXF 0x10
				#define ISS_FP_IDF 0x80
	#define ISS_INSN_FnV (0x01 << 10)			#define ISS_INSN_FnV (0x01 << 10)
	#define ISS_INSN_EA (0x01 << 9)			#define ISS_INSN_EA (0x01 << 9)
	#define ISS_INSN_S1PTW (0x01 << 7)			#define ISS_INSN_S1PTW (0x01 << 7)
	#define ISS_INSN_IFSC_MASK (0x1f << 0)			#define ISS_INSN_IFSC_MASK (0x1f << 0)

	#define ISS_MSR_DIR_SHIFT 0			#define ISS_MSR_DIR_SHIFT 0
	#define ISS_MSR_DIR (0x01 << ISS_MSR_DIR_SHIFT)			#define ISS_MSR_DIR (0x01 << ISS_MSR_DIR_SHIFT)
	#define ISS_MSR_Rt_SHIFT 5			#define ISS_MSR_Rt_SHIFT 5
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	#define ISS_MSR_OP0_MASK (0x3 << ISS_MSR_OP0_SHIFT)			#define ISS_MSR_OP0_MASK (0x3 << ISS_MSR_OP0_SHIFT)
	#define ISS_MSR_OP0(x) (((x) & ISS_MSR_OP0_MASK) >> ISS_MSR_OP0_SHIFT)			#define ISS_MSR_OP0(x) (((x) & ISS_MSR_OP0_MASK) >> ISS_MSR_OP0_SHIFT)
	#define ISS_MSR_REG_MASK \			#define ISS_MSR_REG_MASK \
	(ISS_MSR_OP0_MASK \| ISS_MSR_OP2_MASK \| ISS_MSR_OP1_MASK \| \			(ISS_MSR_OP0_MASK \| ISS_MSR_OP2_MASK \| ISS_MSR_OP1_MASK \| \
	ISS_MSR_CRn_MASK \| ISS_MSR_CRm_MASK)			ISS_MSR_CRn_MASK \| ISS_MSR_CRm_MASK)

	#define ISS_DATA_ISV_SHIFT 24			#define ISS_DATA_ISV_SHIFT 24
	#define ISS_DATA_ISV (0x01 << ISS_DATA_ISV_SHIFT)			#define ISS_DATA_ISV (0x01 << ISS_DATA_ISV_SHIFT)
	#define ISS_DATA_SAS_SHIFT 22			#define ISS_DATA_SAS_SHIFT 22
	#define ISS_DATA_SAS_MASK (0x03 << ISS_DATA_SAS_SHIFT)			#define ISS_DATA_SAS_MASK (0x03 << ISS_DATA_SAS_SHIFT)
	#define ISS_DATA_SSE_SHIFT 21			#define ISS_DATA_SSE_SHIFT 21
	#define ISS_DATA_SSE (0x01 << ISS_DATA_SSE_SHIFT)			#define ISS_DATA_SSE (0x01 << ISS_DATA_SSE_SHIFT)
	#define ISS_DATA_SRT_SHIFT 16			#define ISS_DATA_SRT_SHIFT 16
	#define ISS_DATA_SRT_MASK (0x1f << ISS_DATA_SRT_SHIFT)			#define ISS_DATA_SRT_MASK (0x1f << ISS_DATA_SRT_SHIFT)
	#define ISS_DATA_SF (0x01 << 15)			#define ISS_DATA_SF (0x01 << 15)
	#define ISS_DATA_AR (0x01 << 14)			#define ISS_DATA_AR (0x01 << 14)
				andrewUnsubmitted Done Inline Actions These should be named something like `ISS_FP_TFV_FOO` and placed before the `ISS_INSN_` definitions. The `ISS_DATA_` macros are for data aborts. andrew: These should be named something like `ISS_FP_TFV_FOO` and placed before the `ISS_INSN_*`…
				dchaginAuthorUnsubmitted Done Inline Actions I'd prefer ISS_FP_FOO as TVF and FOO are bits in the same word, but if you insist, I'll change the naming dchagin: I'd prefer ISS_FP_FOO as TVF and FOO are bits in the same word, but if you insist, I'll change…
	#define ISS_DATA_FnV (0x01 << 10)			#define ISS_DATA_FnV (0x01 << 10)
	#define ISS_DATA_EA (0x01 << 9)			#define ISS_DATA_EA (0x01 << 9)
	#define ISS_DATA_CM (0x01 << 8)			#define ISS_DATA_CM (0x01 << 8)
	#define ISS_DATA_S1PTW (0x01 << 7)			#define ISS_DATA_S1PTW (0x01 << 7)
	#define ISS_DATA_WnR_SHIFT 6			#define ISS_DATA_WnR_SHIFT 6
	#define ISS_DATA_WnR (0x01 << ISS_DATA_WnR_SHIFT)			#define ISS_DATA_WnR (0x01 << ISS_DATA_WnR_SHIFT)
	#define ISS_DATA_DFSC_MASK (0x3f << 0)			#define ISS_DATA_DFSC_MASK (0x3f << 0)
	#define ISS_DATA_DFSC_ASF_L0 (0x00 << 0)			#define ISS_DATA_DFSC_ASF_L0 (0x00 << 0)
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