Differential D34024 Diff 104209 sys/dev/ice/ice_hw_autogen.h

Changeset View

Standalone View

sys/dev/ice/ice_hw_autogen.h

This file is larger than 256 KB, so syntax highlighting is disabled by default.

	Show All 24 Lines
	* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS			* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
	* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN			* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
	* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)			* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
	* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE			* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
	* POSSIBILITY OF SUCH DAMAGE.			* POSSIBILITY OF SUCH DAMAGE.
	*/			*/
	/$FreeBSD$/			/$FreeBSD$/

	/* Machine-generated file; do not edit */			/* Machine generated file. Do not edit. */

	#ifndef _ICE_HW_AUTOGEN_H_			#ifndef _ICE_HW_AUTOGEN_H_
	#define _ICE_HW_AUTOGEN_H_			#define _ICE_HW_AUTOGEN_H_

				#define GL_HIDA(_i) (0x00082000 + ((_i) * 4))
				#define GL_HIBA(_i) (0x00081000 + ((_i) * 4))
				#define GL_HICR 0x00082040
				#define GL_HICR_EN 0x00082044
				#define GLGEN_CSR_DEBUG_C 0x00075750
				#define GLNVM_GENS 0x000B6100
				#define GLNVM_FLA 0x000B6108
				#define GL_HIDA_MAX_INDEX 15
				#define GL_HIBA_MAX_INDEX 1023
	#define GL_RDPU_CNTRL 0x00052054 /* Reset Source: CORER */			#define GL_RDPU_CNTRL 0x00052054 /* Reset Source: CORER */
	#define GL_RDPU_CNTRL_RX_PAD_EN_S 0			#define GL_RDPU_CNTRL_RX_PAD_EN_S 0
	#define GL_RDPU_CNTRL_RX_PAD_EN_M BIT(0)			#define GL_RDPU_CNTRL_RX_PAD_EN_M BIT(0)
	#define GL_RDPU_CNTRL_UDP_ZERO_EN_S 1			#define GL_RDPU_CNTRL_UDP_ZERO_EN_S 1
	#define GL_RDPU_CNTRL_UDP_ZERO_EN_M BIT(1)			#define GL_RDPU_CNTRL_UDP_ZERO_EN_M BIT(1)
	#define GL_RDPU_CNTRL_BLNC_EN_S 2			#define GL_RDPU_CNTRL_BLNC_EN_S 2
	#define GL_RDPU_CNTRL_BLNC_EN_M BIT(2)			#define GL_RDPU_CNTRL_BLNC_EN_M BIT(2)
	#define GL_RDPU_CNTRL_RECIPE_BYPASS_S 3			#define GL_RDPU_CNTRL_RECIPE_BYPASS_S 3
	▲ Show 20 Lines • Show All 426 Lines • ▼ Show 20 Lines
	#define PF0INT_OICR_CPM_PAGE_PCI_EXCEPTION_S 21			#define PF0INT_OICR_CPM_PAGE_PCI_EXCEPTION_S 21
	#define PF0INT_OICR_CPM_PAGE_PCI_EXCEPTION_M BIT(21)			#define PF0INT_OICR_CPM_PAGE_PCI_EXCEPTION_M BIT(21)
	#define PF0INT_OICR_CPM_PAGE_GPIO_S 22			#define PF0INT_OICR_CPM_PAGE_GPIO_S 22
	#define PF0INT_OICR_CPM_PAGE_GPIO_M BIT(22)			#define PF0INT_OICR_CPM_PAGE_GPIO_M BIT(22)
	#define PF0INT_OICR_CPM_PAGE_RSV3_S 23			#define PF0INT_OICR_CPM_PAGE_RSV3_S 23
	#define PF0INT_OICR_CPM_PAGE_RSV3_M BIT(23)			#define PF0INT_OICR_CPM_PAGE_RSV3_M BIT(23)
	#define PF0INT_OICR_CPM_PAGE_STORM_DETECT_S 24			#define PF0INT_OICR_CPM_PAGE_STORM_DETECT_S 24
	#define PF0INT_OICR_CPM_PAGE_STORM_DETECT_M BIT(24)			#define PF0INT_OICR_CPM_PAGE_STORM_DETECT_M BIT(24)
	#define PF0INT_OICR_CPM_PAGE_LINK_STAT_CHANGE_S 25			#define PF0INT_OICR_CPM_PAGE_LINK_STAT_CHANGE_S 25
	#define PF0INT_OICR_CPM_PAGE_LINK_STAT_CHANGE_M BIT(25)			#define PF0INT_OICR_CPM_PAGE_LINK_STAT_CHANGE_M BIT(25)
	#define PF0INT_OICR_CPM_PAGE_HMC_ERR_S 26			#define PF0INT_OICR_CPM_PAGE_HMC_ERR_S 26
	#define PF0INT_OICR_CPM_PAGE_HMC_ERR_M BIT(26)			#define PF0INT_OICR_CPM_PAGE_HMC_ERR_M BIT(26)
	#define PF0INT_OICR_CPM_PAGE_PE_PUSH_S 27			#define PF0INT_OICR_CPM_PAGE_PE_PUSH_S 27
	#define PF0INT_OICR_CPM_PAGE_PE_PUSH_M BIT(27)			#define PF0INT_OICR_CPM_PAGE_PE_PUSH_M BIT(27)
	#define PF0INT_OICR_CPM_PAGE_PE_CRITERR_S 28			#define PF0INT_OICR_CPM_PAGE_PE_CRITERR_S 28
	#define PF0INT_OICR_CPM_PAGE_PE_CRITERR_M BIT(28)			#define PF0INT_OICR_CPM_PAGE_PE_CRITERR_M BIT(28)
	#define PF0INT_OICR_CPM_PAGE_VFLR_S 29			#define PF0INT_OICR_CPM_PAGE_VFLR_S 29
	#define PF0INT_OICR_CPM_PAGE_VFLR_M BIT(29)			#define PF0INT_OICR_CPM_PAGE_VFLR_M BIT(29)
	▲ Show 20 Lines • Show All 46 Lines • ▼ Show 20 Lines
	#define PF0INT_OICR_HLP_PAGE_PCI_EXCEPTION_S 21			#define PF0INT_OICR_HLP_PAGE_PCI_EXCEPTION_S 21
	#define PF0INT_OICR_HLP_PAGE_PCI_EXCEPTION_M BIT(21)			#define PF0INT_OICR_HLP_PAGE_PCI_EXCEPTION_M BIT(21)
	#define PF0INT_OICR_HLP_PAGE_GPIO_S 22			#define PF0INT_OICR_HLP_PAGE_GPIO_S 22
	#define PF0INT_OICR_HLP_PAGE_GPIO_M BIT(22)			#define PF0INT_OICR_HLP_PAGE_GPIO_M BIT(22)
	#define PF0INT_OICR_HLP_PAGE_RSV3_S 23			#define PF0INT_OICR_HLP_PAGE_RSV3_S 23
	#define PF0INT_OICR_HLP_PAGE_RSV3_M BIT(23)			#define PF0INT_OICR_HLP_PAGE_RSV3_M BIT(23)
	#define PF0INT_OICR_HLP_PAGE_STORM_DETECT_S 24			#define PF0INT_OICR_HLP_PAGE_STORM_DETECT_S 24
	#define PF0INT_OICR_HLP_PAGE_STORM_DETECT_M BIT(24)			#define PF0INT_OICR_HLP_PAGE_STORM_DETECT_M BIT(24)
	#define PF0INT_OICR_HLP_PAGE_LINK_STAT_CHANGE_S 25			#define PF0INT_OICR_HLP_PAGE_LINK_STAT_CHANGE_S 25
	#define PF0INT_OICR_HLP_PAGE_LINK_STAT_CHANGE_M BIT(25)			#define PF0INT_OICR_HLP_PAGE_LINK_STAT_CHANGE_M BIT(25)
	#define PF0INT_OICR_HLP_PAGE_HMC_ERR_S 26			#define PF0INT_OICR_HLP_PAGE_HMC_ERR_S 26
	#define PF0INT_OICR_HLP_PAGE_HMC_ERR_M BIT(26)			#define PF0INT_OICR_HLP_PAGE_HMC_ERR_M BIT(26)
	#define PF0INT_OICR_HLP_PAGE_PE_PUSH_S 27			#define PF0INT_OICR_HLP_PAGE_PE_PUSH_S 27
	#define PF0INT_OICR_HLP_PAGE_PE_PUSH_M BIT(27)			#define PF0INT_OICR_HLP_PAGE_PE_PUSH_M BIT(27)
	#define PF0INT_OICR_HLP_PAGE_PE_CRITERR_S 28			#define PF0INT_OICR_HLP_PAGE_PE_CRITERR_S 28
	#define PF0INT_OICR_HLP_PAGE_PE_CRITERR_M BIT(28)			#define PF0INT_OICR_HLP_PAGE_PE_CRITERR_M BIT(28)
	#define PF0INT_OICR_HLP_PAGE_VFLR_S 29			#define PF0INT_OICR_HLP_PAGE_VFLR_S 29
	#define PF0INT_OICR_HLP_PAGE_VFLR_M BIT(29)			#define PF0INT_OICR_HLP_PAGE_VFLR_M BIT(29)
	Show All 31 Lines
	#define PF0INT_OICR_PSM_PAGE_PCI_EXCEPTION_S 21			#define PF0INT_OICR_PSM_PAGE_PCI_EXCEPTION_S 21
	#define PF0INT_OICR_PSM_PAGE_PCI_EXCEPTION_M BIT(21)			#define PF0INT_OICR_PSM_PAGE_PCI_EXCEPTION_M BIT(21)
	#define PF0INT_OICR_PSM_PAGE_GPIO_S 22			#define PF0INT_OICR_PSM_PAGE_GPIO_S 22
	#define PF0INT_OICR_PSM_PAGE_GPIO_M BIT(22)			#define PF0INT_OICR_PSM_PAGE_GPIO_M BIT(22)
	#define PF0INT_OICR_PSM_PAGE_RSV3_S 23			#define PF0INT_OICR_PSM_PAGE_RSV3_S 23
	#define PF0INT_OICR_PSM_PAGE_RSV3_M BIT(23)			#define PF0INT_OICR_PSM_PAGE_RSV3_M BIT(23)
	#define PF0INT_OICR_PSM_PAGE_STORM_DETECT_S 24			#define PF0INT_OICR_PSM_PAGE_STORM_DETECT_S 24
	#define PF0INT_OICR_PSM_PAGE_STORM_DETECT_M BIT(24)			#define PF0INT_OICR_PSM_PAGE_STORM_DETECT_M BIT(24)
	#define PF0INT_OICR_PSM_PAGE_LINK_STAT_CHANGE_S 25			#define PF0INT_OICR_PSM_PAGE_LINK_STAT_CHANGE_S 25
	#define PF0INT_OICR_PSM_PAGE_LINK_STAT_CHANGE_M BIT(25)			#define PF0INT_OICR_PSM_PAGE_LINK_STAT_CHANGE_M BIT(25)
	#define PF0INT_OICR_PSM_PAGE_HMC_ERR_S 26			#define PF0INT_OICR_PSM_PAGE_HMC_ERR_S 26
	#define PF0INT_OICR_PSM_PAGE_HMC_ERR_M BIT(26)			#define PF0INT_OICR_PSM_PAGE_HMC_ERR_M BIT(26)
	#define PF0INT_OICR_PSM_PAGE_PE_PUSH_S 27			#define PF0INT_OICR_PSM_PAGE_PE_PUSH_S 27
	#define PF0INT_OICR_PSM_PAGE_PE_PUSH_M BIT(27)			#define PF0INT_OICR_PSM_PAGE_PE_PUSH_M BIT(27)
	#define PF0INT_OICR_PSM_PAGE_PE_CRITERR_S 28			#define PF0INT_OICR_PSM_PAGE_PE_CRITERR_S 28
	#define PF0INT_OICR_PSM_PAGE_PE_CRITERR_M BIT(28)			#define PF0INT_OICR_PSM_PAGE_PE_CRITERR_M BIT(28)
	#define PF0INT_OICR_PSM_PAGE_VFLR_S 29			#define PF0INT_OICR_PSM_PAGE_VFLR_S 29
	#define PF0INT_OICR_PSM_PAGE_VFLR_M BIT(29)			#define PF0INT_OICR_PSM_PAGE_VFLR_M BIT(29)
	▲ Show 20 Lines • Show All 123 Lines • ▼ Show 20 Lines
	#define GL_ACL_PROFILE_BWSB_SEL(_i) (0x00391008 + ((_i) * 4)) /* _i=0...31 / / Reset Source: CORER */			#define GL_ACL_PROFILE_BWSB_SEL(_i) (0x00391008 + ((_i) * 4)) /* _i=0...31 / / Reset Source: CORER */
	#define GL_ACL_PROFILE_BWSB_SEL_MAX_INDEX 31			#define GL_ACL_PROFILE_BWSB_SEL_MAX_INDEX 31
	#define GL_ACL_PROFILE_BWSB_SEL_BSB_SRC_OFF_S 0			#define GL_ACL_PROFILE_BWSB_SEL_BSB_SRC_OFF_S 0
	#define GL_ACL_PROFILE_BWSB_SEL_BSB_SRC_OFF_M MAKEMASK(0x3F, 0)			#define GL_ACL_PROFILE_BWSB_SEL_BSB_SRC_OFF_M MAKEMASK(0x3F, 0)
	#define GL_ACL_PROFILE_BWSB_SEL_WSB_SRC_OFF_S 8			#define GL_ACL_PROFILE_BWSB_SEL_WSB_SRC_OFF_S 8
	#define GL_ACL_PROFILE_BWSB_SEL_WSB_SRC_OFF_M MAKEMASK(0x1F, 8)			#define GL_ACL_PROFILE_BWSB_SEL_WSB_SRC_OFF_M MAKEMASK(0x1F, 8)
	#define GL_ACL_PROFILE_DWSB_SEL(_i) (0x00391088 + ((_i) * 4)) /* _i=0...15 / / Reset Source: CORER */			#define GL_ACL_PROFILE_DWSB_SEL(_i) (0x00391088 + ((_i) * 4)) /* _i=0...15 / / Reset Source: CORER */
	#define GL_ACL_PROFILE_DWSB_SEL_MAX_INDEX 15			#define GL_ACL_PROFILE_DWSB_SEL_MAX_INDEX 15
	#define GL_ACL_PROFILE_DWSB_SEL_DWORD_SEL_OFF_S 0			#define GL_ACL_PROFILE_DWSB_SEL_DWORD_SEL_OFF_S 0
	#define GL_ACL_PROFILE_DWSB_SEL_DWORD_SEL_OFF_M MAKEMASK(0xF, 0)			#define GL_ACL_PROFILE_DWSB_SEL_DWORD_SEL_OFF_M MAKEMASK(0xF, 0)
	#define GL_ACL_PROFILE_PF_CFG(_i) (0x003910C8 + ((_i) * 4)) /* _i=0...7 / / Reset Source: CORER */			#define GL_ACL_PROFILE_PF_CFG(_i) (0x003910C8 + ((_i) * 4)) /* _i=0...7 / / Reset Source: CORER */
	#define GL_ACL_PROFILE_PF_CFG_MAX_INDEX 7			#define GL_ACL_PROFILE_PF_CFG_MAX_INDEX 7
	#define GL_ACL_PROFILE_PF_CFG_SCEN_SEL_S 0			#define GL_ACL_PROFILE_PF_CFG_SCEN_SEL_S 0
	#define GL_ACL_PROFILE_PF_CFG_SCEN_SEL_M MAKEMASK(0x3F, 0)			#define GL_ACL_PROFILE_PF_CFG_SCEN_SEL_M MAKEMASK(0x3F, 0)
	#define GL_ACL_PROFILE_RC_CFG(_i) (0x003910E8 + ((_i) * 4)) /* _i=0...7 / / Reset Source: CORER */			#define GL_ACL_PROFILE_RC_CFG(_i) (0x003910E8 + ((_i) * 4)) /* _i=0...7 / / Reset Source: CORER */
	#define GL_ACL_PROFILE_RC_CFG_MAX_INDEX 7			#define GL_ACL_PROFILE_RC_CFG_MAX_INDEX 7
	#define GL_ACL_PROFILE_RC_CFG_LOW_BOUND_S 0			#define GL_ACL_PROFILE_RC_CFG_LOW_BOUND_S 0
	#define GL_ACL_PROFILE_RC_CFG_LOW_BOUND_M MAKEMASK(0xFFFF, 0)			#define GL_ACL_PROFILE_RC_CFG_LOW_BOUND_M MAKEMASK(0xFFFF, 0)
	▲ Show 20 Lines • Show All 141 Lines • ▼ Show 20 Lines
	#define GLCOMM_QUANTA_PROF_MAX_DESC_M MAKEMASK(0x3F, 24)			#define GLCOMM_QUANTA_PROF_MAX_DESC_M MAKEMASK(0x3F, 24)
	#define GLLAN_TCLAN_CACHE_CTL 0x000FC0B8 /* Reset Source: CORER */			#define GLLAN_TCLAN_CACHE_CTL 0x000FC0B8 /* Reset Source: CORER */
	#define GLLAN_TCLAN_CACHE_CTL_MIN_FETCH_THRESH_S 0			#define GLLAN_TCLAN_CACHE_CTL_MIN_FETCH_THRESH_S 0
	#define GLLAN_TCLAN_CACHE_CTL_MIN_FETCH_THRESH_M MAKEMASK(0x3F, 0)			#define GLLAN_TCLAN_CACHE_CTL_MIN_FETCH_THRESH_M MAKEMASK(0x3F, 0)
	#define GLLAN_TCLAN_CACHE_CTL_FETCH_CL_ALIGN_S 6			#define GLLAN_TCLAN_CACHE_CTL_FETCH_CL_ALIGN_S 6
	#define GLLAN_TCLAN_CACHE_CTL_FETCH_CL_ALIGN_M BIT(6)			#define GLLAN_TCLAN_CACHE_CTL_FETCH_CL_ALIGN_M BIT(6)
	#define GLLAN_TCLAN_CACHE_CTL_MIN_ALLOC_THRESH_S 7			#define GLLAN_TCLAN_CACHE_CTL_MIN_ALLOC_THRESH_S 7
	#define GLLAN_TCLAN_CACHE_CTL_MIN_ALLOC_THRESH_M MAKEMASK(0x7F, 7)			#define GLLAN_TCLAN_CACHE_CTL_MIN_ALLOC_THRESH_M MAKEMASK(0x7F, 7)
	#define GLLAN_TCLAN_CACHE_CTL_CACHE_ENTRY_CNT_S 14			#define GLLAN_TCLAN_CACHE_CTL_CACHE_ENTRY_CNT_S 14
	#define GLLAN_TCLAN_CACHE_CTL_CACHE_ENTRY_CNT_M MAKEMASK(0xFF, 14)			#define GLLAN_TCLAN_CACHE_CTL_CACHE_ENTRY_CNT_M MAKEMASK(0xFF, 14)
	#define GLLAN_TCLAN_CACHE_CTL_CACHE_DESC_LIM_S 22			#define GLLAN_TCLAN_CACHE_CTL_CACHE_DESC_LIM_S 22
	#define GLLAN_TCLAN_CACHE_CTL_CACHE_DESC_LIM_M MAKEMASK(0x3FF, 22)			#define GLLAN_TCLAN_CACHE_CTL_CACHE_DESC_LIM_M MAKEMASK(0x3FF, 22)
	#define GLTCLAN_CQ_CNTX0(_CQ) (0x000F0800 + ((_CQ) * 4)) /* _i=0...511 / / Reset Source: CORER */			#define GLTCLAN_CQ_CNTX0(_CQ) (0x000F0800 + ((_CQ) * 4)) /* _i=0...511 / / Reset Source: CORER */
	#define GLTCLAN_CQ_CNTX0_MAX_INDEX 511			#define GLTCLAN_CQ_CNTX0_MAX_INDEX 511
	#define GLTCLAN_CQ_CNTX0_RING_ADDR_LSB_S 0			#define GLTCLAN_CQ_CNTX0_RING_ADDR_LSB_S 0
	#define GLTCLAN_CQ_CNTX0_RING_ADDR_LSB_M MAKEMASK(0xFFFFFFFF, 0)			#define GLTCLAN_CQ_CNTX0_RING_ADDR_LSB_M MAKEMASK(0xFFFFFFFF, 0)
	#define GLTCLAN_CQ_CNTX1(_CQ) (0x000F1000 + ((_CQ) * 4)) /* _i=0...511 / / Reset Source: CORER */			#define GLTCLAN_CQ_CNTX1(_CQ) (0x000F1000 + ((_CQ) * 4)) /* _i=0...511 / / Reset Source: CORER */
	#define GLTCLAN_CQ_CNTX1_MAX_INDEX 511			#define GLTCLAN_CQ_CNTX1_MAX_INDEX 511
	▲ Show 20 Lines • Show All 1,326 Lines • ▼ Show 20 Lines
	#define PRTDCB_TUP2TC_UP5TC_M MAKEMASK(0x7, 15)			#define PRTDCB_TUP2TC_UP5TC_M MAKEMASK(0x7, 15)
	#define PRTDCB_TUP2TC_UP6TC_S 18			#define PRTDCB_TUP2TC_UP6TC_S 18
	#define PRTDCB_TUP2TC_UP6TC_M MAKEMASK(0x7, 18)			#define PRTDCB_TUP2TC_UP6TC_M MAKEMASK(0x7, 18)
	#define PRTDCB_TUP2TC_UP7TC_S 21			#define PRTDCB_TUP2TC_UP7TC_S 21
	#define PRTDCB_TUP2TC_UP7TC_M MAKEMASK(0x7, 21)			#define PRTDCB_TUP2TC_UP7TC_M MAKEMASK(0x7, 21)
	#define PRTDCB_TX_DSCP2UP_CTL 0x00040980 /* Reset Source: CORER */			#define PRTDCB_TX_DSCP2UP_CTL 0x00040980 /* Reset Source: CORER */
	#define PRTDCB_TX_DSCP2UP_CTL_DSCP2UP_ENA_S 0			#define PRTDCB_TX_DSCP2UP_CTL_DSCP2UP_ENA_S 0
	#define PRTDCB_TX_DSCP2UP_CTL_DSCP2UP_ENA_M BIT(0)			#define PRTDCB_TX_DSCP2UP_CTL_DSCP2UP_ENA_M BIT(0)
	#define PRTDCB_TX_DSCP2UP_CTL_DSCP_DEFAULT_UP_S 1			#define PRTDCB_TX_DSCP2UP_CTL_DSCP_DEFAULT_UP_S 1
	#define PRTDCB_TX_DSCP2UP_CTL_DSCP_DEFAULT_UP_M MAKEMASK(0x7, 1)			#define PRTDCB_TX_DSCP2UP_CTL_DSCP_DEFAULT_UP_M MAKEMASK(0x7, 1)
	#define PRTDCB_TX_DSCP2UP_IPV4_LUT(_i) (0x000409A0 + ((_i) * 32)) /* _i=0...7 / / Reset Source: CORER */			#define PRTDCB_TX_DSCP2UP_IPV4_LUT(_i) (0x000409A0 + ((_i) * 32)) /* _i=0...7 / / Reset Source: CORER */
	#define PRTDCB_TX_DSCP2UP_IPV4_LUT_MAX_INDEX 7			#define PRTDCB_TX_DSCP2UP_IPV4_LUT_MAX_INDEX 7
	#define PRTDCB_TX_DSCP2UP_IPV4_LUT_DSCP2UP_LUT_0_S 0			#define PRTDCB_TX_DSCP2UP_IPV4_LUT_DSCP2UP_LUT_0_S 0
	#define PRTDCB_TX_DSCP2UP_IPV4_LUT_DSCP2UP_LUT_0_M MAKEMASK(0x7, 0)			#define PRTDCB_TX_DSCP2UP_IPV4_LUT_DSCP2UP_LUT_0_M MAKEMASK(0x7, 0)
	#define PRTDCB_TX_DSCP2UP_IPV4_LUT_DSCP2UP_LUT_1_S 4			#define PRTDCB_TX_DSCP2UP_IPV4_LUT_DSCP2UP_LUT_1_S 4
	#define PRTDCB_TX_DSCP2UP_IPV4_LUT_DSCP2UP_LUT_1_M MAKEMASK(0x7, 4)			#define PRTDCB_TX_DSCP2UP_IPV4_LUT_DSCP2UP_LUT_1_M MAKEMASK(0x7, 4)
	#define PRTDCB_TX_DSCP2UP_IPV4_LUT_DSCP2UP_LUT_2_S 8			#define PRTDCB_TX_DSCP2UP_IPV4_LUT_DSCP2UP_LUT_2_S 8
	#define PRTDCB_TX_DSCP2UP_IPV4_LUT_DSCP2UP_LUT_2_M MAKEMASK(0x7, 8)			#define PRTDCB_TX_DSCP2UP_IPV4_LUT_DSCP2UP_LUT_2_M MAKEMASK(0x7, 8)
	▲ Show 20 Lines • Show All 131 Lines • ▼ Show 20 Lines
	#define TPB_PRTTCB_BULK_DWRR_WB_CREDITS_CREDITS_M MAKEMASK(0x3FFFF, 0)			#define TPB_PRTTCB_BULK_DWRR_WB_CREDITS_CREDITS_M MAKEMASK(0x3FFFF, 0)
	#define TPB_PRTTCB_CREDIT_EXP 0x00099644 /* Reset Source: CORER */			#define TPB_PRTTCB_CREDIT_EXP 0x00099644 /* Reset Source: CORER */
	#define TPB_PRTTCB_CREDIT_EXP_EXPANSION_S 0			#define TPB_PRTTCB_CREDIT_EXP_EXPANSION_S 0
	#define TPB_PRTTCB_CREDIT_EXP_EXPANSION_M MAKEMASK(0xFF, 0)			#define TPB_PRTTCB_CREDIT_EXP_EXPANSION_M MAKEMASK(0xFF, 0)
	#define TPB_PRTTCB_LL_DWRR_REG_CREDITS 0x00099300 /* Reset Source: CORER */			#define TPB_PRTTCB_LL_DWRR_REG_CREDITS 0x00099300 /* Reset Source: CORER */
	#define TPB_PRTTCB_LL_DWRR_REG_CREDITS_CREDITS_S 0			#define TPB_PRTTCB_LL_DWRR_REG_CREDITS_CREDITS_S 0
	#define TPB_PRTTCB_LL_DWRR_REG_CREDITS_CREDITS_M MAKEMASK(0x3FFFF, 0)			#define TPB_PRTTCB_LL_DWRR_REG_CREDITS_CREDITS_M MAKEMASK(0x3FFFF, 0)
	#define TPB_PRTTCB_LL_DWRR_WB_CREDITS 0x00099320 /* Reset Source: CORER */			#define TPB_PRTTCB_LL_DWRR_WB_CREDITS 0x00099320 /* Reset Source: CORER */
	#define TPB_PRTTCB_LL_DWRR_WB_CREDITS_CREDITS_S 0			#define TPB_PRTTCB_LL_DWRR_WB_CREDITS_CREDITS_S 0
	#define TPB_PRTTCB_LL_DWRR_WB_CREDITS_CREDITS_M MAKEMASK(0x3FFFF, 0)			#define TPB_PRTTCB_LL_DWRR_WB_CREDITS_CREDITS_M MAKEMASK(0x3FFFF, 0)
	#define TPB_WB_RL_TC_CFG(_i) (0x00099360 + ((_i) * 4)) /* _i=0...31 / / Reset Source: CORER */			#define TPB_WB_RL_TC_CFG(_i) (0x00099360 + ((_i) * 4)) /* _i=0...31 / / Reset Source: CORER */
	#define TPB_WB_RL_TC_CFG_MAX_INDEX 31			#define TPB_WB_RL_TC_CFG_MAX_INDEX 31
	#define TPB_WB_RL_TC_CFG_TOKENS_S 0			#define TPB_WB_RL_TC_CFG_TOKENS_S 0
	#define TPB_WB_RL_TC_CFG_TOKENS_M MAKEMASK(0xFFF, 0)			#define TPB_WB_RL_TC_CFG_TOKENS_M MAKEMASK(0xFFF, 0)
	#define TPB_WB_RL_TC_CFG_BURST_SIZE_S 12			#define TPB_WB_RL_TC_CFG_BURST_SIZE_S 12
	#define TPB_WB_RL_TC_CFG_BURST_SIZE_M MAKEMASK(0x3FF, 12)			#define TPB_WB_RL_TC_CFG_BURST_SIZE_M MAKEMASK(0x3FF, 12)
	#define TPB_WB_RL_TC_STAT(_i) (0x000993E0 + ((_i) * 4)) /* _i=0...31 / / Reset Source: CORER */			#define TPB_WB_RL_TC_STAT(_i) (0x000993E0 + ((_i) * 4)) /* _i=0...31 / / Reset Source: CORER */
	#define TPB_WB_RL_TC_STAT_MAX_INDEX 31			#define TPB_WB_RL_TC_STAT_MAX_INDEX 31
	▲ Show 20 Lines • Show All 48 Lines • ▼ Show 20 Lines
	#define GL_ACLEXT_FLGS_L1TBL_LSB_S 0			#define GL_ACLEXT_FLGS_L1TBL_LSB_S 0
	#define GL_ACLEXT_FLGS_L1TBL_LSB_M MAKEMASK(0xFFFF, 0)			#define GL_ACLEXT_FLGS_L1TBL_LSB_M MAKEMASK(0xFFFF, 0)
	#define GL_ACLEXT_FLGS_L1TBL_MSB_S 16			#define GL_ACLEXT_FLGS_L1TBL_MSB_S 16
	#define GL_ACLEXT_FLGS_L1TBL_MSB_M MAKEMASK(0xFFFF, 16)			#define GL_ACLEXT_FLGS_L1TBL_MSB_M MAKEMASK(0xFFFF, 16)
	#define GL_ACLEXT_FORCE_L1CDID(_i) (0x00210018 + ((_i) * 4)) /* _i=0...2 / / Reset Source: CORER */			#define GL_ACLEXT_FORCE_L1CDID(_i) (0x00210018 + ((_i) * 4)) /* _i=0...2 / / Reset Source: CORER */
	#define GL_ACLEXT_FORCE_L1CDID_MAX_INDEX 2			#define GL_ACLEXT_FORCE_L1CDID_MAX_INDEX 2
	#define GL_ACLEXT_FORCE_L1CDID_STATIC_CDID_S 0			#define GL_ACLEXT_FORCE_L1CDID_STATIC_CDID_S 0
	#define GL_ACLEXT_FORCE_L1CDID_STATIC_CDID_M MAKEMASK(0xF, 0)			#define GL_ACLEXT_FORCE_L1CDID_STATIC_CDID_M MAKEMASK(0xF, 0)
	#define GL_ACLEXT_FORCE_L1CDID_STATIC_CDID_EN_S 31			#define GL_ACLEXT_FORCE_L1CDID_STATIC_CDID_EN_S 31
	#define GL_ACLEXT_FORCE_L1CDID_STATIC_CDID_EN_M BIT(31)			#define GL_ACLEXT_FORCE_L1CDID_STATIC_CDID_EN_M BIT(31)
	#define GL_ACLEXT_FORCE_PID(_i) (0x00210000 + ((_i) * 4)) /* _i=0...2 / / Reset Source: CORER */			#define GL_ACLEXT_FORCE_PID(_i) (0x00210000 + ((_i) * 4)) /* _i=0...2 / / Reset Source: CORER */
	#define GL_ACLEXT_FORCE_PID_MAX_INDEX 2			#define GL_ACLEXT_FORCE_PID_MAX_INDEX 2
	#define GL_ACLEXT_FORCE_PID_STATIC_PID_S 0			#define GL_ACLEXT_FORCE_PID_STATIC_PID_S 0
	#define GL_ACLEXT_FORCE_PID_STATIC_PID_M MAKEMASK(0xFFFF, 0)			#define GL_ACLEXT_FORCE_PID_STATIC_PID_M MAKEMASK(0xFFFF, 0)
	#define GL_ACLEXT_FORCE_PID_STATIC_PID_EN_S 31			#define GL_ACLEXT_FORCE_PID_STATIC_PID_EN_S 31
	#define GL_ACLEXT_FORCE_PID_STATIC_PID_EN_M BIT(31)			#define GL_ACLEXT_FORCE_PID_STATIC_PID_EN_M BIT(31)
	#define GL_ACLEXT_K2N_L2ADDR(_i) (0x00210144 + ((_i) * 4)) /* _i=0...2 / / Reset Source: CORER */			#define GL_ACLEXT_K2N_L2ADDR(_i) (0x00210144 + ((_i) * 4)) /* _i=0...2 / / Reset Source: CORER */
	#define GL_ACLEXT_K2N_L2ADDR_MAX_INDEX 2			#define GL_ACLEXT_K2N_L2ADDR_MAX_INDEX 2
	▲ Show 20 Lines • Show All 176 Lines • ▼ Show 20 Lines
	#define GL_PREEXT_FLGS_L1TBL_LSB_S 0			#define GL_PREEXT_FLGS_L1TBL_LSB_S 0
	#define GL_PREEXT_FLGS_L1TBL_LSB_M MAKEMASK(0xFFFF, 0)			#define GL_PREEXT_FLGS_L1TBL_LSB_M MAKEMASK(0xFFFF, 0)
	#define GL_PREEXT_FLGS_L1TBL_MSB_S 16			#define GL_PREEXT_FLGS_L1TBL_MSB_S 16
	#define GL_PREEXT_FLGS_L1TBL_MSB_M MAKEMASK(0xFFFF, 16)			#define GL_PREEXT_FLGS_L1TBL_MSB_M MAKEMASK(0xFFFF, 16)
	#define GL_PREEXT_FORCE_L1CDID(_i) (0x0020F018 + ((_i) * 4)) /* _i=0...2 / / Reset Source: CORER */			#define GL_PREEXT_FORCE_L1CDID(_i) (0x0020F018 + ((_i) * 4)) /* _i=0...2 / / Reset Source: CORER */
	#define GL_PREEXT_FORCE_L1CDID_MAX_INDEX 2			#define GL_PREEXT_FORCE_L1CDID_MAX_INDEX 2
	#define GL_PREEXT_FORCE_L1CDID_STATIC_CDID_S 0			#define GL_PREEXT_FORCE_L1CDID_STATIC_CDID_S 0
	#define GL_PREEXT_FORCE_L1CDID_STATIC_CDID_M MAKEMASK(0xF, 0)			#define GL_PREEXT_FORCE_L1CDID_STATIC_CDID_M MAKEMASK(0xF, 0)
	#define GL_PREEXT_FORCE_L1CDID_STATIC_CDID_EN_S 31			#define GL_PREEXT_FORCE_L1CDID_STATIC_CDID_EN_S 31
	#define GL_PREEXT_FORCE_L1CDID_STATIC_CDID_EN_M BIT(31)			#define GL_PREEXT_FORCE_L1CDID_STATIC_CDID_EN_M BIT(31)
	#define GL_PREEXT_FORCE_PID(_i) (0x0020F000 + ((_i) * 4)) /* _i=0...2 / / Reset Source: CORER */			#define GL_PREEXT_FORCE_PID(_i) (0x0020F000 + ((_i) * 4)) /* _i=0...2 / / Reset Source: CORER */
	#define GL_PREEXT_FORCE_PID_MAX_INDEX 2			#define GL_PREEXT_FORCE_PID_MAX_INDEX 2
	#define GL_PREEXT_FORCE_PID_STATIC_PID_S 0			#define GL_PREEXT_FORCE_PID_STATIC_PID_S 0
	#define GL_PREEXT_FORCE_PID_STATIC_PID_M MAKEMASK(0xFFFF, 0)			#define GL_PREEXT_FORCE_PID_STATIC_PID_M MAKEMASK(0xFFFF, 0)
	#define GL_PREEXT_FORCE_PID_STATIC_PID_EN_S 31			#define GL_PREEXT_FORCE_PID_STATIC_PID_EN_S 31
	#define GL_PREEXT_FORCE_PID_STATIC_PID_EN_M BIT(31)			#define GL_PREEXT_FORCE_PID_STATIC_PID_EN_M BIT(31)
	#define GL_PREEXT_K2N_L2ADDR(_i) (0x0020F144 + ((_i) * 4)) /* _i=0...2 / / Reset Source: CORER */			#define GL_PREEXT_K2N_L2ADDR(_i) (0x0020F144 + ((_i) * 4)) /* _i=0...2 / / Reset Source: CORER */
	#define GL_PREEXT_K2N_L2ADDR_MAX_INDEX 2			#define GL_PREEXT_K2N_L2ADDR_MAX_INDEX 2
	▲ Show 20 Lines • Show All 184 Lines • ▼ Show 20 Lines
	#define GL_PSTEXT_FLGS_L1TBL_LSB_S 0			#define GL_PSTEXT_FLGS_L1TBL_LSB_S 0
	#define GL_PSTEXT_FLGS_L1TBL_LSB_M MAKEMASK(0xFFFF, 0)			#define GL_PSTEXT_FLGS_L1TBL_LSB_M MAKEMASK(0xFFFF, 0)
	#define GL_PSTEXT_FLGS_L1TBL_MSB_S 16			#define GL_PSTEXT_FLGS_L1TBL_MSB_S 16
	#define GL_PSTEXT_FLGS_L1TBL_MSB_M MAKEMASK(0xFFFF, 16)			#define GL_PSTEXT_FLGS_L1TBL_MSB_M MAKEMASK(0xFFFF, 16)
	#define GL_PSTEXT_FORCE_L1CDID(_i) (0x0020E018 + ((_i) * 4)) /* _i=0...2 / / Reset Source: CORER */			#define GL_PSTEXT_FORCE_L1CDID(_i) (0x0020E018 + ((_i) * 4)) /* _i=0...2 / / Reset Source: CORER */
	#define GL_PSTEXT_FORCE_L1CDID_MAX_INDEX 2			#define GL_PSTEXT_FORCE_L1CDID_MAX_INDEX 2
	#define GL_PSTEXT_FORCE_L1CDID_STATIC_CDID_S 0			#define GL_PSTEXT_FORCE_L1CDID_STATIC_CDID_S 0
	#define GL_PSTEXT_FORCE_L1CDID_STATIC_CDID_M MAKEMASK(0xF, 0)			#define GL_PSTEXT_FORCE_L1CDID_STATIC_CDID_M MAKEMASK(0xF, 0)
	#define GL_PSTEXT_FORCE_L1CDID_STATIC_CDID_EN_S 31			#define GL_PSTEXT_FORCE_L1CDID_STATIC_CDID_EN_S 31
	#define GL_PSTEXT_FORCE_L1CDID_STATIC_CDID_EN_M BIT(31)			#define GL_PSTEXT_FORCE_L1CDID_STATIC_CDID_EN_M BIT(31)
	#define GL_PSTEXT_FORCE_PID(_i) (0x0020E000 + ((_i) * 4)) /* _i=0...2 / / Reset Source: CORER */			#define GL_PSTEXT_FORCE_PID(_i) (0x0020E000 + ((_i) * 4)) /* _i=0...2 / / Reset Source: CORER */
	#define GL_PSTEXT_FORCE_PID_MAX_INDEX 2			#define GL_PSTEXT_FORCE_PID_MAX_INDEX 2
	#define GL_PSTEXT_FORCE_PID_STATIC_PID_S 0			#define GL_PSTEXT_FORCE_PID_STATIC_PID_S 0
	#define GL_PSTEXT_FORCE_PID_STATIC_PID_M MAKEMASK(0xFFFF, 0)			#define GL_PSTEXT_FORCE_PID_STATIC_PID_M MAKEMASK(0xFFFF, 0)
	#define GL_PSTEXT_FORCE_PID_STATIC_PID_EN_S 31			#define GL_PSTEXT_FORCE_PID_STATIC_PID_EN_S 31
	#define GL_PSTEXT_FORCE_PID_STATIC_PID_EN_M BIT(31)			#define GL_PSTEXT_FORCE_PID_STATIC_PID_EN_M BIT(31)
	#define GL_PSTEXT_K2N_L2ADDR(_i) (0x0020E144 + ((_i) * 4)) /* _i=0...2 / / Reset Source: CORER */			#define GL_PSTEXT_K2N_L2ADDR(_i) (0x0020E144 + ((_i) * 4)) /* _i=0...2 / / Reset Source: CORER */
	#define GL_PSTEXT_K2N_L2ADDR_MAX_INDEX 2			#define GL_PSTEXT_K2N_L2ADDR_MAX_INDEX 2
	▲ Show 20 Lines • Show All 150 Lines • ▼ Show 20 Lines
	#define GLFLXP_RX_CMD_LX_PROT_IDX(_i) (0x0045C400 + ((_i) * 4)) /* _i=0...255 / / Reset Source: CORER */			#define GLFLXP_RX_CMD_LX_PROT_IDX(_i) (0x0045C400 + ((_i) * 4)) /* _i=0...255 / / Reset Source: CORER */
	#define GLFLXP_RX_CMD_LX_PROT_IDX_MAX_INDEX 255			#define GLFLXP_RX_CMD_LX_PROT_IDX_MAX_INDEX 255
	#define GLFLXP_RX_CMD_LX_PROT_IDX_INNER_CLOUD_OFFSET_INDEX_S 0			#define GLFLXP_RX_CMD_LX_PROT_IDX_INNER_CLOUD_OFFSET_INDEX_S 0
	#define GLFLXP_RX_CMD_LX_PROT_IDX_INNER_CLOUD_OFFSET_INDEX_M MAKEMASK(0x7, 0)			#define GLFLXP_RX_CMD_LX_PROT_IDX_INNER_CLOUD_OFFSET_INDEX_M MAKEMASK(0x7, 0)
	#define GLFLXP_RX_CMD_LX_PROT_IDX_L4_OFFSET_INDEX_S 4			#define GLFLXP_RX_CMD_LX_PROT_IDX_L4_OFFSET_INDEX_S 4
	#define GLFLXP_RX_CMD_LX_PROT_IDX_L4_OFFSET_INDEX_M MAKEMASK(0x7, 4)			#define GLFLXP_RX_CMD_LX_PROT_IDX_L4_OFFSET_INDEX_M MAKEMASK(0x7, 4)
	#define GLFLXP_RX_CMD_LX_PROT_IDX_PAYLOAD_OFFSET_INDEX_S 8			#define GLFLXP_RX_CMD_LX_PROT_IDX_PAYLOAD_OFFSET_INDEX_S 8
	#define GLFLXP_RX_CMD_LX_PROT_IDX_PAYLOAD_OFFSET_INDEX_M MAKEMASK(0x7, 8)			#define GLFLXP_RX_CMD_LX_PROT_IDX_PAYLOAD_OFFSET_INDEX_M MAKEMASK(0x7, 8)
	#define GLFLXP_RX_CMD_LX_PROT_IDX_L3_PROTOCOL_S 12			#define GLFLXP_RX_CMD_LX_PROT_IDX_L3_PROTOCOL_S 12
	#define GLFLXP_RX_CMD_LX_PROT_IDX_L3_PROTOCOL_M MAKEMASK(0x3, 12)			#define GLFLXP_RX_CMD_LX_PROT_IDX_L3_PROTOCOL_M MAKEMASK(0x3, 12)
	#define GLFLXP_RX_CMD_LX_PROT_IDX_L4_PROTOCOL_S 14			#define GLFLXP_RX_CMD_LX_PROT_IDX_L4_PROTOCOL_S 14
	#define GLFLXP_RX_CMD_LX_PROT_IDX_L4_PROTOCOL_M MAKEMASK(0x3, 14)			#define GLFLXP_RX_CMD_LX_PROT_IDX_L4_PROTOCOL_M MAKEMASK(0x3, 14)
	#define GLFLXP_RX_CMD_PROTIDS(_i, _j) (0x0045A000 + ((_i) * 4 + (_j) * 1024)) /* _i=0...255, _j=0...5 / / Reset Source: CORER */			#define GLFLXP_RX_CMD_PROTIDS(_i, _j) (0x0045A000 + ((_i) * 4 + (_j) * 1024)) /* _i=0...255, _j=0...5 / / Reset Source: CORER */
	#define GLFLXP_RX_CMD_PROTIDS_MAX_INDEX 255			#define GLFLXP_RX_CMD_PROTIDS_MAX_INDEX 255
	#define GLFLXP_RX_CMD_PROTIDS_PROTID_4N_S 0			#define GLFLXP_RX_CMD_PROTIDS_PROTID_4N_S 0
	#define GLFLXP_RX_CMD_PROTIDS_PROTID_4N_M MAKEMASK(0xFF, 0)			#define GLFLXP_RX_CMD_PROTIDS_PROTID_4N_M MAKEMASK(0xFF, 0)
	#define GLFLXP_RX_CMD_PROTIDS_PROTID_4N_1_S 8			#define GLFLXP_RX_CMD_PROTIDS_PROTID_4N_1_S 8
	#define GLFLXP_RX_CMD_PROTIDS_PROTID_4N_1_M MAKEMASK(0xFF, 8)			#define GLFLXP_RX_CMD_PROTIDS_PROTID_4N_1_M MAKEMASK(0xFF, 8)
	#define GLFLXP_RX_CMD_PROTIDS_PROTID_4N_2_S 16			#define GLFLXP_RX_CMD_PROTIDS_PROTID_4N_2_S 16
	#define GLFLXP_RX_CMD_PROTIDS_PROTID_4N_2_M MAKEMASK(0xFF, 16)			#define GLFLXP_RX_CMD_PROTIDS_PROTID_4N_2_M MAKEMASK(0xFF, 16)
	▲ Show 20 Lines • Show All 62 Lines • ▼ Show 20 Lines
	#define GLFLXP_RXDID_FLX_WRD_5_RXDID_OPCODE_S 30			#define GLFLXP_RXDID_FLX_WRD_5_RXDID_OPCODE_S 30
	#define GLFLXP_RXDID_FLX_WRD_5_RXDID_OPCODE_M MAKEMASK(0x3, 30)			#define GLFLXP_RXDID_FLX_WRD_5_RXDID_OPCODE_M MAKEMASK(0x3, 30)
	#define GLFLXP_TX_SCHED_CORRECT(_i, _j) (0x00458000 + ((_i) * 4 + (_j) * 256)) /* _i=0...63, _j=0...31 / / Reset Source: CORER */			#define GLFLXP_TX_SCHED_CORRECT(_i, _j) (0x00458000 + ((_i) * 4 + (_j) * 256)) /* _i=0...63, _j=0...31 / / Reset Source: CORER */
	#define GLFLXP_TX_SCHED_CORRECT_MAX_INDEX 63			#define GLFLXP_TX_SCHED_CORRECT_MAX_INDEX 63
	#define GLFLXP_TX_SCHED_CORRECT_PROTD_ID_2N_S 0			#define GLFLXP_TX_SCHED_CORRECT_PROTD_ID_2N_S 0
	#define GLFLXP_TX_SCHED_CORRECT_PROTD_ID_2N_M MAKEMASK(0xFF, 0)			#define GLFLXP_TX_SCHED_CORRECT_PROTD_ID_2N_M MAKEMASK(0xFF, 0)
	#define GLFLXP_TX_SCHED_CORRECT_RECIPE_2N_S 8			#define GLFLXP_TX_SCHED_CORRECT_RECIPE_2N_S 8
	#define GLFLXP_TX_SCHED_CORRECT_RECIPE_2N_M MAKEMASK(0x1F, 8)			#define GLFLXP_TX_SCHED_CORRECT_RECIPE_2N_M MAKEMASK(0x1F, 8)
	#define GLFLXP_TX_SCHED_CORRECT_PROTD_ID_2N_1_S 16			#define GLFLXP_TX_SCHED_CORRECT_PROTD_ID_2N_1_S 16
	#define GLFLXP_TX_SCHED_CORRECT_PROTD_ID_2N_1_M MAKEMASK(0xFF, 16)			#define GLFLXP_TX_SCHED_CORRECT_PROTD_ID_2N_1_M MAKEMASK(0xFF, 16)
	#define GLFLXP_TX_SCHED_CORRECT_RECIPE_2N_1_S 24			#define GLFLXP_TX_SCHED_CORRECT_RECIPE_2N_1_S 24
	#define GLFLXP_TX_SCHED_CORRECT_RECIPE_2N_1_M MAKEMASK(0x1F, 24)			#define GLFLXP_TX_SCHED_CORRECT_RECIPE_2N_1_M MAKEMASK(0x1F, 24)
	#define QRXFLXP_CNTXT(_QRX) (0x00480000 + ((_QRX) * 4)) /* _i=0...2047 / / Reset Source: CORER */			#define QRXFLXP_CNTXT(_QRX) (0x00480000 + ((_QRX) * 4)) /* _i=0...2047 / / Reset Source: CORER */
	#define QRXFLXP_CNTXT_MAX_INDEX 2047			#define QRXFLXP_CNTXT_MAX_INDEX 2047
	#define QRXFLXP_CNTXT_RXDID_IDX_S 0			#define QRXFLXP_CNTXT_RXDID_IDX_S 0
	#define QRXFLXP_CNTXT_RXDID_IDX_M MAKEMASK(0x3F, 0)			#define QRXFLXP_CNTXT_RXDID_IDX_M MAKEMASK(0x3F, 0)
	#define QRXFLXP_CNTXT_RXDID_PRIO_S 8			#define QRXFLXP_CNTXT_RXDID_PRIO_S 8
	#define QRXFLXP_CNTXT_RXDID_PRIO_M MAKEMASK(0x7, 8)			#define QRXFLXP_CNTXT_RXDID_PRIO_M MAKEMASK(0x7, 8)
	▲ Show 20 Lines • Show All 196 Lines • ▼ Show 20 Lines
	#define GLGEN_ANA_PG0_HASHKEY_HASH_KEY_M MAKEMASK(0xFFFFFFFF, 0)			#define GLGEN_ANA_PG0_HASHKEY_HASH_KEY_M MAKEMASK(0xFFFFFFFF, 0)
	#define GLGEN_ANA_PROFIL_CTRL 0x0020C1FC /* Reset Source: CORER */			#define GLGEN_ANA_PROFIL_CTRL 0x0020C1FC /* Reset Source: CORER */
	#define GLGEN_ANA_PROFIL_CTRL_PROFILE_SELECT_MDID_S 0			#define GLGEN_ANA_PROFIL_CTRL_PROFILE_SELECT_MDID_S 0
	#define GLGEN_ANA_PROFIL_CTRL_PROFILE_SELECT_MDID_M MAKEMASK(0x1F, 0)			#define GLGEN_ANA_PROFIL_CTRL_PROFILE_SELECT_MDID_M MAKEMASK(0x1F, 0)
	#define GLGEN_ANA_PROFIL_CTRL_PROFILE_SELECT_MDSTART_S 5			#define GLGEN_ANA_PROFIL_CTRL_PROFILE_SELECT_MDSTART_S 5
	#define GLGEN_ANA_PROFIL_CTRL_PROFILE_SELECT_MDSTART_M MAKEMASK(0xF, 5)			#define GLGEN_ANA_PROFIL_CTRL_PROFILE_SELECT_MDSTART_M MAKEMASK(0xF, 5)
	#define GLGEN_ANA_PROFIL_CTRL_PROFILE_SELECT_MD_LEN_S 9			#define GLGEN_ANA_PROFIL_CTRL_PROFILE_SELECT_MD_LEN_S 9
	#define GLGEN_ANA_PROFIL_CTRL_PROFILE_SELECT_MD_LEN_M MAKEMASK(0x1F, 9)			#define GLGEN_ANA_PROFIL_CTRL_PROFILE_SELECT_MD_LEN_M MAKEMASK(0x1F, 9)
	#define GLGEN_ANA_PROFIL_CTRL_NUM_CTRL_DOMAIN_S 14			#define GLGEN_ANA_PROFIL_CTRL_NUM_CTRL_DOMAIN_S 14
	#define GLGEN_ANA_PROFIL_CTRL_NUM_CTRL_DOMAIN_M MAKEMASK(0x3, 14)			#define GLGEN_ANA_PROFIL_CTRL_NUM_CTRL_DOMAIN_M MAKEMASK(0x3, 14)
	#define GLGEN_ANA_PROFIL_CTRL_DEF_PROF_ID_S 16			#define GLGEN_ANA_PROFIL_CTRL_DEF_PROF_ID_S 16
	#define GLGEN_ANA_PROFIL_CTRL_DEF_PROF_ID_M MAKEMASK(0xF, 16)			#define GLGEN_ANA_PROFIL_CTRL_DEF_PROF_ID_M MAKEMASK(0xF, 16)
	#define GLGEN_ANA_PROFIL_CTRL_SEL_DEF_PROF_ID_S 20			#define GLGEN_ANA_PROFIL_CTRL_SEL_DEF_PROF_ID_S 20
	#define GLGEN_ANA_PROFIL_CTRL_SEL_DEF_PROF_ID_M BIT(20)			#define GLGEN_ANA_PROFIL_CTRL_SEL_DEF_PROF_ID_M BIT(20)
	#define GLGEN_ANA_TX_ABORT_PTYPE 0x0020D21C /* Reset Source: CORER */			#define GLGEN_ANA_TX_ABORT_PTYPE 0x0020D21C /* Reset Source: CORER */
	#define GLGEN_ANA_TX_ABORT_PTYPE_ABORT_S 0			#define GLGEN_ANA_TX_ABORT_PTYPE_ABORT_S 0
	#define GLGEN_ANA_TX_ABORT_PTYPE_ABORT_M MAKEMASK(0x3FF, 0)			#define GLGEN_ANA_TX_ABORT_PTYPE_ABORT_M MAKEMASK(0x3FF, 0)
	#define GLGEN_ANA_TX_ALU_ACCSS_OUT_OF_PKT 0x0020D208 /* Reset Source: CORER */			#define GLGEN_ANA_TX_ALU_ACCSS_OUT_OF_PKT 0x0020D208 /* Reset Source: CORER */
	#define GLGEN_ANA_TX_ALU_ACCSS_OUT_OF_PKT_NPC_S 0			#define GLGEN_ANA_TX_ALU_ACCSS_OUT_OF_PKT_NPC_S 0
	#define GLGEN_ANA_TX_ALU_ACCSS_OUT_OF_PKT_NPC_M MAKEMASK(0xFF, 0)			#define GLGEN_ANA_TX_ALU_ACCSS_OUT_OF_PKT_NPC_M MAKEMASK(0xFF, 0)
	#define GLGEN_ANA_TX_CFG_CTRL 0x0020D104 /* Reset Source: CORER */			#define GLGEN_ANA_TX_CFG_CTRL 0x0020D104 /* Reset Source: CORER */
	#define GLGEN_ANA_TX_CFG_CTRL_LINE_IDX_S 0			#define GLGEN_ANA_TX_CFG_CTRL_LINE_IDX_S 0
	#define GLGEN_ANA_TX_CFG_CTRL_LINE_IDX_M MAKEMASK(0x3FFFF, 0)			#define GLGEN_ANA_TX_CFG_CTRL_LINE_IDX_M MAKEMASK(0x3FFFF, 0)
	#define GLGEN_ANA_TX_CFG_CTRL_TABLE_ID_S 18			#define GLGEN_ANA_TX_CFG_CTRL_TABLE_ID_S 18
	#define GLGEN_ANA_TX_CFG_CTRL_TABLE_ID_M MAKEMASK(0xFF, 18)			#define GLGEN_ANA_TX_CFG_CTRL_TABLE_ID_M MAKEMASK(0xFF, 18)
	#define GLGEN_ANA_TX_CFG_CTRL_RESRVED_S 26			#define GLGEN_ANA_TX_CFG_CTRL_RESRVED_S 26
	#define GLGEN_ANA_TX_CFG_CTRL_RESRVED_M MAKEMASK(0x7, 26)			#define GLGEN_ANA_TX_CFG_CTRL_RESRVED_M MAKEMASK(0x7, 26)
	#define GLGEN_ANA_TX_CFG_CTRL_OPERATION_ID_S 29			#define GLGEN_ANA_TX_CFG_CTRL_OPERATION_ID_S 29
	Show All 9 Lines
	#define GLGEN_ANA_TX_CFG_LU_KEY_MAX_INDEX 2			#define GLGEN_ANA_TX_CFG_LU_KEY_MAX_INDEX 2
	#define GLGEN_ANA_TX_CFG_LU_KEY_LU_KEY_S 0			#define GLGEN_ANA_TX_CFG_LU_KEY_LU_KEY_S 0
	#define GLGEN_ANA_TX_CFG_LU_KEY_LU_KEY_M MAKEMASK(0xFFFFFFFF, 0)			#define GLGEN_ANA_TX_CFG_LU_KEY_LU_KEY_M MAKEMASK(0xFFFFFFFF, 0)
	#define GLGEN_ANA_TX_CFG_RDDATA(_i) (0x0020D10C + ((_i) * 4)) /* _i=0...15 / / Reset Source: CORER */			#define GLGEN_ANA_TX_CFG_RDDATA(_i) (0x0020D10C + ((_i) * 4)) /* _i=0...15 / / Reset Source: CORER */
	#define GLGEN_ANA_TX_CFG_RDDATA_MAX_INDEX 15			#define GLGEN_ANA_TX_CFG_RDDATA_MAX_INDEX 15
	#define GLGEN_ANA_TX_CFG_RDDATA_RD_DATA_S 0			#define GLGEN_ANA_TX_CFG_RDDATA_RD_DATA_S 0
	#define GLGEN_ANA_TX_CFG_RDDATA_RD_DATA_M MAKEMASK(0xFFFFFFFF, 0)			#define GLGEN_ANA_TX_CFG_RDDATA_RD_DATA_M MAKEMASK(0xFFFFFFFF, 0)
	#define GLGEN_ANA_TX_CFG_SPLBUF_LU_RESULT 0x0020D15C /* Reset Source: CORER */			#define GLGEN_ANA_TX_CFG_SPLBUF_LU_RESULT 0x0020D15C /* Reset Source: CORER */
	#define GLGEN_ANA_TX_CFG_SPLBUF_LU_RESULT_HIT_S 0			#define GLGEN_ANA_TX_CFG_SPLBUF_LU_RESULT_HIT_S 0
	#define GLGEN_ANA_TX_CFG_SPLBUF_LU_RESULT_HIT_M BIT(0)			#define GLGEN_ANA_TX_CFG_SPLBUF_LU_RESULT_HIT_M BIT(0)
	#define GLGEN_ANA_TX_CFG_SPLBUF_LU_RESULT_RSV_S 1			#define GLGEN_ANA_TX_CFG_SPLBUF_LU_RESULT_RSV_S 1
	#define GLGEN_ANA_TX_CFG_SPLBUF_LU_RESULT_RSV_M MAKEMASK(0x7, 1)			#define GLGEN_ANA_TX_CFG_SPLBUF_LU_RESULT_RSV_M MAKEMASK(0x7, 1)
	#define GLGEN_ANA_TX_CFG_SPLBUF_LU_RESULT_ADDR_S 4			#define GLGEN_ANA_TX_CFG_SPLBUF_LU_RESULT_ADDR_S 4
	#define GLGEN_ANA_TX_CFG_SPLBUF_LU_RESULT_ADDR_M MAKEMASK(0x1FF, 4)			#define GLGEN_ANA_TX_CFG_SPLBUF_LU_RESULT_ADDR_M MAKEMASK(0x1FF, 4)
	#define GLGEN_ANA_TX_CFG_WRDATA 0x0020D108 /* Reset Source: CORER */			#define GLGEN_ANA_TX_CFG_WRDATA 0x0020D108 /* Reset Source: CORER */
	#define GLGEN_ANA_TX_CFG_WRDATA_WR_DATA_S 0			#define GLGEN_ANA_TX_CFG_WRDATA_WR_DATA_S 0
	#define GLGEN_ANA_TX_CFG_WRDATA_WR_DATA_M MAKEMASK(0xFFFFFFFF, 0)			#define GLGEN_ANA_TX_CFG_WRDATA_WR_DATA_M MAKEMASK(0xFFFFFFFF, 0)
	#define GLGEN_ANA_TX_DEF_PTYPE 0x0020D100 /* Reset Source: CORER */			#define GLGEN_ANA_TX_DEF_PTYPE 0x0020D100 /* Reset Source: CORER */
	#define GLGEN_ANA_TX_DEF_PTYPE_DEF_PTYPE_S 0			#define GLGEN_ANA_TX_DEF_PTYPE_DEF_PTYPE_S 0
	#define GLGEN_ANA_TX_DEF_PTYPE_DEF_PTYPE_M MAKEMASK(0x3FF, 0)			#define GLGEN_ANA_TX_DEF_PTYPE_DEF_PTYPE_M MAKEMASK(0x3FF, 0)
	▲ Show 20 Lines • Show All 302 Lines • ▼ Show 20 Lines
	#define GLHMC_FWPDINV_FPMAT_PMSDPARTSEL_S 15			#define GLHMC_FWPDINV_FPMAT_PMSDPARTSEL_S 15
	#define GLHMC_FWPDINV_FPMAT_PMSDPARTSEL_M BIT(15)			#define GLHMC_FWPDINV_FPMAT_PMSDPARTSEL_M BIT(15)
	#define GLHMC_FWPDINV_FPMAT_PMPDIDX_S 16			#define GLHMC_FWPDINV_FPMAT_PMPDIDX_S 16
	#define GLHMC_FWPDINV_FPMAT_PMPDIDX_M MAKEMASK(0x1FF, 16)			#define GLHMC_FWPDINV_FPMAT_PMPDIDX_M MAKEMASK(0x1FF, 16)
	#define GLHMC_FWSDDATAHIGH 0x00522078 /* Reset Source: CORER */			#define GLHMC_FWSDDATAHIGH 0x00522078 /* Reset Source: CORER */
	#define GLHMC_FWSDDATAHIGH_PMSDDATAHIGH_S 0			#define GLHMC_FWSDDATAHIGH_PMSDDATAHIGH_S 0
	#define GLHMC_FWSDDATAHIGH_PMSDDATAHIGH_M MAKEMASK(0xFFFFFFFF, 0)			#define GLHMC_FWSDDATAHIGH_PMSDDATAHIGH_M MAKEMASK(0xFFFFFFFF, 0)
	#define GLHMC_FWSDDATAHIGH_FPMAT 0x00102078 /* Reset Source: CORER */			#define GLHMC_FWSDDATAHIGH_FPMAT 0x00102078 /* Reset Source: CORER */
	#define GLHMC_FWSDDATAHIGH_FPMAT_PMSDDATAHIGH_S 0			#define GLHMC_FWSDDATAHIGH_FPMAT_PMSDDATAHIGH_S 0
	#define GLHMC_FWSDDATAHIGH_FPMAT_PMSDDATAHIGH_M MAKEMASK(0xFFFFFFFF, 0)			#define GLHMC_FWSDDATAHIGH_FPMAT_PMSDDATAHIGH_M MAKEMASK(0xFFFFFFFF, 0)
	#define GLHMC_FWSDDATALOW 0x00522074 /* Reset Source: CORER */			#define GLHMC_FWSDDATALOW 0x00522074 /* Reset Source: CORER */
	#define GLHMC_FWSDDATALOW_PMSDVALID_S 0			#define GLHMC_FWSDDATALOW_PMSDVALID_S 0
	#define GLHMC_FWSDDATALOW_PMSDVALID_M BIT(0)			#define GLHMC_FWSDDATALOW_PMSDVALID_M BIT(0)
	#define GLHMC_FWSDDATALOW_PMSDTYPE_S 1			#define GLHMC_FWSDDATALOW_PMSDTYPE_S 1
	#define GLHMC_FWSDDATALOW_PMSDTYPE_M BIT(1)			#define GLHMC_FWSDDATALOW_PMSDTYPE_M BIT(1)
	#define GLHMC_FWSDDATALOW_PMSDBPCOUNT_S 2			#define GLHMC_FWSDDATALOW_PMSDBPCOUNT_S 2
	#define GLHMC_FWSDDATALOW_PMSDBPCOUNT_M MAKEMASK(0x3FF, 2)			#define GLHMC_FWSDDATALOW_PMSDBPCOUNT_M MAKEMASK(0x3FF, 2)
	#define GLHMC_FWSDDATALOW_PMSDDATALOW_S 12			#define GLHMC_FWSDDATALOW_PMSDDATALOW_S 12
	▲ Show 20 Lines • Show All 381 Lines • ▼ Show 20 Lines
	#define GLHMC_VFPEMRBASE_FPMPEMRBASE_S 0			#define GLHMC_VFPEMRBASE_FPMPEMRBASE_S 0
	#define GLHMC_VFPEMRBASE_FPMPEMRBASE_M MAKEMASK(0xFFFFFF, 0)			#define GLHMC_VFPEMRBASE_FPMPEMRBASE_M MAKEMASK(0xFFFFFF, 0)
	#define GLHMC_VFPEMRCNT(_i) (0x0052CD00 + ((_i) * 4)) /* _i=0...31 / / Reset Source: CORER */			#define GLHMC_VFPEMRCNT(_i) (0x0052CD00 + ((_i) * 4)) /* _i=0...31 / / Reset Source: CORER */
	#define GLHMC_VFPEMRCNT_MAX_INDEX 31			#define GLHMC_VFPEMRCNT_MAX_INDEX 31
	#define GLHMC_VFPEMRCNT_FPMPEMRSZ_S 0			#define GLHMC_VFPEMRCNT_FPMPEMRSZ_S 0
	#define GLHMC_VFPEMRCNT_FPMPEMRSZ_M MAKEMASK(0x1FFFFFFF, 0)			#define GLHMC_VFPEMRCNT_FPMPEMRSZ_M MAKEMASK(0x1FFFFFFF, 0)
	#define GLHMC_VFPEOOISCBASE(_i) (0x0052E600 + ((_i) * 4)) /* _i=0...31 / / Reset Source: CORER */			#define GLHMC_VFPEOOISCBASE(_i) (0x0052E600 + ((_i) * 4)) /* _i=0...31 / / Reset Source: CORER */
	#define GLHMC_VFPEOOISCBASE_MAX_INDEX 31			#define GLHMC_VFPEOOISCBASE_MAX_INDEX 31
	#define GLHMC_VFPEOOISCBASE_GLHMC_PEOOISCBASE_S 0			#define GLHMC_VFPEOOISCBASE_GLHMC_PEOOISCBASE_S 0
	#define GLHMC_VFPEOOISCBASE_GLHMC_PEOOISCBASE_M MAKEMASK(0xFFFFFFFF, 0)			#define GLHMC_VFPEOOISCBASE_GLHMC_PEOOISCBASE_M MAKEMASK(0xFFFFFFFF, 0)
	#define GLHMC_VFPEOOISCCNT(_i) (0x0052E700 + ((_i) * 4)) /* _i=0...31 / / Reset Source: CORER */			#define GLHMC_VFPEOOISCCNT(_i) (0x0052E700 + ((_i) * 4)) /* _i=0...31 / / Reset Source: CORER */
	#define GLHMC_VFPEOOISCCNT_MAX_INDEX 31			#define GLHMC_VFPEOOISCCNT_MAX_INDEX 31
	#define GLHMC_VFPEOOISCCNT_GLHMC_PEOOISCCNT_S 0			#define GLHMC_VFPEOOISCCNT_GLHMC_PEOOISCCNT_S 0
	#define GLHMC_VFPEOOISCCNT_GLHMC_PEOOISCCNT_M MAKEMASK(0xFFFFFFFF, 0)			#define GLHMC_VFPEOOISCCNT_GLHMC_PEOOISCCNT_M MAKEMASK(0xFFFFFFFF, 0)
	#define GLHMC_VFPEOOISCFFLBASE(_i) (0x0052EC00 + ((_i) * 4)) /* _i=0...31 / / Reset Source: CORER */			#define GLHMC_VFPEOOISCFFLBASE(_i) (0x0052EC00 + ((_i) * 4)) /* _i=0...31 / / Reset Source: CORER */
	#define GLHMC_VFPEOOISCFFLBASE_MAX_INDEX 31			#define GLHMC_VFPEOOISCFFLBASE_MAX_INDEX 31
	#define GLHMC_VFPEOOISCFFLBASE_GLHMC_PEOOISCFFLBASE_S 0			#define GLHMC_VFPEOOISCFFLBASE_GLHMC_PEOOISCFFLBASE_S 0
	#define GLHMC_VFPEOOISCFFLBASE_GLHMC_PEOOISCFFLBASE_M MAKEMASK(0xFFFFFFFF, 0)			#define GLHMC_VFPEOOISCFFLBASE_GLHMC_PEOOISCFFLBASE_M MAKEMASK(0xFFFFFFFF, 0)
	Show All 30 Lines
	#define GLHMC_VFPERRFBASE_GLHMC_PERRFBASE_S 0			#define GLHMC_VFPERRFBASE_GLHMC_PERRFBASE_S 0
	#define GLHMC_VFPERRFBASE_GLHMC_PERRFBASE_M MAKEMASK(0xFFFFFFFF, 0)			#define GLHMC_VFPERRFBASE_GLHMC_PERRFBASE_M MAKEMASK(0xFFFFFFFF, 0)
	#define GLHMC_VFPERRFCNT(_i) (0x0052E900 + ((_i) * 4)) /* _i=0...31 / / Reset Source: CORER */			#define GLHMC_VFPERRFCNT(_i) (0x0052E900 + ((_i) * 4)) /* _i=0...31 / / Reset Source: CORER */
	#define GLHMC_VFPERRFCNT_MAX_INDEX 31			#define GLHMC_VFPERRFCNT_MAX_INDEX 31
	#define GLHMC_VFPERRFCNT_GLHMC_PERRFCNT_S 0			#define GLHMC_VFPERRFCNT_GLHMC_PERRFCNT_S 0
	#define GLHMC_VFPERRFCNT_GLHMC_PERRFCNT_M MAKEMASK(0xFFFFFFFF, 0)			#define GLHMC_VFPERRFCNT_GLHMC_PERRFCNT_M MAKEMASK(0xFFFFFFFF, 0)
	#define GLHMC_VFPERRFFLBASE(_i) (0x0052EA00 + ((_i) * 4)) /* _i=0...31 / / Reset Source: CORER */			#define GLHMC_VFPERRFFLBASE(_i) (0x0052EA00 + ((_i) * 4)) /* _i=0...31 / / Reset Source: CORER */
	#define GLHMC_VFPERRFFLBASE_MAX_INDEX 31			#define GLHMC_VFPERRFFLBASE_MAX_INDEX 31
	#define GLHMC_VFPERRFFLBASE_GLHMC_PERRFFLBASE_S 0			#define GLHMC_VFPERRFFLBASE_GLHMC_PERRFFLBASE_S 0
	#define GLHMC_VFPERRFFLBASE_GLHMC_PERRFFLBASE_M MAKEMASK(0xFFFFFFFF, 0)			#define GLHMC_VFPERRFFLBASE_GLHMC_PERRFFLBASE_M MAKEMASK(0xFFFFFFFF, 0)
	#define GLHMC_VFPETIMERBASE(_i) (0x0052DA00 + ((_i) * 4)) /* _i=0...31 / / Reset Source: CORER */			#define GLHMC_VFPETIMERBASE(_i) (0x0052DA00 + ((_i) * 4)) /* _i=0...31 / / Reset Source: CORER */
	#define GLHMC_VFPETIMERBASE_MAX_INDEX 31			#define GLHMC_VFPETIMERBASE_MAX_INDEX 31
	#define GLHMC_VFPETIMERBASE_FPMPETIMERBASE_S 0			#define GLHMC_VFPETIMERBASE_FPMPETIMERBASE_S 0
	#define GLHMC_VFPETIMERBASE_FPMPETIMERBASE_M MAKEMASK(0xFFFFFF, 0)			#define GLHMC_VFPETIMERBASE_FPMPETIMERBASE_M MAKEMASK(0xFFFFFF, 0)
	#define GLHMC_VFPETIMERCNT(_i) (0x0052DB00 + ((_i) * 4)) /* _i=0...31 / / Reset Source: CORER */			#define GLHMC_VFPETIMERCNT(_i) (0x0052DB00 + ((_i) * 4)) /* _i=0...31 / / Reset Source: CORER */
	#define GLHMC_VFPETIMERCNT_MAX_INDEX 31			#define GLHMC_VFPETIMERCNT_MAX_INDEX 31
	#define GLHMC_VFPETIMERCNT_FPMPETIMERCNT_S 0			#define GLHMC_VFPETIMERCNT_FPMPETIMERCNT_S 0
	#define GLHMC_VFPETIMERCNT_FPMPETIMERCNT_M MAKEMASK(0x1FFFFFFF, 0)			#define GLHMC_VFPETIMERCNT_FPMPETIMERCNT_M MAKEMASK(0x1FFFFFFF, 0)
	Show All 10 Lines
	#define GLHMC_VFPEXFFLBASE_FPMPEXFFLBASE_S 0			#define GLHMC_VFPEXFFLBASE_FPMPEXFFLBASE_S 0
	#define GLHMC_VFPEXFFLBASE_FPMPEXFFLBASE_M MAKEMASK(0xFFFFFF, 0)			#define GLHMC_VFPEXFFLBASE_FPMPEXFFLBASE_M MAKEMASK(0xFFFFFF, 0)
	#define GLHMC_VFSDDATAHIGH(_i) (0x00528200 + ((_i) * 4)) /* _i=0...31 / / Reset Source: CORER */			#define GLHMC_VFSDDATAHIGH(_i) (0x00528200 + ((_i) * 4)) /* _i=0...31 / / Reset Source: CORER */
	#define GLHMC_VFSDDATAHIGH_MAX_INDEX 31			#define GLHMC_VFSDDATAHIGH_MAX_INDEX 31
	#define GLHMC_VFSDDATAHIGH_PMSDDATAHIGH_S 0			#define GLHMC_VFSDDATAHIGH_PMSDDATAHIGH_S 0
	#define GLHMC_VFSDDATAHIGH_PMSDDATAHIGH_M MAKEMASK(0xFFFFFFFF, 0)			#define GLHMC_VFSDDATAHIGH_PMSDDATAHIGH_M MAKEMASK(0xFFFFFFFF, 0)
	#define GLHMC_VFSDDATAHIGH_FPMAT(_i) (0x00108200 + ((_i) * 4)) /* _i=0...31 / / Reset Source: CORER */			#define GLHMC_VFSDDATAHIGH_FPMAT(_i) (0x00108200 + ((_i) * 4)) /* _i=0...31 / / Reset Source: CORER */
	#define GLHMC_VFSDDATAHIGH_FPMAT_MAX_INDEX 31			#define GLHMC_VFSDDATAHIGH_FPMAT_MAX_INDEX 31
	#define GLHMC_VFSDDATAHIGH_FPMAT_PMSDDATAHIGH_S 0			#define GLHMC_VFSDDATAHIGH_FPMAT_PMSDDATAHIGH_S 0
	#define GLHMC_VFSDDATAHIGH_FPMAT_PMSDDATAHIGH_M MAKEMASK(0xFFFFFFFF, 0)			#define GLHMC_VFSDDATAHIGH_FPMAT_PMSDDATAHIGH_M MAKEMASK(0xFFFFFFFF, 0)
	#define GLHMC_VFSDDATALOW(_i) (0x00528100 + ((_i) * 4)) /* _i=0...31 / / Reset Source: CORER */			#define GLHMC_VFSDDATALOW(_i) (0x00528100 + ((_i) * 4)) /* _i=0...31 / / Reset Source: CORER */
	#define GLHMC_VFSDDATALOW_MAX_INDEX 31			#define GLHMC_VFSDDATALOW_MAX_INDEX 31
	#define GLHMC_VFSDDATALOW_PMSDVALID_S 0			#define GLHMC_VFSDDATALOW_PMSDVALID_S 0
	#define GLHMC_VFSDDATALOW_PMSDVALID_M BIT(0)			#define GLHMC_VFSDDATALOW_PMSDVALID_M BIT(0)
	#define GLHMC_VFSDDATALOW_PMSDTYPE_S 1			#define GLHMC_VFSDDATALOW_PMSDTYPE_S 1
	#define GLHMC_VFSDDATALOW_PMSDTYPE_M BIT(1)			#define GLHMC_VFSDDATALOW_PMSDTYPE_M BIT(1)
	#define GLHMC_VFSDDATALOW_PMSDBPCOUNT_S 2			#define GLHMC_VFSDDATALOW_PMSDBPCOUNT_S 2
	#define GLHMC_VFSDDATALOW_PMSDBPCOUNT_M MAKEMASK(0x3FF, 2)			#define GLHMC_VFSDDATALOW_PMSDBPCOUNT_M MAKEMASK(0x3FF, 2)
	▲ Show 20 Lines • Show All 89 Lines • ▼ Show 20 Lines
	#define PFHMC_ERRORINFO_ERROR_DETECTED_M BIT(31)			#define PFHMC_ERRORINFO_ERROR_DETECTED_M BIT(31)
	#define PFHMC_ERRORINFO_FPMAT 0x00100400 /* Reset Source: PFR */			#define PFHMC_ERRORINFO_FPMAT 0x00100400 /* Reset Source: PFR */
	#define PFHMC_ERRORINFO_FPMAT_PMF_INDEX_S 0			#define PFHMC_ERRORINFO_FPMAT_PMF_INDEX_S 0
	#define PFHMC_ERRORINFO_FPMAT_PMF_INDEX_M MAKEMASK(0x1F, 0)			#define PFHMC_ERRORINFO_FPMAT_PMF_INDEX_M MAKEMASK(0x1F, 0)
	#define PFHMC_ERRORINFO_FPMAT_PMF_ISVF_S 7			#define PFHMC_ERRORINFO_FPMAT_PMF_ISVF_S 7
	#define PFHMC_ERRORINFO_FPMAT_PMF_ISVF_M BIT(7)			#define PFHMC_ERRORINFO_FPMAT_PMF_ISVF_M BIT(7)
	#define PFHMC_ERRORINFO_FPMAT_HMC_ERROR_TYPE_S 8			#define PFHMC_ERRORINFO_FPMAT_HMC_ERROR_TYPE_S 8
	#define PFHMC_ERRORINFO_FPMAT_HMC_ERROR_TYPE_M MAKEMASK(0xF, 8)			#define PFHMC_ERRORINFO_FPMAT_HMC_ERROR_TYPE_M MAKEMASK(0xF, 8)
	#define PFHMC_ERRORINFO_FPMAT_HMC_OBJECT_TYPE_S 16			#define PFHMC_ERRORINFO_FPMAT_HMC_OBJECT_TYPE_S 16
	#define PFHMC_ERRORINFO_FPMAT_HMC_OBJECT_TYPE_M MAKEMASK(0x1F, 16)			#define PFHMC_ERRORINFO_FPMAT_HMC_OBJECT_TYPE_M MAKEMASK(0x1F, 16)
	#define PFHMC_ERRORINFO_FPMAT_ERROR_DETECTED_S 31			#define PFHMC_ERRORINFO_FPMAT_ERROR_DETECTED_S 31
	#define PFHMC_ERRORINFO_FPMAT_ERROR_DETECTED_M BIT(31)			#define PFHMC_ERRORINFO_FPMAT_ERROR_DETECTED_M BIT(31)
	#define PFHMC_PDINV 0x00520300 /* Reset Source: PFR */			#define PFHMC_PDINV 0x00520300 /* Reset Source: PFR */
	#define PFHMC_PDINV_PMSDIDX_S 0			#define PFHMC_PDINV_PMSDIDX_S 0
	#define PFHMC_PDINV_PMSDIDX_M MAKEMASK(0xFFF, 0)			#define PFHMC_PDINV_PMSDIDX_M MAKEMASK(0xFFF, 0)
	#define PFHMC_PDINV_PMSDPARTSEL_S 15			#define PFHMC_PDINV_PMSDPARTSEL_S 15
	#define PFHMC_PDINV_PMSDPARTSEL_M BIT(15)			#define PFHMC_PDINV_PMSDPARTSEL_M BIT(15)
	#define PFHMC_PDINV_PMPDIDX_S 16			#define PFHMC_PDINV_PMPDIDX_S 16
	▲ Show 20 Lines • Show All 70 Lines • ▼ Show 20 Lines
	#define GL_MDCK_TDAT_TCLAN_TSO_TAIL_REACHED_BEFORE_TLEN_END_S 9			#define GL_MDCK_TDAT_TCLAN_TSO_TAIL_REACHED_BEFORE_TLEN_END_S 9
	#define GL_MDCK_TDAT_TCLAN_TSO_TAIL_REACHED_BEFORE_TLEN_END_M BIT(9)			#define GL_MDCK_TDAT_TCLAN_TSO_TAIL_REACHED_BEFORE_TLEN_END_M BIT(9)
	#define GL_MDCK_TDAT_TCLAN_TSO_MORE_THAN_3_HDRS_S 10			#define GL_MDCK_TDAT_TCLAN_TSO_MORE_THAN_3_HDRS_S 10
	#define GL_MDCK_TDAT_TCLAN_TSO_MORE_THAN_3_HDRS_M BIT(10)			#define GL_MDCK_TDAT_TCLAN_TSO_MORE_THAN_3_HDRS_M BIT(10)
	#define GL_MDCK_TDAT_TCLAN_TSO_SUM_BUFFS_LT_SUM_HDRS_S 11			#define GL_MDCK_TDAT_TCLAN_TSO_SUM_BUFFS_LT_SUM_HDRS_S 11
	#define GL_MDCK_TDAT_TCLAN_TSO_SUM_BUFFS_LT_SUM_HDRS_M BIT(11)			#define GL_MDCK_TDAT_TCLAN_TSO_SUM_BUFFS_LT_SUM_HDRS_M BIT(11)
	#define GL_MDCK_TDAT_TCLAN_TSO_ZERO_MSS_TLEN_HDRS_S 12			#define GL_MDCK_TDAT_TCLAN_TSO_ZERO_MSS_TLEN_HDRS_S 12
	#define GL_MDCK_TDAT_TCLAN_TSO_ZERO_MSS_TLEN_HDRS_M BIT(12)			#define GL_MDCK_TDAT_TCLAN_TSO_ZERO_MSS_TLEN_HDRS_M BIT(12)
	#define GL_MDCK_TDAT_TCLAN_TSO_CTX_DESC_IPSEC_S 13			#define GL_MDCK_TDAT_TCLAN_TSO_CTX_DESC_IPSEC_S 13
	#define GL_MDCK_TDAT_TCLAN_TSO_CTX_DESC_IPSEC_M BIT(13)			#define GL_MDCK_TDAT_TCLAN_TSO_CTX_DESC_IPSEC_M BIT(13)
	#define GL_MDCK_TDAT_TCLAN_SSO_COMS_NOT_WHOLE_PKT_NUM_IN_QUANTA_S 14			#define GL_MDCK_TDAT_TCLAN_SSO_COMS_NOT_WHOLE_PKT_NUM_IN_QUANTA_S 14
	#define GL_MDCK_TDAT_TCLAN_SSO_COMS_NOT_WHOLE_PKT_NUM_IN_QUANTA_M BIT(14)			#define GL_MDCK_TDAT_TCLAN_SSO_COMS_NOT_WHOLE_PKT_NUM_IN_QUANTA_M BIT(14)
	#define GL_MDCK_TDAT_TCLAN_COMS_QUANTA_BYTES_EXCEED_PKTLEN_X_64_S 15			#define GL_MDCK_TDAT_TCLAN_COMS_QUANTA_BYTES_EXCEED_PKTLEN_X_64_S 15
	#define GL_MDCK_TDAT_TCLAN_COMS_QUANTA_BYTES_EXCEED_PKTLEN_X_64_M BIT(15)			#define GL_MDCK_TDAT_TCLAN_COMS_QUANTA_BYTES_EXCEED_PKTLEN_X_64_M BIT(15)
	#define GL_MDCK_TDAT_TCLAN_COMS_QUANTA_CMDS_EXCEED_S 16			#define GL_MDCK_TDAT_TCLAN_COMS_QUANTA_CMDS_EXCEED_S 16
	#define GL_MDCK_TDAT_TCLAN_COMS_QUANTA_CMDS_EXCEED_M BIT(16)			#define GL_MDCK_TDAT_TCLAN_COMS_QUANTA_CMDS_EXCEED_M BIT(16)
	#define GL_MDCK_TDAT_TCLAN_TSO_COMS_TSO_DESCS_LAST_LSO_QUANTA_S 17			#define GL_MDCK_TDAT_TCLAN_TSO_COMS_TSO_DESCS_LAST_LSO_QUANTA_S 17
	#define GL_MDCK_TDAT_TCLAN_TSO_COMS_TSO_DESCS_LAST_LSO_QUANTA_M BIT(17)			#define GL_MDCK_TDAT_TCLAN_TSO_COMS_TSO_DESCS_LAST_LSO_QUANTA_M BIT(17)
	▲ Show 20 Lines • Show All 878 Lines • ▼ Show 20 Lines
	#define PRTMAC_HSEC_CTL_RX_ENABLE_GPP_HSEC_CTL_RX_ENABLE_GPP_S 0			#define PRTMAC_HSEC_CTL_RX_ENABLE_GPP_HSEC_CTL_RX_ENABLE_GPP_S 0
	#define PRTMAC_HSEC_CTL_RX_ENABLE_GPP_HSEC_CTL_RX_ENABLE_GPP_M BIT(0)			#define PRTMAC_HSEC_CTL_RX_ENABLE_GPP_HSEC_CTL_RX_ENABLE_GPP_M BIT(0)
	#define PRTMAC_HSEC_CTL_RX_ENABLE_PPP 0x001E35C0 /* Reset Source: GLOBR */			#define PRTMAC_HSEC_CTL_RX_ENABLE_PPP 0x001E35C0 /* Reset Source: GLOBR */
	#define PRTMAC_HSEC_CTL_RX_ENABLE_PPP_HSEC_CTL_RX_ENABLE_PPP_S 0			#define PRTMAC_HSEC_CTL_RX_ENABLE_PPP_HSEC_CTL_RX_ENABLE_PPP_S 0
	#define PRTMAC_HSEC_CTL_RX_ENABLE_PPP_HSEC_CTL_RX_ENABLE_PPP_M BIT(0)			#define PRTMAC_HSEC_CTL_RX_ENABLE_PPP_HSEC_CTL_RX_ENABLE_PPP_M BIT(0)
	#define PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL 0x001E36C0 /* Reset Source: GLOBR */			#define PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL 0x001E36C0 /* Reset Source: GLOBR */
	#define PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL_HSEC_CTL_RX_FORWARD_CONTROL_S 0			#define PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL_HSEC_CTL_RX_FORWARD_CONTROL_S 0
	#define PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL_HSEC_CTL_RX_FORWARD_CONTROL_M BIT(0)			#define PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL_HSEC_CTL_RX_FORWARD_CONTROL_M BIT(0)
	#define PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1 0x001E3220 /* Reset Source: GLOBR */			#define PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1 0x001E3220 /* Reset Source: GLOBR */
	#define PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1_S 0			#define PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1_S 0
	#define PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1_M MAKEMASK(0xFFFFFFFF, 0)			#define PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1_M MAKEMASK(0xFFFFFFFF, 0)
	#define PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2 0x001E3240 /* Reset Source: GLOBR */			#define PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2 0x001E3240 /* Reset Source: GLOBR */
	#define PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2_S 0			#define PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2_S 0
	#define PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2_M MAKEMASK(0xFFFF, 0)			#define PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2_M MAKEMASK(0xFFFF, 0)
	#define PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE 0x001E3180 /* Reset Source: GLOBR */			#define PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE 0x001E3180 /* Reset Source: GLOBR */
	#define PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE_HSEC_CTL_RX_PAUSE_ENABLE_S 0			#define PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE_HSEC_CTL_RX_PAUSE_ENABLE_S 0
	#define PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE_HSEC_CTL_RX_PAUSE_ENABLE_M MAKEMASK(0x1FF, 0)			#define PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE_HSEC_CTL_RX_PAUSE_ENABLE_M MAKEMASK(0x1FF, 0)
	#define PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART1 0x001E3280 /* Reset Source: GLOBR */			#define PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART1 0x001E3280 /* Reset Source: GLOBR */
	#define PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART1_HSEC_CTL_RX_PAUSE_SA_PART1_S 0			#define PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART1_HSEC_CTL_RX_PAUSE_SA_PART1_S 0
	#define PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART1_HSEC_CTL_RX_PAUSE_SA_PART1_M MAKEMASK(0xFFFFFFFF, 0)			#define PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART1_HSEC_CTL_RX_PAUSE_SA_PART1_M MAKEMASK(0xFFFFFFFF, 0)
	▲ Show 20 Lines • Show All 84 Lines • ▼ Show 20 Lines
	#define GL_MDCK_EN_TX_PQM_SSO_LENGTH_EXCEED_S 15			#define GL_MDCK_EN_TX_PQM_SSO_LENGTH_EXCEED_S 15
	#define GL_MDCK_EN_TX_PQM_SSO_LENGTH_EXCEED_M BIT(15)			#define GL_MDCK_EN_TX_PQM_SSO_LENGTH_EXCEED_M BIT(15)
	#define GL_MDCK_EN_TX_PQM_SSO_PKTCNT_ZERO_S 16			#define GL_MDCK_EN_TX_PQM_SSO_PKTCNT_ZERO_S 16
	#define GL_MDCK_EN_TX_PQM_SSO_PKTCNT_ZERO_M BIT(16)			#define GL_MDCK_EN_TX_PQM_SSO_PKTCNT_ZERO_M BIT(16)
	#define GL_MDCK_EN_TX_PQM_SSO_PKTCNT_EXCEED_S 17			#define GL_MDCK_EN_TX_PQM_SSO_PKTCNT_EXCEED_S 17
	#define GL_MDCK_EN_TX_PQM_SSO_PKTCNT_EXCEED_M BIT(17)			#define GL_MDCK_EN_TX_PQM_SSO_PKTCNT_EXCEED_M BIT(17)
	#define GL_MDCK_EN_TX_PQM_SSO_NUMDESCS_ZERO_S 18			#define GL_MDCK_EN_TX_PQM_SSO_NUMDESCS_ZERO_S 18
	#define GL_MDCK_EN_TX_PQM_SSO_NUMDESCS_ZERO_M BIT(18)			#define GL_MDCK_EN_TX_PQM_SSO_NUMDESCS_ZERO_M BIT(18)
	#define GL_MDCK_EN_TX_PQM_SSO_NUMDESCS_EXCEED_S 19			#define GL_MDCK_EN_TX_PQM_SSO_NUMDESCS_EXCEED_S 19
	#define GL_MDCK_EN_TX_PQM_SSO_NUMDESCS_EXCEED_M BIT(19)			#define GL_MDCK_EN_TX_PQM_SSO_NUMDESCS_EXCEED_M BIT(19)
	#define GL_MDCK_EN_TX_PQM_TAIL_GT_RING_LENGTH_S 20			#define GL_MDCK_EN_TX_PQM_TAIL_GT_RING_LENGTH_S 20
	#define GL_MDCK_EN_TX_PQM_TAIL_GT_RING_LENGTH_M BIT(20)			#define GL_MDCK_EN_TX_PQM_TAIL_GT_RING_LENGTH_M BIT(20)
	#define GL_MDCK_EN_TX_PQM_RESERVED_DBL_TYPE_S 21			#define GL_MDCK_EN_TX_PQM_RESERVED_DBL_TYPE_S 21
	#define GL_MDCK_EN_TX_PQM_RESERVED_DBL_TYPE_M BIT(21)			#define GL_MDCK_EN_TX_PQM_RESERVED_DBL_TYPE_M BIT(21)
	#define GL_MDCK_EN_TX_PQM_ILLEGAL_HEAD_DROP_DBL_S 22			#define GL_MDCK_EN_TX_PQM_ILLEGAL_HEAD_DROP_DBL_S 22
	#define GL_MDCK_EN_TX_PQM_ILLEGAL_HEAD_DROP_DBL_M BIT(22)			#define GL_MDCK_EN_TX_PQM_ILLEGAL_HEAD_DROP_DBL_M BIT(22)
	#define GL_MDCK_EN_TX_PQM_LSO_OVER_COMMS_Q_S 23			#define GL_MDCK_EN_TX_PQM_LSO_OVER_COMMS_Q_S 23
	#define GL_MDCK_EN_TX_PQM_LSO_OVER_COMMS_Q_M BIT(23)			#define GL_MDCK_EN_TX_PQM_LSO_OVER_COMMS_Q_M BIT(23)
	#define GL_MDCK_EN_TX_PQM_ILLEGAL_VF_QNUM_S 24			#define GL_MDCK_EN_TX_PQM_ILLEGAL_VF_QNUM_S 24
	#define GL_MDCK_EN_TX_PQM_ILLEGAL_VF_QNUM_M BIT(24)			#define GL_MDCK_EN_TX_PQM_ILLEGAL_VF_QNUM_M BIT(24)
	#define GL_MDCK_EN_TX_PQM_QTAIL_GT_RING_LENGTH_S 25			#define GL_MDCK_EN_TX_PQM_QTAIL_GT_RING_LENGTH_S 25
	#define GL_MDCK_EN_TX_PQM_QTAIL_GT_RING_LENGTH_M BIT(25)			#define GL_MDCK_EN_TX_PQM_QTAIL_GT_RING_LENGTH_M BIT(25)
	#define GL_MDCK_EN_TX_PQM_RSVD_S 26			#define GL_MDCK_EN_TX_PQM_RSVD_S 26
	#define GL_MDCK_EN_TX_PQM_RSVD_M MAKEMASK(0x3F, 26)			#define GL_MDCK_EN_TX_PQM_RSVD_M MAKEMASK(0x3F, 26)
	#define GL_MDCK_RX 0x0029422C /* Reset Source: CORER */			#define GL_MDCK_RX 0x0029422C /* Reset Source: CORER */
	#define GL_MDCK_RX_DESC_ADDR_S 0			#define GL_MDCK_RX_DESC_ADDR_S 0
	#define GL_MDCK_RX_DESC_ADDR_M BIT(0)			#define GL_MDCK_RX_DESC_ADDR_M BIT(0)
	#define GL_MDCK_TX_TDPU 0x00049348 /* Reset Source: CORER */			#define GL_MDCK_TX_TDPU 0x00049348 /* Reset Source: CORER */
	#define GL_MDCK_TX_TDPU_TTL_ERR_ITR_DIS_S 0			#define GL_MDCK_TX_TDPU_TTL_ERR_ITR_DIS_S 0
	#define GL_MDCK_TX_TDPU_TTL_ERR_ITR_DIS_M BIT(0)			#define GL_MDCK_TX_TDPU_TTL_ERR_ITR_DIS_M BIT(0)
	#define GL_MDCK_TX_TDPU_RCU_ANTISPOOF_ITR_DIS_S 1			#define GL_MDCK_TX_TDPU_RCU_ANTISPOOF_ITR_DIS_S 1
	#define GL_MDCK_TX_TDPU_RCU_ANTISPOOF_ITR_DIS_M BIT(1)			#define GL_MDCK_TX_TDPU_RCU_ANTISPOOF_ITR_DIS_M BIT(1)
	#define GL_MDCK_TX_TDPU_PCIE_UR_ITR_DIS_S 2			#define GL_MDCK_TX_TDPU_PCIE_UR_ITR_DIS_S 2
	#define GL_MDCK_TX_TDPU_PCIE_UR_ITR_DIS_M BIT(2)			#define GL_MDCK_TX_TDPU_PCIE_UR_ITR_DIS_M BIT(2)
	#define GL_MDCK_TX_TDPU_MAL_OFFSET_ITR_DIS_S 3			#define GL_MDCK_TX_TDPU_MAL_OFFSET_ITR_DIS_S 3
	#define GL_MDCK_TX_TDPU_MAL_OFFSET_ITR_DIS_M BIT(3)			#define GL_MDCK_TX_TDPU_MAL_OFFSET_ITR_DIS_M BIT(3)
	#define GL_MDCK_TX_TDPU_MAL_CMD_ITR_DIS_S 4			#define GL_MDCK_TX_TDPU_MAL_CMD_ITR_DIS_S 4
	#define GL_MDCK_TX_TDPU_MAL_CMD_ITR_DIS_M BIT(4)			#define GL_MDCK_TX_TDPU_MAL_CMD_ITR_DIS_M BIT(4)
	#define GL_MDCK_TX_TDPU_BIG_PKT_SIZE_ITR_DIS_S 5			#define GL_MDCK_TX_TDPU_BIG_PKT_SIZE_ITR_DIS_S 5
	#define GL_MDCK_TX_TDPU_BIG_PKT_SIZE_ITR_DIS_M BIT(5)			#define GL_MDCK_TX_TDPU_BIG_PKT_SIZE_ITR_DIS_M BIT(5)
	#define GL_MDCK_TX_TDPU_L2_ACCEPT_FAIL_ITR_DIS_S 6			#define GL_MDCK_TX_TDPU_L2_ACCEPT_FAIL_ITR_DIS_S 6
	#define GL_MDCK_TX_TDPU_L2_ACCEPT_FAIL_ITR_DIS_M BIT(6)			#define GL_MDCK_TX_TDPU_L2_ACCEPT_FAIL_ITR_DIS_M BIT(6)
	#define GL_MDCK_TX_TDPU_NIC_DSI_ITR_DIS_S 7			#define GL_MDCK_TX_TDPU_NIC_DSI_ITR_DIS_S 7
	#define GL_MDCK_TX_TDPU_NIC_DSI_ITR_DIS_M BIT(7)			#define GL_MDCK_TX_TDPU_NIC_DSI_ITR_DIS_M BIT(7)
	#define GL_MDCK_TX_TDPU_MAL_IPSEC_CMD_ITR_DIS_S 8			#define GL_MDCK_TX_TDPU_MAL_IPSEC_CMD_ITR_DIS_S 8
	#define GL_MDCK_TX_TDPU_MAL_IPSEC_CMD_ITR_DIS_M BIT(8)			#define GL_MDCK_TX_TDPU_MAL_IPSEC_CMD_ITR_DIS_M BIT(8)
	#define GL_MDCK_TX_TDPU_DSCP_CHECK_FAIL_ITR_DIS_S 9			#define GL_MDCK_TX_TDPU_DSCP_CHECK_FAIL_ITR_DIS_S 9
	#define GL_MDCK_TX_TDPU_DSCP_CHECK_FAIL_ITR_DIS_M BIT(9)			#define GL_MDCK_TX_TDPU_DSCP_CHECK_FAIL_ITR_DIS_M BIT(9)
	#define GL_MDCK_TX_TDPU_NIC_IPSEC_ITR_DIS_S 10			#define GL_MDCK_TX_TDPU_NIC_IPSEC_ITR_DIS_S 10
	#define GL_MDCK_TX_TDPU_NIC_IPSEC_ITR_DIS_M BIT(10)			#define GL_MDCK_TX_TDPU_NIC_IPSEC_ITR_DIS_M BIT(10)
	#define GL_MDET_RX 0x00294C00 /* Reset Source: CORER */			#define GL_MDET_RX 0x00294C00 /* Reset Source: CORER */
	#define GL_MDET_RX_QNUM_S 0			#define GL_MDET_RX_QNUM_S 0
	#define GL_MDET_RX_QNUM_M MAKEMASK(0x7FFF, 0)			#define GL_MDET_RX_QNUM_M MAKEMASK(0x7FFF, 0)
	#define GL_MDET_RX_VF_NUM_S 15			#define GL_MDET_RX_VF_NUM_S 15
	▲ Show 20 Lines • Show All 65 Lines • ▼ Show 20 Lines
	#define VP_MDET_TX_TCLAN_VALID_S 0			#define VP_MDET_TX_TCLAN_VALID_S 0
	#define VP_MDET_TX_TCLAN_VALID_M BIT(0)			#define VP_MDET_TX_TCLAN_VALID_M BIT(0)
	#define VP_MDET_TX_TDPU(_VF) (0x00040000 + ((_VF) * 4)) /* _i=0...255 / / Reset Source: CORER */			#define VP_MDET_TX_TDPU(_VF) (0x00040000 + ((_VF) * 4)) /* _i=0...255 / / Reset Source: CORER */
	#define VP_MDET_TX_TDPU_MAX_INDEX 255			#define VP_MDET_TX_TDPU_MAX_INDEX 255
	#define VP_MDET_TX_TDPU_VALID_S 0			#define VP_MDET_TX_TDPU_VALID_S 0
	#define VP_MDET_TX_TDPU_VALID_M BIT(0)			#define VP_MDET_TX_TDPU_VALID_M BIT(0)
	#define GENERAL_MNG_FW_DBG_CSR(_i) (0x000B6180 + ((_i) * 4)) /* _i=0...9 / / Reset Source: POR */			#define GENERAL_MNG_FW_DBG_CSR(_i) (0x000B6180 + ((_i) * 4)) /* _i=0...9 / / Reset Source: POR */
	#define GENERAL_MNG_FW_DBG_CSR_MAX_INDEX 9			#define GENERAL_MNG_FW_DBG_CSR_MAX_INDEX 9
	#define GENERAL_MNG_FW_DBG_CSR_GENERAL_FW_DBG_S 0			#define GENERAL_MNG_FW_DBG_CSR_GENERAL_FW_DBG_S 0
	#define GENERAL_MNG_FW_DBG_CSR_GENERAL_FW_DBG_M MAKEMASK(0xFFFFFFFF, 0)			#define GENERAL_MNG_FW_DBG_CSR_GENERAL_FW_DBG_M MAKEMASK(0xFFFFFFFF, 0)
	#define GL_FWRESETCNT 0x00083100 /* Reset Source: POR */			#define GL_FWRESETCNT 0x00083100 /* Reset Source: POR */
	#define GL_FWRESETCNT_FWRESETCNT_S 0			#define GL_FWRESETCNT_FWRESETCNT_S 0
	#define GL_FWRESETCNT_FWRESETCNT_M MAKEMASK(0xFFFFFFFF, 0)			#define GL_FWRESETCNT_FWRESETCNT_M MAKEMASK(0xFFFFFFFF, 0)
	#define GL_MNG_FW_RAM_STAT 0x0008309C /* Reset Source: POR */			#define GL_MNG_FW_RAM_STAT 0x0008309C /* Reset Source: POR */
	#define GL_MNG_FW_RAM_STAT_FW_RAM_RST_STAT_S 0			#define GL_MNG_FW_RAM_STAT_FW_RAM_RST_STAT_S 0
	#define GL_MNG_FW_RAM_STAT_FW_RAM_RST_STAT_M BIT(0)			#define GL_MNG_FW_RAM_STAT_FW_RAM_RST_STAT_M BIT(0)
	#define GL_MNG_FW_RAM_STAT_MNG_MEM_ECC_ERR_S 1			#define GL_MNG_FW_RAM_STAT_MNG_MEM_ECC_ERR_S 1
	#define GL_MNG_FW_RAM_STAT_MNG_MEM_ECC_ERR_M BIT(1)			#define GL_MNG_FW_RAM_STAT_MNG_MEM_ECC_ERR_M BIT(1)
	▲ Show 20 Lines • Show All 395 Lines • ▼ Show 20 Lines
	#define GL_XLR_MARKER_TRIG_PE_VM_VF_TYPE_M MAKEMASK(0x3, 10)			#define GL_XLR_MARKER_TRIG_PE_VM_VF_TYPE_M MAKEMASK(0x3, 10)
	#define GL_XLR_MARKER_TRIG_PE_PF_NUM_S 12			#define GL_XLR_MARKER_TRIG_PE_PF_NUM_S 12
	#define GL_XLR_MARKER_TRIG_PE_PF_NUM_M MAKEMASK(0x7, 12)			#define GL_XLR_MARKER_TRIG_PE_PF_NUM_M MAKEMASK(0x7, 12)
	#define GL_XLR_MARKER_TRIG_PE_PORT_NUM_S 16			#define GL_XLR_MARKER_TRIG_PE_PORT_NUM_S 16
	#define GL_XLR_MARKER_TRIG_PE_PORT_NUM_M MAKEMASK(0x7, 16)			#define GL_XLR_MARKER_TRIG_PE_PORT_NUM_M MAKEMASK(0x7, 16)
	#define GL_XLR_MARKER_TRIG_RCU_PRS 0x002001C0 /* Reset Source: CORER */			#define GL_XLR_MARKER_TRIG_RCU_PRS 0x002001C0 /* Reset Source: CORER */
	#define GL_XLR_MARKER_TRIG_RCU_PRS_VM_VF_NUM_S 0			#define GL_XLR_MARKER_TRIG_RCU_PRS_VM_VF_NUM_S 0
	#define GL_XLR_MARKER_TRIG_RCU_PRS_VM_VF_NUM_M MAKEMASK(0x3FF, 0)			#define GL_XLR_MARKER_TRIG_RCU_PRS_VM_VF_NUM_M MAKEMASK(0x3FF, 0)
	#define GL_XLR_MARKER_TRIG_RCU_PRS_VM_VF_TYPE_S 10			#define GL_XLR_MARKER_TRIG_RCU_PRS_VM_VF_TYPE_S 10
	#define GL_XLR_MARKER_TRIG_RCU_PRS_VM_VF_TYPE_M MAKEMASK(0x3, 10)			#define GL_XLR_MARKER_TRIG_RCU_PRS_VM_VF_TYPE_M MAKEMASK(0x3, 10)
	#define GL_XLR_MARKER_TRIG_RCU_PRS_PF_NUM_S 12			#define GL_XLR_MARKER_TRIG_RCU_PRS_PF_NUM_S 12
	#define GL_XLR_MARKER_TRIG_RCU_PRS_PF_NUM_M MAKEMASK(0x7, 12)			#define GL_XLR_MARKER_TRIG_RCU_PRS_PF_NUM_M MAKEMASK(0x7, 12)
	#define GL_XLR_MARKER_TRIG_RCU_PRS_PORT_NUM_S 16			#define GL_XLR_MARKER_TRIG_RCU_PRS_PORT_NUM_S 16
	#define GL_XLR_MARKER_TRIG_RCU_PRS_PORT_NUM_M MAKEMASK(0x7, 16)			#define GL_XLR_MARKER_TRIG_RCU_PRS_PORT_NUM_M MAKEMASK(0x7, 16)
	#define GL_CLKGATE_EVENTS 0x0009DE70 /* Reset Source: PERST */			#define GL_CLKGATE_EVENTS 0x0009DE70 /* Reset Source: PERST */
	#define GL_CLKGATE_EVENTS_PRIMARY_CLKGATE_EVENTS_S 0			#define GL_CLKGATE_EVENTS_PRIMARY_CLKGATE_EVENTS_S 0
	#define GL_CLKGATE_EVENTS_PRIMARY_CLKGATE_EVENTS_M MAKEMASK(0xFFFF, 0)			#define GL_CLKGATE_EVENTS_PRIMARY_CLKGATE_EVENTS_M MAKEMASK(0xFFFF, 0)
	#define GL_CLKGATE_EVENTS_SIDEBAND_CLKGATE_EVENTS_S 16			#define GL_CLKGATE_EVENTS_SIDEBAND_CLKGATE_EVENTS_S 16
	▲ Show 20 Lines • Show All 862 Lines • ▼ Show 20 Lines
	#define GLPES_RDMARXOOODDPLO_RDMARXOOODDPLO_M MAKEMASK(0xFFFFFFFF, 0)			#define GLPES_RDMARXOOODDPLO_RDMARXOOODDPLO_M MAKEMASK(0xFFFFFFFF, 0)
	#define GLPES_RDMARXOOONOMARK 0x0055E004 /* Reset Source: CORER */			#define GLPES_RDMARXOOONOMARK 0x0055E004 /* Reset Source: CORER */
	#define GLPES_RDMARXOOONOMARK_RDMAOOONOMARK_S 0			#define GLPES_RDMARXOOONOMARK_RDMAOOONOMARK_S 0
	#define GLPES_RDMARXOOONOMARK_RDMAOOONOMARK_M MAKEMASK(0xFFFFFFFF, 0)			#define GLPES_RDMARXOOONOMARK_RDMAOOONOMARK_M MAKEMASK(0xFFFFFFFF, 0)
	#define GLPES_RDMARXUNALIGN 0x0055E000 /* Reset Source: CORER */			#define GLPES_RDMARXUNALIGN 0x0055E000 /* Reset Source: CORER */
	#define GLPES_RDMARXUNALIGN_RDMRXAUNALIGN_S 0			#define GLPES_RDMARXUNALIGN_RDMRXAUNALIGN_S 0
	#define GLPES_RDMARXUNALIGN_RDMRXAUNALIGN_M MAKEMASK(0xFFFFFFFF, 0)			#define GLPES_RDMARXUNALIGN_RDMRXAUNALIGN_M MAKEMASK(0xFFFFFFFF, 0)
	#define GLPES_TCPRXFOURHOLEHI 0x0055E03C /* Reset Source: CORER */			#define GLPES_TCPRXFOURHOLEHI 0x0055E03C /* Reset Source: CORER */
	#define GLPES_TCPRXFOURHOLEHI_TCPRXFOURHOLEHI_S 0			#define GLPES_TCPRXFOURHOLEHI_TCPRXFOURHOLEHI_S 0
	#define GLPES_TCPRXFOURHOLEHI_TCPRXFOURHOLEHI_M MAKEMASK(0xFFFFFF, 0)			#define GLPES_TCPRXFOURHOLEHI_TCPRXFOURHOLEHI_M MAKEMASK(0xFFFFFF, 0)
	#define GLPES_TCPRXFOURHOLELO 0x0055E038 /* Reset Source: CORER */			#define GLPES_TCPRXFOURHOLELO 0x0055E038 /* Reset Source: CORER */
	#define GLPES_TCPRXFOURHOLELO_TCPRXFOURHOLELO_S 0			#define GLPES_TCPRXFOURHOLELO_TCPRXFOURHOLELO_S 0
	#define GLPES_TCPRXFOURHOLELO_TCPRXFOURHOLELO_M MAKEMASK(0xFFFFFFFF, 0)			#define GLPES_TCPRXFOURHOLELO_TCPRXFOURHOLELO_M MAKEMASK(0xFFFFFFFF, 0)
	#define GLPES_TCPRXONEHOLEHI 0x0055E024 /* Reset Source: CORER */			#define GLPES_TCPRXONEHOLEHI 0x0055E024 /* Reset Source: CORER */
	#define GLPES_TCPRXONEHOLEHI_TCPRXONEHOLEHI_S 0			#define GLPES_TCPRXONEHOLEHI_TCPRXONEHOLEHI_S 0
	#define GLPES_TCPRXONEHOLEHI_TCPRXONEHOLEHI_M MAKEMASK(0xFFFFFF, 0)			#define GLPES_TCPRXONEHOLEHI_TCPRXONEHOLEHI_M MAKEMASK(0xFFFFFF, 0)
	#define GLPES_TCPRXONEHOLELO 0x0055E020 /* Reset Source: CORER */			#define GLPES_TCPRXONEHOLELO 0x0055E020 /* Reset Source: CORER */
	#define GLPES_TCPRXONEHOLELO_TCPRXONEHOLELO_S 0			#define GLPES_TCPRXONEHOLELO_TCPRXONEHOLELO_S 0
	#define GLPES_TCPRXONEHOLELO_TCPRXONEHOLELO_M MAKEMASK(0xFFFFFFFF, 0)			#define GLPES_TCPRXONEHOLELO_TCPRXONEHOLELO_M MAKEMASK(0xFFFFFFFF, 0)
	#define GLPES_TCPRXPUREACKHI 0x0055E01C /* Reset Source: CORER */			#define GLPES_TCPRXPUREACKHI 0x0055E01C /* Reset Source: CORER */
	#define GLPES_TCPRXPUREACKHI_TCPRXPUREACKSHI_S 0			#define GLPES_TCPRXPUREACKHI_TCPRXPUREACKSHI_S 0
	▲ Show 20 Lines • Show All 1,464 Lines • ▼ Show 20 Lines
	#define PRTTPB_STAT_TC_BYTES_SENTL_MAX_INDEX 63			#define PRTTPB_STAT_TC_BYTES_SENTL_MAX_INDEX 63
	#define PRTTPB_STAT_TC_BYTES_SENTL_TCCNT_S 0			#define PRTTPB_STAT_TC_BYTES_SENTL_TCCNT_S 0
	#define PRTTPB_STAT_TC_BYTES_SENTL_TCCNT_M MAKEMASK(0xFFFFFFFF, 0)			#define PRTTPB_STAT_TC_BYTES_SENTL_TCCNT_M MAKEMASK(0xFFFFFFFF, 0)
	#define TPB_PRTTPB_STAT_PKT_SENT(_i) (0x00099470 + ((_i) * 4)) /* _i=0...7 / / Reset Source: CORER */			#define TPB_PRTTPB_STAT_PKT_SENT(_i) (0x00099470 + ((_i) * 4)) /* _i=0...7 / / Reset Source: CORER */
	#define TPB_PRTTPB_STAT_PKT_SENT_MAX_INDEX 7			#define TPB_PRTTPB_STAT_PKT_SENT_MAX_INDEX 7
	#define TPB_PRTTPB_STAT_PKT_SENT_PKTCNT_S 0			#define TPB_PRTTPB_STAT_PKT_SENT_PKTCNT_S 0
	#define TPB_PRTTPB_STAT_PKT_SENT_PKTCNT_M MAKEMASK(0xFFFFFFFF, 0)			#define TPB_PRTTPB_STAT_PKT_SENT_PKTCNT_M MAKEMASK(0xFFFFFFFF, 0)
	#define TPB_PRTTPB_STAT_TC_BYTES_SENT(_i) (0x00099094 + ((_i) * 4)) /* _i=0...63 / / Reset Source: CORER */			#define TPB_PRTTPB_STAT_TC_BYTES_SENT(_i) (0x00099094 + ((_i) * 4)) /* _i=0...63 / / Reset Source: CORER */
	#define TPB_PRTTPB_STAT_TC_BYTES_SENT_MAX_INDEX 63			#define TPB_PRTTPB_STAT_TC_BYTES_SENT_MAX_INDEX 63
	#define TPB_PRTTPB_STAT_TC_BYTES_SENT_TCCNT_S 0			#define TPB_PRTTPB_STAT_TC_BYTES_SENT_TCCNT_S 0
	#define TPB_PRTTPB_STAT_TC_BYTES_SENT_TCCNT_M MAKEMASK(0xFFFFFFFF, 0)			#define TPB_PRTTPB_STAT_TC_BYTES_SENT_TCCNT_M MAKEMASK(0xFFFFFFFF, 0)
	#define EMP_SWT_PRUNIND 0x00204020 /* Reset Source: CORER */			#define EMP_SWT_PRUNIND 0x00204020 /* Reset Source: CORER */
	#define EMP_SWT_PRUNIND_OPCODE_S 0			#define EMP_SWT_PRUNIND_OPCODE_S 0
	#define EMP_SWT_PRUNIND_OPCODE_M MAKEMASK(0xF, 0)			#define EMP_SWT_PRUNIND_OPCODE_M MAKEMASK(0xF, 0)
	#define EMP_SWT_PRUNIND_LIST_INDEX_NUM_S 4			#define EMP_SWT_PRUNIND_LIST_INDEX_NUM_S 4
	#define EMP_SWT_PRUNIND_LIST_INDEX_NUM_M MAKEMASK(0x3FF, 4)			#define EMP_SWT_PRUNIND_LIST_INDEX_NUM_M MAKEMASK(0x3FF, 4)
	#define EMP_SWT_PRUNIND_VSI_NUM_S 16			#define EMP_SWT_PRUNIND_VSI_NUM_S 16
	▲ Show 20 Lines • Show All 1,225 Lines • ▼ Show 20 Lines
	#define VFPE_TCPNOWTIMER1 0x0000A800 /* Reset Source: VFR */			#define VFPE_TCPNOWTIMER1 0x0000A800 /* Reset Source: VFR */
	#define VFPE_TCPNOWTIMER1_TCP_NOW_S 0			#define VFPE_TCPNOWTIMER1_TCP_NOW_S 0
	#define VFPE_TCPNOWTIMER1_TCP_NOW_M MAKEMASK(0xFFFFFFFF, 0)			#define VFPE_TCPNOWTIMER1_TCP_NOW_M MAKEMASK(0xFFFFFFFF, 0)
	#define VFPE_WQEALLOC1 0x0000C000 /* Reset Source: VFR */			#define VFPE_WQEALLOC1 0x0000C000 /* Reset Source: VFR */
	#define VFPE_WQEALLOC1_PEQPID_S 0			#define VFPE_WQEALLOC1_PEQPID_S 0
	#define VFPE_WQEALLOC1_PEQPID_M MAKEMASK(0x3FFFF, 0)			#define VFPE_WQEALLOC1_PEQPID_M MAKEMASK(0x3FFFF, 0)
	#define VFPE_WQEALLOC1_WQE_DESC_INDEX_S 20			#define VFPE_WQEALLOC1_WQE_DESC_INDEX_S 20
	#define VFPE_WQEALLOC1_WQE_DESC_INDEX_M MAKEMASK(0xFFF, 20)			#define VFPE_WQEALLOC1_WQE_DESC_INDEX_M MAKEMASK(0xFFF, 20)
				#endif /* !_ICE_HW_AUTOGEN_H_ */

	#endif