Differential D34024 Diff 104209 sys/dev/ice/ice_adminq_cmd.h

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sys/dev/ice/ice_adminq_cmd.h

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#define ICE_AQC_CAPS_SDP 0x0062		#define ICE_AQC_CAPS_SDP 0x0062
#define ICE_AQC_CAPS_WR_CSR_PROT 0x0064		#define ICE_AQC_CAPS_WR_CSR_PROT 0x0064
#define ICE_AQC_CAPS_LOGI_TO_PHYSI_PORT_MAP 0x0073		#define ICE_AQC_CAPS_LOGI_TO_PHYSI_PORT_MAP 0x0073
#define ICE_AQC_CAPS_SKU 0x0074		#define ICE_AQC_CAPS_SKU 0x0074
#define ICE_AQC_CAPS_PORT_MAP 0x0075		#define ICE_AQC_CAPS_PORT_MAP 0x0075
#define ICE_AQC_CAPS_PCIE_RESET_AVOIDANCE 0x0076		#define ICE_AQC_CAPS_PCIE_RESET_AVOIDANCE 0x0076
#define ICE_AQC_CAPS_POST_UPDATE_RESET_RESTRICT 0x0077		#define ICE_AQC_CAPS_POST_UPDATE_RESET_RESTRICT 0x0077
#define ICE_AQC_CAPS_NVM_MGMT 0x0080		#define ICE_AQC_CAPS_NVM_MGMT 0x0080
		#define ICE_AQC_CAPS_EXT_TOPO_DEV_IMG0 0x0081
		#define ICE_AQC_CAPS_EXT_TOPO_DEV_IMG1 0x0082
		#define ICE_AQC_CAPS_EXT_TOPO_DEV_IMG2 0x0083
		#define ICE_AQC_CAPS_EXT_TOPO_DEV_IMG3 0x0084

u8 major_ver;		u8 major_ver;
u8 minor_ver;		u8 minor_ver;
/* Number of resources described by this capability */		/* Number of resources described by this capability */
__le32 number;		__le32 number;
/* Only meaningful for some types of resources */		/* Only meaningful for some types of resources */
__le32 logical_id;		__le32 logical_id;
/* Only meaningful for some types of resources */		/* Only meaningful for some types of resources */
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/* Get PHY capabilities (indirect 0x0600) */		/* Get PHY capabilities (indirect 0x0600) */
struct ice_aqc_get_phy_caps {		struct ice_aqc_get_phy_caps {
u8 lport_num;		u8 lport_num;
u8 reserved;		u8 reserved;
__le16 param0;		__le16 param0;
/* 18.0 - Report qualified modules */		/* 18.0 - Report qualified modules */
#define ICE_AQC_GET_PHY_RQM BIT(0)		#define ICE_AQC_GET_PHY_RQM BIT(0)
/* 18.1 - 18.3 : Report mode		/* 18.1 - 18.3 : Report mode
* 000b - Report NVM capabilities		* 000b - Report topology capabilities, without media
* 001b - Report topology capabilities		* 001b - Report topology capabilities, with media
* 010b - Report SW configured		* 010b - Report Active configuration
* 100b - Report default capabilities		* 011b - Report PHY Type and FEC mode capabilities
		* 100b - Report Default capabilities
*/		*/
#define ICE_AQC_REPORT_MODE_S 1		#define ICE_AQC_REPORT_MODE_S 1
#define ICE_AQC_REPORT_MODE_M (7 << ICE_AQC_REPORT_MODE_S)		#define ICE_AQC_REPORT_MODE_M (7 << ICE_AQC_REPORT_MODE_S)
#define ICE_AQC_REPORT_TOPO_CAP_NO_MEDIA 0		#define ICE_AQC_REPORT_TOPO_CAP_NO_MEDIA 0
#define ICE_AQC_REPORT_TOPO_CAP_MEDIA BIT(1)		#define ICE_AQC_REPORT_TOPO_CAP_MEDIA BIT(1)
#define ICE_AQC_REPORT_ACTIVE_CFG BIT(2)		#define ICE_AQC_REPORT_ACTIVE_CFG BIT(2)
#define ICE_AQC_REPORT_DFLT_CFG BIT(3)		#define ICE_AQC_REPORT_DFLT_CFG BIT(3)
__le32 reserved1;		__le32 reserved1;
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#define ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM BIT(4)		#define ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM BIT(4)
#define ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS BIT(5)		#define ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS BIT(5)
#define ICE_AQ_LINK_EVENT_SIGNAL_DETECT BIT(6)		#define ICE_AQ_LINK_EVENT_SIGNAL_DETECT BIT(6)
#define ICE_AQ_LINK_EVENT_AN_COMPLETED BIT(7)		#define ICE_AQ_LINK_EVENT_AN_COMPLETED BIT(7)
#define ICE_AQ_LINK_EVENT_MODULE_QUAL_FAIL BIT(8)		#define ICE_AQ_LINK_EVENT_MODULE_QUAL_FAIL BIT(8)
#define ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED BIT(9)		#define ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED BIT(9)
#define ICE_AQ_LINK_EVENT_TOPO_CONFLICT BIT(10)		#define ICE_AQ_LINK_EVENT_TOPO_CONFLICT BIT(10)
#define ICE_AQ_LINK_EVENT_MEDIA_CONFLICT BIT(11)		#define ICE_AQ_LINK_EVENT_MEDIA_CONFLICT BIT(11)
		#define ICE_AQ_LINK_EVENT_PHY_FW_LOAD_FAIL BIT(12)
u8 reserved1[6];		u8 reserved1[6];
};		};

/* Set PHY Loopback command (direct 0x0619) */		/* Set PHY Loopback command (direct 0x0619) */
struct ice_aqc_set_phy_lb {		struct ice_aqc_set_phy_lb {
u8 lport_num;		u8 lport_num;
u8 lport_num_valid;		u8 lport_num_valid;
#define ICE_AQ_PHY_LB_PORT_NUM_VALID BIT(0)		#define ICE_AQ_PHY_LB_PORT_NUM_VALID BIT(0)
▲ Show 20 Lines • Show All 172 Lines • ▼ Show 20 Lines	struct ice_aqc_dnl_read_log_response {
__le16 reserved;		__le16 reserved;
__le16 size;		__le16 size;
__le32 data;		__le32 data;
__le32 addr_high;		__le32 addr_high;
__le32 addr_low;		__le32 addr_low;

};		};

struct ice_aqc_link_topo_addr {		struct ice_aqc_link_topo_params {
u8 lport_num;		u8 lport_num;
u8 lport_num_valid;		u8 lport_num_valid;
#define ICE_AQC_LINK_TOPO_PORT_NUM_VALID BIT(0)		#define ICE_AQC_LINK_TOPO_PORT_NUM_VALID BIT(0)
u8 node_type_ctx;		u8 node_type_ctx;
#define ICE_AQC_LINK_TOPO_NODE_TYPE_S 0		#define ICE_AQC_LINK_TOPO_NODE_TYPE_S 0
#define ICE_AQC_LINK_TOPO_NODE_TYPE_M (0xF << ICE_AQC_LINK_TOPO_NODE_TYPE_S)		#define ICE_AQC_LINK_TOPO_NODE_TYPE_M (0xF << ICE_AQC_LINK_TOPO_NODE_TYPE_S)
#define ICE_AQC_LINK_TOPO_NODE_TYPE_PHY 0		#define ICE_AQC_LINK_TOPO_NODE_TYPE_PHY 0
#define ICE_AQC_LINK_TOPO_NODE_TYPE_GPIO_CTRL 1		#define ICE_AQC_LINK_TOPO_NODE_TYPE_GPIO_CTRL 1
Show All 9 Lines	#define ICE_AQC_LINK_TOPO_NODE_CTX_M \
(0xF << ICE_AQC_LINK_TOPO_NODE_CTX_S)		(0xF << ICE_AQC_LINK_TOPO_NODE_CTX_S)
#define ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL 0		#define ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL 0
#define ICE_AQC_LINK_TOPO_NODE_CTX_BOARD 1		#define ICE_AQC_LINK_TOPO_NODE_CTX_BOARD 1
#define ICE_AQC_LINK_TOPO_NODE_CTX_PORT 2		#define ICE_AQC_LINK_TOPO_NODE_CTX_PORT 2
#define ICE_AQC_LINK_TOPO_NODE_CTX_NODE 3		#define ICE_AQC_LINK_TOPO_NODE_CTX_NODE 3
#define ICE_AQC_LINK_TOPO_NODE_CTX_PROVIDED 4		#define ICE_AQC_LINK_TOPO_NODE_CTX_PROVIDED 4
#define ICE_AQC_LINK_TOPO_NODE_CTX_OVERRIDE 5		#define ICE_AQC_LINK_TOPO_NODE_CTX_OVERRIDE 5
u8 index;		u8 index;
		};

		struct ice_aqc_link_topo_addr {
		struct ice_aqc_link_topo_params topo_params;
__le16 handle;		__le16 handle;
#define ICE_AQC_LINK_TOPO_HANDLE_S 0		#define ICE_AQC_LINK_TOPO_HANDLE_S 0
#define ICE_AQC_LINK_TOPO_HANDLE_M (0x3FF << ICE_AQC_LINK_TOPO_HANDLE_S)		#define ICE_AQC_LINK_TOPO_HANDLE_M (0x3FF << ICE_AQC_LINK_TOPO_HANDLE_S)
/* Used to decode the handle field */		/* Used to decode the handle field */
#define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_M BIT(9)		#define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_M BIT(9)
#define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_LOM BIT(9)		#define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_LOM BIT(9)
#define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_MEZZ 0		#define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_MEZZ 0
#define ICE_AQC_LINK_TOPO_HANDLE_NODE_S 0		#define ICE_AQC_LINK_TOPO_HANDLE_NODE_S 0
/* In case of a Mezzanine type */		/* In case of a Mezzanine type */
#define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_NODE_M \		#define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_NODE_M \
(0x3F << ICE_AQC_LINK_TOPO_HANDLE_NODE_S)		(0x3F << ICE_AQC_LINK_TOPO_HANDLE_NODE_S)
#define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_S 6		#define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_S 6
#define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_M (0x7 << ICE_AQC_LINK_TOPO_HANDLE_MEZZ_S)		#define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_M (0x7 << ICE_AQC_LINK_TOPO_HANDLE_MEZZ_S)
/* In case of a LOM type */		/* In case of a LOM type */
#define ICE_AQC_LINK_TOPO_HANDLE_LOM_NODE_M \		#define ICE_AQC_LINK_TOPO_HANDLE_LOM_NODE_M \
(0x1FF << ICE_AQC_LINK_TOPO_HANDLE_NODE_S)		(0x1FF << ICE_AQC_LINK_TOPO_HANDLE_NODE_S)
};		};

/* Get Link Topology Handle (direct, 0x06E0) */		/* Get Link Topology Handle (direct, 0x06E0) */
struct ice_aqc_get_link_topo {		struct ice_aqc_get_link_topo {
struct ice_aqc_link_topo_addr addr;		struct ice_aqc_link_topo_addr addr;
u8 node_part_num;		u8 node_part_num;
		#define ICE_ACQ_GET_LINK_TOPO_NODE_NR_PCA9575 0x21
u8 rsvd[9];		u8 rsvd[9];
};		};

/* Get Link Topology Pin (direct, 0x06E1) */
struct ice_aqc_get_link_topo_pin {
struct ice_aqc_link_topo_addr addr;
u8 input_io_params;
#define ICE_AQC_LINK_TOPO_INPUT_IO_FUNC_S 0
#define ICE_AQC_LINK_TOPO_INPUT_IO_FUNC_M \
(0x1F << ICE_AQC_LINK_TOPO_INPUT_IO_FUNC_S)
#define ICE_AQC_LINK_TOPO_IO_FUNC_GPIO 0
#define ICE_AQC_LINK_TOPO_IO_FUNC_RESET_N 1
#define ICE_AQC_LINK_TOPO_IO_FUNC_INT_N 2
#define ICE_AQC_LINK_TOPO_IO_FUNC_PRESENT_N 3
#define ICE_AQC_LINK_TOPO_IO_FUNC_TX_DIS 4
#define ICE_AQC_LINK_TOPO_IO_FUNC_MODSEL_N 5
#define ICE_AQC_LINK_TOPO_IO_FUNC_LPMODE 6
#define ICE_AQC_LINK_TOPO_IO_FUNC_TX_FAULT 7
#define ICE_AQC_LINK_TOPO_IO_FUNC_RX_LOSS 8
#define ICE_AQC_LINK_TOPO_IO_FUNC_RS0 9
#define ICE_AQC_LINK_TOPO_IO_FUNC_RS1 10
#define ICE_AQC_LINK_TOPO_IO_FUNC_EEPROM_WP 11
/* 12 repeats intentionally due to two different uses depending on context */
#define ICE_AQC_LINK_TOPO_IO_FUNC_LED 12
#define ICE_AQC_LINK_TOPO_IO_FUNC_RED_LED 12
#define ICE_AQC_LINK_TOPO_IO_FUNC_GREEN_LED 13
#define ICE_AQC_LINK_TOPO_IO_FUNC_BLUE_LED 14
#define ICE_AQC_LINK_TOPO_INPUT_IO_TYPE_S 5
#define ICE_AQC_LINK_TOPO_INPUT_IO_TYPE_M \
(0x7 << ICE_AQC_LINK_TOPO_INPUT_IO_TYPE_S)
/* Use ICE_AQC_LINK_TOPO_NODE_TYPE_* for the type values */
u8 output_io_params;
#define ICE_AQC_LINK_TOPO_OUTPUT_IO_FUNC_S 0
#define ICE_AQC_LINK_TOPO_OUTPUT_IO_FUNC_M \
(0x1F << \ ICE_AQC_LINK_TOPO_INPUT_IO_FUNC_NUM_S)
/* Use ICE_AQC_LINK_TOPO_IO_FUNC_* for the non-numerical options */
#define ICE_AQC_LINK_TOPO_OUTPUT_IO_TYPE_S 5
#define ICE_AQC_LINK_TOPO_OUTPUT_IO_TYPE_M \
(0x7 << ICE_AQC_LINK_TOPO_INPUT_IO_TYPE_S)
/* Use ICE_AQC_LINK_TOPO_NODE_TYPE_* for the type values */
u8 output_io_flags;
#define ICE_AQC_LINK_TOPO_OUTPUT_SPEED_S 0
#define ICE_AQC_LINK_TOPO_OUTPUT_SPEED_M \
(0x7 << ICE_AQC_LINK_TOPO_OUTPUT_SPEED_S)
#define ICE_AQC_LINK_TOPO_OUTPUT_INT_S 3
#define ICE_AQC_LINK_TOPO_OUTPUT_INT_M \
(0x3 << ICE_AQC_LINK_TOPO_OUTPUT_INT_S)
#define ICE_AQC_LINK_TOPO_OUTPUT_POLARITY BIT(5)
#define ICE_AQC_LINK_TOPO_OUTPUT_VALUE BIT(6)
#define ICE_AQC_LINK_TOPO_OUTPUT_DRIVEN BIT(7)
u8 rsvd[7];
};

/* Read/Write I2C (direct, 0x06E2/0x06E3) */		/* Read/Write I2C (direct, 0x06E2/0x06E3) */
struct ice_aqc_i2c {		struct ice_aqc_i2c {
struct ice_aqc_link_topo_addr topo_addr;		struct ice_aqc_link_topo_addr topo_addr;
__le16 i2c_addr;		__le16 i2c_addr;
u8 i2c_params;		u8 i2c_params;
#define ICE_AQC_I2C_DATA_SIZE_S 0		#define ICE_AQC_I2C_DATA_SIZE_S 0
#define ICE_AQC_I2C_DATA_SIZE_M (0xF << ICE_AQC_I2C_DATA_SIZE_S)		#define ICE_AQC_I2C_DATA_SIZE_M (0xF << ICE_AQC_I2C_DATA_SIZE_S)
#define ICE_AQC_I2C_ADDR_TYPE_M BIT(4)		#define ICE_AQC_I2C_ADDR_TYPE_M BIT(4)
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#define ICE_AQC_SW_GPIO_NUMBER_S 0		#define ICE_AQC_SW_GPIO_NUMBER_S 0
#define ICE_AQC_SW_GPIO_NUMBER_M (0x1F << ICE_AQC_SW_GPIO_NUMBER_S)		#define ICE_AQC_SW_GPIO_NUMBER_M (0x1F << ICE_AQC_SW_GPIO_NUMBER_S)
u8 gpio_params;		u8 gpio_params;
#define ICE_AQC_SW_GPIO_PARAMS_DIRECTION BIT(1)		#define ICE_AQC_SW_GPIO_PARAMS_DIRECTION BIT(1)
#define ICE_AQC_SW_GPIO_PARAMS_VALUE BIT(0)		#define ICE_AQC_SW_GPIO_PARAMS_VALUE BIT(0)
u8 rsvd[12];		u8 rsvd[12];
};		};

/* Program topology device NVM (direct, 0x06F2) */		/* Program Topology Device NVM (direct, 0x06F2) */
struct ice_aqc_program_topology_device_nvm {		struct ice_aqc_prog_topo_dev_nvm {
u8 lport_num;		struct ice_aqc_link_topo_params topo_params;
u8 lport_num_valid;
u8 node_type_ctx;
u8 index;
u8 rsvd[12];		u8 rsvd[12];
};		};

/* Read topology device NVM (indirect, 0x06F3) */		/* Read Topology Device NVM (direct, 0x06F3) */
struct ice_aqc_read_topology_device_nvm {		struct ice_aqc_read_topo_dev_nvm {
u8 lport_num;		struct ice_aqc_link_topo_params topo_params;
u8 lport_num_valid;
u8 node_type_ctx;
u8 index;
__le32 start_address;		__le32 start_address;
u8 data_read[8];		#define ICE_AQC_READ_TOPO_DEV_NVM_DATA_READ_SIZE 8
		u8 data_read[ICE_AQC_READ_TOPO_DEV_NVM_DATA_READ_SIZE];
};		};

/* NVM Read command (indirect 0x0701)		/* NVM Read command (indirect 0x0701)
* NVM Erase commands (direct 0x0702)		* NVM Erase commands (direct 0x0702)
* NVM Write commands (indirect 0x0703)		* NVM Write commands (indirect 0x0703)
* NVM Write Activate commands (direct 0x0707)		* NVM Write Activate commands (direct 0x0707)
* NVM Shadow RAM Dump commands (direct 0x0707)		* NVM Shadow RAM Dump commands (direct 0x0707)
*/		*/
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#define ICE_AQC_NVM_PRESERVE_SELECTED (3 << ICE_AQC_NVM_PRESERVATION_S)		#define ICE_AQC_NVM_PRESERVE_SELECTED (3 << ICE_AQC_NVM_PRESERVATION_S)
#define ICE_AQC_NVM_ACTIV_SEL_NVM BIT(3) /* Write Activate/SR Dump only */		#define ICE_AQC_NVM_ACTIV_SEL_NVM BIT(3) /* Write Activate/SR Dump only */
#define ICE_AQC_NVM_ACTIV_SEL_OROM BIT(4)		#define ICE_AQC_NVM_ACTIV_SEL_OROM BIT(4)
#define ICE_AQC_NVM_ACTIV_SEL_NETLIST BIT(5)		#define ICE_AQC_NVM_ACTIV_SEL_NETLIST BIT(5)
#define ICE_AQC_NVM_SPECIAL_UPDATE BIT(6)		#define ICE_AQC_NVM_SPECIAL_UPDATE BIT(6)
#define ICE_AQC_NVM_REVERT_LAST_ACTIV BIT(6) /* Write Activate only */		#define ICE_AQC_NVM_REVERT_LAST_ACTIV BIT(6) /* Write Activate only */
#define ICE_AQC_NVM_ACTIV_SEL_MASK MAKEMASK(0x7, 3)		#define ICE_AQC_NVM_ACTIV_SEL_MASK MAKEMASK(0x7, 3)
#define ICE_AQC_NVM_FLASH_ONLY BIT(7)		#define ICE_AQC_NVM_FLASH_ONLY BIT(7)
#define ICE_AQC_NVM_POR_FLAG 0 /* Used by NVM Write completion on ARQ */		#define ICE_AQC_NVM_RESET_LVL_M MAKEMASK(0x3, 0) /* Write reply only */
		#define ICE_AQC_NVM_POR_FLAG 0
#define ICE_AQC_NVM_PERST_FLAG 1		#define ICE_AQC_NVM_PERST_FLAG 1
#define ICE_AQC_NVM_EMPR_FLAG 2		#define ICE_AQC_NVM_EMPR_FLAG 2
#define ICE_AQC_NVM_EMPR_ENA BIT(0)		#define ICE_AQC_NVM_EMPR_ENA BIT(0) /* Write Activate reply only */
__le16 module_typeid;		__le16 module_typeid;
__le16 length;		__le16 length;
#define ICE_AQC_NVM_ERASE_LEN 0xFFFF		#define ICE_AQC_NVM_ERASE_LEN 0xFFFF
__le32 addr_high;		__le32 addr_high;
__le32 addr_low;		__le32 addr_low;
};		};

/* NVM Module_Type ID, needed offset and read_len for struct ice_aqc_nvm. */		/* NVM Module_Type ID, needed offset and read_len for struct ice_aqc_nvm. */
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/* Lan Queue Overflow Event (direct, 0x1001) */		/* Lan Queue Overflow Event (direct, 0x1001) */
struct ice_aqc_event_lan_overflow {		struct ice_aqc_event_lan_overflow {
__le32 prtdcb_ruptq;		__le32 prtdcb_ruptq;
__le32 qtx_ctl;		__le32 qtx_ctl;
u8 reserved[8];		u8 reserved[8];
};		};

		/* Debug Dump Internal Data (indirect 0xFF08) */
		struct ice_aqc_debug_dump_internals {
		u8 cluster_id;
		#define ICE_AQC_DBG_DUMP_CLUSTER_ID_SW 0
		#define ICE_AQC_DBG_DUMP_CLUSTER_ID_TXSCHED 2
		#define ICE_AQC_DBG_DUMP_CLUSTER_ID_PROFILES 3
		/* EMP_DRAM only dumpable in device debug mode */
		#define ICE_AQC_DBG_DUMP_CLUSTER_ID_EMP_DRAM 4
		#define ICE_AQC_DBG_DUMP_CLUSTER_ID_LINK 5
		/* AUX_REGS only dumpable in device debug mode */
		#define ICE_AQC_DBG_DUMP_CLUSTER_ID_AUX_REGS 6
		#define ICE_AQC_DBG_DUMP_CLUSTER_ID_DCB 7
		#define ICE_AQC_DBG_DUMP_CLUSTER_ID_L2P 8
		u8 reserved;
		__le16 table_id; /* Used only for non-memory clusters */
		__le32 idx; /* In table entries for tables, in bytes for memory */
		__le32 addr_high;
		__le32 addr_low;
		};

		enum ice_aqc_fw_logging_mod {
		ICE_AQC_FW_LOG_ID_GENERAL = 0,
		ICE_AQC_FW_LOG_ID_CTRL,
		ICE_AQC_FW_LOG_ID_LINK,
		ICE_AQC_FW_LOG_ID_LINK_TOPO,
		ICE_AQC_FW_LOG_ID_DNL,
		ICE_AQC_FW_LOG_ID_I2C,
		ICE_AQC_FW_LOG_ID_SDP,
		ICE_AQC_FW_LOG_ID_MDIO,
		ICE_AQC_FW_LOG_ID_ADMINQ,
		ICE_AQC_FW_LOG_ID_HDMA,
		ICE_AQC_FW_LOG_ID_LLDP,
		ICE_AQC_FW_LOG_ID_DCBX,
		ICE_AQC_FW_LOG_ID_DCB,
		ICE_AQC_FW_LOG_ID_XLR,
		ICE_AQC_FW_LOG_ID_NVM,
		ICE_AQC_FW_LOG_ID_AUTH,
		ICE_AQC_FW_LOG_ID_VPD,
		ICE_AQC_FW_LOG_ID_IOSF,
		ICE_AQC_FW_LOG_ID_PARSER,
		ICE_AQC_FW_LOG_ID_SW,
		ICE_AQC_FW_LOG_ID_SCHEDULER,
		ICE_AQC_FW_LOG_ID_TXQ,
		ICE_AQC_FW_LOG_ID_RSVD,
		ICE_AQC_FW_LOG_ID_POST,
		ICE_AQC_FW_LOG_ID_WATCHDOG,
		ICE_AQC_FW_LOG_ID_TASK_DISPATCH,
		ICE_AQC_FW_LOG_ID_MNG,
		ICE_AQC_FW_LOG_ID_SYNCE,
		ICE_AQC_FW_LOG_ID_HEALTH,
		ICE_AQC_FW_LOG_ID_TSDRV,
		ICE_AQC_FW_LOG_ID_PFREG,
		ICE_AQC_FW_LOG_ID_MDLVER,
		ICE_AQC_FW_LOG_ID_MAX,
		};


/* Set Health Status (direct 0xFF20) */		/* Set Health Status (direct 0xFF20) */
struct ice_aqc_set_health_status_config {		struct ice_aqc_set_health_status_config {
u8 event_source;		u8 event_source;
#define ICE_AQC_HEALTH_STATUS_SET_PF_SPECIFIC_MASK BIT(0)		#define ICE_AQC_HEALTH_STATUS_SET_PF_SPECIFIC_MASK BIT(0)
#define ICE_AQC_HEALTH_STATUS_SET_ALL_PF_MASK BIT(1)		#define ICE_AQC_HEALTH_STATUS_SET_ALL_PF_MASK BIT(1)
#define ICE_AQC_HEALTH_STATUS_SET_GLOBAL_MASK BIT(2)		#define ICE_AQC_HEALTH_STATUS_SET_GLOBAL_MASK BIT(2)
u8 reserved[15];		u8 reserved[15];
};		};
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#define ICE_AQC_HEALTH_STATUS_ERR_PARALLEL_FAULT 0x110		#define ICE_AQC_HEALTH_STATUS_ERR_PARALLEL_FAULT 0x110
#define ICE_AQC_HEALTH_STATUS_INFO_PORT_SPEED_PHY_LIMITED 0x111		#define ICE_AQC_HEALTH_STATUS_INFO_PORT_SPEED_PHY_LIMITED 0x111
#define ICE_AQC_HEALTH_STATUS_ERR_NETLIST_TOPO 0x112		#define ICE_AQC_HEALTH_STATUS_ERR_NETLIST_TOPO 0x112
#define ICE_AQC_HEALTH_STATUS_ERR_NETLIST 0x113		#define ICE_AQC_HEALTH_STATUS_ERR_NETLIST 0x113
#define ICE_AQC_HEALTH_STATUS_ERR_TOPO_CONFLICT 0x114		#define ICE_AQC_HEALTH_STATUS_ERR_TOPO_CONFLICT 0x114
#define ICE_AQC_HEALTH_STATUS_ERR_LINK_HW_ACCESS 0x115		#define ICE_AQC_HEALTH_STATUS_ERR_LINK_HW_ACCESS 0x115
#define ICE_AQC_HEALTH_STATUS_ERR_LINK_RUNTIME 0x116		#define ICE_AQC_HEALTH_STATUS_ERR_LINK_RUNTIME 0x116
#define ICE_AQC_HEALTH_STATUS_ERR_DNL_INIT 0x117		#define ICE_AQC_HEALTH_STATUS_ERR_DNL_INIT 0x117
		#define ICE_AQC_HEALTH_STATUS_ERR_PHY_NVM_PROG 0x120
		#define ICE_AQC_HEALTH_STATUS_ERR_PHY_FW_LOAD 0x121
#define ICE_AQC_HEALTH_STATUS_INFO_RECOVERY 0x500		#define ICE_AQC_HEALTH_STATUS_INFO_RECOVERY 0x500
#define ICE_AQC_HEALTH_STATUS_ERR_FLASH_ACCESS 0x501		#define ICE_AQC_HEALTH_STATUS_ERR_FLASH_ACCESS 0x501
#define ICE_AQC_HEALTH_STATUS_ERR_NVM_AUTH 0x502		#define ICE_AQC_HEALTH_STATUS_ERR_NVM_AUTH 0x502
#define ICE_AQC_HEALTH_STATUS_ERR_OROM_AUTH 0x503		#define ICE_AQC_HEALTH_STATUS_ERR_OROM_AUTH 0x503
#define ICE_AQC_HEALTH_STATUS_ERR_DDP_AUTH 0x504		#define ICE_AQC_HEALTH_STATUS_ERR_DDP_AUTH 0x504
#define ICE_AQC_HEALTH_STATUS_ERR_NVM_COMPAT 0x505		#define ICE_AQC_HEALTH_STATUS_ERR_NVM_COMPAT 0x505
#define ICE_AQC_HEALTH_STATUS_ERR_OROM_COMPAT 0x506		#define ICE_AQC_HEALTH_STATUS_ERR_OROM_COMPAT 0x506
#define ICE_AQC_HEALTH_STATUS_ERR_DCB_MIB 0x509		#define ICE_AQC_HEALTH_STATUS_ERR_DCB_MIB 0x509
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/* Set FW Logging configuration (indirect 0xFF30)		/* Set FW Logging configuration (indirect 0xFF30)
* Register for FW Logging (indirect 0xFF31)		* Register for FW Logging (indirect 0xFF31)
* Query FW Logging (indirect 0xFF32)		* Query FW Logging (indirect 0xFF32)
* FW Log Event (indirect 0xFF33)		* FW Log Event (indirect 0xFF33)
* Get FW Log (indirect 0xFF34)		* Get FW Log (indirect 0xFF34)
* Clear FW Log (indirect 0xFF35)		* Clear FW Log (indirect 0xFF35)
*/		*/

struct ice_aqc_fw_log {		struct ice_aqc_fw_log {
u8 cmd_flags;		u8 cmd_flags;
#define ICE_AQC_FW_LOG_CONF_UART_EN BIT(0)		#define ICE_AQC_FW_LOG_CONF_UART_EN BIT(0)
#define ICE_AQC_FW_LOG_CONF_AQ_EN BIT(1)		#define ICE_AQC_FW_LOG_CONF_AQ_EN BIT(1)
		#define ICE_AQC_FW_LOG_QUERY_REGISTERED BIT(2)
#define ICE_AQC_FW_LOG_CONF_SET_VALID BIT(3)		#define ICE_AQC_FW_LOG_CONF_SET_VALID BIT(3)
#define ICE_AQC_FW_LOG_AQ_REGISTER BIT(0)		#define ICE_AQC_FW_LOG_AQ_REGISTER BIT(0)
#define ICE_AQC_FW_LOG_AQ_QUERY BIT(2)		#define ICE_AQC_FW_LOG_AQ_QUERY BIT(2)
#define ICE_AQC_FW_LOG_PERSISTENT BIT(0)		#define ICE_AQC_FW_LOG_PERSISTENT BIT(0)
u8 rsp_flag;		u8 rsp_flag;
#define ICE_AQC_FW_LOG_MORE_DATA BIT(1)		#define ICE_AQC_FW_LOG_MORE_DATA BIT(1)
__le16 fw_rt_msb;		__le16 fw_rt_msb;
union {		union {
▲ Show 20 Lines • Show All 71 Lines • ▼ Show 20 Lines	union {
struct ice_aqc_dnl_set_breakpoints_command dnl_set_brk;		struct ice_aqc_dnl_set_breakpoints_command dnl_set_brk;
struct ice_aqc_dnl_read_log_command dnl_read_log;		struct ice_aqc_dnl_read_log_command dnl_read_log;
struct ice_aqc_dnl_read_log_response dnl_read_log_resp;		struct ice_aqc_dnl_read_log_response dnl_read_log_resp;
struct ice_aqc_i2c read_write_i2c;		struct ice_aqc_i2c read_write_i2c;
struct ice_aqc_read_i2c_resp read_i2c_resp;		struct ice_aqc_read_i2c_resp read_i2c_resp;
struct ice_aqc_mdio read_write_mdio;		struct ice_aqc_mdio read_write_mdio;
struct ice_aqc_gpio_by_func read_write_gpio_by_func;		struct ice_aqc_gpio_by_func read_write_gpio_by_func;
struct ice_aqc_gpio read_write_gpio;		struct ice_aqc_gpio read_write_gpio;
		struct ice_aqc_sw_gpio sw_read_write_gpio;
struct ice_aqc_set_led set_led;		struct ice_aqc_set_led set_led;
struct ice_aqc_mdio read_mdio;		struct ice_aqc_mdio read_mdio;
struct ice_aqc_mdio write_mdio;		struct ice_aqc_mdio write_mdio;
struct ice_aqc_sff_eeprom read_write_sff_param;		struct ice_aqc_sff_eeprom read_write_sff_param;
struct ice_aqc_set_port_id_led set_port_id_led;		struct ice_aqc_set_port_id_led set_port_id_led;
struct ice_aqc_get_port_options get_port_options;		struct ice_aqc_get_port_options get_port_options;
struct ice_aqc_set_port_option set_port_option;		struct ice_aqc_set_port_option set_port_option;
struct ice_aqc_get_sw_cfg get_sw_conf;		struct ice_aqc_get_sw_cfg get_sw_conf;
Show All 34 Lines	union {
struct ice_aqc_move_txqs move_txqs;		struct ice_aqc_move_txqs move_txqs;
struct ice_aqc_txqs_cleanup txqs_cleanup;		struct ice_aqc_txqs_cleanup txqs_cleanup;
struct ice_aqc_add_get_update_free_vsi vsi_cmd;		struct ice_aqc_add_get_update_free_vsi vsi_cmd;
struct ice_aqc_add_update_free_vsi_resp add_update_free_vsi_res;		struct ice_aqc_add_update_free_vsi_resp add_update_free_vsi_res;
struct ice_aqc_get_vsi_resp get_vsi_resp;		struct ice_aqc_get_vsi_resp get_vsi_resp;
struct ice_aqc_download_pkg download_pkg;		struct ice_aqc_download_pkg download_pkg;
struct ice_aqc_get_pkg_info_list get_pkg_info_list;		struct ice_aqc_get_pkg_info_list get_pkg_info_list;
struct ice_aqc_driver_shared_params drv_shared_params;		struct ice_aqc_driver_shared_params drv_shared_params;
		struct ice_aqc_fw_log fw_log;
		struct ice_aqc_debug_dump_internals debug_dump;
struct ice_aqc_set_mac_lb set_mac_lb;		struct ice_aqc_set_mac_lb set_mac_lb;
struct ice_aqc_alloc_free_res_cmd sw_res_ctrl;		struct ice_aqc_alloc_free_res_cmd sw_res_ctrl;
struct ice_aqc_get_res_alloc get_res;		struct ice_aqc_get_res_alloc get_res;
struct ice_aqc_get_allocd_res_desc get_res_desc;		struct ice_aqc_get_allocd_res_desc get_res_desc;
struct ice_aqc_set_mac_cfg set_mac_cfg;		struct ice_aqc_set_mac_cfg set_mac_cfg;
struct ice_aqc_set_event_mask set_event_mask;		struct ice_aqc_set_event_mask set_event_mask;
struct ice_aqc_get_link_status get_link_status;		struct ice_aqc_get_link_status get_link_status;
struct ice_aqc_event_lan_overflow lan_overflow;		struct ice_aqc_event_lan_overflow lan_overflow;
struct ice_aqc_get_link_topo get_link_topo;		struct ice_aqc_get_link_topo get_link_topo;
struct ice_aqc_set_health_status_config		struct ice_aqc_set_health_status_config
set_health_status_config;		set_health_status_config;
struct ice_aqc_get_supported_health_status_codes		struct ice_aqc_get_supported_health_status_codes
get_supported_health_status_codes;		get_supported_health_status_codes;
struct ice_aqc_get_health_status get_health_status;		struct ice_aqc_get_health_status get_health_status;
struct ice_aqc_clear_health_status clear_health_status;		struct ice_aqc_clear_health_status clear_health_status;
		struct ice_aqc_prog_topo_dev_nvm prog_topo_dev_nvm;
		struct ice_aqc_read_topo_dev_nvm read_topo_dev_nvm;
} params;		} params;
};		};

/* FW defined boundary for a large buffer, 4k >= Large buffer > 512 bytes */		/* FW defined boundary for a large buffer, 4k >= Large buffer > 512 bytes */
#define ICE_AQ_LG_BUF 512		#define ICE_AQ_LG_BUF 512

/* Flags sub-structure		/* Flags sub-structure
* \|0 \|1 \|2 \|3 \|4 \|5 \|6 \|7 \|8 \|9 \|10 \|11 \|12 \|13 \|14 \|15 \|		* \|0 \|1 \|2 \|3 \|4 \|5 \|6 \|7 \|8 \|9 \|10 \|11 \|12 \|13 \|14 \|15 \|
▲ Show 20 Lines • Show All 151 Lines • ▼ Show 20 Lines	enum ice_adminq_opc {
ice_aqc_opc_dnl_get_status = 0x0680,		ice_aqc_opc_dnl_get_status = 0x0680,
ice_aqc_opc_dnl_run = 0x0681,		ice_aqc_opc_dnl_run = 0x0681,
ice_aqc_opc_dnl_call = 0x0682,		ice_aqc_opc_dnl_call = 0x0682,
ice_aqc_opc_dnl_read_sto = 0x0683,		ice_aqc_opc_dnl_read_sto = 0x0683,
ice_aqc_opc_dnl_write_sto = 0x0684,		ice_aqc_opc_dnl_write_sto = 0x0684,
ice_aqc_opc_dnl_set_breakpoints = 0x0686,		ice_aqc_opc_dnl_set_breakpoints = 0x0686,
ice_aqc_opc_dnl_read_log = 0x0687,		ice_aqc_opc_dnl_read_log = 0x0687,
ice_aqc_opc_get_link_topo = 0x06E0,		ice_aqc_opc_get_link_topo = 0x06E0,
ice_aqc_opc_get_link_topo_pin = 0x06E1,
ice_aqc_opc_read_i2c = 0x06E2,		ice_aqc_opc_read_i2c = 0x06E2,
ice_aqc_opc_write_i2c = 0x06E3,		ice_aqc_opc_write_i2c = 0x06E3,
ice_aqc_opc_read_mdio = 0x06E4,		ice_aqc_opc_read_mdio = 0x06E4,
ice_aqc_opc_write_mdio = 0x06E5,		ice_aqc_opc_write_mdio = 0x06E5,
ice_aqc_opc_set_gpio_by_func = 0x06E6,		ice_aqc_opc_set_gpio_by_func = 0x06E6,
ice_aqc_opc_get_gpio_by_func = 0x06E7,		ice_aqc_opc_get_gpio_by_func = 0x06E7,
ice_aqc_opc_set_led = 0x06E8,		ice_aqc_opc_set_led = 0x06E8,
ice_aqc_opc_set_port_id_led = 0x06E9,		ice_aqc_opc_set_port_id_led = 0x06E9,
ice_aqc_opc_get_port_options = 0x06EA,		ice_aqc_opc_get_port_options = 0x06EA,
ice_aqc_opc_set_port_option = 0x06EB,		ice_aqc_opc_set_port_option = 0x06EB,
ice_aqc_opc_set_gpio = 0x06EC,		ice_aqc_opc_set_gpio = 0x06EC,
ice_aqc_opc_get_gpio = 0x06ED,		ice_aqc_opc_get_gpio = 0x06ED,
ice_aqc_opc_sff_eeprom = 0x06EE,		ice_aqc_opc_sff_eeprom = 0x06EE,
ice_aqc_opc_sw_set_gpio = 0x06EF,		ice_aqc_opc_sw_set_gpio = 0x06EF,
ice_aqc_opc_sw_get_gpio = 0x06F0,		ice_aqc_opc_sw_get_gpio = 0x06F0,
ice_aqc_opc_program_topology_device_nvm = 0x06F2,		ice_aqc_opc_prog_topo_dev_nvm = 0x06F2,
ice_aqc_opc_read_topology_device_nvm = 0x06F3,		ice_aqc_opc_read_topo_dev_nvm = 0x06F3,

/* NVM commands */		/* NVM commands */
ice_aqc_opc_nvm_read = 0x0701,		ice_aqc_opc_nvm_read = 0x0701,
ice_aqc_opc_nvm_erase = 0x0702,		ice_aqc_opc_nvm_erase = 0x0702,
ice_aqc_opc_nvm_write = 0x0703,		ice_aqc_opc_nvm_write = 0x0703,
ice_aqc_opc_nvm_cfg_read = 0x0704,		ice_aqc_opc_nvm_cfg_read = 0x0704,
ice_aqc_opc_nvm_cfg_write = 0x0705,		ice_aqc_opc_nvm_cfg_write = 0x0705,
ice_aqc_opc_nvm_checksum = 0x0706,		ice_aqc_opc_nvm_checksum = 0x0706,
▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Lines	enum ice_adminq_opc {
ice_aqc_opc_upload_section = 0x0C41,		ice_aqc_opc_upload_section = 0x0C41,
ice_aqc_opc_update_pkg = 0x0C42,		ice_aqc_opc_update_pkg = 0x0C42,
ice_aqc_opc_get_pkg_info_list = 0x0C43,		ice_aqc_opc_get_pkg_info_list = 0x0C43,

ice_aqc_opc_driver_shared_params = 0x0C90,		ice_aqc_opc_driver_shared_params = 0x0C90,

/* Standalone Commands/Events */		/* Standalone Commands/Events */
ice_aqc_opc_event_lan_overflow = 0x1001,		ice_aqc_opc_event_lan_overflow = 0x1001,

		/* debug commands */
		ice_aqc_opc_debug_dump_internals = 0xFF08,

/* SystemDiagnostic commands */		/* SystemDiagnostic commands */
ice_aqc_opc_set_health_status_config = 0xFF20,		ice_aqc_opc_set_health_status_config = 0xFF20,
ice_aqc_opc_get_supported_health_status_codes = 0xFF21,		ice_aqc_opc_get_supported_health_status_codes = 0xFF21,
ice_aqc_opc_get_health_status = 0xFF22,		ice_aqc_opc_get_health_status = 0xFF22,
ice_aqc_opc_clear_health_status = 0xFF23,		ice_aqc_opc_clear_health_status = 0xFF23,

/* FW Logging Commands */		/* FW Logging Commands */
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