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brcmwl.h
audioone.official_gmail.com (audioone)
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Sep 17 2018, 2:57 PM
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brcmwl.h
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/*
* $FreeBSD$
*/
#ifndef _IF_BRCMWL_H
#define _IF_BRCMWL_H
struct siba_dev_softc;
struct brcmwl_softc;
struct bwn_mac;
#define MANPREFIX_LEN 3
#define FWCHAR_LEN 15
#define SDIO_CCCR_BRCM_CARDCTRL 0xf1
#define SDIO_CCCR_BRCM_CARDCTRL_WLANRESET (1 << 1)
#define letoh32(x) le32toh(x)
#define letoh16(x) le16toh(x)
/* sprom command and status */
#define SBSDIO_SPROM_CS 0x10000
/* sprom info register */
#define SBSDIO_SPROM_INFO 0x10001
/* sprom indirect access data byte 0 */
#define SBSDIO_SPROM_DATA_LOW 0x10002
/* sprom indirect access data byte 1 */
#define SBSDIO_SPROM_DATA_HIGH 0x10003
/* sprom indirect access addr byte 0 */
#define SBSDIO_SPROM_ADDR_LOW 0x10004
/* gpio select */
#define SBSDIO_GPIO_SELECT 0x10005
/* gpio output */
#define SBSDIO_GPIO_OUT 0x10006
/* gpio enable */
#define SBSDIO_GPIO_EN 0x10007
/* rev < 7, watermark for sdio device */
#define SBSDIO_WATERMARK 0x10008
/* control busy signal generation */
#define SBSDIO_DEVICE_CTL 0x10009
#define SBSDIO_DEVCTL_SETBUSY 0x01
#define SBSDIO_DEVCTL_SPI_INTR_SYNC 0x02
#define SBSDIO_DEVCTL_CA_INT_ONLY 0x04
#define SBSDIO_DEVCTL_PADS_ISO 0x08
#define SBSDIO_DEVCTL_SB_RST_CTL 0x30
#define SBSDIO_DEVCTL_RST_CORECTL 0x00
#define SBSDIO_DEVCTL_RST_BPRESET 0x10
#define SBSDIO_DEVCTL_RST_NOBPRESET 0x20
#define HOSTINTMASK (I_HMB_SW_MASK | I_CHIPACTIVE)
#define I_HMB_SW_MASK 0x000000f0 /* To Host Mail S/W interrupts mask */
#define I_HMB_SW_SHIFT 4 /* To Host Mail S/W interrupts shift */
#define I_CHIPACTIVE (1 << 29) /* chip from doze to active state */
/* SB Address Window Low (b15) */
#define OFFSET_FUNC1_SBADDRLOW 0x1000A
#define BCMA_CC_CAP_EXT_AOB_PRESENT 0x00000040
#define BCMA_CORE_PMU 0x827
#define DMP_MASTER_PORT_UID 0x0000FF00
#define DMP_MASTER_PORT_UID_S 8
#define DMP_MASTER_PORT_NUM 0x000000F0
#define DMP_MASTER_PORT_NUM_S 4
#define DMP_SLAVE_ADDR_BASE 0xFFFFF000
#define DMP_SLAVE_ADDR_BASE_S 12
#define DMP_SLAVE_PORT_NUM 0x00000F00
#define DMP_SLAVE_PORT_NUM_S 8
#define DMP_SLAVE_TYPE 0x000000C0
#define DMP_SLAVE_TYPE_S 6
#define DMP_SLAVE_TYPE_SLAVE 0
#define DMP_SLAVE_TYPE_BRIDGE 1
#define DMP_SLAVE_TYPE_SWRAP 2
#define DMP_SLAVE_TYPE_MWRAP 3
#define DMP_SLAVE_SIZE_TYPE 0x00000030
#define DMP_SLAVE_SIZE_TYPE_S 4
#define DMP_SLAVE_SIZE_4K 0
#define DMP_SLAVE_SIZE_8K 1
#define DMP_SLAVE_SIZE_16K 2
#define DMP_SLAVE_SIZE_DESC 3
#define PMU_MAX_TRANSITION_DLY 1000000
#define BCMA_CC_PMU_CTL 0x0600 /* PMU control */
#define BCMA_CC_PMU_CTL_ILP_DIV 0xFFFF0000 /* ILP div mask */
#define BCMA_CC_PMU_CTL_ILP_DIV_SHIFT 16
#define BCMA_CC_PMU_CTL_RES 0x00006000 /* reset control mask */
#define BCMA_CC_PMU_CTL_RES_SHIFT 13
#define BCMA_CC_PMU_CTL_RES_RELOAD 0x2 /* reload POR values */
#define BCMA_CC_PMU_CTL_PLL_UPD 0x00000400
#define BCMA_CC_PMU_CTL_NOILPONW 0x00000200 /* No ILP on wait */
#define BCMA_CC_PMU_CTL_HTREQEN 0x00000100 /* HT req enable */
#define BCMA_CC_PMU_CTL_ALPREQEN 0x00000080 /* ALP req enable */
#define BCMA_CC_PMU_CTL_XTALFREQ 0x0000007C /* Crystal freq */
#define BCMA_CC_PMU_CTL_XTALFREQ_SHIFT 2
#define BCMA_CC_PMU_CTL_ILPDIVEN 0x00000002 /* ILP div enable */
#define BCMA_CC_PMU_CTL_LPOSEL 0x00000001 /* LPO sel */
#define BCMA_CC_PMU_CAP 0x0604 /* PMU capabilities */
#define BCMA_CC_PMU_CAP_REVISION 0x000000FF /* Revision mask */
#define BCMA_CC_PMU_STAT 0x0608 /* PMU status */
#define BCMA_CC_PMU_STAT_EXT_LPO_AVAIL 0x00000100
#define BCMA_CC_PMU_STAT_WDRESET 0x00000080
#define BCMA_CC_PMU_STAT_INTPEND 0x00000040 /* Interrupt pending */
#define BCMA_CC_PMU_STAT_SBCLKST 0x00000030 /* Backplane clock status? */
#define BCMA_CC_PMU_STAT_HAVEALP 0x00000008 /* ALP available */
#define BCMA_CC_PMU_STAT_HAVEHT 0x00000004 /* HT available */
#define BCMA_CC_PMU_STAT_RESINIT 0x00000003 /* Res init */
#define BCMA_CC_PMU_RES_STAT 0x060C /* PMU res status */
#define BCMA_CC_PMU_RES_PEND 0x0610 /* PMU res pending */
#define BCMA_CC_PMU_TIMER 0x0614 /* PMU timer */
#define BCMA_CC_PMU_MINRES_MSK 0x0618 /* PMU min res mask */
#define BCMA_CC_PMU_MAXRES_MSK 0x061C /* PMU max res mask */
#define BCMA_CC_PMU_RES_TABSEL 0x0620 /* PMU res table sel */
#define BCMA_CC_PMU_RES_DEPMSK 0x0624 /* PMU res dep mask */
#define BCMA_CC_PMU_RES_UPDNTM 0x0628 /* PMU res updown timer */
#define BCMA_CC_PMU_RES_TIMER 0x062C /* PMU res timer */
#define BCMA_CC_PMU_CLKSTRETCH 0x0630 /* PMU clockstretch */
#define BCMA_CC_PMU_WATCHDOG 0x0634 /* PMU watchdog */
#define BCMA_CC_PMU_RES_REQTS 0x0640 /* PMU res req timer sel */
#define BCMA_CC_PMU_RES_REQT 0x0644 /* PMU res req timer */
#define BCMA_CC_PMU_RES_REQM 0x0648 /* PMU res req mask */
#define BCMA_CC_PMU_CHIPCTL_ADDR 0x0650
#define BCMA_CC_PMU_CHIPCTL_DATA 0x0654
#define BCMA_CC_PMU_REGCTL_ADDR 0x0658
#define BCMA_CC_PMU_REGCTL_DATA 0x065C
#define BCMA_CC_PMU_PLLCTL_ADDR 0x0660
#define BCMA_CC_PMU_PLLCTL_DATA 0x0664
#define BCMA_CC_PMU_STRAPOPT 0x0668 /* (corerev >= 28) */
#define BCMA_CC_PMU_XTAL_FREQ 0x066C /* (pmurev >= 10) */
#define BCMA_CC_PMU_XTAL_FREQ_ILPCTL_MASK 0x00001FFF
#define BCMA_CC_PMU_XTAL_FREQ_MEASURE_MASK 0x80000000
#define BCMA_CC_PMU_XTAL_FREQ_MEASURE_SHIFT 31
#define BCMA_CC_SPROM 0x0800 /* SPROM beginning */
#define ARMCR4_BCMA_IOCTL_CPUHALT 0x0020
#define BCMA_IOCTL 0x0408
#define D11_BCMA_IOCTL_PHYCLOCKEN 0x0004
#define D11_BCMA_IOCTL_PHYRESET 0x0008
#define DMP_DESC_TYPE_MSK 0x0000000F
#define DMP_DESC_EMPTY 0x00000000
#define DMP_DESC_VALID 0x00000001
#define DMP_DESC_COMPONENT 0x00000001
#define DMP_DESC_MASTER_PORT 0x00000003
#define DMP_DESC_ADDRESS 0x00000005
#define DMP_DESC_ADDRSIZE_GT32 0x00000008
#define DMP_DESC_EOT 0x0000000F
#define DMP_COMP_DESIGNER 0xFFF00000
#define DMP_COMP_DESIGNER_S 20
#define DMP_COMP_PARTNUM 0x000FFF00
#define DMP_COMP_PARTNUM_S 8
#define DMP_COMP_CLASS 0x000000F0
#define DMP_COMP_CLASS_S 4
#define DMP_COMP_REVISION 0xFF000000
#define DMP_COMP_REVISION_S 24
#define DMP_COMP_NUM_SWRAP 0x00F80000
#define DMP_COMP_NUM_SWRAP_S 19
#define DMP_COMP_NUM_MWRAP 0x0007C000
#define DMP_COMP_NUM_MWRAP_S 14
#define DMP_COMP_NUM_SPORT 0x00003E00
#define DMP_COMP_NUM_SPORT_S 9
#define DMP_COMP_NUM_MPORT 0x000001F0
#define DMP_COMP_NUM_MPORT_S 4
#define BCMA_RESET_CTL 0x0800
#define BCMA_RESET_CTL_RESET 0x0001
#define BCMA_IOCTL_CLK 0x0001
#define BCMA_IOCTL_FGC 0x0002
#define BCM4329_CORE_SOCRAM_BASE 0x18003000
#define SOCRAM_BANKINFO_RETNTRAM_MASK 0x00010000
#define SOCRAM_BANKINFO_SZMASK 0x0000007f
#define SOCRAM_BANKIDX_ROM_MASK 0x00000100
#define SOCRAM_BANKIDX_MEMTYPE_SHIFT 8
#define SOCRAM_MEMTYPE_RAM 0
#define SOCRAM_MEMTYPE_R0M 1
#define SOCRAM_MEMTYPE_DEVRAM 2
#define SOCRAM_BANKINFO_SZBASE 8192
#define BRCMWL_CHIP_MAX_MEMSIZE (4 * 1024 * 1024)
/* Status: ALP is ready */
#define SBSDIO_ALP_AVAIL 0x40
/* Status: HT is ready */
#define SBSDIO_HT_AVAIL 0x80
#define SBSDIO_HT_AVAIL_REQ 0x10
#define SBSDIO_ALP_AVAIL_REQ 0x08
#define SBSDIO_CSR_MASK 0x1F
#define SBSDIO_AVBITS (SBSDIO_HT_AVAIL | SBSDIO_ALP_AVAIL)
#define SBSDIO_ALPAV(regval) ((regval) & SBSDIO_AVBITS)
#define SBSDIO_HTAV(regval) (((regval) & SBSDIO_AVBITS) == SBSDIO_AVBITS)
#define SBSDIO_ALPONLY(regval) (SBSDIO_ALPAV(regval) && !SBSDIO_HTAV(regval))
#define SBSDIO_CLKAV(regval, alponly) \
(SBSDIO_ALPAV(regval) && (alponly ? 1 : SBSDIO_HTAV(regval)))
#define BRCMWL_SDIO_FUNC1_CHIPCLKCSR_FORCE_ALP 0x01
#define BRCMWL_SDIO_FUNC1_CHIPCLKCSR_FORCE_HT 0x02
#define BRCMWL_SDIO_FUNC1_CHIPCLKCSR_FORCE_ILP 0x04
#define BRCMWL_SDIO_FUNC1_CHIPCLKCSR_ALP_AVAIL_REQ 0x08
#define BRCMWL_SDIO_FUNC1_CHIPCLKCSR_HT_AVAIL_REQ 0x10
#define BRCMWL_SDIO_FUNC1_CHIPCLKCSR_FORCE_HW_CLKREQ_OFF 0x20
#define BRCMWL_SDIO_FUNC1_CHIPCLKCSR_ALP_AVAIL 0x40
#define BRCMWL_SDIO_FUNC1_CHIPCLKCSR_HT_AVAIL 0x80
#define BRCMWL_SDIO_FUNC1_CHIPCLKCSR_CSR_MASK 0x1F
#define BRCMWL_SDIO_FUNC1_CHIPCLKCSR_AVBITS \
(BRCMWL_SDIO_FUNC1_CHIPCLKCSR_HT_AVAIL | \
BRCMWL_SDIO_FUNC1_CHIPCLKCSR_ALP_AVAIL)
#define BRCMWL_SDIO_FUNC1_CHIPCLKCSR_ALPAV(regval) \
((regval) & BRCMWL_SDIO_FUNC1_CHIPCLKCSR_AVBITS)
#define BRCMWL_SDIO_FUNC1_CHIPCLKCSR_HTAV(regval) \
(((regval) & BRCMWL_SDIO_FUNC1_CHIPCLKCSR_AVBITS) == BRCMWL_SDIO_FUNC1_CHIPCLKCSR_AVBITS)
#define BRCMWL_SDIO_FUNC1_CHIPCLKCSR_ALPONLY(regval) \
(BRCMWL_SDIO_FUNC1_CHIPCLKCSR_ALPAV(regval) && \
!BRCMWL_SDIO_FUNC1_CHIPCLKCSR_HTAV(regval))
#define BRCMWL_SDIO_FUNC1_CHIPCLKCSR_CLKAV(regval, alponly) \
(BRCMWL_SDIO_FUNC1_CHIPCLKCSR_ALPAV(regval) && \
(alponly ? 1 : BRCMWL_SDIO_FUNC1_CHIPCLKCSR_HTAV(regval)))
#define SBSDIO_SBADDRLOW_MASK 0x80 /* Valid bits in SBADDRLOW */
#define SBSDIO_SBADDRMID_MASK 0xff /* Valid bits in SBADDRMID */
#define SBSDIO_SBADDRHIGH_MASK 0xffU /* Valid bits in SBADDRHIGH */
/* Address bits from SBADDR regs */
#define SBSDIO_SBWINDOW_MASK 0xffff8000
#define SRCI_LSS_SHIFT 20
#define SRCI_SRBSZ_MASK 0xf
#define SRCI_SRNB_MASK 0xf0
#define SRCI_SRNB_SHIFT 4
#define SRCI_LSS_MASK 0x00f00000
#define SR_BSZ_BASE 14
#define SBSDIO_FORCE_HW_CLKREQ_OFF 0x20
#define SBSDIO_AVBITS (SBSDIO_HT_AVAIL | SBSDIO_ALP_AVAIL)
#define BRCMWL_SDIO_FUNC1_SLEEPCSR 0x1001F
#define BRCMWL_SDIO_FUNC1_SLEEPCSR_KSO (1 << 0)
#define BRCMWL_SDIO_FUNC1_SLEEPCSR_DEVON (1 << 2)
#define BRCMWL_INIT_CLKCTL1 (SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_ALP_AVAIL_REQ)
/* SB Address Window Mid (b23:b16) */
#define OFFSET_FUNC1_SBADDRMID 0x1000B
/* SB Address Window High (b31:b24) */
#define OFFSET_FUNC1_SBADDRHIGH 0x1000C
/* Frame Control (frame term/abort) */
#define SBSDIO_FUNC1_FRAMECTRL 0x1000D
/* ChipClockCSR (ALP/HT ctl/status) */
#define SBSDIO_FUNC1_CHIPCLKCSR 0x1000E
/* SdioPullUp (on cmd, d0-d2) */
#define SBSDIO_FUNC1_SDIOPULLUP 0x1000F
/* Write Frame Byte Count Low */
#define SBSDIO_FUNC1_WFRAMEBCLO 0x10019
/* Write Frame Byte Count High */
#define SBSDIO_FUNC1_WFRAMEBCHI 0x1001A
/* Read Frame Byte Count Low */
#define SBSDIO_FUNC1_RFRAMEBCLO 0x1001B
/* Read Frame Byte Count High */
#define SBSDIO_FUNC1_RFRAMEBCHI 0x1001C
/* MesBusyCtl (rev 11) */
#define SBSDIO_FUNC1_MESBUSYCTRL 0x1001D
/* Sdio Core Rev 12 */
#define SBSDIO_FUNC1_WAKEUPCTRL 0x1001E
#define SBSDIO_FUNC1_WCTRL_ALPWAIT_MASK 0x1
#define SBSDIO_FUNC1_WCTRL_ALPWAIT_SHIFT 0
#define SBSDIO_FUNC1_WCTRL_HTWAIT_MASK 0x2
#define SBSDIO_FUNC1_WCTRL_HTWAIT_SHIFT 1
#define SBSDIO_FUNC1_SLEEPCSR 0x1001F
#define SBSDIO_FUNC1_SLEEPCSR_KSO_MASK 0x1
#define SBSDIO_FUNC1_SLEEPCSR_KSO_SHIFT 0
#define SBSDIO_FUNC1_SLEEPCSR_KSO_EN 1
#define SBSDIO_FUNC1_SLEEPCSR_DEVON_MASK 0x2
#define SBSDIO_FUNC1_SLEEPCSR_DEVON_SHIFT 1
#define SBSDIO_FUNC1_MISC_REG_START 0x10000 /* f1 misc register start */
#define SBSDIO_FUNC1_MISC_REG_LIMIT 0x1001F /* f1 misc register end */
/* function 0 vendor specific CCCR registers */
#define SDIO_CCCR_BRCM_CARDCAP 0xf0
#define SDIO_CCCR_BRCM_CARDCAP_CMD14_SUPPORT (1 << 1)
#define SDIO_CCCR_BRCM_CARDCAP_CMD14_EXT (1 << 2)
#define SDIO_CCCR_BRCM_CARDCAP_CMD_NODEC (1 << 3)
/* function 1 OCP space */
/* sb offset addr is <= 15 bits, 32k */
#define OFFSET_OFT_ADDR_MASK 0x07FFF
#define SBSDIO_SB_OFT_ADDR_LIMIT 0x08000
/* with b15, maps to 32-bit SB access */
#define OFFSET_ACCESS_2_4B_FLAG 0x08000
#define BRCMWL_SDIO_SB_OFT_ADDR_PAGE 0x08000
#define SOCRAMREGOFFS(_f) offsetof(struct sb_socramregs_t, _f)
#define SYSMEMREGOFFS(_f) offsetof(struct sb_socramregs_t, _f)
/* Protocol defines */
#define SDPCM_PROT_VERSION 4
#define SDPCM_PROT_VERSION_SHIFT 16
#define SDPCM_SHARED_VERSION 0x0003
#define SDPCM_SHARED_VERSION_MASK 0x00FF
#define SDPCM_SHARED_ASSERT_BUILT 0x0100
#define SDPCM_SHARED_ASSERT 0x0200
#define SDPCM_SHARED_TRAP 0x0400
#define SDPCMD_INTSTATUS 0x020
#define SDPCMD_INTSTATUS_SMB_SW0 (1 << 0) /* To SB Mail S/W interrupt 0 */
#define SDPCMD_INTSTATUS_SMB_SW1 (1 << 1) /* To SB Mail S/W interrupt 1 */
#define SDPCMD_INTSTATUS_SMB_SW2 (1 << 2) /* To SB Mail S/W interrupt 2 */
#define SDPCMD_INTSTATUS_SMB_SW3 (1 << 3) /* To SB Mail S/W interrupt 3 */
#define SDPCMD_INTSTATUS_SMB_SW_MASK 0x0000000f /* To SB Mail S/W interrupts mask */
#define SDPCMD_INTSTATUS_SMB_SW_SHIFT 0 /* To SB Mail S/W interrupts shift */
#define SDPCMD_INTSTATUS_HMB_SW0 (1 << 4) /* To Host Mail S/W interrupt 0 */
#define SDPCMD_INTSTATUS_HMB_SW1 (1 << 5) /* To Host Mail S/W interrupt 1 */
#define SDPCMD_INTSTATUS_HMB_SW2 (1 << 6) /* To Host Mail S/W interrupt 2 */
#define SDPCMD_INTSTATUS_HMB_SW3 (1 << 7) /* To Host Mail S/W interrupt 3 */
#define SDPCMD_INTSTATUS_HMB_FC_STATE SDPCMD_INTSTATUS_HMB_SW0
#define SDPCMD_INTSTATUS_HMB_FC_CHANGE SDPCMD_INTSTATUS_HMB_SW1
#define SDPCMD_INTSTATUS_HMB_FRAME_IND SDPCMD_INTSTATUS_HMB_SW2
#define SDPCMD_INTSTATUS_HMB_HOST_INT SDPCMD_INTSTATUS_HMB_SW3
#define SDPCMD_INTSTATUS_HMB_SW_MASK 0x000000f0 /* To Host Mail S/W interrupts mask */
#define SDPCMD_INTSTATUS_HMB_SW_SHIFT 4 /* To Host Mail S/W interrupts shift */
#define SDPCMD_INTSTATUS_WR_OOSYNC (1 << 8) /* Write Frame Out Of Sync */
#define SDPCMD_INTSTATUS_RD_OOSYNC (1 << 9) /* Read Frame Out Of Sync */
#define SDPCMD_INTSTATUS_PC (1 << 10)/* descriptor error */
#define SDPCMD_INTSTATUS_PD (1 << 11)/* data error */
#define SDPCMD_INTSTATUS_DE (1 << 12)/* Descriptor protocol Error */
#define SDPCMD_INTSTATUS_RU (1 << 13)/* Receive descriptor Underflow */
#define SDPCMD_INTSTATUS_RO (1 << 14)/* Receive fifo Overflow */
#define SDPCMD_INTSTATUS_XU (1 << 15)/* Transmit fifo Underflow */
#define SDPCMD_INTSTATUS_RI (1 << 16)/* Receive Interrupt */
#define SDPCMD_INTSTATUS_BUSPWR (1 << 17)/* SDIO Bus Power Change (rev 9) */
#define SDPCMD_INTSTATUS_XMTDATA_AVAIL (1 << 23)/* bits in fifo */
#define SDPCMD_INTSTATUS_XI (1 << 24)/* Transmit Interrupt */
#define SDPCMD_INTSTATUS_RF_TERM (1 << 25)/* Read Frame Terminate */
#define SDPCMD_INTSTATUS_WF_TERM (1 << 26)/* Write Frame Terminate */
#define SDPCMD_INTSTATUS_PCMCIA_XU (1 << 27)/* PCMCIA Transmit FIFO Underflow */
#define SDPCMD_INTSTATUS_SBINT (1 << 28)/* sbintstatus Interrupt */
#define SDPCMD_INTSTATUS_CHIPACTIVE (1 << 29)/* chip from doze to active state */
#define SDPCMD_INTSTATUS_SRESET (1 << 30)/* CCCR RES interrupt */
#define SDPCMD_INTSTATUS_IOE2 (1U << 31)/* CCCR IOE2 Bit Changed */
#define SDPCMD_INTSTATUS_ERRORS (SDPCMD_INTSTATUS_PC | \
SDPCMD_INTSTATUS_PD | \
SDPCMD_INTSTATUS_DE | \
SDPCMD_INTSTATUS_RU | \
SDPCMD_INTSTATUS_RO | \
SDPCMD_INTSTATUS_XU)
#define SDPCMD_INTSTATUS_DMA (SDPCMD_INTSTATUS_RI | \
SDPCMD_INTSTATUS_XI | \
SDPCMD_INTSTATUS_ERRORS)
#define SDPCMD_HOSTINTMASK 0x024
#define SDPCMD_INTMASK 0x028
#define SDPCMD_SBINTSTATUS 0x02c
#define SDPCMD_SBINTMASK 0x030
#define SDPCMD_FUNCTINTMASK 0x034
#define SDPCMD_TOSBMAILBOX 0x040
#define SDPCMD_TOSBMAILBOX_NAK (1 << 0)
#define SDPCMD_TOSBMAILBOX_INT_ACK (1 << 1)
#define SDPCMD_TOSBMAILBOX_USE_OOB (1 << 2)
#define SDPCMD_TOSBMAILBOX_DEV_INT (1 << 3)
#define SDPCMD_TOHOSTMAILBOX 0x044
#define SDPCMD_TOSBMAILBOXDATA 0x048
#define SDPCMD_TOHOSTMAILBOXDATA 0x04C
#define SDPCMD_TOHOSTMAILBOXDATA_NAKHANDLED (1 << 0)
#define SDPCMD_TOHOSTMAILBOXDATA_DEVREADY (1 << 1)
#define SDPCMD_TOHOSTMAILBOXDATA_FC (1 << 2)
#define SDPCMD_TOHOSTMAILBOXDATA_FWREADY (1 << 3)
#define SDPCMD_TOHOSTMAILBOXDATA_FWHALT (1 << 4)
#define SDIO_BROADCOM 0x02d0
#define BRCMWL_SOFTC(d) (struct brcmwl_softc *) device_get_softc(d)
#define N(a) (sizeof(a) / sizeof(a[0]))
#define BWN_ALIGN 0x1000
#define BWN_BUS_SPACE_MAXADDR_30BIT 0x3fffffff
#define BWN_RETRY_SHORT 7
#define BWN_RETRY_LONG 4
#define BWN_STAID_MAX 64
#define BWN_TXPWR_IGNORE_TIME (1 << 0)
#define BWN_TXPWR_IGNORE_TSSI (1 << 1)
#define BWN_HAS_TXMAG(phy) \
(((phy)->rev >= 2) && ((phy)->rf_ver == 0x2050) && \
((phy)->rf_rev == 8))
#define BWN_HAS_LOOPBACK(phy) \
(((phy)->rev > 1) || ((phy)->gmode))
#define BWN_TXERROR_MAX 1000
#define BWN_GETTIME(v) do { \
struct timespec ts; \
nanouptime(&ts); \
(v) = ts.tv_nsec / 1000000 + ts.tv_sec * 1000; \
} while (0)
#define BWN_ISOLDFMT(mac) ((mac)->mac_fw.rev <= 351)
#define BWN_TSSI2DBM(num, den) \
((int32_t)((num < 0) ? num / den : (num + den / 2) / den))
#define BWN_HDRSIZE(mac) bwn_tx_hdrsize(mac)
#define BWN_MAXTXHDRSIZE (112 + (sizeof(struct bwn_plcp6)))
#define BWN_PIO_COOKIE(tq, tp) \
((uint16_t)((((uint16_t)tq->tq_index + 1) << 12) | tp->tp_index))
#define BWN_DMA_COOKIE(dr, slot) \
((uint16_t)(((uint16_t)dr->dr_index + 1) << 12) | (uint16_t)slot)
#define BWN_READ_2(mac, o) (siba_read_2(mac->mac_sc->sc_dev, o))
#define BWN_READ_4(mac, o) (siba_read_4(mac->mac_sc->sc_dev, o))
#define BWN_WRITE_2(mac, o, v) \
(siba_write_2(mac->mac_sc->sc_dev, o, v))
#define BWN_WRITE_2_F(mac, o, v) do { \
(BWN_WRITE_2(mac, o, v)); \
BWN_READ_2(mac, o); \
} while(0)
#define BWN_WRITE_SETMASK2(mac, offset, mask, set) \
BWN_WRITE_2(mac, offset, (BWN_READ_2(mac, offset) & mask) | set)
#define BWN_WRITE_4(mac, o, v) \
(siba_write_4(mac->mac_sc->sc_dev, o, v))
#define BWN_WRITE_SETMASK4(mac, offset, mask, set) \
BWN_WRITE_4(mac, offset, (BWN_READ_4(mac, offset) & mask) | set)
#define BWN_PIO_TXQOFFSET(mac) \
((siba_get_revid(mac->mac_sc->sc_dev) >= 11) ? 0x18 : 0)
#define BWN_PIO_RXQOFFSET(mac) \
((siba_get_revid(mac->mac_sc->sc_dev) >= 11) ? 0x38 : 8)
#define BWN_SEC_NEWAPI(mac) (mac->mac_fw.rev >= 351)
#define BWN_SEC_KEY2FW(mac, idx) \
(BWN_SEC_NEWAPI(mac) ? idx : ((idx >= 4) ? idx - 4 : idx))
#define BWN_RF_READ(mac, r) (mac->mac_phy.rf_read(mac, r))
#define BWN_RF_WRITE(mac, r, v) (mac->mac_phy.rf_write(mac, r, v))
#define BWN_RF_MASK(mac, o, m) \
BWN_RF_WRITE(mac, o, BWN_RF_READ(mac, o) & m)
#define BWN_RF_SETMASK(mac, offset, mask, set) \
BWN_RF_WRITE(mac, offset, (BWN_RF_READ(mac, offset) & mask) | set)
#define BWN_RF_SET(mac, offset, set) \
BWN_RF_WRITE(mac, offset, BWN_RF_READ(mac, offset) | set)
#define BWN_PHY_READ(mac, r) (mac->mac_phy.phy_read(mac, r))
#define BWN_PHY_WRITE(mac, r, v) \
(mac->mac_phy.phy_write(mac, r, v))
#define BWN_PHY_SET(mac, offset, set) do { \
if (mac->mac_phy.phy_maskset != NULL) { \
KASSERT(mac->mac_status < BWN_MAC_STATUS_INITED || \
mac->mac_suspended > 0, \
("dont access PHY or RF registers after turning on MAC")); \
mac->mac_phy.phy_maskset(mac, offset, 0xffff, set); \
} else \
BWN_PHY_WRITE(mac, offset, \
BWN_PHY_READ(mac, offset) | (set)); \
} while (0)
#define BWN_PHY_SETMASK(mac, offset, mask, set) do { \
if (mac->mac_phy.phy_maskset != NULL) { \
KASSERT(mac->mac_status < BWN_MAC_STATUS_INITED || \
mac->mac_suspended > 0, \
("dont access PHY or RF registers after turning on MAC")); \
mac->mac_phy.phy_maskset(mac, offset, mask, set); \
} else \
BWN_PHY_WRITE(mac, offset, \
(BWN_PHY_READ(mac, offset) & (mask)) | (set)); \
} while (0)
#define BWN_PHY_MASK(mac, offset, mask) do { \
if (mac->mac_phy.phy_maskset != NULL) { \
KASSERT(mac->mac_status < BWN_MAC_STATUS_INITED || \
mac->mac_suspended > 0, \
("dont access PHY or RF registers after turning on MAC")); \
mac->mac_phy.phy_maskset(mac, offset, mask, 0); \
} else \
BWN_PHY_WRITE(mac, offset, \
BWN_PHY_READ(mac, offset) & mask); \
} while (0)
#define BWN_PHY_COPY(mac, dst, src) do { \
KASSERT(mac->mac_status < BWN_MAC_STATUS_INITED || \
mac->mac_suspended > 0, \
("dont access PHY or RF registers after turning on MAC")); \
BWN_PHY_WRITE(mac, dst, BWN_PHY_READ(mac, src)); \
} while (0)
#define BWN_LO_CALIB_EXPIRE (1000 * (30 - 2))
#define BWN_LO_PWRVEC_EXPIRE (1000 * (30 - 2))
#define BWN_LO_TXCTL_EXPIRE (1000 * (180 - 4))
#define BWN_DMA_BIT_MASK(n) (((n) == 64) ? ~0ULL : ((1ULL<<(n))-1))
#define BWN_LPD(L, P, D) (((L) << 2) | ((P) << 1) | ((D) << 0))
#define BWN_BITREV4(tmp) (BWN_BITREV8(tmp) >> 4)
#define BWN_BITREV8(byte) (bwn_bitrev_table[byte])
#define BWN_BBATTCMP(a, b) ((a)->att == (b)->att)
#define BWN_RFATTCMP(a, b) \
(((a)->att == (b)->att) && ((a)->padmix == (b)->padmix))
#define BWN_PIO_WRITE_2(mac, tq, offset, value) \
BWN_WRITE_2(mac, (tq)->tq_base + offset, value)
#define BWN_PIO_READ_4(mac, tq, offset) \
BWN_READ_4(mac, tq->tq_base + offset)
#define BWN_ISCCKRATE(rate) \
(rate == BWN_CCK_RATE_1MB || rate == BWN_CCK_RATE_2MB || \
rate == BWN_CCK_RATE_5MB || rate == BWN_CCK_RATE_11MB)
#define BWN_ISOFDMRATE(rate) (!BWN_ISCCKRATE(rate))
#define BWN_BARRIER(mac, flags) siba_barrier(mac->mac_sc->sc_dev, flags)
#define BWN_DMA_READ(dr, offset) \
(BWN_READ_4(dr->dr_mac, dr->dr_base + offset))
#define BWN_DMA_WRITE(dr, offset, value) \
(BWN_WRITE_4(dr->dr_mac, dr->dr_base + offset, value))
/* chipid */
#define CID_ID_MASK 0x0000ffff /* Chip Id mask */
#define CID_REV_MASK 0x000f0000 /* Chip Revision mask */
#define CID_REV_SHIFT 16 /* Chip Revision shift */
#define CID_PKG_MASK 0x00f00000 /* Package Option mask */
#define CID_PKG_SHIFT 20 /* Package Option shift */
#define CID_CC_MASK 0x0f000000 /* CoreCount (corerev >= 4) */
#define CID_CC_SHIFT 24
#define CID_TYPE_MASK 0xf0000000 /* Chip Type */
#define CID_TYPE_SHIFT 28
#define SI_ENUM_BASE 0x18000000
/* capabilities */
#define CC_CAP_UARTS_MASK 0x00000003 /* Number of UARTs */
#define CC_CAP_MIPSEB 0x00000004 /* MIPS is in big-endian mode */
#define CC_CAP_UCLKSEL 0x00000018 /* UARTs clock select */
/* UARTs are driven by internal divided clock */
#define CC_CAP_UINTCLK 0x00000008
#define CC_CAP_UARTGPIO 0x00000020 /* UARTs own GPIOs 15:12 */
#define CC_CAP_EXTBUS_MASK 0x000000c0 /* External bus mask */
#define CC_CAP_EXTBUS_NONE 0x00000000 /* No ExtBus present */
#define CC_CAP_EXTBUS_FULL 0x00000040 /* ExtBus: PCMCIA, IDE & Prog */
#define CC_CAP_EXTBUS_PROG 0x00000080 /* ExtBus: ProgIf only */
#define CC_CAP_FLASH_MASK 0x00000700 /* Type of flash */
#define CC_CAP_PLL_MASK 0x00038000 /* Type of PLL */
#define CC_CAP_PWR_CTL 0x00040000 /* Power control */
#define CC_CAP_OTPSIZE 0x00380000 /* OTP Size (0 = none) */
#define CC_CAP_OTPSIZE_SHIFT 19 /* OTP Size shift */
#define CC_CAP_OTPSIZE_BASE 5 /* OTP Size base */
#define CC_CAP_JTAGP 0x00400000 /* JTAG Master Present */
#define CC_CAP_ROM 0x00800000 /* Internal boot rom active */
#define CC_CAP_BKPLN64 0x08000000 /* 64-bit backplane */
#define CC_CAP_PMU 0x10000000 /* PMU Present, rev >= 20 */
#define CC_CAP_SROM 0x40000000 /* Srom Present, rev >= 32 */
/* Nand flash present, rev >= 35 */
#define CC_CAP_NFLASH 0x80000000
#define CC_CAP2_SECI 0x00000001 /* SECI Present, rev >= 36 */
/* GSIO (spi/i2c) present, rev >= 37 */
#define CC_CAP2_GSIO 0x00000002
/* pmucapabilities */
#define PCAP_REV_MASK 0x000000ff
#define PCAP_RC_MASK 0x00001f00
#define PCAP_RC_SHIFT 8
#define PCAP_TC_MASK 0x0001e000
#define PCAP_TC_SHIFT 13
#define PCAP_PC_MASK 0x001e0000
#define PCAP_PC_SHIFT 17
#define PCAP_VC_MASK 0x01e00000
#define PCAP_VC_SHIFT 21
#define PCAP_CC_MASK 0x1e000000
#define PCAP_CC_SHIFT 25
#define PCAP5_PC_MASK 0x003e0000 /* PMU corerev >= 5 */
#define PCAP5_PC_SHIFT 17
#define PCAP5_VC_MASK 0x07c00000
#define PCAP5_VC_SHIFT 22
#define PCAP5_CC_MASK 0xf8000000
#define PCAP5_CC_SHIFT 27
/* pmucapabilites_ext PMU rev >= 15 */
#define PCAPEXT_SR_SUPPORTED_MASK (1 << 1)
/* retention_ctl PMU rev >= 15 */
#define PMU_RCTL_MACPHY_DISABLE_MASK (1 << 26)
#define PMU_RCTL_LOGIC_DISABLE_MASK (1 << 27)
/* Core-ID values. */
#define BCMA_CORE_OOB_ROUTER 0x367 /* Out of band */
#define BCMA_CORE_4706_CHIPCOMMON 0x500
#define BCMA_CORE_NS_PCIEG2 0x501
#define BCMA_CORE_NS_DMA 0x502
#define BCMA_CORE_NS_SDIO3 0x503
#define BCMA_CORE_NS_USB20 0x504
#define BCMA_CORE_NS_USB30 0x505
#define BCMA_CORE_NS_A9JTAG 0x506
#define BCMA_CORE_NS_DDR23 0x507
#define BCMA_CORE_NS_ROM 0x508
#define BCMA_CORE_NS_NAND 0x509
#define BCMA_CORE_NS_QSPI 0x50A
#define BCMA_CORE_NS_CHIPCOMMON_B 0x50B
#define BCMA_CORE_4706_SOC_RAM 0x50E
#define BCMA_CORE_ARMCA9 0x510
#define BCMA_CORE_4706_MAC_GBIT 0x52D
#define BCMA_CORE_AMEMC 0x52E /* DDR1/2 memory controller core */
#define BCMA_CORE_ALTA 0x534 /* I2S core */
#define BCMA_CORE_4706_MAC_GBIT_COMMON 0x5DC
#define BCMA_CORE_DDR23_PHY 0x5DD
#define BCMA_CORE_INVALID 0x700
#define BCMA_CORE_CHIPCOMMON 0x800
#define BCMA_CORE_ILINE20 0x801
#define BCMA_CORE_SRAM 0x802
#define BCMA_CORE_SDRAM 0x803
#define BCMA_CORE_PCI 0x804
#define BCMA_CORE_MIPS 0x805
#define BCMA_CORE_ETHERNET 0x806
#define BCMA_CORE_V90 0x807
#define BCMA_CORE_USB11_HOSTDEV 0x808
#define BCMA_CORE_ADSL 0x809
#define BCMA_CORE_ILINE100 0x80A
#define BCMA_CORE_IPSEC 0x80B
#define BCMA_CORE_UTOPIA 0x80C
#define BCMA_CORE_PCMCIA 0x80D
#define BCMA_CORE_INTERNAL_MEM 0x80E
#define BCMA_CORE_MEMC_SDRAM 0x80F
#define BCMA_CORE_OFDM 0x810
#define BCMA_CORE_EXTIF 0x811
#define BCMA_CORE_80211 0x812
#define BCMA_CORE_PHY_A 0x813
#define BCMA_CORE_PHY_B 0x814
#define BCMA_CORE_PHY_G 0x815
#define BCMA_CORE_MIPS_3302 0x816
#define BCMA_CORE_USB11_HOST 0x817
#define BCMA_CORE_USB11_DEV 0x818
#define BCMA_CORE_USB20_HOST 0x819
#define BCMA_CORE_USB20_DEV 0x81A
#define BCMA_CORE_SDIO_HOST 0x81B
#define BCMA_CORE_ROBOSWITCH 0x81C
#define BCMA_CORE_PARA_ATA 0x81D
#define BCMA_CORE_SATA_XORDMA 0x81E
#define BCMA_CORE_ETHERNET_GBIT 0x81F
#define BCMA_CORE_PCIE 0x820
#define BCMA_CORE_PHY_N 0x821
#define BCMA_CORE_SRAM_CTL 0x822
#define BCMA_CORE_MINI_MACPHY 0x823
#define BCMA_CORE_ARM_1176 0x824
#define BCMA_CORE_ARM_7TDMI 0x825
#define BCMA_CORE_PHY_LP 0x826
#define BCMA_CORE_PMU 0x827
#define BCMA_CORE_PHY_SSN 0x828
#define BCMA_CORE_SDIO_DEV 0x829
#define BCMA_CORE_PHY_HT 0x82B
#define BCMA_CORE_MIPS_74K 0x82C
#define BCMA_CORE_MAC_GBIT 0x82D
#define BCMA_CORE_DDR12_MEM_CTL 0x82E
#define BCMA_CORE_PCIE_RC 0x82F /* PCIe Root Complex */
#define BCMA_CORE_OCP_OCP_BRIDGE 0x830
#define BCMA_CORE_SHARED_COMMON 0x831
#define BCMA_CORE_OCP_AHB_BRIDGE 0x832
#define BCMA_CORE_SPI_HOST 0x833
#define BCMA_CORE_I2S 0x834
#define BCMA_CORE_SDR_DDR1_MEM_CTL 0x835 /* SDR/DDR1 memory controller core */
#define BCMA_CORE_SHIM 0x837 /* SHIM component in ubus/6362 */
#define BCMA_CORE_PHY_AC 0x83B
#define BCMA_CORE_PCIE2 0x83C /* PCI Express Gen2 */
#define BCMA_CORE_USB30_DEV 0x83D
#define BCMA_CORE_GCI 0x840
#define BCMA_CORE_CMEM 0x846 /* CNDS DDR2/3 memory controller */
#define BCMA_CORE_ARM_CR4 0x83E
#define BCMA_CORE_ARM_CA7 0x847
#define BCMA_CORE_ARM_CM3 0x82A
#define BCMA_CORE_SYS_MEM 0x849
#define BCMA_CORE_DEFAULT 0xFFF
#define BCMA_MAX_NR_CORES 16
#define BCMA_CORE_SIZE 0x1000
/* clkstate */
#define CLK_NONE 0
#define CLK_SDONLY 1
#define CLK_PENDING 2
#define CLK_AVAIL 3
struct brcmwl_event_msg {
uint16_t version;
uint16_t flags;
uint32_t event_type;
uint32_t status;
uint32_t reason;
uint32_t auth_type;
uint32_t datalen;
struct ether_addr addr;
char ifname[IFNAMSIZ];
uint8_t ifidx;
uint8_t bsscfgidx;
} ;
struct brcmwl_ethhdr {
uint16_t subtype;
uint16_t length;
uint8_t version;
uint8_t oui[3];
#define BRCMWL_BRCM_OUI "\x00\x10\x18"
uint16_t usr_subtype;
#define BRCMWL_BRCM_SUBTYPE_EVENT 1
};
struct brcmwl_event {
struct ether_header ehdr;
#define BRCMWL_ETHERTYPE_LINK_CTL 0x886c
struct brcmwl_ethhdr hdr;
struct brcmwl_event_msg msg;
};
struct brcmwl_proto_bcdc_ctl {
int reqid;
char *buf;
size_t len;
int done;
TAILQ_ENTRY(brcmwl_proto_bcdc_ctl) next;
};
struct brcmwl_proto_bcdc_dcmd {
struct {
uint32_t cmd;
uint32_t len;
uint32_t flags;
#define BRCMWL_BCDC_DCMD_ERROR (1 << 0)
#define BRCMWL_BCDC_DCMD_GET (0 << 1)
#define BRCMWL_BCDC_DCMD_SET (1 << 1)
#define BRCMWL_BCDC_DCMD_IF_GET(x) (((x) >> 12) & 0xf)
#define BRCMWL_BCDC_DCMD_IF_SET(x) (((x) & 0xf) << 12)
#define BRCMWL_BCDC_DCMD_ID_GET(x) (((x) >> 16) & 0xffff)
#define BRCMWL_BCDC_DCMD_ID_SET(x) (((x) & 0xffff) << 16)
uint32_t status;
} hdr;
char buf[8192];
};
struct brcmwl_sdio_sdpcm_t {
uint32_t flags;
uint32_t trap_addr;
uint32_t assert_exp_addr;
uint32_t assert_file_addr;
uint32_t assert_line;
uint32_t console_addr;
uint32_t msgtrace_addr;
uint8_t tag[32];
uint32_t brpt_addr;
};
struct brcmwl_sdio_console_t {
uint32_t vcons_in;
uint32_t vcons_out;
uint32_t log_buf;
uint32_t log_bufsz;
uint32_t log_idx;
};
struct brcmwl_proto_bcdc_hdr {
uint8_t flags;
#define BRCMWL_BCDC_FLAG_PROTO_VER 2
#define BRCMWL_BCDC_FLAG_VER(x) (((x) & 0xf) << 4)
#define BRCMWL_BCDC_FLAG_SUM_GOOD (1 << 2) /* rx */
#define BRCMWL_BCDC_FLAG_SUM_NEEDED (1 << 3) /* tx */
uint8_t priority;
#define BRCMWL_BCDC_PRIORITY_MASK 0x7
uint8_t flags2;
#define BRCMWL_BCDC_FLAG2_IF_MASK 0xf
uint8_t data_offset;
};
struct brcmwl_sdio_hwhdr {
uint16_t frmlen;
uint16_t cksum;
};
struct brcmwl_sdio_hwexthdr {
uint16_t pktlen;
uint8_t res0;
uint8_t flags;
uint16_t res1;
uint16_t padlen;
};
struct brcmwl_sdio_swhdr {
uint8_t seqnr;
uint8_t chanflag; /* channel + flag */
#define BRCMWL_SDIO_SWHDR_CHANNEL_CONTROL 0x00
#define BRCMWL_SDIO_SWHDR_CHANNEL_EVENT 0x01
#define BRCMWL_SDIO_SWHDR_CHANNEL_DATA 0x02
#define BRCMWL_SDIO_SWHDR_CHANNEL_GLOM 0x03
#define BRCMWL_SDIO_SWHDR_CHANNEL_TEST 0x0F
#define BRCMWL_SDIO_SWHDR_CHANNEL_MASK 0x0F
uint8_t nextlen;
uint8_t dataoff;
uint8_t flowctl;
uint8_t maxseqnr;
uint16_t res0;
};
/**
* struct brcmwl_core - core related information.
*
* @id: core identifier.
* @rev: core revision.
* @base: base address of core register space.
*/
struct brcmwl_core_t {
uint16_t id;
uint16_t rev;
uint32_t base;
};
struct brcmwl_chip_t {
uint32_t chip;
uint32_t chiprev;
uint32_t cc_caps;
uint32_t cc_caps_ext;
uint32_t pmucaps;
uint32_t pmurev;
uint32_t rambase;
uint32_t ramsize;
uint32_t srsize;
char name[FWCHAR_LEN];
};
struct brcmwl_chip_priv_t {
struct brcmwl_chip_t pub;
////const struct brcmwl_buscore_ops *ops;
///void *ctx;
//// assured first core is chipcommon, second core is buscore
//lst struct list_head cores;
uint16_t num_cores;
///bool (*iscoreup)(struct brcmwl_core_priv *core);
//void (*coredisable)(struct brcmwl_core_priv *core, u32 prereset, u32 reset);
///void (*resetcore)(struct brcmwl_core_priv *core, u32 prereset, u32 reset, u32 postreset);
};
struct brcmwl_core_priv_t {
struct brcmwl_core_t pub;
uint32_t wrapbase;
//lst struct list_head coreLst;
struct brcmwl_chip_priv_t *chip;
};
struct sb_socramregs_t {
uint32_t coreinfo;
uint32_t bwalloc;
uint32_t extracoreinfo;
uint32_t biststat;
uint32_t bankidx;
uint32_t standbyctrl;
uint32_t errlogstatus; /* rev 6 */
uint32_t errlogaddr; /* rev 6 */
/* used for patching rev 3 & 5 */
uint32_t cambankidx;
uint32_t cambankstandbyctrl;
uint32_t cambankpatchctrl;
uint32_t cambankpatchtblbaseaddr;
uint32_t cambankcmdreg;
uint32_t cambankdatareg;
uint32_t cambankmaskreg;
uint32_t PAD0[1];
uint32_t bankinfo; /* corev 8 */
uint32_t bankpda;
uint32_t PAD1[14];
uint32_t extmemconfig;
uint32_t extmemparitycsr;
uint32_t extmemparityerrdata;
uint32_t extmemparityerrcnt;
uint32_t extmemwrctrlandsize;
uint32_t PAD2[84];
uint32_t workaround;
uint32_t pwrctl; /* corerev >= 2 */
uint32_t PAD3[133];
uint32_t sr_control; /* corerev >= 15 */
uint32_t sr_status; /* corerev >= 15 */
uint32_t sr_address; /* corerev >= 15 */
uint32_t sr_data; /* corerev >= 15 */
};
struct bcm_chipcregs_t {
uint32_t chipid; /* 0x0 */
uint32_t capabilities;
uint32_t corecontrol; /* corerev >= 1 */
uint32_t bist;
/* OTP */
uint32_t otpstatus; /* 0x10, corerev >= 10 */
uint32_t otpcontrol;
uint32_t otpprog;
uint32_t otplayout; /* corerev >= 23 */
/* Interrupt control */
uint32_t intstatus; /* 0x20 */
uint32_t intmask;
/* Chip specific regs */
uint32_t chipcontrol; /* 0x28, rev >= 11 */
uint32_t chipstatus; /* 0x2c, rev >= 11 */
/* Jtag Master */
uint32_t jtagcmd; /* 0x30, rev >= 10 */
uint32_t jtagir;
uint32_t jtagdr;
uint32_t jtagctrl;
/* serial flash interface registers */
uint32_t flashcontrol; /* 0x40 */
uint32_t flashaddress;
uint32_t flashdata;
uint32_t PAD1[1];
/* Silicon backplane configuration broadcast control */
uint32_t broadcastaddress; /* 0x50 */
uint32_t broadcastdata;
/* gpio - cleared only by power-on-reset */
uint32_t gpiopullup; /* 0x58, corerev >= 20 */
uint32_t gpiopulldown; /* 0x5c, corerev >= 20 */
uint32_t gpioin; /* 0x60 */
uint32_t gpioout; /* 0x64 */
uint32_t gpioouten; /* 0x68 */
uint32_t gpiocontrol; /* 0x6C */
uint32_t gpiointpolarity; /* 0x70 */
uint32_t gpiointmask; /* 0x74 */
/* GPIO events corerev >= 11 */
uint32_t gpioevent;
uint32_t gpioeventintmask;
/* Watchdog timer */
uint32_t watchdog; /* 0x80 */
/* GPIO events corerev >= 11 */
uint32_t gpioeventintpolarity;
/* GPIO based LED powersave registers corerev >= 16 */
uint32_t gpiotimerval; /* 0x88 */
uint32_t gpiotimeroutmask;
/* clock control */
uint32_t clockcontrol_n; /* 0x90 */
uint32_t clockcontrol_sb; /* aka m0 */
uint32_t clockcontrol_pci; /* aka m1 */
uint32_t clockcontrol_m2; /* mii/uart/mipsref */
uint32_t clockcontrol_m3; /* cpu */
uint32_t clkdiv; /* corerev >= 3 */
uint32_t gpiodebugsel; /* corerev >= 28 */
uint32_t capabilities_ext; /* 0xac */
/* pll delay registers (corerev >= 4) */
uint32_t pll_on_delay; /* 0xb0 */
uint32_t fref_sel_delay;
uint32_t slow_clk_ctl; /* 5 < corerev < 10 */
uint32_t PAD2;
/* Instaclock registers (corerev >= 10) */
uint32_t system_clk_ctl; /* 0xc0 */
uint32_t clkstatestretch;
uint32_t PAD3[2];
/* Indirect backplane access (corerev >= 22) */
uint32_t bp_addrlow; /* 0xd0 */
uint32_t bp_addrhigh;
uint32_t bp_data;
uint32_t PAD4;
uint32_t bp_indaccess;
uint32_t PAD5[3];
/* More clock dividers (corerev >= 32) */
uint32_t clkdiv2;
uint32_t PAD6[2];
/* In AI chips, pointer to erom */
uint32_t eromptr; /* 0xfc */
/* ExtBus control registers (corerev >= 3) */
uint32_t pcmcia_config; /* 0x100 */
uint32_t pcmcia_memwait;
uint32_t pcmcia_attrwait;
uint32_t pcmcia_iowait;
uint32_t ide_config;
uint32_t ide_memwait;
uint32_t ide_attrwait;
uint32_t ide_iowait;
uint32_t prog_config;
uint32_t prog_waitcount;
uint32_t flash_config;
uint32_t flash_waitcount;
uint32_t SECI_config; /* 0x130 SECI configuration */
uint32_t PAD7[3];
/* Enhanced Coexistence Interface (ECI) registers (corerev >= 21) */
uint32_t eci_output; /* 0x140 */
uint32_t eci_control;
uint32_t eci_inputlo;
uint32_t eci_inputmi;
uint32_t eci_inputhi;
uint32_t eci_inputintpolaritylo;
uint32_t eci_inputintpolaritymi;
uint32_t eci_inputintpolarityhi;
uint32_t eci_intmasklo;
uint32_t eci_intmaskmi;
uint32_t eci_intmaskhi;
uint32_t eci_eventlo;
uint32_t eci_eventmi;
uint32_t eci_eventhi;
uint32_t eci_eventmasklo;
uint32_t eci_eventmaskmi;
uint32_t eci_eventmaskhi;
uint32_t PAD8[3];
/* SROM interface (corerev >= 32) */
uint32_t sromcontrol; /* 0x190 */
uint32_t sromaddress;
uint32_t sromdata;
uint32_t PAD9[17];
/* Clock control and hardware workarounds (corerev >= 20) */
uint32_t clk_ctl_st; /* 0x1e0 */
uint32_t hw_war;
uint32_t PAD10[70];
/* UARTs */
uint8_t uart0data; /* 0x300 */
uint8_t uart0imr;
uint8_t uart0fcr;
uint8_t uart0lcr;
uint8_t uart0mcr;
uint8_t uart0lsr;
uint8_t uart0msr;
uint8_t uart0scratch;
uint8_t PAD11[248]; /* corerev >= 1 */
uint8_t uart1data; /* 0x400 */
uint8_t uart1imr;
uint8_t uart1fcr;
uint8_t uart1lcr;
uint8_t uart1mcr;
uint8_t uart1lsr;
uint8_t uart1msr;
uint8_t uart1scratch;
uint32_t PAD12[62];
/* save/restore, corerev >= 48 */
uint32_t sr_capability; /* 0x500 */
uint32_t sr_control0; /* 0x504 */
uint32_t sr_control1; /* 0x508 */
uint32_t gpio_control; /* 0x50C */
uint32_t PAD13[60];
/* PMU registers (corerev >= 20) */
uint32_t pmucontrol; /* 0x600 */
uint32_t pmucapabilities;
uint32_t pmustatus;
uint32_t res_state;
uint32_t res_pending;
uint32_t pmutimer;
uint32_t min_res_mask;
uint32_t max_res_mask;
uint32_t res_table_sel;
uint32_t res_dep_mask;
uint32_t res_updn_timer;
uint32_t res_timer;
uint32_t clkstretch;
uint32_t pmuwatchdog;
uint32_t gpiosel; /* 0x638, rev >= 1 */
uint32_t gpioenable; /* 0x63c, rev >= 1 */
uint32_t res_req_timer_sel;
uint32_t res_req_timer;
uint32_t res_req_mask;
uint32_t pmucapabilities_ext; /* 0x64c, pmurev >=15 */
uint32_t chipcontrol_addr; /* 0x650 */
uint32_t chipcontrol_data; /* 0x654 */
uint32_t regcontrol_addr;
uint32_t regcontrol_data;
uint32_t pllcontrol_addr;
uint32_t pllcontrol_data;
uint32_t pmustrapopt; /* 0x668, corerev >= 28 */
uint32_t pmu_xtalfreq; /* 0x66C, pmurev >= 10 */
uint32_t retention_ctl; /* 0x670, pmurev >= 15 */
uint32_t PAD14[3];
uint32_t retention_grpidx; /* 0x680 */
uint32_t retention_grpctl; /* 0x684 */
uint32_t PAD15[94];
uint16_t sromotp[768];
};
/* sdio core registers */
struct sdpcmd_regs_t {
uint32_t corecontrol; /* 0x00, rev8 */
uint32_t corestatus; /* rev8 */
uint32_t PAD0[1];
uint32_t biststatus; /* rev8 */
/* PCMCIA access */
uint16_t pcmciamesportaladdr; /* 0x010, rev8 */
uint16_t PAD1[1];
uint16_t pcmciamesportalmask; /* rev8 */
uint16_t PAD2[1];
uint16_t pcmciawrframebc; /* rev8 */
uint16_t PAD3[1];
uint16_t pcmciaunderflowtimer; /* rev8 */
uint16_t PAD4[1];
/* interrupt */
uint32_t intstatus; /* 0x020, rev8 */
uint32_t hostintmask; /* rev8 */
uint32_t intmask; /* rev8 */
uint32_t sbintstatus; /* rev8 */
uint32_t sbintmask; /* rev8 */
uint32_t funcintmask; /* rev4 */
uint32_t PAD5[2];
uint32_t tosbmailbox; /* 0x040, rev8 */
uint32_t tohostmailbox; /* rev8 */
uint32_t tosbmailboxdata; /* rev8 */
uint32_t tohostmailboxdata; /* rev8 */
/* synchronized access to registers in SDIO clock domain */
uint32_t sdioaccess; /* 0x050, rev8 */
uint32_t PAD6[3];
/* PCMCIA frame control */
uint8_t pcmciaframectrl; /* 0x060, rev8 */
uint8_t PAD7[3];
uint8_t pcmciawatermark; /* rev8 */
uint8_t PAD8[155];
/* interrupt batching control */
uint32_t intrcvlazy; /* 0x100, rev8 */
uint32_t PAD9[3];
/* counters */
uint32_t cmd52rd; /* 0x110, rev8 */
uint32_t cmd52wr; /* rev8 */
uint32_t cmd53rd; /* rev8 */
uint32_t cmd53wr; /* rev8 */
uint32_t abort; /* rev8 */
uint32_t datacrcerror; /* rev8 */
uint32_t rdoutofsync; /* rev8 */
uint32_t wroutofsync; /* rev8 */
uint32_t writebusy; /* rev8 */
uint32_t readwait; /* rev8 */
uint32_t readterm; /* rev8 */
uint32_t writeterm; /* rev8 */
uint32_t PAD10[40];
uint32_t clockctlstatus; /* rev8 */
uint32_t PAD11[7];
uint32_t PAD12[128]; /* DMA engines */
/* SDIO/PCMCIA CIS region */
char cis13[512]; /* 0x400-0x5ff, rev6 */
/* PCMCIA function control registers */
char pcmciafcr[256]; /* 0x600-6ff, rev6 */
uint16_t PAD14[55];
/* PCMCIA backplane access */
uint16_t backplanecsr; /* 0x76E, rev6 */
uint16_t backplaneaddr0; /* rev6 */
uint16_t backplaneaddr1; /* rev6 */
uint16_t backplaneaddr2; /* rev6 */
uint16_t backplaneaddr3; /* rev6 */
uint16_t backplanedata0; /* rev6 */
uint16_t backplanedata1; /* rev6 */
uint16_t backplanedata2; /* rev6 */
uint16_t backplanedata3; /* rev6 */
uint16_t PAD15[31];
/* sprom "size" & "blank" info */
uint16_t spromstatus; /* 0x7BE, rev2 */
uint32_t PAD16[464];
uint16_t PAD17[0x80];
};
#define SD_REG(field) \
(offsetof(struct sdpcmd_regs_t, field))
/* Current protocol version */
#define SDPCM_PROT_VERSION 4
/* tosbmailboxdata */
#define SMB_DATA_VERSION_SHIFT 16 /* host protocol version */
#define CORE_CC_REG(base, field) (base + offsetof(struct bcm_chipcregs_t, field))
typedef enum {
BWN_PHY_BAND_2G = 0,
BWN_PHY_BAND_5G_LO = 1,
BWN_PHY_BAND_5G_MI = 2,
BWN_PHY_BAND_5G_HI = 3
} bwn_phy_band_t;
typedef enum {
BWN_BAND_2G,
BWN_BAND_5G,
} bwn_band_t;
typedef enum {
BWN_CHAN_TYPE_20,
BWN_CHAN_TYPE_20_HT,
BWN_CHAN_TYPE_40_HT_U,
BWN_CHAN_TYPE_40_HT_D,
} bwn_chan_type_t;
struct bwn_rate {
uint16_t rateid;
uint32_t flags;
};
#define BWN_ANT0 0
#define BWN_ANT1 1
#define BWN_ANTAUTO0 2
#define BWN_ANTAUTO1 3
#define BWN_ANT2 4
#define BWN_ANT3 8
#define BWN_ANTAUTO BWN_ANTAUTO0
#define BWN_ANT_DEFAULT BWN_ANTAUTO
#define BWN_TX_SLOTS_PER_FRAME 2
struct bwn_channel {
unsigned freq;
unsigned ieee;
unsigned maxTxPow;
};
struct bwn_channelinfo {
struct bwn_channel channels[IEEE80211_CHAN_MAX];
unsigned nchannels;
};
struct bwn_bbatt {
uint8_t att;
};
struct bwn_bbatt_list {
const struct bwn_bbatt *array;
uint8_t len;
uint8_t min;
uint8_t max;
};
struct bwn_rfatt {
uint8_t att;
int padmix;
};
struct bwn_rfatt_list {
const struct bwn_rfatt *array;
uint8_t len;
uint8_t min;
uint8_t max;
};
#define BWN_DC_LT_SIZE 32
struct bwn_loctl {
int8_t i;
int8_t q;
};
typedef enum {
BWN_TXPWR_RES_NEED_ADJUST,
BWN_TXPWR_RES_DONE,
} bwn_txpwr_result_t;
struct bwn_lo_calib {
struct bwn_bbatt bbatt;
struct bwn_rfatt rfatt;
struct bwn_loctl ctl;
unsigned long calib_time;
TAILQ_ENTRY(bwn_lo_calib) list;
};
struct bwn_rxhdr4 {
uint16_t frame_len;
uint8_t pad1[2];
uint16_t phy_status0;
union {
struct {
uint8_t rssi;
uint8_t sig_qual;
} __packed abg;
struct {
int8_t power0;
int8_t power1;
} __packed n;
} __packed phy;
union {
struct {
int8_t power2;
uint8_t pad;
} __packed n;
struct {
uint8_t pad;
int8_t ht_power0;
} __packed ht;
uint16_t phy_status2;
} __packed ps2;
union {
struct {
uint16_t phy_status3;
} __packed lp;
struct {
int8_t phy_ht_power1;
int8_t phy_ht_power2;
} __packed ht;
} __packed ps3;
union {
struct {
uint32_t mac_status;
uint16_t mac_time;
uint16_t channel;
} __packed r351;
struct {
uint16_t phy_status4;
uint16_t phy_status5;
uint32_t mac_status;
uint16_t mac_time;
uint16_t channel;
} __packed r598;
} __packed ps4;
} __packed;
struct bwn_txstatus {
uint16_t cookie;
uint16_t seq;
uint8_t phy_stat;
uint8_t framecnt;
uint8_t rtscnt;
uint8_t sreason;
uint8_t pm;
uint8_t im;
uint8_t ampdu;
uint8_t ack;
};
#define BWN_TXCTL_PA3DB 0x40
#define BWN_TXCTL_PA2DB 0x20
#define BWN_TXCTL_TXMIX 0x10
struct bwn_txpwr_loctl {
struct bwn_rfatt_list rfatt;
struct bwn_bbatt_list bbatt;
uint16_t dc_lt[BWN_DC_LT_SIZE];
TAILQ_HEAD(, bwn_lo_calib) calib_list;
unsigned long pwr_vec_read_time;
unsigned long txctl_measured_time;
uint8_t tx_bias;
uint8_t tx_magn;
uint64_t power_vector;
};
#define BWN_OFDMTAB_DIR_UNKNOWN 0
#define BWN_OFDMTAB_DIR_READ 1
#define BWN_OFDMTAB_DIR_WRITE 2
struct bwn_phy_g {
unsigned pg_flags;
#define BWN_PHY_G_FLAG_TSSITABLE_ALLOC (1 << 0)
#define BWN_PHY_G_FLAG_RADIOCTX_VALID (1 << 1)
int pg_aci_enable;
int pg_aci_wlan_automatic;
int pg_aci_hw_rssi;
int pg_rf_on;
uint16_t pg_radioctx_over;
uint16_t pg_radioctx_overval;
uint16_t pg_minlowsig[2];
uint16_t pg_minlowsigpos[2];
int8_t *pg_tssi2dbm;
int pg_idletssi;
int pg_curtssi;
uint8_t pg_avgtssi;
struct bwn_bbatt pg_bbatt;
struct bwn_rfatt pg_rfatt;
uint8_t pg_txctl;
int pg_bbatt_delta;
int pg_rfatt_delta;
struct bwn_txpwr_loctl pg_loctl;
int16_t pg_max_lb_gain;
int16_t pg_trsw_rx_gain;
int16_t pg_lna_lod_gain;
int16_t pg_lna_gain;
int16_t pg_pga_gain;
int pg_immode;
#define BWN_INTERFSTACK_SIZE 26
uint32_t pg_interfstack[BWN_INTERFSTACK_SIZE];
int16_t pg_nrssi[2];
int32_t pg_nrssi_slope;
int8_t pg_nrssi_lt[64];
uint16_t pg_lofcal;
uint16_t pg_initval;
uint16_t pg_ofdmtab_addr;
unsigned pg_ofdmtab_dir;
};
#define BWN_IMMODE_NONE 0
#define BWN_IMMODE_NONWLAN 1
#define BWN_IMMODE_MANUAL 2
#define BWN_IMMODE_AUTO 3
#define BWN_PHYLP_TXPCTL_UNKNOWN 0
#define BWN_PHYLP_TXPCTL_OFF 1
#define BWN_PHYLP_TXPCTL_ON_SW 2
#define BWN_PHYLP_TXPCTL_ON_HW 3
struct bwn_phy_lp {
uint8_t plp_chan;
uint8_t plp_chanfullcal;
int32_t plp_antenna;
uint8_t plp_txpctlmode;
uint8_t plp_txisoband_h;
uint8_t plp_txisoband_m;
uint8_t plp_txisoband_l;
uint8_t plp_rxpwroffset;
int8_t plp_txpwridx;
uint16_t plp_tssiidx;
uint16_t plp_tssinpt;
uint8_t plp_rssivf;
uint8_t plp_rssivc;
uint8_t plp_rssigs;
uint8_t plp_rccap;
uint8_t plp_bxarch;
uint8_t plp_crsusr_off;
uint8_t plp_crssys_off;
uint32_t plp_div;
int32_t plp_tonefreq;
uint16_t plp_digfilt[9];
};
/* for LP */
struct bwn_txgain {
uint16_t tg_gm;
uint16_t tg_pga;
uint16_t tg_pad;
uint16_t tg_dac;
};
struct bwn_rxcompco {
uint8_t rc_chan;
int8_t rc_c1;
int8_t rc_c0;
};
struct bwn_phy_lp_iq_est {
uint32_t ie_iqprod;
uint32_t ie_ipwr;
uint32_t ie_qpwr;
};
struct bwn_txgain_entry {
uint8_t te_gm;
uint8_t te_pga;
uint8_t te_pad;
uint8_t te_dac;
uint8_t te_bbmult;
};
/* only for LP PHY */
struct bwn_stxtable {
uint16_t st_phyoffset;
uint16_t st_physhift;
uint16_t st_rfaddr;
uint16_t st_rfshift;
uint16_t st_mask;
};
struct bwn_b206x_chan {
uint8_t bc_chan;
uint16_t bc_freq;
const uint8_t *bc_data;
};
struct bwn_b206x_rfinit_entry {
uint16_t br_offset;
uint16_t br_valuea;
uint16_t br_valueg;
uint8_t br_flags;
};
struct bwn_phy_n;
struct bwn_phy {
uint8_t type;
uint8_t rev;
uint8_t analog;
int supports_2ghz;
int supports_5ghz;
int gmode;
struct bwn_phy_g phy_g;
struct bwn_phy_lp phy_lp;
/*
* I'd like the newer PHY code to not hide in the top-level
* structs..
*/
struct bwn_phy_n *phy_n;
uint16_t rf_manuf;
uint16_t rf_ver;
uint8_t rf_rev;
int rf_on;
int phy_do_full_init;
int txpower;
int hwpctl;
unsigned long nexttime;
unsigned int chan;
int txerrors;
int (*attach)(struct bwn_mac *);
void (*detach)(struct bwn_mac *);
int (*prepare_hw)(struct bwn_mac *);
void (*init_pre)(struct bwn_mac *);
int (*init)(struct bwn_mac *);
void (*exit)(struct bwn_mac *);
uint16_t (*phy_read)(struct bwn_mac *, uint16_t);
void (*phy_write)(struct bwn_mac *, uint16_t,
uint16_t);
void (*phy_maskset)(struct bwn_mac *,
uint16_t, uint16_t, uint16_t);
uint16_t (*rf_read)(struct bwn_mac *, uint16_t);
void (*rf_write)(struct bwn_mac *, uint16_t,
uint16_t);
int (*use_hwpctl)(struct bwn_mac *);
void (*rf_onoff)(struct bwn_mac *, int);
void (*switch_analog)(struct bwn_mac *, int);
int (*switch_channel)(struct bwn_mac *,
unsigned int);
uint32_t (*get_default_chan)(struct bwn_mac *);
void (*set_antenna)(struct bwn_mac *, int);
int (*set_im)(struct bwn_mac *, int);
bwn_txpwr_result_t (*recalc_txpwr)(struct bwn_mac *, int);
void (*set_txpwr)(struct bwn_mac *);
void (*task_15s)(struct bwn_mac *);
void (*task_60s)(struct bwn_mac *);
};
struct bwn_chan_band {
uint32_t flags;
uint8_t nchan;
#define BWN_MAX_CHAN_PER_BAND 14
uint8_t chan[BWN_MAX_CHAN_PER_BAND];
};
#define BWN_NR_WMEPARAMS 16
enum {
BWN_WMEPARAM_TXOP = 0,
BWN_WMEPARAM_CWMIN,
BWN_WMEPARAM_CWMAX,
BWN_WMEPARAM_CWCUR,
BWN_WMEPARAM_AIFS,
BWN_WMEPARAM_BSLOTS,
BWN_WMEPARAM_REGGAP,
BWN_WMEPARAM_STATUS,
};
#define BWN_WME_PARAMS(queue) \
(BWN_SHARED_EDCFQ + (BWN_NR_WMEPARAMS * sizeof(uint16_t) * (queue)))
#define BWN_WME_BACKGROUND BWN_WME_PARAMS(0)
#define BWN_WME_BESTEFFORT BWN_WME_PARAMS(1)
#define BWN_WME_VIDEO BWN_WME_PARAMS(2)
#define BWN_WME_VOICE BWN_WME_PARAMS(3)
/*
* Radio capture format.
*/
#define BWN_RX_RADIOTAP_PRESENT ( \
(1 << IEEE80211_RADIOTAP_TSFT) | \
(1 << IEEE80211_RADIOTAP_FLAGS) | \
(1 << IEEE80211_RADIOTAP_RATE) | \
(1 << IEEE80211_RADIOTAP_CHANNEL) | \
(1 << IEEE80211_RADIOTAP_ANTENNA) | \
(1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL) | \
(1 << IEEE80211_RADIOTAP_DBM_ANTNOISE) | \
0)
struct bwn_rx_radiotap_header {
struct ieee80211_radiotap_header wr_ihdr;
uint64_t wr_tsf;
u_int8_t wr_flags;
u_int8_t wr_rate;
u_int16_t wr_chan_freq;
u_int16_t wr_chan_flags;
int8_t wr_antsignal;
int8_t wr_antnoise;
u_int8_t wr_antenna;
};
#define BWN_TX_RADIOTAP_PRESENT ( \
(1 << IEEE80211_RADIOTAP_FLAGS) | \
(1 << IEEE80211_RADIOTAP_RATE) | \
(1 << IEEE80211_RADIOTAP_CHANNEL) | \
(1 << IEEE80211_RADIOTAP_DBM_TX_POWER) | \
(1 << IEEE80211_RADIOTAP_ANTENNA) | \
0)
struct bwn_tx_radiotap_header {
struct ieee80211_radiotap_header wt_ihdr;
u_int8_t wt_flags;
u_int8_t wt_rate;
u_int16_t wt_chan_freq;
u_int16_t wt_chan_flags;
u_int8_t wt_txpower;
u_int8_t wt_antenna;
};
struct bwn_stats {
int32_t rtsfail;
int32_t rts;
int32_t link_noise;
};
/* Noise Calculation (Link Quality) */
struct bwn_noise {
uint8_t noi_running;
uint8_t noi_nsamples;
int8_t noi_samples[8][4];
};
#define BWN_DMA_30BIT 30
#define BWN_DMA_32BIT 32
#define BWN_DMA_64BIT 64
struct bwn_dmadesc_meta {
bus_dmamap_t mt_dmap;
bus_addr_t mt_paddr;
struct mbuf *mt_m;
struct ieee80211_node *mt_ni;
uint8_t mt_txtype;
#define BWN_DMADESC_METATYPE_HEADER 0
#define BWN_DMADESC_METATYPE_BODY 1
uint8_t mt_islast;
};
#define BWN_DMAINTR_FATALMASK \
((1 << 10) | (1 << 11) | (1 << 12) | (1 << 14) | (1 << 15))
#define BWN_DMAINTR_NONFATALMASK (1 << 13)
#define BWN_DMAINTR_RX_DONE (1 << 16)
#define BWN_DMA32_DCTL_BYTECNT 0x00001fff
#define BWN_DMA32_DCTL_ADDREXT_MASK 0x00030000
#define BWN_DMA32_DCTL_ADDREXT_SHIFT 16
#define BWN_DMA32_DCTL_DTABLEEND 0x10000000
#define BWN_DMA32_DCTL_IRQ 0x20000000
#define BWN_DMA32_DCTL_FRAMEEND 0x40000000
#define BWN_DMA32_DCTL_FRAMESTART 0x80000000
struct bwn_dmadesc32 {
uint32_t control;
uint32_t address;
} __packed;
#define BWN_DMA64_DCTL0_DTABLEEND 0x10000000
#define BWN_DMA64_DCTL0_IRQ 0x20000000
#define BWN_DMA64_DCTL0_FRAMEEND 0x40000000
#define BWN_DMA64_DCTL0_FRAMESTART 0x80000000
#define BWN_DMA64_DCTL1_BYTECNT 0x00001fff
#define BWN_DMA64_DCTL1_ADDREXT_MASK 0x00030000
#define BWN_DMA64_DCTL1_ADDREXT_SHIFT 16
struct bwn_dmadesc64 {
uint32_t control0;
uint32_t control1;
uint32_t address_low;
uint32_t address_high;
} __packed;
struct bwn_dmadesc_generic {
union {
struct bwn_dmadesc32 dma32;
struct bwn_dmadesc64 dma64;
} __packed dma;
} __packed;
struct bwn_dma_ring;
struct bwn_dma_ring {
struct bwn_mac *dr_mac;
const struct bwn_dma_ops *dr_ops;
struct bwn_dmadesc_meta *dr_meta;
void *dr_txhdr_cache;
bus_dma_tag_t dr_ring_dtag;
bus_dma_tag_t dr_txring_dtag;
bus_dmamap_t dr_spare_dmap; /* only for RX */
bus_dmamap_t dr_ring_dmap;
bus_addr_t dr_txring_paddr;
void *dr_ring_descbase;
bus_addr_t dr_ring_dmabase;
int dr_numslots;
int dr_usedslot;
int dr_curslot;
uint32_t dr_frameoffset;
uint16_t dr_rx_bufsize;
uint16_t dr_base;
int dr_index;
uint8_t dr_tx;
uint8_t dr_stop;
int dr_type;
void (*getdesc)(struct bwn_dma_ring *,
int, struct bwn_dmadesc_generic **,
struct bwn_dmadesc_meta **);
void (*setdesc)(struct bwn_dma_ring *,
struct bwn_dmadesc_generic *,
bus_addr_t, uint16_t, int, int,
int);
void (*start_transfer)(struct bwn_dma_ring *,
int);
void (*suspend)(struct bwn_dma_ring *);
void (*resume)(struct bwn_dma_ring *);
int (*get_curslot)(struct bwn_dma_ring *);
void (*set_curslot)(struct bwn_dma_ring *,
int);
};
struct bwn_dma {
int dmatype;
bus_dma_tag_t parent_dtag;
bus_dma_tag_t rxbuf_dtag;
bus_dma_tag_t txbuf_dtag;
struct bwn_dma_ring *wme[5];
struct bwn_dma_ring *mcast;
struct bwn_dma_ring *rx;
uint64_t lastseq; /* XXX FIXME */
};
struct bwn_pio_rxqueue {
struct bwn_mac *prq_mac;
uint16_t prq_base;
uint8_t prq_rev;
};
struct bwn_pio_txqueue;
struct bwn_pio_txpkt {
struct bwn_pio_txqueue *tp_queue;
struct ieee80211_node *tp_ni;
struct mbuf *tp_m;
uint8_t tp_index;
TAILQ_ENTRY(bwn_pio_txpkt) tp_list;
};
#define BWN_PIO_MAX_TXPACKETS 32
struct bwn_pio_txqueue {
uint16_t tq_base;
uint16_t tq_size;
uint16_t tq_used;
uint16_t tq_free;
uint8_t tq_index;
struct bwn_pio_txpkt tq_pkts[BWN_PIO_MAX_TXPACKETS];
TAILQ_HEAD(, bwn_pio_txpkt) tq_pktlist;
};
struct bwn_pio {
struct bwn_pio_txqueue wme[5];
struct bwn_pio_txqueue mcast;
struct bwn_pio_rxqueue rx;
};
struct bwn_plcp4 {
union {
uint32_t data;
uint8_t raw[4];
} __packed o;
} __packed;
struct bwn_plcp6 {
union {
uint32_t data;
uint8_t raw[6];
} __packed o;
} __packed;
struct bwn_txhdr {
uint32_t macctl;
uint8_t macfc[2];
uint16_t tx_festime;
uint16_t phyctl;
uint16_t phyctl_1;
uint16_t phyctl_1fb;
uint16_t phyctl_1rts;
uint16_t phyctl_1rtsfb;
uint8_t phyrate;
uint8_t phyrate_rts;
uint8_t eftypes; /* extra frame types */
uint8_t chan;
uint8_t iv[16];
uint8_t addr1[IEEE80211_ADDR_LEN];
uint16_t tx_festime_fb;
struct bwn_plcp6 rts_plcp_fb;
uint16_t rts_dur_fb;
struct bwn_plcp6 plcp_fb;
uint16_t dur_fb;
uint16_t mimo_modelen;
uint16_t mimo_ratelen_fb;
uint32_t timeout;
union {
/* format <= r351 */
struct {
uint8_t pad0[2];
uint16_t cookie;
uint16_t tx_status;
struct bwn_plcp6 rts_plcp;
uint8_t rts_frame[16];
uint8_t pad1[2];
struct bwn_plcp6 plcp;
} __packed r351;
/* format > r410 < r598 */
struct {
uint16_t mimo_antenna;
uint16_t preload_size;
uint8_t pad0[2];
uint16_t cookie;
uint16_t tx_status;
struct bwn_plcp6 rts_plcp;
uint8_t rts_frame[16];
uint8_t pad1[2];
struct bwn_plcp6 plcp;
} __packed r410;
struct {
uint16_t mimo_antenna;
uint16_t preload_size;
uint8_t pad0[2];
uint16_t cookie;
uint16_t tx_status;
uint16_t max_n_mpdus;
uint16_t max_a_bytes_mrt;
uint16_t max_a_bytes_fbr;
uint16_t min_m_bytes;
struct bwn_plcp6 rts_plcp;
uint8_t rts_frame[16];
uint8_t pad1[2];
struct bwn_plcp6 plcp;
} __packed r598;
} __packed body;
} __packed;
#define BWN_FWTYPE_UCODE 'u'
#define BWN_FWTYPE_PCM 'p'
#define BWN_FWTYPE_IV 'i'
struct bwn_fwhdr {
uint8_t type;
uint8_t ver;
uint8_t pad[2];
uint32_t size;
} __packed;
#define BWN_FWINITVALS_OFFSET_MASK 0x7fff
#define BWN_FWINITVALS_32BIT 0x8000
struct bwn_fwinitvals {
uint16_t offset_size;
union {
uint16_t d16;
uint32_t d32;
} __packed data;
} __packed;
enum bwn_fw_hdr_format {
BWN_FW_HDR_598,
BWN_FW_HDR_410,
BWN_FW_HDR_351,
};
enum bwn_fwtype {
BWN_FWTYPE_DEFAULT,
BWN_FWTYPE_OPENSOURCE,
BWN_NR_FWTYPES,
};
struct bwn_fwfile {
const char *filename;
const struct firmware *fw;
enum bwn_fwtype type;
};
struct bwn_key {
void *keyconf;
uint8_t algorithm;
};
struct bwn_fw {
struct bwn_fwfile bin;
struct bwn_fwfile nvram;
struct bwn_fwfile ucode;
struct bwn_fwfile pcm;
struct bwn_fwfile initvals;
struct bwn_fwfile initvals_band;
enum bwn_fw_hdr_format fw_hdr_format;
uint16_t rev;
uint16_t patch;
uint8_t opensource;
uint8_t no_pcmfile;
};
struct bwn_lo_g_sm {
int curstate;
int nmeasure;
int multipler;
uint16_t feedth;
struct bwn_loctl loctl;
};
struct bwn_lo_g_value {
uint8_t old_channel;
uint16_t phy_lomask;
uint16_t phy_extg;
uint16_t phy_dacctl_hwpctl;
uint16_t phy_dacctl;
uint16_t phy_hpwr_tssictl;
uint16_t phy_analogover;
uint16_t phy_analogoverval;
uint16_t phy_rfover;
uint16_t phy_rfoverval;
uint16_t phy_classctl;
uint16_t phy_crs0;
uint16_t phy_pgactl;
uint16_t phy_syncctl;
uint16_t phy_cck0;
uint16_t phy_cck1;
uint16_t phy_cck2;
uint16_t phy_cck3;
uint16_t phy_cck4;
uint16_t reg0;
uint16_t reg1;
uint16_t rf0;
uint16_t rf1;
uint16_t rf2;
};
#define BWN_LED_MAX 4
#define BWN_LED_EVENT_NONE -1
#define BWN_LED_EVENT_POLL 0
#define BWN_LED_EVENT_TX 1
#define BWN_LED_EVENT_RX 2
#define BWN_LED_SLOWDOWN(dur) (dur) = (((dur) * 3) / 2)
struct bwn_led {
uint8_t led_flags; /* BWN_LED_F_ */
uint8_t led_act; /* BWN_LED_ACT_ */
uint8_t led_mask;
};
#define BWN_LED_F_ACTLOW 0x1
#define BWN_LED_F_BLINK 0x2
#define BWN_LED_F_POLLABLE 0x4
#define BWN_LED_F_SLOW 0x8
struct bwn_mac {
struct brcmwl_softc *mac_sc;
unsigned mac_status;
#define BWN_MAC_STATUS_UNINIT 0
#define BWN_MAC_STATUS_INITED 1
#define BWN_MAC_STATUS_STARTED 2
unsigned mac_flags;
/* use "Bad Frames Preemption" */
#define BWN_MAC_FLAG_BADFRAME_PREEMP (1 << 0)
#define BWN_MAC_FLAG_DFQVALID (1 << 1)
#define BWN_MAC_FLAG_RADIO_ON (1 << 2)
#define BWN_MAC_FLAG_DMA (1 << 3)
#define BWN_MAC_FLAG_WME (1 << 4)
#define BWN_MAC_FLAG_HWCRYPTO (1 << 5)
/* struct resource_spec *mac_intr_spec;
#define BWN_MSI_MESSAGES 1
struct resource *mac_res_irq[BWN_MSI_MESSAGES];
void *mac_intrhand[BWN_MSI_MESSAGES];
int mac_msi;*/
struct bwn_noise mac_noise;
struct bwn_phy mac_phy;
struct bwn_stats mac_stats;
uint32_t mac_reason_intr;
uint32_t mac_reason[6];
uint32_t mac_intr_mask;
int mac_suspended;
struct bwn_fw mac_fw;
union {
struct bwn_dma dma;
struct bwn_pio pio;
} mac_method;
uint16_t mac_ktp; /* Key table pointer */
uint8_t mac_max_nr_keys;
struct bwn_key mac_key[58];
unsigned int mac_task_state;
struct task mac_intrtask;
struct task mac_hwreset;
struct task mac_txpower;
TAILQ_ENTRY(bwn_mac) mac_list;
};
static inline int
bwn_tx_hdrsize(struct bwn_mac *mac)
{
switch (mac->mac_fw.fw_hdr_format) {
case BWN_FW_HDR_598:
return (112 + (sizeof(struct bwn_plcp6)));
case BWN_FW_HDR_410:
return (104 + (sizeof(struct bwn_plcp6)));
case BWN_FW_HDR_351:
return (100 + (sizeof(struct bwn_plcp6)));
default:
printf("%s: unknown header format (%d)\n", __func__,
mac->mac_fw.fw_hdr_format);
return (112 + (sizeof(struct bwn_plcp6)));
}
}
/*
* Driver-specific vap state.
*/
struct bwn_vap {
struct ieee80211vap bv_vap; /* base class */
int (*bv_newstate)(struct ieee80211vap *,
enum ieee80211_state, int);
};
#define BWN_VAP(vap) ((struct bwn_vap *)(vap))
#define BWN_VAP_CONST(vap) ((const struct mwl_vap *)(vap))
struct id_struct_t {
char fwname[FWCHAR_LEN];
uint32_t rambase;
uint32_t ramsize;
uint32_t srsize;
};
struct brcmwl_softc {
device_t sc_dev;
struct brcmwl_core_priv_t *prCoreSoc;
struct brcmwl_core_priv_t *prCoreRam;
struct brcmwl_core_priv_t *prCoreNet;
struct brcmwl_core_priv_t *prCoreComm;
struct brcmwl_core_priv_t *prCorePmu;
struct brcmwl_core_priv_t *prCoreSdio;
struct brcmwl_chip_priv_t *bcmChip;
if_t ifp;
struct ifmedia ifmedia; /* network interface media structure */
int mtu;
uint8_t macaddr[6];
uint8_t *sc_bounce_buf;
uint32_t sc_bounce_size;
int sc_tx_count;
uint8_t sc_tx_seq;
uint8_t sc_tx_max_seq;
int sc_bcdc_reqid;
TAILQ_HEAD(, brcmwl_proto_bcdc_ctl) sc_bcdc_rxctlq;
unsigned int clkstate;
bool alp_only;
bool sr_enabled;
uint32_t console_addr;
unsigned int blocksize;
unsigned int roundup;
uint32_t hostintmask;
struct id_struct_t predef_val;
uint32_t backplaneAddr;
struct mtx sc_mtx;
struct ieee80211com sc_ic;
struct mbufq sc_snd;
unsigned sc_flags;
#define BWN_FLAG_ATTACHED (1 << 0)
#define BWN_FLAG_INVALID (1 << 1)
#define BWN_FLAG_NEED_BEACON_TP (1 << 2)
#define BWN_FLAG_RUNNING (1 << 3)
unsigned sc_debug;
struct bwn_mac *sc_curmac;
TAILQ_HEAD(, bwn_mac) sc_maclist;
uint8_t sc_bssid[IEEE80211_ADDR_LEN];
unsigned int sc_filters;
uint8_t sc_beacons[2];
uint8_t sc_rf_enabled;
struct wmeParams sc_wmeParams[4];
struct callout sc_rfswitch_ch; /* for laptop */
struct callout sc_task_ch;
struct callout sc_watchdog_ch;
int sc_watchdog_timer;
struct taskqueue *sc_tq; /* private task queue */
int (*sc_newstate)(struct ieee80211com *,
enum ieee80211_state, int);
void (*sc_node_cleanup)(
struct ieee80211_node *);
int sc_rx_rate;
int sc_tx_rate;
int sc_led_blinking;
int sc_led_ticks;
struct bwn_led *sc_blink_led;
struct callout sc_led_blink_ch;
int sc_led_blink_offdur;
struct bwn_led sc_leds[BWN_LED_MAX];
int sc_led_idle;
int sc_led_blink;
struct bwn_tx_radiotap_header sc_tx_th;
struct bwn_rx_radiotap_header sc_rx_th;
};
#define BWN_LOCK_INIT(sc) \
mtx_init(&(sc)->sc_mtx, device_get_nameunit((sc)->sc_dev), \
MTX_NETWORK_LOCK, MTX_DEF)
#define BWN_LOCK_DESTROY(sc) mtx_destroy(&(sc)->sc_mtx)
#define BWN_LOCK(sc) mtx_lock(&(sc)->sc_mtx)
#define BWN_UNLOCK(sc) mtx_unlock(&(sc)->sc_mtx)
#define BWN_ASSERT_LOCKED(sc) mtx_assert(&(sc)->sc_mtx, MA_OWNED)
static inline bwn_band_t
bwn_channel_band(struct bwn_mac *mac, struct ieee80211_channel *c)
{
if (IEEE80211_IS_CHAN_5GHZ(c))
return BWN_BAND_5G;
/* XXX check 2g, log error if not 2g or 5g? */
return BWN_BAND_2G;
}
static inline bwn_band_t
bwn_current_band(struct bwn_mac *mac)
{
struct ieee80211com *ic = &mac->mac_sc->sc_ic;
if (IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan))
return BWN_BAND_5G;
/* XXX check 2g, log error if not 2g or 5g? */
return BWN_BAND_2G;
}
static inline bool
bwn_is_40mhz(struct bwn_mac *mac)
{
struct ieee80211com *ic = &mac->mac_sc->sc_ic;
return !! (IEEE80211_IS_CHAN_HT40(ic->ic_curchan));
}
static inline int
bwn_get_centre_freq(struct bwn_mac *mac)
{
struct ieee80211com *ic = &mac->mac_sc->sc_ic;
/* XXX TODO: calculate correctly for HT40 mode */
return ic->ic_curchan->ic_freq;
}
static inline int
bwn_get_chan_centre_freq(struct bwn_mac *mac, struct ieee80211_channel *chan)
{
/* XXX TODO: calculate correctly for HT40 mode */
return chan->ic_freq;
}
static inline int
bwn_get_chan(struct bwn_mac *mac)
{
struct ieee80211com *ic = &mac->mac_sc->sc_ic;
/* XXX TODO: calculate correctly for HT40 mode */
return ic->ic_curchan->ic_ieee;
}
static inline struct ieee80211_channel *
bwn_get_channel(struct bwn_mac *mac)
{
struct ieee80211com *ic = &mac->mac_sc->sc_ic;
return ic->ic_curchan;
}
static inline bool
bwn_is_chan_passive(struct bwn_mac *mac)
{
struct ieee80211com *ic = &mac->mac_sc->sc_ic;
return !! IEEE80211_IS_CHAN_PASSIVE(ic->ic_curchan);
}
static inline bwn_chan_type_t
bwn_get_chan_type(struct bwn_mac *mac, struct ieee80211_channel *c)
{
struct ieee80211com *ic = &mac->mac_sc->sc_ic;
if (c == NULL)
c = ic->ic_curchan;
if (IEEE80211_IS_CHAN_HT40U(c))
return BWN_CHAN_TYPE_40_HT_U;
else if (IEEE80211_IS_CHAN_HT40D(c))
return BWN_CHAN_TYPE_40_HT_D;
else if (IEEE80211_IS_CHAN_HT20(c))
return BWN_CHAN_TYPE_20_HT;
else
return BWN_CHAN_TYPE_20;
}
static inline int
bwn_get_chan_power(struct bwn_mac *mac, struct ieee80211_channel *c)
{
/* return in dbm */
return c->ic_maxpower / 2;
}
/*
* For now there's no bhnd bus support. Places where it matters
* should call this routine so we can start logging things.
*/
static inline int
bwn_is_bus_siba(struct bwn_mac *mac)
{
return 1;
}
#endif /* !_IF_BRCMWL_H */

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