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D61126.1794664096.diff
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D61126.1794664096.diff
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diff --git a/sys/riscv/vmm/vmm_sbi.c b/sys/riscv/vmm/vmm_sbi.c
--- a/sys/riscv/vmm/vmm_sbi.c
+++ b/sys/riscv/vmm/vmm_sbi.c
@@ -78,21 +78,25 @@
return (SBI_ERR_NOT_SUPPORTED);
}
- /* Construct cpuset_t from the mask supplied. */
- CPU_ZERO(&cpus);
hyp = hypctx->hyp;
active_cpus = vm_active_cpus(hyp->vm);
+
+ if (hart_mask_base == -1UL) {
+ CPU_COPY(&active_cpus, &cpus);
+ goto inject;
+ }
+
+ /* Construct cpuset_t from the mask supplied. */
+ CPU_ZERO(&cpus);
maxcpus = vm_get_maxcpus(hyp->vm);
for (i = 0; i < maxcpus; i++) {
vcpu = vm_vcpu(hyp->vm, i);
if (vcpu == NULL)
continue;
- if (hart_mask_base != -1UL) {
- if (i < hart_mask_base)
- continue;
- if (!(hart_mask & (1UL << (i - hart_mask_base))))
- continue;
- }
+ if (i < hart_mask_base)
+ continue;
+ if (!(hart_mask & (1UL << (i - hart_mask_base))))
+ continue;
/*
* If either hart_mask_base or at least one hartid from
* hart_mask is not valid, then return error.
@@ -102,9 +106,11 @@
CPU_SET(i, &cpus);
}
+ /* Empty mask is a valid no-op per the SBI specification. */
if (CPU_EMPTY(&cpus))
- return (SBI_ERR_INVALID_PARAM);
+ return (SBI_SUCCESS);
+inject:
vmm_fence_add(hyp->vm, &cpus, &fence);
return (SBI_SUCCESS);
@@ -149,17 +155,19 @@
dprintf("%s: hart_mask %lx\n", __func__, hart_mask);
hyp = hypctx->hyp;
-
active_cpus = vm_active_cpus(hyp->vm);
+ if (hart_mask_base == -1UL) {
+ CPU_COPY(&active_cpus, &cpus);
+ goto inject;
+ }
+
CPU_ZERO(&cpus);
switch (func_id) {
case SBI_IPI_SEND_IPI:
- while ((bit = ffs(hart_mask))) {
- hart_id = (bit - 1);
- hart_mask &= ~(1u << hart_id);
- if (hart_mask_base != -1)
- hart_id += hart_mask_base;
+ while ((bit = ffsl(hart_mask))) {
+ hart_id = (bit - 1) + hart_mask_base;
+ hart_mask &= ~(1UL << (bit - 1));
if (!CPU_ISSET(hart_id, &active_cpus))
return (SBI_ERR_INVALID_PARAM);
CPU_SET(hart_id, &cpus);
@@ -170,9 +178,11 @@
return (SBI_ERR_NOT_SUPPORTED);
}
+ /* Empty mask is a valid no-op per the SBI specification. */
if (CPU_EMPTY(&cpus))
- return (SBI_ERR_INVALID_PARAM);
+ return (SBI_SUCCESS);
+inject:
riscv_send_ipi(hyp, &cpus);
return (SBI_SUCCESS);
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D61126.1794664096.diff (2 KB)
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D61126: bhyve/riscv: correctly handle empty masks and broadcast in SBI IPI/RFNC
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