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D8203.1794307268.diff
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Index: head/sys/dev/sfxge/common/ef10_nic.c
===================================================================
--- head/sys/dev/sfxge/common/ef10_nic.c
+++ head/sys/dev/sfxge/common/ef10_nic.c
@@ -164,6 +164,7 @@
break;
case TLV_PORT_MODE_10G_10G_10G_10G:
case TLV_PORT_MODE_10G_10G_10G_10G_Q:
+ case TLV_PORT_MODE_10G_10G_10G_10G_Q1_Q2:
case TLV_PORT_MODE_10G_10G_10G_10G_Q2:
bandwidth = 10000 * 4;
break;
@@ -1098,57 +1099,74 @@
/*
- * The external port mapping is a one-based numbering of the external
- * connectors on the board. It does not distinguish off-board separated
- * outputs such as multi-headed cables.
- * The number of ports that map to each external port connector
- * on the board is determined by the chip family and the port modes to
- * which the NIC can be configured. The mapping table lists modes with
- * port numbering requirements in increasing order.
+ * Table of mapping schemes from port number to the number of the external
+ * connector on the board. The external numbering does not distinguish
+ * off-board separated outputs such as from multi-headed cables.
+ *
+ * The count of adjacent port numbers that map to each external port
+ * and the offset in the numbering, is determined by the chip family and
+ * current port mode.
+ *
+ * For the Huntington family, the current port mode cannot be discovered,
+ * so the mapping used is instead the last match in the table to the full
+ * set of port modes to which the NIC can be configured. Therefore the
+ * ordering of entries in the the mapping table is significant.
*/
static struct {
efx_family_t family;
uint32_t modes_mask;
- uint32_t stride;
+ int32_t count;
+ int32_t offset;
} __ef10_external_port_mappings[] = {
- /* Supported modes requiring 1 output per port */
+ /* Supported modes with 1 output per external port */
{
EFX_FAMILY_HUNTINGTON,
(1 << TLV_PORT_MODE_10G) |
(1 << TLV_PORT_MODE_10G_10G) |
(1 << TLV_PORT_MODE_10G_10G_10G_10G),
+ 1,
1
},
{
EFX_FAMILY_MEDFORD,
(1 << TLV_PORT_MODE_10G) |
- (1 << TLV_PORT_MODE_10G_10G) |
- (1 << TLV_PORT_MODE_10G_10G_10G_10G),
+ (1 << TLV_PORT_MODE_10G_10G),
+ 1,
1
},
- /* Supported modes requiring 2 outputs per port */
+ /* Supported modes with 2 outputs per external port */
{
EFX_FAMILY_HUNTINGTON,
(1 << TLV_PORT_MODE_40G) |
(1 << TLV_PORT_MODE_40G_40G) |
(1 << TLV_PORT_MODE_40G_10G_10G) |
(1 << TLV_PORT_MODE_10G_10G_40G),
- 2
+ 2,
+ 1
},
{
EFX_FAMILY_MEDFORD,
(1 << TLV_PORT_MODE_40G) |
(1 << TLV_PORT_MODE_40G_40G) |
(1 << TLV_PORT_MODE_40G_10G_10G) |
- (1 << TLV_PORT_MODE_10G_10G_40G),
- 2
+ (1 << TLV_PORT_MODE_10G_10G_40G) |
+ (1 << TLV_PORT_MODE_10G_10G_10G_10G_Q1_Q2),
+ 2,
+ 1
},
- /* Supported modes requiring 4 outputs per port */
+ /* Supported modes with 4 outputs per external port */
{
EFX_FAMILY_MEDFORD,
(1 << TLV_PORT_MODE_10G_10G_10G_10G_Q) |
+ (1 << TLV_PORT_MODE_10G_10G_10G_10G_Q1),
+ 4,
+ 1,
+ },
+ {
+ EFX_FAMILY_MEDFORD,
(1 << TLV_PORT_MODE_10G_10G_10G_10G_Q2),
- 4
+ 4,
+ 2
},
};
@@ -1162,11 +1180,26 @@
int i;
uint32_t port_modes;
uint32_t matches;
- uint32_t stride = 1; /* default 1-1 mapping */
-
- if ((rc = efx_mcdi_get_port_modes(enp, &port_modes, NULL)) != 0) {
- /* No port mode information available - use default mapping */
- goto out;
+ uint32_t current;
+ int32_t count = 1; /* Default 1-1 mapping */
+ int32_t offset = 1; /* Default starting external port number */
+
+ if ((rc = efx_mcdi_get_port_modes(enp, &port_modes, &current)) != 0) {
+ /*
+ * No current port mode information
+ * - infer mapping from available modes
+ */
+ if ((rc = efx_mcdi_get_port_modes(enp,
+ &port_modes, NULL)) != 0) {
+ /*
+ * No port mode information available
+ * - use default mapping
+ */
+ goto out;
+ }
+ } else {
+ /* Only need to scan the current mode */
+ port_modes = 1 << current;
}
/*
@@ -1180,7 +1213,8 @@
matches = (__ef10_external_port_mappings[i].modes_mask &
port_modes);
if (matches != 0) {
- stride = __ef10_external_port_mappings[i].stride;
+ count = __ef10_external_port_mappings[i].count;
+ offset = __ef10_external_port_mappings[i].offset;
port_modes &= ~matches;
}
}
@@ -1194,9 +1228,9 @@
out:
/*
* Scale as required by last matched mode and then convert to
- * one-based numbering
+ * correctly offset numbering
*/
- *external_portp = (uint8_t)(port / stride) + 1;
+ *external_portp = (uint8_t)((port / count) + offset);
return (0);
fail1:
Index: head/sys/dev/sfxge/common/ef10_tlv_layout.h
===================================================================
--- head/sys/dev/sfxge/common/ef10_tlv_layout.h
+++ head/sys/dev/sfxge/common/ef10_tlv_layout.h
@@ -553,12 +553,14 @@
#define TLV_PORT_MODE_40G (1) /* 40G, single QSFP/40G-KR */
#define TLV_PORT_MODE_10G_10G (2) /* 2x10G, dual SFP/10G-KR or single QSFP */
#define TLV_PORT_MODE_40G_40G (3) /* 40G + 40G, dual QSFP/40G-KR (Greenport, Medford) */
-#define TLV_PORT_MODE_10G_10G_10G_10G (4) /* 2x10G + 2x10G, quad SFP/10G-KR or dual QSFP (Greenport, Medford) */
-#define TLV_PORT_MODE_10G_10G_10G_10G_Q (5) /* 4x10G, single QSFP, cage 0 (Medford) */
+#define TLV_PORT_MODE_10G_10G_10G_10G (4) /* 2x10G + 2x10G, quad SFP/10G-KR or dual QSFP (Greenport) */
+#define TLV_PORT_MODE_10G_10G_10G_10G_Q1 (4) /* 4x10G, single QSFP, cage 0 (Medford) */
+#define TLV_PORT_MODE_10G_10G_10G_10G_Q (5) /* 4x10G, single QSFP, cage 0 (Medford) OBSOLETE DO NOT USE */
#define TLV_PORT_MODE_40G_10G_10G (6) /* 1x40G + 2x10G, dual QSFP (Greenport, Medford) */
#define TLV_PORT_MODE_10G_10G_40G (7) /* 2x10G + 1x40G, dual QSFP (Greenport, Medford) */
#define TLV_PORT_MODE_10G_10G_10G_10G_Q2 (8) /* 4x10G, single QSFP, cage 1 (Medford) */
-#define TLV_PORT_MODE_MAX TLV_PORT_MODE_10G_10G_10G_10G_Q2
+#define TLV_PORT_MODE_10G_10G_10G_10G_Q1_Q2 (9) /* 2x10G + 2x10G, dual QSFP (Medford) */
+#define TLV_PORT_MODE_MAX TLV_PORT_MODE_10G_10G_10G_10G_Q1_Q2
};
/* Type of the v-switch created implicitly by the firmware */
@@ -765,8 +767,8 @@
#define TLV_RX_EVENT_MERGING_CONFIG_MAX_EVENTS_MAX ((1 << 4) - 1)
uint32_t timeout_ns;
};
-#define TLV_RX_EVENT_MERGING_MAX_EVENTS_DEFAULT 7
-#define TLV_RX_EVENT_MERGING_TIMEOUT_NS_DEFAULT 8740
+#define TLV_RX_EVENT_MERGING_MAX_EVENTS_DEFAULT (0xffffffff)
+#define TLV_RX_EVENT_MERGING_TIMEOUT_NS_DEFAULT (0xffffffff)
#define TLV_TAG_PCIE_LINK_SETTINGS (0x101f0000)
struct tlv_pcie_link_settings {
@@ -791,9 +793,9 @@
uint32_t timeout_ns;
uint32_t qempty_timeout_ns; /* Medford only */
};
-#define TLV_TX_EVENT_MERGING_MAX_EVENTS_DEFAULT 7
-#define TLV_TX_EVENT_MERGING_TIMEOUT_NS_DEFAULT 1400
-#define TLV_TX_EVENT_MERGING_QEMPTY_TIMEOUT_NS_DEFAULT 700
+#define TLV_TX_EVENT_MERGING_MAX_EVENTS_DEFAULT (0xffffffff)
+#define TLV_TX_EVENT_MERGING_TIMEOUT_NS_DEFAULT (0xffffffff)
+#define TLV_TX_EVENT_MERGING_QEMPTY_TIMEOUT_NS_DEFAULT (0xffffffff)
/* Tx vFIFO Low latency configuration
*
@@ -809,6 +811,20 @@
#define TLV_TX_VFIFO_ULL_MODE_DEFAULT 0
};
+/* BIU mode
+ *
+ * Medford2 tag for selecting VI window decode (see values below)
+ */
+#define TLV_TAG_BIU_VI_WINDOW_MODE (0x10280000)
+struct tlv_biu_vi_window_mode {
+ uint32_t tag;
+ uint32_t length;
+ uint8_t mode;
+#define TLV_BIU_VI_WINDOW_MODE_8K 0 /* 8k per VI, CTPIO not mapped, medford/hunt compatible */
+#define TLV_BIU_VI_WINDOW_MODE_16K 1 /* 16k per VI, CTPIO mapped */
+#define TLV_BIU_VI_WINDOW_MODE_64K 2 /* 64k per VI, CTPIO mapped, POWER-friendly */
+};
+
#define TLV_TAG_LICENSE (0x30800000)
typedef struct tlv_license {

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