D18224.1794017091.diff
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	Index: head/sys/dev/sfxge/common/efx_regs_mcdi.h
	===================================================================
	--- head/sys/dev/sfxge/common/efx_regs_mcdi.h
	+++ head/sys/dev/sfxge/common/efx_regs_mcdi.h
	@@ -301,7 +301,8 @@
	#define MC_CMD_ERR_NO_PRIVILEGE 0x1013
	/* Workaround 26807 could not be turned on/off because some functions
	* have already installed filters. See the comment at
	- * MC_CMD_WORKAROUND_BUG26807. */
	+ * MC_CMD_WORKAROUND_BUG26807.
	+ * May also returned for other operations such as sub-variant switching. */
	#define MC_CMD_ERR_FILTERS_PRESENT 0x1014
	/* The clock whose frequency you've attempted to set set
	* doesn't exist on this NIC */
	@@ -320,6 +321,10 @@
	* away. This is distinct from MC_CMD_ERR_DATAPATH_DISABLED in that the
	* datapath absence may be temporary*/
	#define MC_CMD_ERR_NO_DATAPATH 0x1019
	+/* The operation could not complete because some VIs are allocated */
	+#define MC_CMD_ERR_VIS_PRESENT 0x101a
	+/* The operation could not complete because some PIO buffers are allocated */
	+#define MC_CMD_ERR_PIOBUFS_PRESENT 0x101b

	#define MC_CMD_ERR_CODE_OFST 0

	@@ -404,7 +409,7 @@
	#define MCDI_EVENT_LEVEL_LBN 33
	#define MCDI_EVENT_LEVEL_WIDTH 3
	/* enum: Info. */
	-#define MCDI_EVENT_LEVEL_INFO 0x0
	+#define MCDI_EVENT_LEVEL_INFO 0x0
	/* enum: Warning. */
	#define MCDI_EVENT_LEVEL_WARN 0x1
	/* enum: Error. */
	@@ -424,21 +429,21 @@
	#define MCDI_EVENT_LINKCHANGE_SPEED_LBN 16
	#define MCDI_EVENT_LINKCHANGE_SPEED_WIDTH 4
	/* enum: Link is down or link speed could not be determined */
	-#define MCDI_EVENT_LINKCHANGE_SPEED_UNKNOWN 0x0
	+#define MCDI_EVENT_LINKCHANGE_SPEED_UNKNOWN 0x0
	/* enum: 100Mbs */
	-#define MCDI_EVENT_LINKCHANGE_SPEED_100M 0x1
	+#define MCDI_EVENT_LINKCHANGE_SPEED_100M 0x1
	/* enum: 1Gbs */
	-#define MCDI_EVENT_LINKCHANGE_SPEED_1G 0x2
	+#define MCDI_EVENT_LINKCHANGE_SPEED_1G 0x2
	/* enum: 10Gbs */
	-#define MCDI_EVENT_LINKCHANGE_SPEED_10G 0x3
	+#define MCDI_EVENT_LINKCHANGE_SPEED_10G 0x3
	/* enum: 40Gbs */
	-#define MCDI_EVENT_LINKCHANGE_SPEED_40G 0x4
	+#define MCDI_EVENT_LINKCHANGE_SPEED_40G 0x4
	/* enum: 25Gbs */
	-#define MCDI_EVENT_LINKCHANGE_SPEED_25G 0x5
	+#define MCDI_EVENT_LINKCHANGE_SPEED_25G 0x5
	/* enum: 50Gbs */
	-#define MCDI_EVENT_LINKCHANGE_SPEED_50G 0x6
	+#define MCDI_EVENT_LINKCHANGE_SPEED_50G 0x6
	/* enum: 100Gbs */
	-#define MCDI_EVENT_LINKCHANGE_SPEED_100G 0x7
	+#define MCDI_EVENT_LINKCHANGE_SPEED_100G 0x7
	#define MCDI_EVENT_LINKCHANGE_FCNTL_LBN 20
	#define MCDI_EVENT_LINKCHANGE_FCNTL_WIDTH 4
	#define MCDI_EVENT_LINKCHANGE_LINK_FLAGS_LBN 24
	@@ -645,23 +650,23 @@
	/* enum: Transmit error */
	#define MCDI_EVENT_CODE_TX_ERR 0xb
	/* enum: Tx flush has completed */
	-#define MCDI_EVENT_CODE_TX_FLUSH 0xc
	+#define MCDI_EVENT_CODE_TX_FLUSH 0xc
	/* enum: PTP packet received timestamp */
	-#define MCDI_EVENT_CODE_PTP_RX 0xd
	+#define MCDI_EVENT_CODE_PTP_RX 0xd
	/* enum: PTP NIC failure */
	-#define MCDI_EVENT_CODE_PTP_FAULT 0xe
	+#define MCDI_EVENT_CODE_PTP_FAULT 0xe
	/* enum: PTP PPS event */
	-#define MCDI_EVENT_CODE_PTP_PPS 0xf
	+#define MCDI_EVENT_CODE_PTP_PPS 0xf
	/* enum: Rx flush has completed */
	-#define MCDI_EVENT_CODE_RX_FLUSH 0x10
	+#define MCDI_EVENT_CODE_RX_FLUSH 0x10
	/* enum: Receive error */
	#define MCDI_EVENT_CODE_RX_ERR 0x11
	/* enum: AOE fault */
	-#define MCDI_EVENT_CODE_AOE 0x12
	+#define MCDI_EVENT_CODE_AOE 0x12
	/* enum: Network port calibration failed (VCAL). */
	-#define MCDI_EVENT_CODE_VCAL_FAIL 0x13
	+#define MCDI_EVENT_CODE_VCAL_FAIL 0x13
	/* enum: HW PPS event */
	-#define MCDI_EVENT_CODE_HW_PPS 0x14
	+#define MCDI_EVENT_CODE_HW_PPS 0x14
	/* enum: The MC has rebooted (huntington and later, siena uses CODE_REBOOT and
	* a different format)
	*/
	@@ -693,7 +698,7 @@
	/* enum: Artificial event generated by host and posted via MC for test
	* purposes.
	*/
	-#define MCDI_EVENT_CODE_TESTGEN 0xfa
	+#define MCDI_EVENT_CODE_TESTGEN 0xfa
	#define MCDI_EVENT_CMDDONE_DATA_OFST 0
	#define MCDI_EVENT_CMDDONE_DATA_LEN 4
	#define MCDI_EVENT_CMDDONE_DATA_LBN 0
	@@ -823,7 +828,7 @@
	#define FCDI_EVENT_LEVEL_LBN 33
	#define FCDI_EVENT_LEVEL_WIDTH 3
	/* enum: Info. */
	-#define FCDI_EVENT_LEVEL_INFO 0x0
	+#define FCDI_EVENT_LEVEL_INFO 0x0
	/* enum: Warning. */
	#define FCDI_EVENT_LEVEL_WARN 0x1
	/* enum: Error. */
	@@ -955,7 +960,7 @@
	#define MUM_EVENT_LEVEL_LBN 33
	#define MUM_EVENT_LEVEL_WIDTH 3
	/* enum: Info. */
	-#define MUM_EVENT_LEVEL_INFO 0x0
	+#define MUM_EVENT_LEVEL_INFO 0x0
	/* enum: Warning. */
	#define MUM_EVENT_LEVEL_WARN 0x1
	/* enum: Error. */
	@@ -1100,7 +1105,7 @@
	#define MC_CMD_COPYCODE 0x3
	#undef MC_CMD_0x3_PRIVILEGE_CTG

	-#define MC_CMD_0x3_PRIVILEGE_CTG SRIOV_CTG_ADMIN
	+#define MC_CMD_0x3_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND

	/* MC_CMD_COPYCODE_IN msgrequest */
	#define MC_CMD_COPYCODE_IN_LEN 16
	@@ -1187,7 +1192,7 @@
	#define MC_CMD_GET_BOOT_STATUS_OUT_BOOT_OFFSET_OFST 0
	#define MC_CMD_GET_BOOT_STATUS_OUT_BOOT_OFFSET_LEN 4
	/* enum: indicates that the MC wasn't flash booted */
	-#define MC_CMD_GET_BOOT_STATUS_OUT_BOOT_OFFSET_NULL 0xdeadbeef
	+#define MC_CMD_GET_BOOT_STATUS_OUT_BOOT_OFFSET_NULL 0xdeadbeef
	#define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_OFST 4
	#define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_LEN 4
	#define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_WATCHDOG_LBN 0
	@@ -1607,11 +1612,10 @@
	#define MC_CMD_PTP_IN_MANFTEST_PACKET_TEST_ENABLE_OFST 8
	#define MC_CMD_PTP_IN_MANFTEST_PACKET_TEST_ENABLE_LEN 4

	-/* MC_CMD_PTP_IN_RESET_STATS msgrequest */
	+/* MC_CMD_PTP_IN_RESET_STATS msgrequest: Reset PTP statistics */
	#define MC_CMD_PTP_IN_RESET_STATS_LEN 8
	/* MC_CMD_PTP_IN_CMD_OFST 0 */
	/* MC_CMD_PTP_IN_CMD_LEN 4 */
	-/* Reset PTP statistics */
	/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
	/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */

	@@ -1762,11 +1766,10 @@
	/* enum: External. */
	#define MC_CMD_PTP_CLK_SRC_EXTERNAL 0x1

	-/* MC_CMD_PTP_IN_RST_CLK msgrequest */
	+/* MC_CMD_PTP_IN_RST_CLK msgrequest: Reset value of Timer Reg. */
	#define MC_CMD_PTP_IN_RST_CLK_LEN 8
	/* MC_CMD_PTP_IN_CMD_OFST 0 */
	/* MC_CMD_PTP_IN_CMD_LEN 4 */
	-/* Reset value of Timer Reg. */
	/* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
	/* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */

	@@ -2246,7 +2249,7 @@
	#define MC_CMD_HP 0x54
	#undef MC_CMD_0x54_PRIVILEGE_CTG

	-#define MC_CMD_0x54_PRIVILEGE_CTG SRIOV_CTG_ADMIN
	+#define MC_CMD_0x54_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND

	/* MC_CMD_HP_IN msgrequest */
	#define MC_CMD_HP_IN_LEN 16
	@@ -2589,28 +2592,51 @@
	#define MC_CMD_GET_BOARD_CFG_OUT_BOARD_TYPE_LEN 4
	#define MC_CMD_GET_BOARD_CFG_OUT_BOARD_NAME_OFST 4
	#define MC_CMD_GET_BOARD_CFG_OUT_BOARD_NAME_LEN 32
	-/* See MC_CMD_CAPABILITIES */
	+/* Capabilities for Siena Port0 (see struct MC_CMD_CAPABILITIES). Unused on
	+ * EF10 and later (use MC_CMD_GET_CAPABILITIES).
	+ */
	#define MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT0_OFST 36
	#define MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT0_LEN 4
	-/* See MC_CMD_CAPABILITIES */
	+/* Capabilities for Siena Port1 (see struct MC_CMD_CAPABILITIES). Unused on
	+ * EF10 and later (use MC_CMD_GET_CAPABILITIES).
	+ */
	#define MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT1_OFST 40
	#define MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT1_LEN 4
	+/* Base MAC address for Siena Port0. Unused on EF10 and later (use
	+ * MC_CMD_GET_MAC_ADDRESSES).
	+ */
	#define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT0_OFST 44
	#define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT0_LEN 6
	+/* Base MAC address for Siena Port1. Unused on EF10 and later (use
	+ * MC_CMD_GET_MAC_ADDRESSES).
	+ */
	#define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT1_OFST 50
	#define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT1_LEN 6
	+/* Size of MAC address pool for Siena Port0. Unused on EF10 and later (use
	+ * MC_CMD_GET_MAC_ADDRESSES).
	+ */
	#define MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT0_OFST 56
	#define MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT0_LEN 4
	+/* Size of MAC address pool for Siena Port1. Unused on EF10 and later (use
	+ * MC_CMD_GET_MAC_ADDRESSES).
	+ */
	#define MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT1_OFST 60
	#define MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT1_LEN 4
	+/* Increment between addresses in MAC address pool for Siena Port0. Unused on
	+ * EF10 and later (use MC_CMD_GET_MAC_ADDRESSES).
	+ */
	#define MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT0_OFST 64
	#define MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT0_LEN 4
	+/* Increment between addresses in MAC address pool for Siena Port1. Unused on
	+ * EF10 and later (use MC_CMD_GET_MAC_ADDRESSES).
	+ */
	#define MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT1_OFST 68
	#define MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT1_LEN 4
	-/* This field contains a 16-bit value for each of the types of NVRAM area. The
	- * values are defined in the firmware/mc/platform/.c file for a specific board
	- * type, but otherwise have no meaning to the MC; they are used by the driver
	- * to manage selection of appropriate firmware updates.
	+/* Siena only. This field contains a 16-bit value for each of the types of
	+ * NVRAM area. The values are defined in the firmware/mc/platform/.c file for a
	+ * specific board type, but otherwise have no meaning to the MC; they are used
	+ * by the driver to manage selection of appropriate firmware updates. Unused on
	+ * EF10 and later (use MC_CMD_NVRAM_METADATA).
	*/
	#define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_OFST 72
	#define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_LEN 2
	@@ -2727,8 +2753,14 @@
	#define MC_CMD_DRV_ATTACH_IN_NEW_STATE_LEN 4
	#define MC_CMD_DRV_ATTACH_LBN 0
	#define MC_CMD_DRV_ATTACH_WIDTH 1
	+#define MC_CMD_DRV_ATTACH_IN_ATTACH_LBN 0
	+#define MC_CMD_DRV_ATTACH_IN_ATTACH_WIDTH 1
	#define MC_CMD_DRV_PREBOOT_LBN 1
	#define MC_CMD_DRV_PREBOOT_WIDTH 1
	+#define MC_CMD_DRV_ATTACH_IN_PREBOOT_LBN 1
	+#define MC_CMD_DRV_ATTACH_IN_PREBOOT_WIDTH 1
	+#define MC_CMD_DRV_ATTACH_IN_SUBVARIANT_AWARE_LBN 2
	+#define MC_CMD_DRV_ATTACH_IN_SUBVARIANT_AWARE_WIDTH 1
	/* 1 to set new state, or 0 to just report the existing state */
	#define MC_CMD_DRV_ATTACH_IN_UPDATE_OFST 4
	#define MC_CMD_DRV_ATTACH_IN_UPDATE_LEN 4
	@@ -2753,8 +2785,12 @@
	#define MC_CMD_FW_RULES_ENGINE 0x5
	/* enum: Prefer to use firmware with additional DPDK support */
	#define MC_CMD_FW_DPDK 0x6
	+/* enum: Prefer to use "l3xudp" custom datapath firmware (see SF-119495-PD and
	+ * bug69716)
	+ */
	+#define MC_CMD_FW_L3XUDP 0x7
	/* enum: Only this option is allowed for non-admin functions */
	-#define MC_CMD_FW_DONT_CARE 0xffffffff
	+#define MC_CMD_FW_DONT_CARE 0xffffffff

	/* MC_CMD_DRV_ATTACH_OUT msgresponse */
	#define MC_CMD_DRV_ATTACH_OUT_LEN 4
	@@ -3101,7 +3137,7 @@
	#define MC_CMD_START_BIST 0x25
	#undef MC_CMD_0x25_PRIVILEGE_CTG

	-#define MC_CMD_0x25_PRIVILEGE_CTG SRIOV_CTG_ADMIN
	+#define MC_CMD_0x25_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND

	/* MC_CMD_START_BIST_IN msgrequest */
	#define MC_CMD_START_BIST_IN_LEN 4
	@@ -3141,7 +3177,7 @@
	#define MC_CMD_POLL_BIST 0x26
	#undef MC_CMD_0x26_PRIVILEGE_CTG

	-#define MC_CMD_0x26_PRIVILEGE_CTG SRIOV_CTG_ADMIN
	+#define MC_CMD_0x26_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND

	/* MC_CMD_POLL_BIST_IN msgrequest */
	#define MC_CMD_POLL_BIST_IN_LEN 0
	@@ -3342,83 +3378,83 @@
	#define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_LO_OFST 0
	#define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_HI_OFST 4
	/* enum: None. */
	-#define MC_CMD_LOOPBACK_NONE 0x0
	+#define MC_CMD_LOOPBACK_NONE 0x0
	/* enum: Data. */
	-#define MC_CMD_LOOPBACK_DATA 0x1
	+#define MC_CMD_LOOPBACK_DATA 0x1
	/* enum: GMAC. */
	-#define MC_CMD_LOOPBACK_GMAC 0x2
	+#define MC_CMD_LOOPBACK_GMAC 0x2
	/* enum: XGMII. */
	#define MC_CMD_LOOPBACK_XGMII 0x3
	/* enum: XGXS. */
	-#define MC_CMD_LOOPBACK_XGXS 0x4
	+#define MC_CMD_LOOPBACK_XGXS 0x4
	/* enum: XAUI. */
	-#define MC_CMD_LOOPBACK_XAUI 0x5
	+#define MC_CMD_LOOPBACK_XAUI 0x5
	/* enum: GMII. */
	-#define MC_CMD_LOOPBACK_GMII 0x6
	+#define MC_CMD_LOOPBACK_GMII 0x6
	/* enum: SGMII. */
	-#define MC_CMD_LOOPBACK_SGMII 0x7
	+#define MC_CMD_LOOPBACK_SGMII 0x7
	/* enum: XGBR. */
	-#define MC_CMD_LOOPBACK_XGBR 0x8
	+#define MC_CMD_LOOPBACK_XGBR 0x8
	/* enum: XFI. */
	-#define MC_CMD_LOOPBACK_XFI 0x9
	+#define MC_CMD_LOOPBACK_XFI 0x9
	/* enum: XAUI Far. */
	-#define MC_CMD_LOOPBACK_XAUI_FAR 0xa
	+#define MC_CMD_LOOPBACK_XAUI_FAR 0xa
	/* enum: GMII Far. */
	-#define MC_CMD_LOOPBACK_GMII_FAR 0xb
	+#define MC_CMD_LOOPBACK_GMII_FAR 0xb
	/* enum: SGMII Far. */
	-#define MC_CMD_LOOPBACK_SGMII_FAR 0xc
	+#define MC_CMD_LOOPBACK_SGMII_FAR 0xc
	/* enum: XFI Far. */
	-#define MC_CMD_LOOPBACK_XFI_FAR 0xd
	+#define MC_CMD_LOOPBACK_XFI_FAR 0xd
	/* enum: GPhy. */
	-#define MC_CMD_LOOPBACK_GPHY 0xe
	+#define MC_CMD_LOOPBACK_GPHY 0xe
	/* enum: PhyXS. */
	-#define MC_CMD_LOOPBACK_PHYXS 0xf
	+#define MC_CMD_LOOPBACK_PHYXS 0xf
	/* enum: PCS. */
	-#define MC_CMD_LOOPBACK_PCS 0x10
	+#define MC_CMD_LOOPBACK_PCS 0x10
	/* enum: PMA-PMD. */
	-#define MC_CMD_LOOPBACK_PMAPMD 0x11
	+#define MC_CMD_LOOPBACK_PMAPMD 0x11
	/* enum: Cross-Port. */
	-#define MC_CMD_LOOPBACK_XPORT 0x12
	+#define MC_CMD_LOOPBACK_XPORT 0x12
	/* enum: XGMII-Wireside. */
	-#define MC_CMD_LOOPBACK_XGMII_WS 0x13
	+#define MC_CMD_LOOPBACK_XGMII_WS 0x13
	/* enum: XAUI Wireside. */
	-#define MC_CMD_LOOPBACK_XAUI_WS 0x14
	+#define MC_CMD_LOOPBACK_XAUI_WS 0x14
	/* enum: XAUI Wireside Far. */
	-#define MC_CMD_LOOPBACK_XAUI_WS_FAR 0x15
	+#define MC_CMD_LOOPBACK_XAUI_WS_FAR 0x15
	/* enum: XAUI Wireside near. */
	-#define MC_CMD_LOOPBACK_XAUI_WS_NEAR 0x16
	+#define MC_CMD_LOOPBACK_XAUI_WS_NEAR 0x16
	/* enum: GMII Wireside. */
	-#define MC_CMD_LOOPBACK_GMII_WS 0x17
	+#define MC_CMD_LOOPBACK_GMII_WS 0x17
	/* enum: XFI Wireside. */
	-#define MC_CMD_LOOPBACK_XFI_WS 0x18
	+#define MC_CMD_LOOPBACK_XFI_WS 0x18
	/* enum: XFI Wireside Far. */
	-#define MC_CMD_LOOPBACK_XFI_WS_FAR 0x19
	+#define MC_CMD_LOOPBACK_XFI_WS_FAR 0x19
	/* enum: PhyXS Wireside. */
	-#define MC_CMD_LOOPBACK_PHYXS_WS 0x1a
	+#define MC_CMD_LOOPBACK_PHYXS_WS 0x1a
	/* enum: PMA lanes MAC-Serdes. */
	-#define MC_CMD_LOOPBACK_PMA_INT 0x1b
	+#define MC_CMD_LOOPBACK_PMA_INT 0x1b
	/* enum: KR Serdes Parallel (Encoder). */
	-#define MC_CMD_LOOPBACK_SD_NEAR 0x1c
	+#define MC_CMD_LOOPBACK_SD_NEAR 0x1c
	/* enum: KR Serdes Serial. */
	-#define MC_CMD_LOOPBACK_SD_FAR 0x1d
	+#define MC_CMD_LOOPBACK_SD_FAR 0x1d
	/* enum: PMA lanes MAC-Serdes Wireside. */
	-#define MC_CMD_LOOPBACK_PMA_INT_WS 0x1e
	+#define MC_CMD_LOOPBACK_PMA_INT_WS 0x1e
	/* enum: KR Serdes Parallel Wireside (Full PCS). */
	-#define MC_CMD_LOOPBACK_SD_FEP2_WS 0x1f
	+#define MC_CMD_LOOPBACK_SD_FEP2_WS 0x1f
	/* enum: KR Serdes Parallel Wireside (Sym Aligner to TX). */
	-#define MC_CMD_LOOPBACK_SD_FEP1_5_WS 0x20
	+#define MC_CMD_LOOPBACK_SD_FEP1_5_WS 0x20
	/* enum: KR Serdes Parallel Wireside (Deserializer to Serializer). */
	-#define MC_CMD_LOOPBACK_SD_FEP_WS 0x21
	+#define MC_CMD_LOOPBACK_SD_FEP_WS 0x21
	/* enum: KR Serdes Serial Wireside. */
	-#define MC_CMD_LOOPBACK_SD_FES_WS 0x22
	+#define MC_CMD_LOOPBACK_SD_FES_WS 0x22
	/* enum: Near side of AOE Siena side port */
	-#define MC_CMD_LOOPBACK_AOE_INT_NEAR 0x23
	+#define MC_CMD_LOOPBACK_AOE_INT_NEAR 0x23
	/* enum: Medford Wireside datapath loopback */
	-#define MC_CMD_LOOPBACK_DATA_WS 0x24
	+#define MC_CMD_LOOPBACK_DATA_WS 0x24
	/* enum: Force link up without setting up any physical loopback (snapper use
	* only)
	*/
	-#define MC_CMD_LOOPBACK_FORCE_EXT_LINK 0x25
	+#define MC_CMD_LOOPBACK_FORCE_EXT_LINK 0x25
	/* Supported loopbacks. */
	#define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_OFST 8
	#define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_LEN 8
	@@ -3458,83 +3494,83 @@
	#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_LO_OFST 0
	#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_HI_OFST 4
	/* enum: None. */
	-/* MC_CMD_LOOPBACK_NONE 0x0 */
	+/* MC_CMD_LOOPBACK_NONE 0x0 */
	/* enum: Data. */
	-/* MC_CMD_LOOPBACK_DATA 0x1 */
	+/* MC_CMD_LOOPBACK_DATA 0x1 */
	/* enum: GMAC. */
	-/* MC_CMD_LOOPBACK_GMAC 0x2 */
	+/* MC_CMD_LOOPBACK_GMAC 0x2 */
	/* enum: XGMII. */
	/* MC_CMD_LOOPBACK_XGMII 0x3 */
	/* enum: XGXS. */
	-/* MC_CMD_LOOPBACK_XGXS 0x4 */
	+/* MC_CMD_LOOPBACK_XGXS 0x4 */
	/* enum: XAUI. */
	-/* MC_CMD_LOOPBACK_XAUI 0x5 */
	+/* MC_CMD_LOOPBACK_XAUI 0x5 */
	/* enum: GMII. */
	-/* MC_CMD_LOOPBACK_GMII 0x6 */
	+/* MC_CMD_LOOPBACK_GMII 0x6 */
	/* enum: SGMII. */
	-/* MC_CMD_LOOPBACK_SGMII 0x7 */
	+/* MC_CMD_LOOPBACK_SGMII 0x7 */
	/* enum: XGBR. */
	-/* MC_CMD_LOOPBACK_XGBR 0x8 */
	+/* MC_CMD_LOOPBACK_XGBR 0x8 */
	/* enum: XFI. */
	-/* MC_CMD_LOOPBACK_XFI 0x9 */
	+/* MC_CMD_LOOPBACK_XFI 0x9 */
	/* enum: XAUI Far. */
	-/* MC_CMD_LOOPBACK_XAUI_FAR 0xa */
	+/* MC_CMD_LOOPBACK_XAUI_FAR 0xa */
	/* enum: GMII Far. */
	-/* MC_CMD_LOOPBACK_GMII_FAR 0xb */
	+/* MC_CMD_LOOPBACK_GMII_FAR 0xb */
	/* enum: SGMII Far. */
	-/* MC_CMD_LOOPBACK_SGMII_FAR 0xc */
	+/* MC_CMD_LOOPBACK_SGMII_FAR 0xc */
	/* enum: XFI Far. */
	-/* MC_CMD_LOOPBACK_XFI_FAR 0xd */
	+/* MC_CMD_LOOPBACK_XFI_FAR 0xd */
	/* enum: GPhy. */
	-/* MC_CMD_LOOPBACK_GPHY 0xe */
	+/* MC_CMD_LOOPBACK_GPHY 0xe */
	/* enum: PhyXS. */
	-/* MC_CMD_LOOPBACK_PHYXS 0xf */
	+/* MC_CMD_LOOPBACK_PHYXS 0xf */
	/* enum: PCS. */
	-/* MC_CMD_LOOPBACK_PCS 0x10 */
	+/* MC_CMD_LOOPBACK_PCS 0x10 */
	/* enum: PMA-PMD. */
	-/* MC_CMD_LOOPBACK_PMAPMD 0x11 */
	+/* MC_CMD_LOOPBACK_PMAPMD 0x11 */
	/* enum: Cross-Port. */
	-/* MC_CMD_LOOPBACK_XPORT 0x12 */
	+/* MC_CMD_LOOPBACK_XPORT 0x12 */
	/* enum: XGMII-Wireside. */
	-/* MC_CMD_LOOPBACK_XGMII_WS 0x13 */
	+/* MC_CMD_LOOPBACK_XGMII_WS 0x13 */
	/* enum: XAUI Wireside. */
	-/* MC_CMD_LOOPBACK_XAUI_WS 0x14 */
	+/* MC_CMD_LOOPBACK_XAUI_WS 0x14 */
	/* enum: XAUI Wireside Far. */
	-/* MC_CMD_LOOPBACK_XAUI_WS_FAR 0x15 */
	+/* MC_CMD_LOOPBACK_XAUI_WS_FAR 0x15 */
	/* enum: XAUI Wireside near. */
	-/* MC_CMD_LOOPBACK_XAUI_WS_NEAR 0x16 */
	+/* MC_CMD_LOOPBACK_XAUI_WS_NEAR 0x16 */
	/* enum: GMII Wireside. */
	-/* MC_CMD_LOOPBACK_GMII_WS 0x17 */
	+/* MC_CMD_LOOPBACK_GMII_WS 0x17 */
	/* enum: XFI Wireside. */
	-/* MC_CMD_LOOPBACK_XFI_WS 0x18 */
	+/* MC_CMD_LOOPBACK_XFI_WS 0x18 */
	/* enum: XFI Wireside Far. */
	-/* MC_CMD_LOOPBACK_XFI_WS_FAR 0x19 */
	+/* MC_CMD_LOOPBACK_XFI_WS_FAR 0x19 */
	/* enum: PhyXS Wireside. */
	-/* MC_CMD_LOOPBACK_PHYXS_WS 0x1a */
	+/* MC_CMD_LOOPBACK_PHYXS_WS 0x1a */
	/* enum: PMA lanes MAC-Serdes. */
	-/* MC_CMD_LOOPBACK_PMA_INT 0x1b */
	+/* MC_CMD_LOOPBACK_PMA_INT 0x1b */
	/* enum: KR Serdes Parallel (Encoder). */
	-/* MC_CMD_LOOPBACK_SD_NEAR 0x1c */
	+/* MC_CMD_LOOPBACK_SD_NEAR 0x1c */
	/* enum: KR Serdes Serial. */
	-/* MC_CMD_LOOPBACK_SD_FAR 0x1d */
	+/* MC_CMD_LOOPBACK_SD_FAR 0x1d */
	/* enum: PMA lanes MAC-Serdes Wireside. */
	-/* MC_CMD_LOOPBACK_PMA_INT_WS 0x1e */
	+/* MC_CMD_LOOPBACK_PMA_INT_WS 0x1e */
	/* enum: KR Serdes Parallel Wireside (Full PCS). */
	-/* MC_CMD_LOOPBACK_SD_FEP2_WS 0x1f */
	+/* MC_CMD_LOOPBACK_SD_FEP2_WS 0x1f */
	/* enum: KR Serdes Parallel Wireside (Sym Aligner to TX). */
	-/* MC_CMD_LOOPBACK_SD_FEP1_5_WS 0x20 */
	+/* MC_CMD_LOOPBACK_SD_FEP1_5_WS 0x20 */
	/* enum: KR Serdes Parallel Wireside (Deserializer to Serializer). */
	-/* MC_CMD_LOOPBACK_SD_FEP_WS 0x21 */
	+/* MC_CMD_LOOPBACK_SD_FEP_WS 0x21 */
	/* enum: KR Serdes Serial Wireside. */
	-/* MC_CMD_LOOPBACK_SD_FES_WS 0x22 */
	+/* MC_CMD_LOOPBACK_SD_FES_WS 0x22 */
	/* enum: Near side of AOE Siena side port */
	-/* MC_CMD_LOOPBACK_AOE_INT_NEAR 0x23 */
	+/* MC_CMD_LOOPBACK_AOE_INT_NEAR 0x23 */
	/* enum: Medford Wireside datapath loopback */
	-/* MC_CMD_LOOPBACK_DATA_WS 0x24 */
	+/* MC_CMD_LOOPBACK_DATA_WS 0x24 */
	/* enum: Force link up without setting up any physical loopback (snapper use
	* only)
	*/
	-/* MC_CMD_LOOPBACK_FORCE_EXT_LINK 0x25 */
	+/* MC_CMD_LOOPBACK_FORCE_EXT_LINK 0x25 */
	/* Supported loopbacks. */
	#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_OFST 8
	#define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_LEN 8
	@@ -3701,9 +3737,9 @@
	/* Set LED state. */
	#define MC_CMD_SET_ID_LED_IN_STATE_OFST 0
	#define MC_CMD_SET_ID_LED_IN_STATE_LEN 4
	-#define MC_CMD_LED_OFF 0x0 /* enum */
	-#define MC_CMD_LED_ON 0x1 /* enum */
	-#define MC_CMD_LED_DEFAULT 0x2 /* enum */
	+#define MC_CMD_LED_OFF 0x0 /* enum */
	+#define MC_CMD_LED_ON 0x1 /* enum */
	+#define MC_CMD_LED_DEFAULT 0x2 /* enum */

	/* MC_CMD_SET_ID_LED_OUT msgresponse */
	#define MC_CMD_SET_ID_LED_OUT_LEN 0
	@@ -3855,53 +3891,53 @@
	#define MC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_LEN 4
	#define MC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_NUM MC_CMD_PHY_NSTATS
	/* enum: OUI. */
	-#define MC_CMD_OUI 0x0
	+#define MC_CMD_OUI 0x0
	/* enum: PMA-PMD Link Up. */
	-#define MC_CMD_PMA_PMD_LINK_UP 0x1
	+#define MC_CMD_PMA_PMD_LINK_UP 0x1
	/* enum: PMA-PMD RX Fault. */
	-#define MC_CMD_PMA_PMD_RX_FAULT 0x2
	+#define MC_CMD_PMA_PMD_RX_FAULT 0x2
	/* enum: PMA-PMD TX Fault. */
	-#define MC_CMD_PMA_PMD_TX_FAULT 0x3
	+#define MC_CMD_PMA_PMD_TX_FAULT 0x3
	/* enum: PMA-PMD Signal */
	-#define MC_CMD_PMA_PMD_SIGNAL 0x4
	+#define MC_CMD_PMA_PMD_SIGNAL 0x4
	/* enum: PMA-PMD SNR A. */
	-#define MC_CMD_PMA_PMD_SNR_A 0x5
	+#define MC_CMD_PMA_PMD_SNR_A 0x5
	/* enum: PMA-PMD SNR B. */
	-#define MC_CMD_PMA_PMD_SNR_B 0x6
	+#define MC_CMD_PMA_PMD_SNR_B 0x6
	/* enum: PMA-PMD SNR C. */
	-#define MC_CMD_PMA_PMD_SNR_C 0x7
	+#define MC_CMD_PMA_PMD_SNR_C 0x7
	/* enum: PMA-PMD SNR D. */
	-#define MC_CMD_PMA_PMD_SNR_D 0x8
	+#define MC_CMD_PMA_PMD_SNR_D 0x8
	/* enum: PCS Link Up. */
	-#define MC_CMD_PCS_LINK_UP 0x9
	+#define MC_CMD_PCS_LINK_UP 0x9
	/* enum: PCS RX Fault. */
	-#define MC_CMD_PCS_RX_FAULT 0xa
	+#define MC_CMD_PCS_RX_FAULT 0xa
	/* enum: PCS TX Fault. */
	-#define MC_CMD_PCS_TX_FAULT 0xb
	+#define MC_CMD_PCS_TX_FAULT 0xb
	/* enum: PCS BER. */
	-#define MC_CMD_PCS_BER 0xc
	+#define MC_CMD_PCS_BER 0xc
	/* enum: PCS Block Errors. */
	-#define MC_CMD_PCS_BLOCK_ERRORS 0xd
	+#define MC_CMD_PCS_BLOCK_ERRORS 0xd
	/* enum: PhyXS Link Up. */
	-#define MC_CMD_PHYXS_LINK_UP 0xe
	+#define MC_CMD_PHYXS_LINK_UP 0xe
	/* enum: PhyXS RX Fault. */
	-#define MC_CMD_PHYXS_RX_FAULT 0xf
	+#define MC_CMD_PHYXS_RX_FAULT 0xf
	/* enum: PhyXS TX Fault. */
	-#define MC_CMD_PHYXS_TX_FAULT 0x10
	+#define MC_CMD_PHYXS_TX_FAULT 0x10
	/* enum: PhyXS Align. */
	-#define MC_CMD_PHYXS_ALIGN 0x11
	+#define MC_CMD_PHYXS_ALIGN 0x11
	/* enum: PhyXS Sync. */
	-#define MC_CMD_PHYXS_SYNC 0x12
	+#define MC_CMD_PHYXS_SYNC 0x12
	/* enum: AN link-up. */
	-#define MC_CMD_AN_LINK_UP 0x13
	+#define MC_CMD_AN_LINK_UP 0x13
	/* enum: AN Complete. */
	-#define MC_CMD_AN_COMPLETE 0x14
	+#define MC_CMD_AN_COMPLETE 0x14
	/* enum: AN 10GBaseT Status. */
	-#define MC_CMD_AN_10GBT_STATUS 0x15
	+#define MC_CMD_AN_10GBT_STATUS 0x15
	/* enum: Clause 22 Link-Up. */
	-#define MC_CMD_CL22_LINK_UP 0x16
	+#define MC_CMD_CL22_LINK_UP 0x16
	/* enum: (Last entry) */
	-#define MC_CMD_PHY_NSTATS 0x17
	+#define MC_CMD_PHY_NSTATS 0x17


	/***********************************/
	@@ -3964,139 +4000,139 @@
	#define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_LO_OFST 0
	#define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_HI_OFST 4
	#define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS
	-#define MC_CMD_MAC_GENERATION_START 0x0 /* enum */
	-#define MC_CMD_MAC_DMABUF_START 0x1 /* enum */
	-#define MC_CMD_MAC_TX_PKTS 0x1 /* enum */
	-#define MC_CMD_MAC_TX_PAUSE_PKTS 0x2 /* enum */
	-#define MC_CMD_MAC_TX_CONTROL_PKTS 0x3 /* enum */
	-#define MC_CMD_MAC_TX_UNICAST_PKTS 0x4 /* enum */
	-#define MC_CMD_MAC_TX_MULTICAST_PKTS 0x5 /* enum */
	-#define MC_CMD_MAC_TX_BROADCAST_PKTS 0x6 /* enum */
	-#define MC_CMD_MAC_TX_BYTES 0x7 /* enum */
	-#define MC_CMD_MAC_TX_BAD_BYTES 0x8 /* enum */
	-#define MC_CMD_MAC_TX_LT64_PKTS 0x9 /* enum */
	-#define MC_CMD_MAC_TX_64_PKTS 0xa /* enum */
	-#define MC_CMD_MAC_TX_65_TO_127_PKTS 0xb /* enum */
	-#define MC_CMD_MAC_TX_128_TO_255_PKTS 0xc /* enum */
	-#define MC_CMD_MAC_TX_256_TO_511_PKTS 0xd /* enum */
	-#define MC_CMD_MAC_TX_512_TO_1023_PKTS 0xe /* enum */
	-#define MC_CMD_MAC_TX_1024_TO_15XX_PKTS 0xf /* enum */
	-#define MC_CMD_MAC_TX_15XX_TO_JUMBO_PKTS 0x10 /* enum */
	-#define MC_CMD_MAC_TX_GTJUMBO_PKTS 0x11 /* enum */
	-#define MC_CMD_MAC_TX_BAD_FCS_PKTS 0x12 /* enum */
	-#define MC_CMD_MAC_TX_SINGLE_COLLISION_PKTS 0x13 /* enum */
	-#define MC_CMD_MAC_TX_MULTIPLE_COLLISION_PKTS 0x14 /* enum */
	-#define MC_CMD_MAC_TX_EXCESSIVE_COLLISION_PKTS 0x15 /* enum */
	-#define MC_CMD_MAC_TX_LATE_COLLISION_PKTS 0x16 /* enum */
	-#define MC_CMD_MAC_TX_DEFERRED_PKTS 0x17 /* enum */
	-#define MC_CMD_MAC_TX_EXCESSIVE_DEFERRED_PKTS 0x18 /* enum */
	-#define MC_CMD_MAC_TX_NON_TCPUDP_PKTS 0x19 /* enum */
	-#define MC_CMD_MAC_TX_MAC_SRC_ERR_PKTS 0x1a /* enum */
	-#define MC_CMD_MAC_TX_IP_SRC_ERR_PKTS 0x1b /* enum */
	-#define MC_CMD_MAC_RX_PKTS 0x1c /* enum */
	-#define MC_CMD_MAC_RX_PAUSE_PKTS 0x1d /* enum */
	-#define MC_CMD_MAC_RX_GOOD_PKTS 0x1e /* enum */
	-#define MC_CMD_MAC_RX_CONTROL_PKTS 0x1f /* enum */
	-#define MC_CMD_MAC_RX_UNICAST_PKTS 0x20 /* enum */
	-#define MC_CMD_MAC_RX_MULTICAST_PKTS 0x21 /* enum */
	-#define MC_CMD_MAC_RX_BROADCAST_PKTS 0x22 /* enum */
	-#define MC_CMD_MAC_RX_BYTES 0x23 /* enum */
	-#define MC_CMD_MAC_RX_BAD_BYTES 0x24 /* enum */
	-#define MC_CMD_MAC_RX_64_PKTS 0x25 /* enum */
	-#define MC_CMD_MAC_RX_65_TO_127_PKTS 0x26 /* enum */
	-#define MC_CMD_MAC_RX_128_TO_255_PKTS 0x27 /* enum */
	-#define MC_CMD_MAC_RX_256_TO_511_PKTS 0x28 /* enum */
	-#define MC_CMD_MAC_RX_512_TO_1023_PKTS 0x29 /* enum */
	-#define MC_CMD_MAC_RX_1024_TO_15XX_PKTS 0x2a /* enum */
	-#define MC_CMD_MAC_RX_15XX_TO_JUMBO_PKTS 0x2b /* enum */
	-#define MC_CMD_MAC_RX_GTJUMBO_PKTS 0x2c /* enum */
	-#define MC_CMD_MAC_RX_UNDERSIZE_PKTS 0x2d /* enum */
	-#define MC_CMD_MAC_RX_BAD_FCS_PKTS 0x2e /* enum */
	-#define MC_CMD_MAC_RX_OVERFLOW_PKTS 0x2f /* enum */
	-#define MC_CMD_MAC_RX_FALSE_CARRIER_PKTS 0x30 /* enum */
	-#define MC_CMD_MAC_RX_SYMBOL_ERROR_PKTS 0x31 /* enum */
	-#define MC_CMD_MAC_RX_ALIGN_ERROR_PKTS 0x32 /* enum */
	-#define MC_CMD_MAC_RX_LENGTH_ERROR_PKTS 0x33 /* enum */
	-#define MC_CMD_MAC_RX_INTERNAL_ERROR_PKTS 0x34 /* enum */
	-#define MC_CMD_MAC_RX_JABBER_PKTS 0x35 /* enum */
	-#define MC_CMD_MAC_RX_NODESC_DROPS 0x36 /* enum */
	-#define MC_CMD_MAC_RX_LANES01_CHAR_ERR 0x37 /* enum */
	-#define MC_CMD_MAC_RX_LANES23_CHAR_ERR 0x38 /* enum */
	-#define MC_CMD_MAC_RX_LANES01_DISP_ERR 0x39 /* enum */
	-#define MC_CMD_MAC_RX_LANES23_DISP_ERR 0x3a /* enum */
	-#define MC_CMD_MAC_RX_MATCH_FAULT 0x3b /* enum */
	+#define MC_CMD_MAC_GENERATION_START 0x0 /* enum */
	+#define MC_CMD_MAC_DMABUF_START 0x1 /* enum */
	+#define MC_CMD_MAC_TX_PKTS 0x1 /* enum */
	+#define MC_CMD_MAC_TX_PAUSE_PKTS 0x2 /* enum */
	+#define MC_CMD_MAC_TX_CONTROL_PKTS 0x3 /* enum */
	+#define MC_CMD_MAC_TX_UNICAST_PKTS 0x4 /* enum */
	+#define MC_CMD_MAC_TX_MULTICAST_PKTS 0x5 /* enum */
	+#define MC_CMD_MAC_TX_BROADCAST_PKTS 0x6 /* enum */
	+#define MC_CMD_MAC_TX_BYTES 0x7 /* enum */
	+#define MC_CMD_MAC_TX_BAD_BYTES 0x8 /* enum */
	+#define MC_CMD_MAC_TX_LT64_PKTS 0x9 /* enum */
	+#define MC_CMD_MAC_TX_64_PKTS 0xa /* enum */
	+#define MC_CMD_MAC_TX_65_TO_127_PKTS 0xb /* enum */
	+#define MC_CMD_MAC_TX_128_TO_255_PKTS 0xc /* enum */
	+#define MC_CMD_MAC_TX_256_TO_511_PKTS 0xd /* enum */
	+#define MC_CMD_MAC_TX_512_TO_1023_PKTS 0xe /* enum */
	+#define MC_CMD_MAC_TX_1024_TO_15XX_PKTS 0xf /* enum */
	+#define MC_CMD_MAC_TX_15XX_TO_JUMBO_PKTS 0x10 /* enum */
	+#define MC_CMD_MAC_TX_GTJUMBO_PKTS 0x11 /* enum */
	+#define MC_CMD_MAC_TX_BAD_FCS_PKTS 0x12 /* enum */
	+#define MC_CMD_MAC_TX_SINGLE_COLLISION_PKTS 0x13 /* enum */
	+#define MC_CMD_MAC_TX_MULTIPLE_COLLISION_PKTS 0x14 /* enum */
	+#define MC_CMD_MAC_TX_EXCESSIVE_COLLISION_PKTS 0x15 /* enum */
	+#define MC_CMD_MAC_TX_LATE_COLLISION_PKTS 0x16 /* enum */
	+#define MC_CMD_MAC_TX_DEFERRED_PKTS 0x17 /* enum */
	+#define MC_CMD_MAC_TX_EXCESSIVE_DEFERRED_PKTS 0x18 /* enum */
	+#define MC_CMD_MAC_TX_NON_TCPUDP_PKTS 0x19 /* enum */
	+#define MC_CMD_MAC_TX_MAC_SRC_ERR_PKTS 0x1a /* enum */
	+#define MC_CMD_MAC_TX_IP_SRC_ERR_PKTS 0x1b /* enum */
	+#define MC_CMD_MAC_RX_PKTS 0x1c /* enum */
	+#define MC_CMD_MAC_RX_PAUSE_PKTS 0x1d /* enum */
	+#define MC_CMD_MAC_RX_GOOD_PKTS 0x1e /* enum */
	+#define MC_CMD_MAC_RX_CONTROL_PKTS 0x1f /* enum */
	+#define MC_CMD_MAC_RX_UNICAST_PKTS 0x20 /* enum */
	+#define MC_CMD_MAC_RX_MULTICAST_PKTS 0x21 /* enum */
	+#define MC_CMD_MAC_RX_BROADCAST_PKTS 0x22 /* enum */
	+#define MC_CMD_MAC_RX_BYTES 0x23 /* enum */
	+#define MC_CMD_MAC_RX_BAD_BYTES 0x24 /* enum */
	+#define MC_CMD_MAC_RX_64_PKTS 0x25 /* enum */
	+#define MC_CMD_MAC_RX_65_TO_127_PKTS 0x26 /* enum */
	+#define MC_CMD_MAC_RX_128_TO_255_PKTS 0x27 /* enum */
	+#define MC_CMD_MAC_RX_256_TO_511_PKTS 0x28 /* enum */
	+#define MC_CMD_MAC_RX_512_TO_1023_PKTS 0x29 /* enum */
	+#define MC_CMD_MAC_RX_1024_TO_15XX_PKTS 0x2a /* enum */
	+#define MC_CMD_MAC_RX_15XX_TO_JUMBO_PKTS 0x2b /* enum */
	+#define MC_CMD_MAC_RX_GTJUMBO_PKTS 0x2c /* enum */
	+#define MC_CMD_MAC_RX_UNDERSIZE_PKTS 0x2d /* enum */
	+#define MC_CMD_MAC_RX_BAD_FCS_PKTS 0x2e /* enum */
	+#define MC_CMD_MAC_RX_OVERFLOW_PKTS 0x2f /* enum */
	+#define MC_CMD_MAC_RX_FALSE_CARRIER_PKTS 0x30 /* enum */
	+#define MC_CMD_MAC_RX_SYMBOL_ERROR_PKTS 0x31 /* enum */
	+#define MC_CMD_MAC_RX_ALIGN_ERROR_PKTS 0x32 /* enum */
	+#define MC_CMD_MAC_RX_LENGTH_ERROR_PKTS 0x33 /* enum */
	+#define MC_CMD_MAC_RX_INTERNAL_ERROR_PKTS 0x34 /* enum */
	+#define MC_CMD_MAC_RX_JABBER_PKTS 0x35 /* enum */
	+#define MC_CMD_MAC_RX_NODESC_DROPS 0x36 /* enum */
	+#define MC_CMD_MAC_RX_LANES01_CHAR_ERR 0x37 /* enum */
	+#define MC_CMD_MAC_RX_LANES23_CHAR_ERR 0x38 /* enum */
	+#define MC_CMD_MAC_RX_LANES01_DISP_ERR 0x39 /* enum */
	+#define MC_CMD_MAC_RX_LANES23_DISP_ERR 0x3a /* enum */
	+#define MC_CMD_MAC_RX_MATCH_FAULT 0x3b /* enum */
	/* enum: PM trunc_bb_overflow counter. Valid for EF10 with PM_AND_RXDP_COUNTERS
	* capability only.
	*/
	-#define MC_CMD_MAC_PM_TRUNC_BB_OVERFLOW 0x3c
	+#define MC_CMD_MAC_PM_TRUNC_BB_OVERFLOW 0x3c
	/* enum: PM discard_bb_overflow counter. Valid for EF10 with
	* PM_AND_RXDP_COUNTERS capability only.
	*/
	-#define MC_CMD_MAC_PM_DISCARD_BB_OVERFLOW 0x3d
	+#define MC_CMD_MAC_PM_DISCARD_BB_OVERFLOW 0x3d
	/* enum: PM trunc_vfifo_full counter. Valid for EF10 with PM_AND_RXDP_COUNTERS
	* capability only.
	*/
	-#define MC_CMD_MAC_PM_TRUNC_VFIFO_FULL 0x3e
	+#define MC_CMD_MAC_PM_TRUNC_VFIFO_FULL 0x3e
	/* enum: PM discard_vfifo_full counter. Valid for EF10 with
	* PM_AND_RXDP_COUNTERS capability only.
	*/
	-#define MC_CMD_MAC_PM_DISCARD_VFIFO_FULL 0x3f
	+#define MC_CMD_MAC_PM_DISCARD_VFIFO_FULL 0x3f
	/* enum: PM trunc_qbb counter. Valid for EF10 with PM_AND_RXDP_COUNTERS
	* capability only.
	*/
	-#define MC_CMD_MAC_PM_TRUNC_QBB 0x40
	+#define MC_CMD_MAC_PM_TRUNC_QBB 0x40
	/* enum: PM discard_qbb counter. Valid for EF10 with PM_AND_RXDP_COUNTERS
	* capability only.
	*/
	-#define MC_CMD_MAC_PM_DISCARD_QBB 0x41
	+#define MC_CMD_MAC_PM_DISCARD_QBB 0x41
	/* enum: PM discard_mapping counter. Valid for EF10 with PM_AND_RXDP_COUNTERS
	* capability only.
	*/
	-#define MC_CMD_MAC_PM_DISCARD_MAPPING 0x42
	+#define MC_CMD_MAC_PM_DISCARD_MAPPING 0x42
	/* enum: RXDP counter: Number of packets dropped due to the queue being
	* disabled. Valid for EF10 with PM_AND_RXDP_COUNTERS capability only.
	*/
	-#define MC_CMD_MAC_RXDP_Q_DISABLED_PKTS 0x43
	+#define MC_CMD_MAC_RXDP_Q_DISABLED_PKTS 0x43
	/* enum: RXDP counter: Number of packets dropped by the DICPU. Valid for EF10
	* with PM_AND_RXDP_COUNTERS capability only.
	*/
	-#define MC_CMD_MAC_RXDP_DI_DROPPED_PKTS 0x45
	+#define MC_CMD_MAC_RXDP_DI_DROPPED_PKTS 0x45
	/* enum: RXDP counter: Number of non-host packets. Valid for EF10 with
	* PM_AND_RXDP_COUNTERS capability only.
	*/
	-#define MC_CMD_MAC_RXDP_STREAMING_PKTS 0x46
	+#define MC_CMD_MAC_RXDP_STREAMING_PKTS 0x46
	/* enum: RXDP counter: Number of times an hlb descriptor fetch was performed.
	* Valid for EF10 with PM_AND_RXDP_COUNTERS capability only.
	*/
	-#define MC_CMD_MAC_RXDP_HLB_FETCH_CONDITIONS 0x47
	+#define MC_CMD_MAC_RXDP_HLB_FETCH_CONDITIONS 0x47
	/* enum: RXDP counter: Number of times the DPCPU waited for an existing
	* descriptor fetch. Valid for EF10 with PM_AND_RXDP_COUNTERS capability only.
	*/
	-#define MC_CMD_MAC_RXDP_HLB_WAIT_CONDITIONS 0x48
	-#define MC_CMD_MAC_VADAPTER_RX_DMABUF_START 0x4c /* enum */
	-#define MC_CMD_MAC_VADAPTER_RX_UNICAST_PACKETS 0x4c /* enum */
	-#define MC_CMD_MAC_VADAPTER_RX_UNICAST_BYTES 0x4d /* enum */
	-#define MC_CMD_MAC_VADAPTER_RX_MULTICAST_PACKETS 0x4e /* enum */
	-#define MC_CMD_MAC_VADAPTER_RX_MULTICAST_BYTES 0x4f /* enum */
	-#define MC_CMD_MAC_VADAPTER_RX_BROADCAST_PACKETS 0x50 /* enum */
	-#define MC_CMD_MAC_VADAPTER_RX_BROADCAST_BYTES 0x51 /* enum */
	-#define MC_CMD_MAC_VADAPTER_RX_BAD_PACKETS 0x52 /* enum */
	-#define MC_CMD_MAC_VADAPTER_RX_BAD_BYTES 0x53 /* enum */
	-#define MC_CMD_MAC_VADAPTER_RX_OVERFLOW 0x54 /* enum */
	-#define MC_CMD_MAC_VADAPTER_TX_DMABUF_START 0x57 /* enum */
	-#define MC_CMD_MAC_VADAPTER_TX_UNICAST_PACKETS 0x57 /* enum */
	-#define MC_CMD_MAC_VADAPTER_TX_UNICAST_BYTES 0x58 /* enum */
	-#define MC_CMD_MAC_VADAPTER_TX_MULTICAST_PACKETS 0x59 /* enum */
	-#define MC_CMD_MAC_VADAPTER_TX_MULTICAST_BYTES 0x5a /* enum */
	-#define MC_CMD_MAC_VADAPTER_TX_BROADCAST_PACKETS 0x5b /* enum */
	-#define MC_CMD_MAC_VADAPTER_TX_BROADCAST_BYTES 0x5c /* enum */
	-#define MC_CMD_MAC_VADAPTER_TX_BAD_PACKETS 0x5d /* enum */
	-#define MC_CMD_MAC_VADAPTER_TX_BAD_BYTES 0x5e /* enum */
	-#define MC_CMD_MAC_VADAPTER_TX_OVERFLOW 0x5f /* enum */
	+#define MC_CMD_MAC_RXDP_HLB_WAIT_CONDITIONS 0x48
	+#define MC_CMD_MAC_VADAPTER_RX_DMABUF_START 0x4c /* enum */
	+#define MC_CMD_MAC_VADAPTER_RX_UNICAST_PACKETS 0x4c /* enum */
	+#define MC_CMD_MAC_VADAPTER_RX_UNICAST_BYTES 0x4d /* enum */
	+#define MC_CMD_MAC_VADAPTER_RX_MULTICAST_PACKETS 0x4e /* enum */
	+#define MC_CMD_MAC_VADAPTER_RX_MULTICAST_BYTES 0x4f /* enum */
	+#define MC_CMD_MAC_VADAPTER_RX_BROADCAST_PACKETS 0x50 /* enum */
	+#define MC_CMD_MAC_VADAPTER_RX_BROADCAST_BYTES 0x51 /* enum */
	+#define MC_CMD_MAC_VADAPTER_RX_BAD_PACKETS 0x52 /* enum */
	+#define MC_CMD_MAC_VADAPTER_RX_BAD_BYTES 0x53 /* enum */
	+#define MC_CMD_MAC_VADAPTER_RX_OVERFLOW 0x54 /* enum */
	+#define MC_CMD_MAC_VADAPTER_TX_DMABUF_START 0x57 /* enum */
	+#define MC_CMD_MAC_VADAPTER_TX_UNICAST_PACKETS 0x57 /* enum */
	+#define MC_CMD_MAC_VADAPTER_TX_UNICAST_BYTES 0x58 /* enum */
	+#define MC_CMD_MAC_VADAPTER_TX_MULTICAST_PACKETS 0x59 /* enum */
	+#define MC_CMD_MAC_VADAPTER_TX_MULTICAST_BYTES 0x5a /* enum */
	+#define MC_CMD_MAC_VADAPTER_TX_BROADCAST_PACKETS 0x5b /* enum */
	+#define MC_CMD_MAC_VADAPTER_TX_BROADCAST_BYTES 0x5c /* enum */
	+#define MC_CMD_MAC_VADAPTER_TX_BAD_PACKETS 0x5d /* enum */
	+#define MC_CMD_MAC_VADAPTER_TX_BAD_BYTES 0x5e /* enum */
	+#define MC_CMD_MAC_VADAPTER_TX_OVERFLOW 0x5f /* enum */
	/* enum: Start of GMAC stats buffer space, for Siena only. */
	-#define MC_CMD_GMAC_DMABUF_START 0x40
	+#define MC_CMD_GMAC_DMABUF_START 0x40
	/* enum: End of GMAC stats buffer space, for Siena only. */
	-#define MC_CMD_GMAC_DMABUF_END 0x5f
	+#define MC_CMD_GMAC_DMABUF_END 0x5f
	/* enum: GENERATION_END value, used together with GENERATION_START to verify
	* consistency of DMAd data. For legacy firmware / drivers without extended
	* stats (more precisely, when DMA_LEN == MC_CMD_MAC_NSTATS *
	@@ -4108,7 +4144,7 @@
	* sizeof(uint64_t). See SF-109306-TC, Section 9.2 for details.
	*/
	#define MC_CMD_MAC_GENERATION_END 0x60
	-#define MC_CMD_MAC_NSTATS 0x61 /* enum */
	+#define MC_CMD_MAC_NSTATS 0x61 /* enum */

	/* MC_CMD_MAC_STATS_V2_OUT_DMA msgresponse */
	#define MC_CMD_MAC_STATS_V2_OUT_DMA_LEN 0
	@@ -4121,25 +4157,25 @@
	#define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_HI_OFST 4
	#define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS_V2
	/* enum: Start of FEC stats buffer space, Medford2 and up */
	-#define MC_CMD_MAC_FEC_DMABUF_START 0x61
	+#define MC_CMD_MAC_FEC_DMABUF_START 0x61
	/* enum: Number of uncorrected FEC codewords on link (RS-FEC only for Medford2)
	*/
	-#define MC_CMD_MAC_FEC_UNCORRECTED_ERRORS 0x61
	+#define MC_CMD_MAC_FEC_UNCORRECTED_ERRORS 0x61
	/* enum: Number of corrected FEC codewords on link (RS-FEC only for Medford2)
	*/
	-#define MC_CMD_MAC_FEC_CORRECTED_ERRORS 0x62
	+#define MC_CMD_MAC_FEC_CORRECTED_ERRORS 0x62
	/* enum: Number of corrected 10-bit symbol errors, lane 0 (RS-FEC only) */
	-#define MC_CMD_MAC_FEC_CORRECTED_SYMBOLS_LANE0 0x63
	+#define MC_CMD_MAC_FEC_CORRECTED_SYMBOLS_LANE0 0x63
	/* enum: Number of corrected 10-bit symbol errors, lane 1 (RS-FEC only) */
	-#define MC_CMD_MAC_FEC_CORRECTED_SYMBOLS_LANE1 0x64
	+#define MC_CMD_MAC_FEC_CORRECTED_SYMBOLS_LANE1 0x64
	/* enum: Number of corrected 10-bit symbol errors, lane 2 (RS-FEC only) */
	-#define MC_CMD_MAC_FEC_CORRECTED_SYMBOLS_LANE2 0x65
	+#define MC_CMD_MAC_FEC_CORRECTED_SYMBOLS_LANE2 0x65
	/* enum: Number of corrected 10-bit symbol errors, lane 3 (RS-FEC only) */
	-#define MC_CMD_MAC_FEC_CORRECTED_SYMBOLS_LANE3 0x66
	+#define MC_CMD_MAC_FEC_CORRECTED_SYMBOLS_LANE3 0x66
	/* enum: This includes the space at offset 103 which is the final
	* GENERATION_END in a MAC_STATS_V2 response and otherwise unused.
	*/
	-#define MC_CMD_MAC_NSTATS_V2 0x68
	+#define MC_CMD_MAC_NSTATS_V2 0x68
	/* Other enum values, see field(s): */
	/* MC_CMD_MAC_STATS_OUT_NO_DMA/STATISTICS */

	@@ -4154,66 +4190,66 @@
	#define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_HI_OFST 4
	#define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS_V3
	/* enum: Start of CTPIO stats buffer space, Medford2 and up */
	-#define MC_CMD_MAC_CTPIO_DMABUF_START 0x68
	+#define MC_CMD_MAC_CTPIO_DMABUF_START 0x68
	/* enum: Number of CTPIO fallbacks because a DMA packet was in progress on the
	* target VI
	*/
	-#define MC_CMD_MAC_CTPIO_VI_BUSY_FALLBACK 0x68
	+#define MC_CMD_MAC_CTPIO_VI_BUSY_FALLBACK 0x68
	/* enum: Number of times a CTPIO send wrote beyond frame end (informational
	* only)
	*/
	-#define MC_CMD_MAC_CTPIO_LONG_WRITE_SUCCESS 0x69
	+#define MC_CMD_MAC_CTPIO_LONG_WRITE_SUCCESS 0x69
	/* enum: Number of CTPIO failures because the TX doorbell was written before
	* the end of the frame data
	*/
	-#define MC_CMD_MAC_CTPIO_MISSING_DBELL_FAIL 0x6a
	+#define MC_CMD_MAC_CTPIO_MISSING_DBELL_FAIL 0x6a
	/* enum: Number of CTPIO failures because the internal FIFO overflowed */
	-#define MC_CMD_MAC_CTPIO_OVERFLOW_FAIL 0x6b
	+#define MC_CMD_MAC_CTPIO_OVERFLOW_FAIL 0x6b
	/* enum: Number of CTPIO failures because the host did not deliver data fast
	* enough to avoid MAC underflow
	*/
	-#define MC_CMD_MAC_CTPIO_UNDERFLOW_FAIL 0x6c
	+#define MC_CMD_MAC_CTPIO_UNDERFLOW_FAIL 0x6c
	/* enum: Number of CTPIO failures because the host did not deliver all the
	* frame data within the timeout
	*/
	-#define MC_CMD_MAC_CTPIO_TIMEOUT_FAIL 0x6d
	+#define MC_CMD_MAC_CTPIO_TIMEOUT_FAIL 0x6d
	/* enum: Number of CTPIO failures because the frame data arrived out of order
	* or with gaps
	*/
	-#define MC_CMD_MAC_CTPIO_NONCONTIG_WR_FAIL 0x6e
	+#define MC_CMD_MAC_CTPIO_NONCONTIG_WR_FAIL 0x6e
	/* enum: Number of CTPIO failures because the host started a new frame before
	* completing the previous one
	*/
	-#define MC_CMD_MAC_CTPIO_FRM_CLOBBER_FAIL 0x6f
	+#define MC_CMD_MAC_CTPIO_FRM_CLOBBER_FAIL 0x6f
	/* enum: Number of CTPIO failures because a write was not a multiple of 32 bits
	* or not 32-bit aligned
	*/
	-#define MC_CMD_MAC_CTPIO_INVALID_WR_FAIL 0x70
	+#define MC_CMD_MAC_CTPIO_INVALID_WR_FAIL 0x70
	/* enum: Number of CTPIO fallbacks because another VI on the same port was
	* sending a CTPIO frame
	*/
	-#define MC_CMD_MAC_CTPIO_VI_CLOBBER_FALLBACK 0x71
	+#define MC_CMD_MAC_CTPIO_VI_CLOBBER_FALLBACK 0x71
	/* enum: Number of CTPIO fallbacks because target VI did not have CTPIO enabled
	*/
	-#define MC_CMD_MAC_CTPIO_UNQUALIFIED_FALLBACK 0x72
	+#define MC_CMD_MAC_CTPIO_UNQUALIFIED_FALLBACK 0x72
	/* enum: Number of CTPIO fallbacks because length in header was less than 29
	* bytes
	*/
	-#define MC_CMD_MAC_CTPIO_RUNT_FALLBACK 0x73
	+#define MC_CMD_MAC_CTPIO_RUNT_FALLBACK 0x73
	/* enum: Total number of successful CTPIO sends on this port */
	-#define MC_CMD_MAC_CTPIO_SUCCESS 0x74
	+#define MC_CMD_MAC_CTPIO_SUCCESS 0x74
	/* enum: Total number of CTPIO fallbacks on this port */
	-#define MC_CMD_MAC_CTPIO_FALLBACK 0x75
	+#define MC_CMD_MAC_CTPIO_FALLBACK 0x75
	/* enum: Total number of CTPIO poisoned frames on this port, whether erased or
	* not
	*/
	-#define MC_CMD_MAC_CTPIO_POISON 0x76
	+#define MC_CMD_MAC_CTPIO_POISON 0x76
	/* enum: Total number of CTPIO erased frames on this port */
	-#define MC_CMD_MAC_CTPIO_ERASE 0x77
	+#define MC_CMD_MAC_CTPIO_ERASE 0x77
	/* enum: This includes the space at offset 120 which is the final
	* GENERATION_END in a MAC_STATS_V3 response and otherwise unused.
	*/
	-#define MC_CMD_MAC_NSTATS_V3 0x79
	+#define MC_CMD_MAC_NSTATS_V3 0x79
	/* Other enum values, see field(s): */
	/* MC_CMD_MAC_STATS_V2_OUT_NO_DMA/STATISTICS */

	@@ -4323,25 +4359,25 @@
	#define MC_CMD_WOL_FILTER_SET_IN_LEN 192
	#define MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0
	#define MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_LEN 4
	-#define MC_CMD_FILTER_MODE_SIMPLE 0x0 /* enum */
	+#define MC_CMD_FILTER_MODE_SIMPLE 0x0 /* enum */
	#define MC_CMD_FILTER_MODE_STRUCTURED 0xffffffff /* enum */
	/* A type value of 1 is unused. */
	#define MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4
	#define MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_LEN 4
	/* enum: Magic */
	-#define MC_CMD_WOL_TYPE_MAGIC 0x0
	+#define MC_CMD_WOL_TYPE_MAGIC 0x0
	/* enum: MS Windows Magic */
	#define MC_CMD_WOL_TYPE_WIN_MAGIC 0x2
	/* enum: IPv4 Syn */
	-#define MC_CMD_WOL_TYPE_IPV4_SYN 0x3
	+#define MC_CMD_WOL_TYPE_IPV4_SYN 0x3
	/* enum: IPv6 Syn */
	-#define MC_CMD_WOL_TYPE_IPV6_SYN 0x4
	+#define MC_CMD_WOL_TYPE_IPV6_SYN 0x4
	/* enum: Bitmap */
	-#define MC_CMD_WOL_TYPE_BITMAP 0x5
	+#define MC_CMD_WOL_TYPE_BITMAP 0x5
	/* enum: Link */
	-#define MC_CMD_WOL_TYPE_LINK 0x6
	+#define MC_CMD_WOL_TYPE_LINK 0x6
	/* enum: (Above this for future use) */
	-#define MC_CMD_WOL_TYPE_MAX 0x7
	+#define MC_CMD_WOL_TYPE_MAX 0x7
	#define MC_CMD_WOL_FILTER_SET_IN_DATA_OFST 8
	#define MC_CMD_WOL_FILTER_SET_IN_DATA_LEN 4
	#define MC_CMD_WOL_FILTER_SET_IN_DATA_NUM 46
	@@ -4574,6 +4610,8 @@
	#define MC_CMD_NVRAM_INFO_OUT_PROTECTED_WIDTH 1
	#define MC_CMD_NVRAM_INFO_OUT_TLV_LBN 1
	#define MC_CMD_NVRAM_INFO_OUT_TLV_WIDTH 1
	+#define MC_CMD_NVRAM_INFO_OUT_READ_ONLY_IF_TSA_BOUND_LBN 2
	+#define MC_CMD_NVRAM_INFO_OUT_READ_ONLY_IF_TSA_BOUND_WIDTH 1
	#define MC_CMD_NVRAM_INFO_OUT_READ_ONLY_LBN 5
	#define MC_CMD_NVRAM_INFO_OUT_READ_ONLY_WIDTH 1
	#define MC_CMD_NVRAM_INFO_OUT_CMAC_LBN 6
	@@ -4601,6 +4639,8 @@
	#define MC_CMD_NVRAM_INFO_V2_OUT_PROTECTED_WIDTH 1
	#define MC_CMD_NVRAM_INFO_V2_OUT_TLV_LBN 1
	#define MC_CMD_NVRAM_INFO_V2_OUT_TLV_WIDTH 1
	+#define MC_CMD_NVRAM_INFO_V2_OUT_READ_ONLY_IF_TSA_BOUND_LBN 2
	+#define MC_CMD_NVRAM_INFO_V2_OUT_READ_ONLY_IF_TSA_BOUND_WIDTH 1
	#define MC_CMD_NVRAM_INFO_V2_OUT_READ_ONLY_LBN 5
	#define MC_CMD_NVRAM_INFO_V2_OUT_READ_ONLY_WIDTH 1
	#define MC_CMD_NVRAM_INFO_V2_OUT_A_B_LBN 7
	@@ -4619,7 +4659,11 @@
	/* MC_CMD_NVRAM_UPDATE_START
	* Start a group of update operations on a virtual NVRAM partition. Locks
	* required: PHY_LOCK if type==PHY. Returns: 0, EINVAL (bad type), EACCES (if
	- * PHY_LOCK required and not held).
	+ * PHY_LOCK required and not held). In an adapter bound to a TSA controller,
	+ * MC_CMD_NVRAM_UPDATE_START can only be used on a subset of partition types
	+ * i.e. static config, dynamic config and expansion ROM config. Attempting to
	+ * perform this operation on a restricted partition will return the error
	+ * EPERM.
	*/
	#define MC_CMD_NVRAM_UPDATE_START 0x38
	#undef MC_CMD_0x38_PRIVILEGE_CTG
	@@ -4783,8 +4827,12 @@
	/***********************************/
	/* MC_CMD_NVRAM_UPDATE_FINISH
	* Finish a group of update operations on a virtual NVRAM partition. Locks
	- * required: PHY_LOCK if type==PHY. Returns: 0, EINVAL (bad
	- * type/offset/length), EACCES (if PHY_LOCK required and not held)
	+ * required: PHY_LOCK if type==PHY. Returns: 0, EINVAL (bad type/offset/
	+ * length), EACCES (if PHY_LOCK required and not held). In an adapter bound to
	+ * a TSA controller, MC_CMD_NVRAM_UPDATE_FINISH can only be used on a subset of
	+ * partition types i.e. static config, dynamic config and expansion ROM config.
	+ * Attempting to perform this operation on a restricted partition will return
	+ * the error EPERM.
	*/
	#define MC_CMD_NVRAM_UPDATE_FINISH 0x3c
	#undef MC_CMD_0x3c_PRIVILEGE_CTG
	@@ -4902,7 +4950,7 @@
	#define MC_CMD_REBOOT 0x3d
	#undef MC_CMD_0x3d_PRIVILEGE_CTG

	-#define MC_CMD_0x3d_PRIVILEGE_CTG SRIOV_CTG_ADMIN
	+#define MC_CMD_0x3d_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND

	/* MC_CMD_REBOOT_IN msgrequest */
	#define MC_CMD_REBOOT_IN_LEN 4
	@@ -5026,177 +5074,181 @@
	#define MC_CMD_SENSOR_INFO_OUT_MASK_OFST 0
	#define MC_CMD_SENSOR_INFO_OUT_MASK_LEN 4
	/* enum: Controller temperature: degC */
	-#define MC_CMD_SENSOR_CONTROLLER_TEMP 0x0
	+#define MC_CMD_SENSOR_CONTROLLER_TEMP 0x0
	/* enum: Phy common temperature: degC */
	-#define MC_CMD_SENSOR_PHY_COMMON_TEMP 0x1
	+#define MC_CMD_SENSOR_PHY_COMMON_TEMP 0x1
	/* enum: Controller cooling: bool */
	-#define MC_CMD_SENSOR_CONTROLLER_COOLING 0x2
	+#define MC_CMD_SENSOR_CONTROLLER_COOLING 0x2
	/* enum: Phy 0 temperature: degC */
	-#define MC_CMD_SENSOR_PHY0_TEMP 0x3
	+#define MC_CMD_SENSOR_PHY0_TEMP 0x3
	/* enum: Phy 0 cooling: bool */
	-#define MC_CMD_SENSOR_PHY0_COOLING 0x4
	+#define MC_CMD_SENSOR_PHY0_COOLING 0x4
	/* enum: Phy 1 temperature: degC */
	-#define MC_CMD_SENSOR_PHY1_TEMP 0x5
	+#define MC_CMD_SENSOR_PHY1_TEMP 0x5
	/* enum: Phy 1 cooling: bool */
	-#define MC_CMD_SENSOR_PHY1_COOLING 0x6
	+#define MC_CMD_SENSOR_PHY1_COOLING 0x6
	/* enum: 1.0v power: mV */
	-#define MC_CMD_SENSOR_IN_1V0 0x7
	+#define MC_CMD_SENSOR_IN_1V0 0x7
	/* enum: 1.2v power: mV */
	-#define MC_CMD_SENSOR_IN_1V2 0x8
	+#define MC_CMD_SENSOR_IN_1V2 0x8
	/* enum: 1.8v power: mV */
	-#define MC_CMD_SENSOR_IN_1V8 0x9
	+#define MC_CMD_SENSOR_IN_1V8 0x9
	/* enum: 2.5v power: mV */
	-#define MC_CMD_SENSOR_IN_2V5 0xa
	+#define MC_CMD_SENSOR_IN_2V5 0xa
	/* enum: 3.3v power: mV */
	-#define MC_CMD_SENSOR_IN_3V3 0xb
	+#define MC_CMD_SENSOR_IN_3V3 0xb
	/* enum: 12v power: mV */
	-#define MC_CMD_SENSOR_IN_12V0 0xc
	+#define MC_CMD_SENSOR_IN_12V0 0xc
	/* enum: 1.2v analogue power: mV */
	-#define MC_CMD_SENSOR_IN_1V2A 0xd
	+#define MC_CMD_SENSOR_IN_1V2A 0xd
	/* enum: reference voltage: mV */
	-#define MC_CMD_SENSOR_IN_VREF 0xe
	+#define MC_CMD_SENSOR_IN_VREF 0xe
	/* enum: AOE FPGA power: mV */
	-#define MC_CMD_SENSOR_OUT_VAOE 0xf
	+#define MC_CMD_SENSOR_OUT_VAOE 0xf
	/* enum: AOE FPGA temperature: degC */
	-#define MC_CMD_SENSOR_AOE_TEMP 0x10
	+#define MC_CMD_SENSOR_AOE_TEMP 0x10
	/* enum: AOE FPGA PSU temperature: degC */
	-#define MC_CMD_SENSOR_PSU_AOE_TEMP 0x11
	+#define MC_CMD_SENSOR_PSU_AOE_TEMP 0x11
	/* enum: AOE PSU temperature: degC */
	-#define MC_CMD_SENSOR_PSU_TEMP 0x12
	+#define MC_CMD_SENSOR_PSU_TEMP 0x12
	/* enum: Fan 0 speed: RPM */
	-#define MC_CMD_SENSOR_FAN_0 0x13
	+#define MC_CMD_SENSOR_FAN_0 0x13
	/* enum: Fan 1 speed: RPM */
	-#define MC_CMD_SENSOR_FAN_1 0x14
	+#define MC_CMD_SENSOR_FAN_1 0x14
	/* enum: Fan 2 speed: RPM */
	-#define MC_CMD_SENSOR_FAN_2 0x15
	+#define MC_CMD_SENSOR_FAN_2 0x15
	/* enum: Fan 3 speed: RPM */
	-#define MC_CMD_SENSOR_FAN_3 0x16
	+#define MC_CMD_SENSOR_FAN_3 0x16
	/* enum: Fan 4 speed: RPM */
	-#define MC_CMD_SENSOR_FAN_4 0x17
	+#define MC_CMD_SENSOR_FAN_4 0x17
	/* enum: AOE FPGA input power: mV */
	-#define MC_CMD_SENSOR_IN_VAOE 0x18
	+#define MC_CMD_SENSOR_IN_VAOE 0x18
	/* enum: AOE FPGA current: mA */
	-#define MC_CMD_SENSOR_OUT_IAOE 0x19
	+#define MC_CMD_SENSOR_OUT_IAOE 0x19
	/* enum: AOE FPGA input current: mA */
	-#define MC_CMD_SENSOR_IN_IAOE 0x1a
	+#define MC_CMD_SENSOR_IN_IAOE 0x1a
	/* enum: NIC power consumption: W */
	-#define MC_CMD_SENSOR_NIC_POWER 0x1b
	+#define MC_CMD_SENSOR_NIC_POWER 0x1b
	/* enum: 0.9v power voltage: mV */
	-#define MC_CMD_SENSOR_IN_0V9 0x1c
	+#define MC_CMD_SENSOR_IN_0V9 0x1c
	/* enum: 0.9v power current: mA */
	-#define MC_CMD_SENSOR_IN_I0V9 0x1d
	+#define MC_CMD_SENSOR_IN_I0V9 0x1d
	/* enum: 1.2v power current: mA */
	-#define MC_CMD_SENSOR_IN_I1V2 0x1e
	+#define MC_CMD_SENSOR_IN_I1V2 0x1e
	/* enum: Not a sensor: reserved for the next page flag */
	-#define MC_CMD_SENSOR_PAGE0_NEXT 0x1f
	+#define MC_CMD_SENSOR_PAGE0_NEXT 0x1f
	/* enum: 0.9v power voltage (at ADC): mV */
	-#define MC_CMD_SENSOR_IN_0V9_ADC 0x20
	+#define MC_CMD_SENSOR_IN_0V9_ADC 0x20
	/* enum: Controller temperature 2: degC */
	-#define MC_CMD_SENSOR_CONTROLLER_2_TEMP 0x21
	+#define MC_CMD_SENSOR_CONTROLLER_2_TEMP 0x21
	/* enum: Voltage regulator internal temperature: degC */
	-#define MC_CMD_SENSOR_VREG_INTERNAL_TEMP 0x22
	+#define MC_CMD_SENSOR_VREG_INTERNAL_TEMP 0x22
	/* enum: 0.9V voltage regulator temperature: degC */
	-#define MC_CMD_SENSOR_VREG_0V9_TEMP 0x23
	+#define MC_CMD_SENSOR_VREG_0V9_TEMP 0x23
	/* enum: 1.2V voltage regulator temperature: degC */
	-#define MC_CMD_SENSOR_VREG_1V2_TEMP 0x24
	+#define MC_CMD_SENSOR_VREG_1V2_TEMP 0x24
	/* enum: controller internal temperature sensor voltage (internal ADC): mV */
	-#define MC_CMD_SENSOR_CONTROLLER_VPTAT 0x25
	+#define MC_CMD_SENSOR_CONTROLLER_VPTAT 0x25
	/* enum: controller internal temperature (internal ADC): degC */
	-#define MC_CMD_SENSOR_CONTROLLER_INTERNAL_TEMP 0x26
	+#define MC_CMD_SENSOR_CONTROLLER_INTERNAL_TEMP 0x26
	/* enum: controller internal temperature sensor voltage (external ADC): mV */
	-#define MC_CMD_SENSOR_CONTROLLER_VPTAT_EXTADC 0x27
	+#define MC_CMD_SENSOR_CONTROLLER_VPTAT_EXTADC 0x27
	/* enum: controller internal temperature (external ADC): degC */
	-#define MC_CMD_SENSOR_CONTROLLER_INTERNAL_TEMP_EXTADC 0x28
	+#define MC_CMD_SENSOR_CONTROLLER_INTERNAL_TEMP_EXTADC 0x28
	/* enum: ambient temperature: degC */
	-#define MC_CMD_SENSOR_AMBIENT_TEMP 0x29
	+#define MC_CMD_SENSOR_AMBIENT_TEMP 0x29
	/* enum: air flow: bool */
	-#define MC_CMD_SENSOR_AIRFLOW 0x2a
	+#define MC_CMD_SENSOR_AIRFLOW 0x2a
	/* enum: voltage between VSS08D and VSS08D at CSR: mV */
	-#define MC_CMD_SENSOR_VDD08D_VSS08D_CSR 0x2b
	+#define MC_CMD_SENSOR_VDD08D_VSS08D_CSR 0x2b
	/* enum: voltage between VSS08D and VSS08D at CSR (external ADC): mV */
	-#define MC_CMD_SENSOR_VDD08D_VSS08D_CSR_EXTADC 0x2c
	+#define MC_CMD_SENSOR_VDD08D_VSS08D_CSR_EXTADC 0x2c
	/* enum: Hotpoint temperature: degC */
	-#define MC_CMD_SENSOR_HOTPOINT_TEMP 0x2d
	+#define MC_CMD_SENSOR_HOTPOINT_TEMP 0x2d
	/* enum: Port 0 PHY power switch over-current: bool */
	-#define MC_CMD_SENSOR_PHY_POWER_PORT0 0x2e
	+#define MC_CMD_SENSOR_PHY_POWER_PORT0 0x2e
	/* enum: Port 1 PHY power switch over-current: bool */
	-#define MC_CMD_SENSOR_PHY_POWER_PORT1 0x2f
	-/* enum: Mop-up microcontroller reference voltage (millivolts) */
	-#define MC_CMD_SENSOR_MUM_VCC 0x30
	+#define MC_CMD_SENSOR_PHY_POWER_PORT1 0x2f
	+/* enum: Mop-up microcontroller reference voltage: mV */
	+#define MC_CMD_SENSOR_MUM_VCC 0x30
	/* enum: 0.9v power phase A voltage: mV */
	-#define MC_CMD_SENSOR_IN_0V9_A 0x31
	+#define MC_CMD_SENSOR_IN_0V9_A 0x31
	/* enum: 0.9v power phase A current: mA */
	-#define MC_CMD_SENSOR_IN_I0V9_A 0x32
	+#define MC_CMD_SENSOR_IN_I0V9_A 0x32
	/* enum: 0.9V voltage regulator phase A temperature: degC */
	-#define MC_CMD_SENSOR_VREG_0V9_A_TEMP 0x33
	+#define MC_CMD_SENSOR_VREG_0V9_A_TEMP 0x33
	/* enum: 0.9v power phase B voltage: mV */
	-#define MC_CMD_SENSOR_IN_0V9_B 0x34
	+#define MC_CMD_SENSOR_IN_0V9_B 0x34
	/* enum: 0.9v power phase B current: mA */
	-#define MC_CMD_SENSOR_IN_I0V9_B 0x35
	+#define MC_CMD_SENSOR_IN_I0V9_B 0x35
	/* enum: 0.9V voltage regulator phase B temperature: degC */
	-#define MC_CMD_SENSOR_VREG_0V9_B_TEMP 0x36
	+#define MC_CMD_SENSOR_VREG_0V9_B_TEMP 0x36
	/* enum: CCOM AVREG 1v2 supply (interval ADC): mV */
	-#define MC_CMD_SENSOR_CCOM_AVREG_1V2_SUPPLY 0x37
	+#define MC_CMD_SENSOR_CCOM_AVREG_1V2_SUPPLY 0x37
	/* enum: CCOM AVREG 1v2 supply (external ADC): mV */
	-#define MC_CMD_SENSOR_CCOM_AVREG_1V2_SUPPLY_EXTADC 0x38
	+#define MC_CMD_SENSOR_CCOM_AVREG_1V2_SUPPLY_EXTADC 0x38
	/* enum: CCOM AVREG 1v8 supply (interval ADC): mV */
	-#define MC_CMD_SENSOR_CCOM_AVREG_1V8_SUPPLY 0x39
	+#define MC_CMD_SENSOR_CCOM_AVREG_1V8_SUPPLY 0x39
	/* enum: CCOM AVREG 1v8 supply (external ADC): mV */
	-#define MC_CMD_SENSOR_CCOM_AVREG_1V8_SUPPLY_EXTADC 0x3a
	+#define MC_CMD_SENSOR_CCOM_AVREG_1V8_SUPPLY_EXTADC 0x3a
	/* enum: CCOM RTS temperature: degC */
	-#define MC_CMD_SENSOR_CONTROLLER_RTS 0x3b
	+#define MC_CMD_SENSOR_CONTROLLER_RTS 0x3b
	/* enum: Not a sensor: reserved for the next page flag */
	-#define MC_CMD_SENSOR_PAGE1_NEXT 0x3f
	+#define MC_CMD_SENSOR_PAGE1_NEXT 0x3f
	/* enum: controller internal temperature sensor voltage on master core
	* (internal ADC): mV
	*/
	-#define MC_CMD_SENSOR_CONTROLLER_MASTER_VPTAT 0x40
	+#define MC_CMD_SENSOR_CONTROLLER_MASTER_VPTAT 0x40
	/* enum: controller internal temperature on master core (internal ADC): degC */
	-#define MC_CMD_SENSOR_CONTROLLER_MASTER_INTERNAL_TEMP 0x41
	+#define MC_CMD_SENSOR_CONTROLLER_MASTER_INTERNAL_TEMP 0x41
	/* enum: controller internal temperature sensor voltage on master core
	* (external ADC): mV
	*/
	-#define MC_CMD_SENSOR_CONTROLLER_MASTER_VPTAT_EXTADC 0x42
	+#define MC_CMD_SENSOR_CONTROLLER_MASTER_VPTAT_EXTADC 0x42
	/* enum: controller internal temperature on master core (external ADC): degC */
	-#define MC_CMD_SENSOR_CONTROLLER_MASTER_INTERNAL_TEMP_EXTADC 0x43
	+#define MC_CMD_SENSOR_CONTROLLER_MASTER_INTERNAL_TEMP_EXTADC 0x43
	/* enum: controller internal temperature on slave core sensor voltage (internal
	* ADC): mV
	*/
	-#define MC_CMD_SENSOR_CONTROLLER_SLAVE_VPTAT 0x44
	+#define MC_CMD_SENSOR_CONTROLLER_SLAVE_VPTAT 0x44
	/* enum: controller internal temperature on slave core (internal ADC): degC */
	-#define MC_CMD_SENSOR_CONTROLLER_SLAVE_INTERNAL_TEMP 0x45
	+#define MC_CMD_SENSOR_CONTROLLER_SLAVE_INTERNAL_TEMP 0x45
	/* enum: controller internal temperature on slave core sensor voltage (external
	* ADC): mV
	*/
	-#define MC_CMD_SENSOR_CONTROLLER_SLAVE_VPTAT_EXTADC 0x46
	+#define MC_CMD_SENSOR_CONTROLLER_SLAVE_VPTAT_EXTADC 0x46
	/* enum: controller internal temperature on slave core (external ADC): degC */
	-#define MC_CMD_SENSOR_CONTROLLER_SLAVE_INTERNAL_TEMP_EXTADC 0x47
	+#define MC_CMD_SENSOR_CONTROLLER_SLAVE_INTERNAL_TEMP_EXTADC 0x47
	/* enum: Voltage supplied to the SODIMMs from their power supply: mV */
	-#define MC_CMD_SENSOR_SODIMM_VOUT 0x49
	+#define MC_CMD_SENSOR_SODIMM_VOUT 0x49
	/* enum: Temperature of SODIMM 0 (if installed): degC */
	-#define MC_CMD_SENSOR_SODIMM_0_TEMP 0x4a
	+#define MC_CMD_SENSOR_SODIMM_0_TEMP 0x4a
	/* enum: Temperature of SODIMM 1 (if installed): degC */
	-#define MC_CMD_SENSOR_SODIMM_1_TEMP 0x4b
	+#define MC_CMD_SENSOR_SODIMM_1_TEMP 0x4b
	/* enum: Voltage supplied to the QSFP #0 from their power supply: mV */
	-#define MC_CMD_SENSOR_PHY0_VCC 0x4c
	+#define MC_CMD_SENSOR_PHY0_VCC 0x4c
	/* enum: Voltage supplied to the QSFP #1 from their power supply: mV */
	-#define MC_CMD_SENSOR_PHY1_VCC 0x4d
	+#define MC_CMD_SENSOR_PHY1_VCC 0x4d
	/* enum: Controller die temperature (TDIODE): degC */
	-#define MC_CMD_SENSOR_CONTROLLER_TDIODE_TEMP 0x4e
	+#define MC_CMD_SENSOR_CONTROLLER_TDIODE_TEMP 0x4e
	/* enum: Board temperature (front): degC */
	-#define MC_CMD_SENSOR_BOARD_FRONT_TEMP 0x4f
	+#define MC_CMD_SENSOR_BOARD_FRONT_TEMP 0x4f
	/* enum: Board temperature (back): degC */
	-#define MC_CMD_SENSOR_BOARD_BACK_TEMP 0x50
	+#define MC_CMD_SENSOR_BOARD_BACK_TEMP 0x50
	/* enum: 1.8v power current: mA */
	-#define MC_CMD_SENSOR_IN_I1V8 0x51
	+#define MC_CMD_SENSOR_IN_I1V8 0x51
	/* enum: 2.5v power current: mA */
	-#define MC_CMD_SENSOR_IN_I2V5 0x52
	+#define MC_CMD_SENSOR_IN_I2V5 0x52
	/* enum: 3.3v power current: mA */
	-#define MC_CMD_SENSOR_IN_I3V3 0x53
	+#define MC_CMD_SENSOR_IN_I3V3 0x53
	/* enum: 12v power current: mA */
	-#define MC_CMD_SENSOR_IN_I12V0 0x54
	+#define MC_CMD_SENSOR_IN_I12V0 0x54
	+/* enum: 1.3v power: mV */
	+#define MC_CMD_SENSOR_IN_1V3 0x55
	+/* enum: 1.3v power current: mA */
	+#define MC_CMD_SENSOR_IN_I1V3 0x56
	/* enum: Not a sensor: reserved for the next page flag */
	-#define MC_CMD_SENSOR_PAGE2_NEXT 0x5f
	+#define MC_CMD_SENSOR_PAGE2_NEXT 0x5f
	/* MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF */
	#define MC_CMD_SENSOR_ENTRY_OFST 4
	#define MC_CMD_SENSOR_ENTRY_LEN 8
	@@ -5299,17 +5351,17 @@
	#define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_OFST 2
	#define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_LEN 1
	/* enum: Ok. */
	-#define MC_CMD_SENSOR_STATE_OK 0x0
	+#define MC_CMD_SENSOR_STATE_OK 0x0
	/* enum: Breached warning threshold. */
	-#define MC_CMD_SENSOR_STATE_WARNING 0x1
	+#define MC_CMD_SENSOR_STATE_WARNING 0x1
	/* enum: Breached fatal threshold. */
	-#define MC_CMD_SENSOR_STATE_FATAL 0x2
	+#define MC_CMD_SENSOR_STATE_FATAL 0x2
	/* enum: Fault with sensor. */
	-#define MC_CMD_SENSOR_STATE_BROKEN 0x3
	+#define MC_CMD_SENSOR_STATE_BROKEN 0x3
	/* enum: Sensor is working but does not currently have a reading. */
	-#define MC_CMD_SENSOR_STATE_NO_READING 0x4
	+#define MC_CMD_SENSOR_STATE_NO_READING 0x4
	/* enum: Sensor initialisation failed. */
	-#define MC_CMD_SENSOR_STATE_INIT_FAILED 0x5
	+#define MC_CMD_SENSOR_STATE_INIT_FAILED 0x5
	#define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_LBN 16
	#define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_WIDTH 8
	#define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_OFST 3
	@@ -5395,7 +5447,7 @@
	#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0
	#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_LEN 4
	#define MC_CMD_LIGHTSOUT_OFFLOAD_PROTOCOL_ARP 0x1 /* enum */
	-#define MC_CMD_LIGHTSOUT_OFFLOAD_PROTOCOL_NS 0x2 /* enum */
	+#define MC_CMD_LIGHTSOUT_OFFLOAD_PROTOCOL_NS 0x2 /* enum */
	#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_OFST 4
	#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_LEN 4
	#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_MINNUM 1
	@@ -5470,7 +5522,7 @@
	#define MC_CMD_TESTASSERT 0x49
	#undef MC_CMD_0x49_PRIVILEGE_CTG

	-#define MC_CMD_0x49_PRIVILEGE_CTG SRIOV_CTG_ADMIN
	+#define MC_CMD_0x49_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND

	/* MC_CMD_TESTASSERT_IN msgrequest */
	#define MC_CMD_TESTASSERT_IN_LEN 0
	@@ -5486,17 +5538,17 @@
	/* enum: Assert using the FAIL_ASSERTION_WITH_USEFUL_VALUES macro. Unless
	* you're testing firmware, this is what you want.
	*/
	-#define MC_CMD_TESTASSERT_V2_IN_FAIL_ASSERTION_WITH_USEFUL_VALUES 0x0
	+#define MC_CMD_TESTASSERT_V2_IN_FAIL_ASSERTION_WITH_USEFUL_VALUES 0x0
	/* enum: Assert using assert(0); */
	-#define MC_CMD_TESTASSERT_V2_IN_ASSERT_FALSE 0x1
	+#define MC_CMD_TESTASSERT_V2_IN_ASSERT_FALSE 0x1
	/* enum: Deliberately trigger a watchdog */
	-#define MC_CMD_TESTASSERT_V2_IN_WATCHDOG 0x2
	+#define MC_CMD_TESTASSERT_V2_IN_WATCHDOG 0x2
	/* enum: Deliberately trigger a trap by loading from an invalid address */
	-#define MC_CMD_TESTASSERT_V2_IN_LOAD_TRAP 0x3
	+#define MC_CMD_TESTASSERT_V2_IN_LOAD_TRAP 0x3
	/* enum: Deliberately trigger a trap by storing to an invalid address */
	-#define MC_CMD_TESTASSERT_V2_IN_STORE_TRAP 0x4
	+#define MC_CMD_TESTASSERT_V2_IN_STORE_TRAP 0x4
	/* enum: Jump to an invalid address */
	-#define MC_CMD_TESTASSERT_V2_IN_JUMP_TRAP 0x5
	+#define MC_CMD_TESTASSERT_V2_IN_JUMP_TRAP 0x5

	/* MC_CMD_TESTASSERT_V2_OUT msgresponse */
	#define MC_CMD_TESTASSERT_V2_OUT_LEN 0
	@@ -5603,7 +5655,7 @@
	#define MC_CMD_NVRAM_TEST 0x4c
	#undef MC_CMD_0x4c_PRIVILEGE_CTG

	-#define MC_CMD_0x4c_PRIVILEGE_CTG SRIOV_CTG_ADMIN
	+#define MC_CMD_0x4c_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND

	/* MC_CMD_NVRAM_TEST_IN msgrequest */
	#define MC_CMD_NVRAM_TEST_IN_LEN 4
	@@ -5836,7 +5888,7 @@
	#define MC_CMD_CLP 0x56
	#undef MC_CMD_0x56_PRIVILEGE_CTG

	-#define MC_CMD_0x56_PRIVILEGE_CTG SRIOV_CTG_ADMIN
	+#define MC_CMD_0x56_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND

	/* MC_CMD_CLP_IN msgrequest */
	#define MC_CMD_CLP_IN_LEN 4
	@@ -6048,7 +6100,7 @@
	/* MC_CMD_MUM_IN_CMD_LEN 4 */
	#define MC_CMD_MUM_IN_LOG_OP_OFST 4
	#define MC_CMD_MUM_IN_LOG_OP_LEN 4
	-#define MC_CMD_MUM_IN_LOG_OP_UART 0x1 /* enum */
	+#define MC_CMD_MUM_IN_LOG_OP_UART 0x1 /* enum */

	/* MC_CMD_MUM_IN_LOG_OP_UART msgrequest */
	#define MC_CMD_MUM_IN_LOG_OP_UART_LEN 12
	@@ -6543,17 +6595,17 @@
	#define EVB_PORT_ID_PORT_ID_OFST 0
	#define EVB_PORT_ID_PORT_ID_LEN 4
	/* enum: An invalid port handle. */
	-#define EVB_PORT_ID_NULL 0x0
	+#define EVB_PORT_ID_NULL 0x0
	/* enum: The port assigned to this function.. */
	-#define EVB_PORT_ID_ASSIGNED 0x1000000
	+#define EVB_PORT_ID_ASSIGNED 0x1000000
	/* enum: External network port 0 */
	-#define EVB_PORT_ID_MAC0 0x2000000
	+#define EVB_PORT_ID_MAC0 0x2000000
	/* enum: External network port 1 */
	-#define EVB_PORT_ID_MAC1 0x2000001
	+#define EVB_PORT_ID_MAC1 0x2000001
	/* enum: External network port 2 */
	-#define EVB_PORT_ID_MAC2 0x2000002
	+#define EVB_PORT_ID_MAC2 0x2000002
	/* enum: External network port 3 */
	-#define EVB_PORT_ID_MAC3 0x2000003
	+#define EVB_PORT_ID_MAC3 0x2000003
	#define EVB_PORT_ID_PORT_ID_LBN 0
	#define EVB_PORT_ID_PORT_ID_WIDTH 32

	@@ -6565,7 +6617,7 @@
	#define EVB_VLAN_TAG_MODE_LBN 12
	#define EVB_VLAN_TAG_MODE_WIDTH 4
	/* enum: Insert the VLAN. */
	-#define EVB_VLAN_TAG_INSERT 0x0
	+#define EVB_VLAN_TAG_INSERT 0x0
	/* enum: Replace the VLAN if already present. */
	#define EVB_VLAN_TAG_REPLACE 0x1

	@@ -6594,105 +6646,110 @@
	#define NVRAM_PARTITION_TYPE_ID_OFST 0
	#define NVRAM_PARTITION_TYPE_ID_LEN 2
	/* enum: Primary MC firmware partition */
	-#define NVRAM_PARTITION_TYPE_MC_FIRMWARE 0x100
	+#define NVRAM_PARTITION_TYPE_MC_FIRMWARE 0x100
	/* enum: Secondary MC firmware partition */
	-#define NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP 0x200
	+#define NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP 0x200
	/* enum: Expansion ROM partition */
	-#define NVRAM_PARTITION_TYPE_EXPANSION_ROM 0x300
	+#define NVRAM_PARTITION_TYPE_EXPANSION_ROM 0x300
	/* enum: Static configuration TLV partition */
	-#define NVRAM_PARTITION_TYPE_STATIC_CONFIG 0x400
	+#define NVRAM_PARTITION_TYPE_STATIC_CONFIG 0x400
	/* enum: Dynamic configuration TLV partition */
	-#define NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG 0x500
	+#define NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG 0x500
	/* enum: Expansion ROM configuration data for port 0 */
	-#define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0 0x600
	+#define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0 0x600
	/* enum: Synonym for EXPROM_CONFIG_PORT0 as used in pmap files */
	-#define NVRAM_PARTITION_TYPE_EXPROM_CONFIG 0x600
	+#define NVRAM_PARTITION_TYPE_EXPROM_CONFIG 0x600
	/* enum: Expansion ROM configuration data for port 1 */
	-#define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT1 0x601
	+#define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT1 0x601
	/* enum: Expansion ROM configuration data for port 2 */
	-#define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT2 0x602
	+#define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT2 0x602
	/* enum: Expansion ROM configuration data for port 3 */
	-#define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT3 0x603
	+#define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT3 0x603
	/* enum: Non-volatile log output partition */
	-#define NVRAM_PARTITION_TYPE_LOG 0x700
	+#define NVRAM_PARTITION_TYPE_LOG 0x700
	/* enum: Non-volatile log output of second core on dual-core device */
	-#define NVRAM_PARTITION_TYPE_LOG_SLAVE 0x701
	+#define NVRAM_PARTITION_TYPE_LOG_SLAVE 0x701
	/* enum: Device state dump output partition */
	-#define NVRAM_PARTITION_TYPE_DUMP 0x800
	+#define NVRAM_PARTITION_TYPE_DUMP 0x800
	/* enum: Application license key storage partition */
	-#define NVRAM_PARTITION_TYPE_LICENSE 0x900
	+#define NVRAM_PARTITION_TYPE_LICENSE 0x900
	/* enum: Start of range used for PHY partitions (low 8 bits are the PHY ID) */
	-#define NVRAM_PARTITION_TYPE_PHY_MIN 0xa00
	+#define NVRAM_PARTITION_TYPE_PHY_MIN 0xa00
	/* enum: End of range used for PHY partitions (low 8 bits are the PHY ID) */
	-#define NVRAM_PARTITION_TYPE_PHY_MAX 0xaff
	+#define NVRAM_PARTITION_TYPE_PHY_MAX 0xaff
	/* enum: Primary FPGA partition */
	-#define NVRAM_PARTITION_TYPE_FPGA 0xb00
	+#define NVRAM_PARTITION_TYPE_FPGA 0xb00
	/* enum: Secondary FPGA partition */
	-#define NVRAM_PARTITION_TYPE_FPGA_BACKUP 0xb01
	+#define NVRAM_PARTITION_TYPE_FPGA_BACKUP 0xb01
	/* enum: FC firmware partition */
	-#define NVRAM_PARTITION_TYPE_FC_FIRMWARE 0xb02
	+#define NVRAM_PARTITION_TYPE_FC_FIRMWARE 0xb02
	/* enum: FC License partition */
	-#define NVRAM_PARTITION_TYPE_FC_LICENSE 0xb03
	+#define NVRAM_PARTITION_TYPE_FC_LICENSE 0xb03
	/* enum: Non-volatile log output partition for FC */
	-#define NVRAM_PARTITION_TYPE_FC_LOG 0xb04
	+#define NVRAM_PARTITION_TYPE_FC_LOG 0xb04
	/* enum: MUM firmware partition */
	-#define NVRAM_PARTITION_TYPE_MUM_FIRMWARE 0xc00
	+#define NVRAM_PARTITION_TYPE_MUM_FIRMWARE 0xc00
	/* enum: SUC firmware partition (this is intentionally an alias of
	* MUM_FIRMWARE)
	*/
	-#define NVRAM_PARTITION_TYPE_SUC_FIRMWARE 0xc00
	+#define NVRAM_PARTITION_TYPE_SUC_FIRMWARE 0xc00
	/* enum: MUM Non-volatile log output partition. */
	-#define NVRAM_PARTITION_TYPE_MUM_LOG 0xc01
	+#define NVRAM_PARTITION_TYPE_MUM_LOG 0xc01
	/* enum: MUM Application table partition. */
	-#define NVRAM_PARTITION_TYPE_MUM_APPTABLE 0xc02
	+#define NVRAM_PARTITION_TYPE_MUM_APPTABLE 0xc02
	/* enum: MUM boot rom partition. */
	-#define NVRAM_PARTITION_TYPE_MUM_BOOT_ROM 0xc03
	+#define NVRAM_PARTITION_TYPE_MUM_BOOT_ROM 0xc03
	/* enum: MUM production signatures & calibration rom partition. */
	-#define NVRAM_PARTITION_TYPE_MUM_PROD_ROM 0xc04
	+#define NVRAM_PARTITION_TYPE_MUM_PROD_ROM 0xc04
	/* enum: MUM user signatures & calibration rom partition. */
	-#define NVRAM_PARTITION_TYPE_MUM_USER_ROM 0xc05
	+#define NVRAM_PARTITION_TYPE_MUM_USER_ROM 0xc05
	/* enum: MUM fuses and lockbits partition. */
	-#define NVRAM_PARTITION_TYPE_MUM_FUSELOCK 0xc06
	+#define NVRAM_PARTITION_TYPE_MUM_FUSELOCK 0xc06
	/* enum: UEFI expansion ROM if separate from PXE */
	-#define NVRAM_PARTITION_TYPE_EXPANSION_UEFI 0xd00
	+#define NVRAM_PARTITION_TYPE_EXPANSION_UEFI 0xd00
	/* enum: Used by the expansion ROM for logging */
	-#define NVRAM_PARTITION_TYPE_PXE_LOG 0x1000
	+#define NVRAM_PARTITION_TYPE_PXE_LOG 0x1000
	/* enum: Used for XIP code of shmbooted images */
	-#define NVRAM_PARTITION_TYPE_XIP_SCRATCH 0x1100
	+#define NVRAM_PARTITION_TYPE_XIP_SCRATCH 0x1100
	/* enum: Spare partition 2 */
	-#define NVRAM_PARTITION_TYPE_SPARE_2 0x1200
	+#define NVRAM_PARTITION_TYPE_SPARE_2 0x1200
	/* enum: Manufacturing partition. Used during manufacture to pass information
	* between XJTAG and Manftest.
	*/
	-#define NVRAM_PARTITION_TYPE_MANUFACTURING 0x1300
	+#define NVRAM_PARTITION_TYPE_MANUFACTURING 0x1300
	/* enum: Spare partition 4 */
	-#define NVRAM_PARTITION_TYPE_SPARE_4 0x1400
	+#define NVRAM_PARTITION_TYPE_SPARE_4 0x1400
	/* enum: Spare partition 5 */
	-#define NVRAM_PARTITION_TYPE_SPARE_5 0x1500
	+#define NVRAM_PARTITION_TYPE_SPARE_5 0x1500
	/* enum: Partition for reporting MC status. See mc_flash_layout.h
	* medford_mc_status_hdr_t for layout on Medford.
	*/
	-#define NVRAM_PARTITION_TYPE_STATUS 0x1600
	+#define NVRAM_PARTITION_TYPE_STATUS 0x1600
	/* enum: Spare partition 13 */
	-#define NVRAM_PARTITION_TYPE_SPARE_13 0x1700
	+#define NVRAM_PARTITION_TYPE_SPARE_13 0x1700
	/* enum: Spare partition 14 */
	-#define NVRAM_PARTITION_TYPE_SPARE_14 0x1800
	+#define NVRAM_PARTITION_TYPE_SPARE_14 0x1800
	/* enum: Spare partition 15 */
	-#define NVRAM_PARTITION_TYPE_SPARE_15 0x1900
	+#define NVRAM_PARTITION_TYPE_SPARE_15 0x1900
	/* enum: Spare partition 16 */
	-#define NVRAM_PARTITION_TYPE_SPARE_16 0x1a00
	+#define NVRAM_PARTITION_TYPE_SPARE_16 0x1a00
	/* enum: Factory defaults for dynamic configuration */
	-#define NVRAM_PARTITION_TYPE_DYNCONFIG_DEFAULTS 0x1b00
	+#define NVRAM_PARTITION_TYPE_DYNCONFIG_DEFAULTS 0x1b00
	/* enum: Factory defaults for expansion ROM configuration */
	-#define NVRAM_PARTITION_TYPE_ROMCONFIG_DEFAULTS 0x1c00
	+#define NVRAM_PARTITION_TYPE_ROMCONFIG_DEFAULTS 0x1c00
	+/* enum: Field Replaceable Unit inventory information for use on IPMI
	+ * platforms. See SF-119124-PS. The STATIC_CONFIG partition may contain a
	+ * subset of the information stored in this partition.
	+ */
	+#define NVRAM_PARTITION_TYPE_FRU_INFORMATION 0x1d00
	/* enum: Start of reserved value range (firmware may use for any purpose) */
	-#define NVRAM_PARTITION_TYPE_RESERVED_VALUES_MIN 0xff00
	+#define NVRAM_PARTITION_TYPE_RESERVED_VALUES_MIN 0xff00
	/* enum: End of reserved value range (firmware may use for any purpose) */
	-#define NVRAM_PARTITION_TYPE_RESERVED_VALUES_MAX 0xfffd
	+#define NVRAM_PARTITION_TYPE_RESERVED_VALUES_MAX 0xfffd
	/* enum: Recovery partition map (provided if real map is missing or corrupt) */
	-#define NVRAM_PARTITION_TYPE_RECOVERY_MAP 0xfffe
	+#define NVRAM_PARTITION_TYPE_RECOVERY_MAP 0xfffe
	/* enum: Partition map (real map as stored in flash) */
	-#define NVRAM_PARTITION_TYPE_PARTITION_MAP 0xffff
	+#define NVRAM_PARTITION_TYPE_PARTITION_MAP 0xffff
	#define NVRAM_PARTITION_TYPE_ID_LBN 0
	#define NVRAM_PARTITION_TYPE_ID_WIDTH 16

	@@ -6701,37 +6758,37 @@
	#define LICENSED_APP_ID_ID_OFST 0
	#define LICENSED_APP_ID_ID_LEN 4
	/* enum: OpenOnload */
	-#define LICENSED_APP_ID_ONLOAD 0x1
	+#define LICENSED_APP_ID_ONLOAD 0x1
	/* enum: PTP timestamping */
	-#define LICENSED_APP_ID_PTP 0x2
	+#define LICENSED_APP_ID_PTP 0x2
	/* enum: SolarCapture Pro */
	-#define LICENSED_APP_ID_SOLARCAPTURE_PRO 0x4
	+#define LICENSED_APP_ID_SOLARCAPTURE_PRO 0x4
	/* enum: SolarSecure filter engine */
	-#define LICENSED_APP_ID_SOLARSECURE 0x8
	+#define LICENSED_APP_ID_SOLARSECURE 0x8
	/* enum: Performance monitor */
	-#define LICENSED_APP_ID_PERF_MONITOR 0x10
	+#define LICENSED_APP_ID_PERF_MONITOR 0x10
	/* enum: SolarCapture Live */
	-#define LICENSED_APP_ID_SOLARCAPTURE_LIVE 0x20
	+#define LICENSED_APP_ID_SOLARCAPTURE_LIVE 0x20
	/* enum: Capture SolarSystem */
	-#define LICENSED_APP_ID_CAPTURE_SOLARSYSTEM 0x40
	+#define LICENSED_APP_ID_CAPTURE_SOLARSYSTEM 0x40
	/* enum: Network Access Control */
	-#define LICENSED_APP_ID_NETWORK_ACCESS_CONTROL 0x80
	+#define LICENSED_APP_ID_NETWORK_ACCESS_CONTROL 0x80
	/* enum: TCP Direct */
	-#define LICENSED_APP_ID_TCP_DIRECT 0x100
	+#define LICENSED_APP_ID_TCP_DIRECT 0x100
	/* enum: Low Latency */
	-#define LICENSED_APP_ID_LOW_LATENCY 0x200
	+#define LICENSED_APP_ID_LOW_LATENCY 0x200
	/* enum: SolarCapture Tap */
	-#define LICENSED_APP_ID_SOLARCAPTURE_TAP 0x400
	+#define LICENSED_APP_ID_SOLARCAPTURE_TAP 0x400
	/* enum: Capture SolarSystem 40G */
	#define LICENSED_APP_ID_CAPTURE_SOLARSYSTEM_40G 0x800
	/* enum: Capture SolarSystem 1G */
	-#define LICENSED_APP_ID_CAPTURE_SOLARSYSTEM_1G 0x1000
	+#define LICENSED_APP_ID_CAPTURE_SOLARSYSTEM_1G 0x1000
	/* enum: ScaleOut Onload */
	-#define LICENSED_APP_ID_SCALEOUT_ONLOAD 0x2000
	+#define LICENSED_APP_ID_SCALEOUT_ONLOAD 0x2000
	/* enum: SCS Network Analytics Dashboard */
	-#define LICENSED_APP_ID_DSHBRD 0x4000
	+#define LICENSED_APP_ID_DSHBRD 0x4000
	/* enum: SolarCapture Trading Analytics */
	-#define LICENSED_APP_ID_SCATRD 0x8000
	+#define LICENSED_APP_ID_SCATRD 0x8000
	#define LICENSED_APP_ID_ID_LBN 0
	#define LICENSED_APP_ID_ID_WIDTH 32

	@@ -6849,23 +6906,23 @@
	#define TX_TIMESTAMP_EVENT_TX_EV_TYPE_OFST 3
	#define TX_TIMESTAMP_EVENT_TX_EV_TYPE_LEN 1
	/* enum: This is a TX completion event, not a timestamp */
	-#define TX_TIMESTAMP_EVENT_TX_EV_COMPLETION 0x0
	+#define TX_TIMESTAMP_EVENT_TX_EV_COMPLETION 0x0
	/* enum: This is a TX completion event for a CTPIO transmit. The event format
	* is the same as for TX_EV_COMPLETION.
	*/
	-#define TX_TIMESTAMP_EVENT_TX_EV_CTPIO_COMPLETION 0x11
	+#define TX_TIMESTAMP_EVENT_TX_EV_CTPIO_COMPLETION 0x11
	/* enum: This is the low part of a TX timestamp for a CTPIO transmission. The
	* event format is the same as for TX_EV_TSTAMP_LO
	*/
	-#define TX_TIMESTAMP_EVENT_TX_EV_CTPIO_TS_LO 0x12
	+#define TX_TIMESTAMP_EVENT_TX_EV_CTPIO_TS_LO 0x12
	/* enum: This is the high part of a TX timestamp for a CTPIO transmission. The
	* event format is the same as for TX_EV_TSTAMP_HI
	*/
	-#define TX_TIMESTAMP_EVENT_TX_EV_CTPIO_TS_HI 0x13
	+#define TX_TIMESTAMP_EVENT_TX_EV_CTPIO_TS_HI 0x13
	/* enum: This is the low part of a TX timestamp event */
	-#define TX_TIMESTAMP_EVENT_TX_EV_TSTAMP_LO 0x51
	+#define TX_TIMESTAMP_EVENT_TX_EV_TSTAMP_LO 0x51
	/* enum: This is the high part of a TX timestamp event */
	-#define TX_TIMESTAMP_EVENT_TX_EV_TSTAMP_HI 0x52
	+#define TX_TIMESTAMP_EVENT_TX_EV_TSTAMP_HI 0x52
	#define TX_TIMESTAMP_EVENT_TX_EV_TYPE_LBN 24
	#define TX_TIMESTAMP_EVENT_TX_EV_TYPE_WIDTH 8
	/* upper 16 bits of timestamp data */
	@@ -6908,7 +6965,43 @@
	#define CTPIO_STATS_MAP_BUCKET_LBN 16
	#define CTPIO_STATS_MAP_BUCKET_WIDTH 16

	+/* MESSAGE_TYPE structuredef: When present this defines the meaning of a
	+ * message, and is used to protect against chosen message attacks in signed
	+ * messages, regardless their origin. The message type also defines the
	+ * signature cryptographic algorithm, encoding, and message fields included in
	+ * the signature. The values are used in different commands but must be unique
	+ * across all commands, e.g. MC_CMD_TSA_BIND_IN_SECURE_UNBIND uses different
	+ * message type than MC_CMD_SECURE_NIC_INFO_IN_STATUS.
	+ */
	+#define MESSAGE_TYPE_LEN 4
	+#define MESSAGE_TYPE_MESSAGE_TYPE_OFST 0
	+#define MESSAGE_TYPE_MESSAGE_TYPE_LEN 4
	+#define MESSAGE_TYPE_UNUSED 0x0 /* enum */
	+/* enum: Message type value for the response to a
	+ * MC_CMD_TSA_BIND_IN_SECURE_UNBIND message. TSA_SECURE_UNBIND messages are
	+ * ECDSA SECP384R1 signed using SHA384 message digest algorithm over fields
	+ * MESSAGE_TYPE, TSANID, TSAID, and UNBINDTOKEN, and encoded as suggested by
	+ * RFC6979 (section 2.4).
	+ */
	+#define MESSAGE_TYPE_TSA_SECURE_UNBIND 0x1
	+/* enum: Message type value for the response to a
	+ * MC_CMD_TSA_BIND_IN_SECURE_DECOMMISSION message. TSA_SECURE_DECOMMISSION
	+ * messages are ECDSA SECP384R1 signed using SHA384 message digest algorithm
	+ * over fields MESSAGE_TYPE, TSAID, USER, and REASON, and encoded as suggested
	+ * by RFC6979 (section 2.4).
	+ */
	+#define MESSAGE_TYPE_TSA_SECURE_DECOMMISSION 0x2
	+/* enum: Message type value for the response to a
	+ * MC_CMD_SECURE_NIC_INFO_IN_STATUS message. This enum value is not sequential
	+ * to other message types for backwards compatibility as the message type for
	+ * MC_CMD_SECURE_NIC_INFO_IN_STATUS was defined before the existence of this
	+ * global enum.
	+ */
	+#define MESSAGE_TYPE_SECURE_NIC_INFO_STATUS 0xdb4
	+#define MESSAGE_TYPE_MESSAGE_TYPE_LBN 0
	+#define MESSAGE_TYPE_MESSAGE_TYPE_WIDTH 32

	+
	/***********************************/
	/* MC_CMD_READ_REGS
	* Get a dump of the MCPU registers
	@@ -7147,17 +7240,17 @@
	#define QUEUE_CRC_MODE_MODE_LBN 0
	#define QUEUE_CRC_MODE_MODE_WIDTH 4
	/* enum: No CRC. */
	-#define QUEUE_CRC_MODE_NONE 0x0
	+#define QUEUE_CRC_MODE_NONE 0x0
	/* enum: CRC Fiber channel over ethernet. */
	-#define QUEUE_CRC_MODE_FCOE 0x1
	+#define QUEUE_CRC_MODE_FCOE 0x1
	/* enum: CRC (digest) iSCSI header only. */
	-#define QUEUE_CRC_MODE_ISCSI_HDR 0x2
	+#define QUEUE_CRC_MODE_ISCSI_HDR 0x2
	/* enum: CRC (digest) iSCSI header and payload. */
	-#define QUEUE_CRC_MODE_ISCSI 0x3
	+#define QUEUE_CRC_MODE_ISCSI 0x3
	/* enum: CRC Fiber channel over IP over ethernet. */
	-#define QUEUE_CRC_MODE_FCOIPOE 0x4
	+#define QUEUE_CRC_MODE_FCOIPOE 0x4
	/* enum: CRC MPA. */
	-#define QUEUE_CRC_MODE_MPA 0x5
	+#define QUEUE_CRC_MODE_MPA 0x5
	#define QUEUE_CRC_MODE_SPARE_LBN 4
	#define QUEUE_CRC_MODE_SPARE_WIDTH 4

	@@ -7270,25 +7363,25 @@
	#define MC_CMD_INIT_RXQ_EXT_IN_DMA_MODE_LBN 10
	#define MC_CMD_INIT_RXQ_EXT_IN_DMA_MODE_WIDTH 4
	/* enum: One packet per descriptor (for normal networking) */
	-#define MC_CMD_INIT_RXQ_EXT_IN_SINGLE_PACKET 0x0
	+#define MC_CMD_INIT_RXQ_EXT_IN_SINGLE_PACKET 0x0
	/* enum: Pack multiple packets into large descriptors (for SolarCapture) */
	-#define MC_CMD_INIT_RXQ_EXT_IN_PACKED_STREAM 0x1
	+#define MC_CMD_INIT_RXQ_EXT_IN_PACKED_STREAM 0x1
	/* enum: Pack multiple packets into large descriptors using the format designed
	* to maximise packet rate. This mode uses 1 "bucket" per descriptor with
	* multiple fixed-size packet buffers within each bucket. For a full
	* description see SF-119419-TC. This mode is only supported by "dpdk" datapath
	* firmware.
	*/
	-#define MC_CMD_INIT_RXQ_EXT_IN_EQUAL_STRIDE_PACKED_STREAM 0x2
	+#define MC_CMD_INIT_RXQ_EXT_IN_EQUAL_STRIDE_PACKED_STREAM 0x2
	#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_SNAPSHOT_MODE_LBN 14
	#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_SNAPSHOT_MODE_WIDTH 1
	#define MC_CMD_INIT_RXQ_EXT_IN_PACKED_STREAM_BUFF_SIZE_LBN 15
	#define MC_CMD_INIT_RXQ_EXT_IN_PACKED_STREAM_BUFF_SIZE_WIDTH 3
	-#define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_1M 0x0 /* enum */
	-#define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_512K 0x1 /* enum */
	-#define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_256K 0x2 /* enum */
	-#define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_128K 0x3 /* enum */
	-#define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_64K 0x4 /* enum */
	+#define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_1M 0x0 /* enum */
	+#define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_512K 0x1 /* enum */
	+#define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_256K 0x2 /* enum */
	+#define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_128K 0x3 /* enum */
	+#define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_64K 0x4 /* enum */
	#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_WANT_OUTER_CLASSES_LBN 18
	#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_WANT_OUTER_CLASSES_WIDTH 1
	#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_FORCE_EV_MERGING_LBN 19
	@@ -7350,25 +7443,25 @@
	#define MC_CMD_INIT_RXQ_V3_IN_DMA_MODE_LBN 10
	#define MC_CMD_INIT_RXQ_V3_IN_DMA_MODE_WIDTH 4
	/* enum: One packet per descriptor (for normal networking) */
	-#define MC_CMD_INIT_RXQ_V3_IN_SINGLE_PACKET 0x0
	+#define MC_CMD_INIT_RXQ_V3_IN_SINGLE_PACKET 0x0
	/* enum: Pack multiple packets into large descriptors (for SolarCapture) */
	-#define MC_CMD_INIT_RXQ_V3_IN_PACKED_STREAM 0x1
	+#define MC_CMD_INIT_RXQ_V3_IN_PACKED_STREAM 0x1
	/* enum: Pack multiple packets into large descriptors using the format designed
	* to maximise packet rate. This mode uses 1 "bucket" per descriptor with
	* multiple fixed-size packet buffers within each bucket. For a full
	* description see SF-119419-TC. This mode is only supported by "dpdk" datapath
	* firmware.
	*/
	-#define MC_CMD_INIT_RXQ_V3_IN_EQUAL_STRIDE_PACKED_STREAM 0x2
	+#define MC_CMD_INIT_RXQ_V3_IN_EQUAL_STRIDE_PACKED_STREAM 0x2
	#define MC_CMD_INIT_RXQ_V3_IN_FLAG_SNAPSHOT_MODE_LBN 14
	#define MC_CMD_INIT_RXQ_V3_IN_FLAG_SNAPSHOT_MODE_WIDTH 1
	#define MC_CMD_INIT_RXQ_V3_IN_PACKED_STREAM_BUFF_SIZE_LBN 15
	#define MC_CMD_INIT_RXQ_V3_IN_PACKED_STREAM_BUFF_SIZE_WIDTH 3
	-#define MC_CMD_INIT_RXQ_V3_IN_PS_BUFF_1M 0x0 /* enum */
	-#define MC_CMD_INIT_RXQ_V3_IN_PS_BUFF_512K 0x1 /* enum */
	-#define MC_CMD_INIT_RXQ_V3_IN_PS_BUFF_256K 0x2 /* enum */
	-#define MC_CMD_INIT_RXQ_V3_IN_PS_BUFF_128K 0x3 /* enum */
	-#define MC_CMD_INIT_RXQ_V3_IN_PS_BUFF_64K 0x4 /* enum */
	+#define MC_CMD_INIT_RXQ_V3_IN_PS_BUFF_1M 0x0 /* enum */
	+#define MC_CMD_INIT_RXQ_V3_IN_PS_BUFF_512K 0x1 /* enum */
	+#define MC_CMD_INIT_RXQ_V3_IN_PS_BUFF_256K 0x2 /* enum */
	+#define MC_CMD_INIT_RXQ_V3_IN_PS_BUFF_128K 0x3 /* enum */
	+#define MC_CMD_INIT_RXQ_V3_IN_PS_BUFF_64K 0x4 /* enum */
	#define MC_CMD_INIT_RXQ_V3_IN_FLAG_WANT_OUTER_CLASSES_LBN 18
	#define MC_CMD_INIT_RXQ_V3_IN_FLAG_WANT_OUTER_CLASSES_WIDTH 1
	#define MC_CMD_INIT_RXQ_V3_IN_FLAG_FORCE_EV_MERGING_LBN 19
	@@ -7670,7 +7763,7 @@
	#define MC_CMD_PROXY_CMD_IN_TARGET_PF_WIDTH 16
	#define MC_CMD_PROXY_CMD_IN_TARGET_VF_LBN 16
	#define MC_CMD_PROXY_CMD_IN_TARGET_VF_WIDTH 16
	-#define MC_CMD_PROXY_CMD_IN_VF_NULL 0xffff /* enum */
	+#define MC_CMD_PROXY_CMD_IN_VF_NULL 0xffff /* enum */

	/* MC_CMD_PROXY_CMD_OUT msgresponse */
	#define MC_CMD_PROXY_CMD_OUT_LEN 0
	@@ -7683,7 +7776,7 @@
	#define MC_PROXY_STATUS_BUFFER_HANDLE_OFST 0
	#define MC_PROXY_STATUS_BUFFER_HANDLE_LEN 4
	/* enum: An invalid handle. */
	-#define MC_PROXY_STATUS_BUFFER_HANDLE_INVALID 0x0
	+#define MC_PROXY_STATUS_BUFFER_HANDLE_INVALID 0x0
	#define MC_PROXY_STATUS_BUFFER_HANDLE_LBN 0
	#define MC_PROXY_STATUS_BUFFER_HANDLE_WIDTH 32
	/* The requesting physical function number */
	@@ -7958,17 +8051,17 @@
	#define MC_CMD_FILTER_OP_IN_OP_OFST 0
	#define MC_CMD_FILTER_OP_IN_OP_LEN 4
	/* enum: single-recipient filter insert */
	-#define MC_CMD_FILTER_OP_IN_OP_INSERT 0x0
	+#define MC_CMD_FILTER_OP_IN_OP_INSERT 0x0
	/* enum: single-recipient filter remove */
	-#define MC_CMD_FILTER_OP_IN_OP_REMOVE 0x1
	+#define MC_CMD_FILTER_OP_IN_OP_REMOVE 0x1
	/* enum: multi-recipient filter subscribe */
	-#define MC_CMD_FILTER_OP_IN_OP_SUBSCRIBE 0x2
	+#define MC_CMD_FILTER_OP_IN_OP_SUBSCRIBE 0x2
	/* enum: multi-recipient filter unsubscribe */
	-#define MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE 0x3
	+#define MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE 0x3
	/* enum: replace one recipient with another (warning - the filter handle may
	* change)
	*/
	-#define MC_CMD_FILTER_OP_IN_OP_REPLACE 0x4
	+#define MC_CMD_FILTER_OP_IN_OP_REPLACE 0x4
	/* filter handle (for remove / unsubscribe operations) */
	#define MC_CMD_FILTER_OP_IN_HANDLE_OFST 4
	#define MC_CMD_FILTER_OP_IN_HANDLE_LEN 8
	@@ -8013,15 +8106,15 @@
	#define MC_CMD_FILTER_OP_IN_RX_DEST_OFST 20
	#define MC_CMD_FILTER_OP_IN_RX_DEST_LEN 4
	/* enum: drop packets */
	-#define MC_CMD_FILTER_OP_IN_RX_DEST_DROP 0x0
	+#define MC_CMD_FILTER_OP_IN_RX_DEST_DROP 0x0
	/* enum: receive to host */
	-#define MC_CMD_FILTER_OP_IN_RX_DEST_HOST 0x1
	+#define MC_CMD_FILTER_OP_IN_RX_DEST_HOST 0x1
	/* enum: receive to MC */
	-#define MC_CMD_FILTER_OP_IN_RX_DEST_MC 0x2
	+#define MC_CMD_FILTER_OP_IN_RX_DEST_MC 0x2
	/* enum: loop back to TXDP 0 */
	-#define MC_CMD_FILTER_OP_IN_RX_DEST_TX0 0x3
	+#define MC_CMD_FILTER_OP_IN_RX_DEST_TX0 0x3
	/* enum: loop back to TXDP 1 */
	-#define MC_CMD_FILTER_OP_IN_RX_DEST_TX1 0x4
	+#define MC_CMD_FILTER_OP_IN_RX_DEST_TX1 0x4
	/* receive queue handle (for multiple queue modes, this is the base queue) */
	#define MC_CMD_FILTER_OP_IN_RX_QUEUE_OFST 24
	#define MC_CMD_FILTER_OP_IN_RX_QUEUE_LEN 4
	@@ -8029,14 +8122,14 @@
	#define MC_CMD_FILTER_OP_IN_RX_MODE_OFST 28
	#define MC_CMD_FILTER_OP_IN_RX_MODE_LEN 4
	/* enum: receive to just the specified queue */
	-#define MC_CMD_FILTER_OP_IN_RX_MODE_SIMPLE 0x0
	+#define MC_CMD_FILTER_OP_IN_RX_MODE_SIMPLE 0x0
	/* enum: receive to multiple queues using RSS context */
	-#define MC_CMD_FILTER_OP_IN_RX_MODE_RSS 0x1
	+#define MC_CMD_FILTER_OP_IN_RX_MODE_RSS 0x1
	/* enum: receive to multiple queues using .1p mapping */
	-#define MC_CMD_FILTER_OP_IN_RX_MODE_DOT1P_MAPPING 0x2
	+#define MC_CMD_FILTER_OP_IN_RX_MODE_DOT1P_MAPPING 0x2
	/* enum: install a filter entry that will never match; for test purposes only
	*/
	-#define MC_CMD_FILTER_OP_IN_RX_MODE_TEST_NEVER_MATCH 0x80000000
	+#define MC_CMD_FILTER_OP_IN_RX_MODE_TEST_NEVER_MATCH 0x80000000
	/* RSS context (for RX_MODE_RSS) or .1p mapping handle (for
	* RX_MODE_DOT1P_MAPPING), as returned by MC_CMD_RSS_CONTEXT_ALLOC or
	* MC_CMD_DOT1P_MAPPING_ALLOC.
	@@ -8053,7 +8146,7 @@
	#define MC_CMD_FILTER_OP_IN_TX_DEST_OFST 40
	#define MC_CMD_FILTER_OP_IN_TX_DEST_LEN 4
	/* enum: request default behaviour (based on filter type) */
	-#define MC_CMD_FILTER_OP_IN_TX_DEST_DEFAULT 0xffffffff
	+#define MC_CMD_FILTER_OP_IN_TX_DEST_DEFAULT 0xffffffff
	#define MC_CMD_FILTER_OP_IN_TX_DEST_MAC_LBN 0
	#define MC_CMD_FILTER_OP_IN_TX_DEST_MAC_WIDTH 1
	#define MC_CMD_FILTER_OP_IN_TX_DEST_PM_LBN 1
	@@ -8181,15 +8274,15 @@
	#define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_OFST 20
	#define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_LEN 4
	/* enum: drop packets */
	-#define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_DROP 0x0
	+#define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_DROP 0x0
	/* enum: receive to host */
	-#define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_HOST 0x1
	+#define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_HOST 0x1
	/* enum: receive to MC */
	-#define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_MC 0x2
	+#define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_MC 0x2
	/* enum: loop back to TXDP 0 */
	-#define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_TX0 0x3
	+#define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_TX0 0x3
	/* enum: loop back to TXDP 1 */
	-#define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_TX1 0x4
	+#define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_TX1 0x4
	/* receive queue handle (for multiple queue modes, this is the base queue) */
	#define MC_CMD_FILTER_OP_EXT_IN_RX_QUEUE_OFST 24
	#define MC_CMD_FILTER_OP_EXT_IN_RX_QUEUE_LEN 4
	@@ -8197,14 +8290,14 @@
	#define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_OFST 28
	#define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_LEN 4
	/* enum: receive to just the specified queue */
	-#define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_SIMPLE 0x0
	+#define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_SIMPLE 0x0
	/* enum: receive to multiple queues using RSS context */
	-#define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_RSS 0x1
	+#define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_RSS 0x1
	/* enum: receive to multiple queues using .1p mapping */
	-#define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_DOT1P_MAPPING 0x2
	+#define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_DOT1P_MAPPING 0x2
	/* enum: install a filter entry that will never match; for test purposes only
	*/
	-#define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_TEST_NEVER_MATCH 0x80000000
	+#define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_TEST_NEVER_MATCH 0x80000000
	/* RSS context (for RX_MODE_RSS) or .1p mapping handle (for
	* RX_MODE_DOT1P_MAPPING), as returned by MC_CMD_RSS_CONTEXT_ALLOC or
	* MC_CMD_DOT1P_MAPPING_ALLOC.
	@@ -8221,7 +8314,7 @@
	#define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_OFST 40
	#define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_LEN 4
	/* enum: request default behaviour (based on filter type) */
	-#define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_DEFAULT 0xffffffff
	+#define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_DEFAULT 0xffffffff
	#define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_MAC_LBN 0
	#define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_MAC_WIDTH 1
	#define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_PM_LBN 1
	@@ -8264,17 +8357,17 @@
	#define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_LBN 24
	#define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_WIDTH 8
	/* enum: Match VXLAN traffic with this VNI */
	-#define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_VXLAN 0x0
	+#define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_VXLAN 0x0
	/* enum: Match Geneve traffic with this VNI */
	-#define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_GENEVE 0x1
	+#define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_GENEVE 0x1
	/* enum: Reserved for experimental development use */
	-#define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_EXPERIMENTAL 0xfe
	+#define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_EXPERIMENTAL 0xfe
	#define MC_CMD_FILTER_OP_EXT_IN_VSID_VALUE_LBN 0
	#define MC_CMD_FILTER_OP_EXT_IN_VSID_VALUE_WIDTH 24
	#define MC_CMD_FILTER_OP_EXT_IN_VSID_TYPE_LBN 24
	#define MC_CMD_FILTER_OP_EXT_IN_VSID_TYPE_WIDTH 8
	/* enum: Match NVGRE traffic with this VSID */
	-#define MC_CMD_FILTER_OP_EXT_IN_VSID_TYPE_NVGRE 0x0
	+#define MC_CMD_FILTER_OP_EXT_IN_VSID_TYPE_NVGRE 0x0
	/* source IP address to match (as bytes in network order; set last 12 bytes to
	* 0 for IPv4 address)
	*/
	@@ -8425,15 +8518,15 @@
	#define MC_CMD_FILTER_OP_V3_IN_RX_DEST_OFST 20
	#define MC_CMD_FILTER_OP_V3_IN_RX_DEST_LEN 4
	/* enum: drop packets */
	-#define MC_CMD_FILTER_OP_V3_IN_RX_DEST_DROP 0x0
	+#define MC_CMD_FILTER_OP_V3_IN_RX_DEST_DROP 0x0
	/* enum: receive to host */
	-#define MC_CMD_FILTER_OP_V3_IN_RX_DEST_HOST 0x1
	+#define MC_CMD_FILTER_OP_V3_IN_RX_DEST_HOST 0x1
	/* enum: receive to MC */
	-#define MC_CMD_FILTER_OP_V3_IN_RX_DEST_MC 0x2
	+#define MC_CMD_FILTER_OP_V3_IN_RX_DEST_MC 0x2
	/* enum: loop back to TXDP 0 */
	-#define MC_CMD_FILTER_OP_V3_IN_RX_DEST_TX0 0x3
	+#define MC_CMD_FILTER_OP_V3_IN_RX_DEST_TX0 0x3
	/* enum: loop back to TXDP 1 */
	-#define MC_CMD_FILTER_OP_V3_IN_RX_DEST_TX1 0x4
	+#define MC_CMD_FILTER_OP_V3_IN_RX_DEST_TX1 0x4
	/* receive queue handle (for multiple queue modes, this is the base queue) */
	#define MC_CMD_FILTER_OP_V3_IN_RX_QUEUE_OFST 24
	#define MC_CMD_FILTER_OP_V3_IN_RX_QUEUE_LEN 4
	@@ -8441,14 +8534,14 @@
	#define MC_CMD_FILTER_OP_V3_IN_RX_MODE_OFST 28
	#define MC_CMD_FILTER_OP_V3_IN_RX_MODE_LEN 4
	/* enum: receive to just the specified queue */
	-#define MC_CMD_FILTER_OP_V3_IN_RX_MODE_SIMPLE 0x0
	+#define MC_CMD_FILTER_OP_V3_IN_RX_MODE_SIMPLE 0x0
	/* enum: receive to multiple queues using RSS context */
	-#define MC_CMD_FILTER_OP_V3_IN_RX_MODE_RSS 0x1
	+#define MC_CMD_FILTER_OP_V3_IN_RX_MODE_RSS 0x1
	/* enum: receive to multiple queues using .1p mapping */
	-#define MC_CMD_FILTER_OP_V3_IN_RX_MODE_DOT1P_MAPPING 0x2
	+#define MC_CMD_FILTER_OP_V3_IN_RX_MODE_DOT1P_MAPPING 0x2
	/* enum: install a filter entry that will never match; for test purposes only
	*/
	-#define MC_CMD_FILTER_OP_V3_IN_RX_MODE_TEST_NEVER_MATCH 0x80000000
	+#define MC_CMD_FILTER_OP_V3_IN_RX_MODE_TEST_NEVER_MATCH 0x80000000
	/* RSS context (for RX_MODE_RSS) or .1p mapping handle (for
	* RX_MODE_DOT1P_MAPPING), as returned by MC_CMD_RSS_CONTEXT_ALLOC or
	* MC_CMD_DOT1P_MAPPING_ALLOC.
	@@ -8465,7 +8558,7 @@
	#define MC_CMD_FILTER_OP_V3_IN_TX_DEST_OFST 40
	#define MC_CMD_FILTER_OP_V3_IN_TX_DEST_LEN 4
	/* enum: request default behaviour (based on filter type) */
	-#define MC_CMD_FILTER_OP_V3_IN_TX_DEST_DEFAULT 0xffffffff
	+#define MC_CMD_FILTER_OP_V3_IN_TX_DEST_DEFAULT 0xffffffff
	#define MC_CMD_FILTER_OP_V3_IN_TX_DEST_MAC_LBN 0
	#define MC_CMD_FILTER_OP_V3_IN_TX_DEST_MAC_WIDTH 1
	#define MC_CMD_FILTER_OP_V3_IN_TX_DEST_PM_LBN 1
	@@ -8508,17 +8601,17 @@
	#define MC_CMD_FILTER_OP_V3_IN_VNI_TYPE_LBN 24
	#define MC_CMD_FILTER_OP_V3_IN_VNI_TYPE_WIDTH 8
	/* enum: Match VXLAN traffic with this VNI */
	-#define MC_CMD_FILTER_OP_V3_IN_VNI_TYPE_VXLAN 0x0
	+#define MC_CMD_FILTER_OP_V3_IN_VNI_TYPE_VXLAN 0x0
	/* enum: Match Geneve traffic with this VNI */
	-#define MC_CMD_FILTER_OP_V3_IN_VNI_TYPE_GENEVE 0x1
	+#define MC_CMD_FILTER_OP_V3_IN_VNI_TYPE_GENEVE 0x1
	/* enum: Reserved for experimental development use */
	-#define MC_CMD_FILTER_OP_V3_IN_VNI_TYPE_EXPERIMENTAL 0xfe
	+#define MC_CMD_FILTER_OP_V3_IN_VNI_TYPE_EXPERIMENTAL 0xfe
	#define MC_CMD_FILTER_OP_V3_IN_VSID_VALUE_LBN 0
	#define MC_CMD_FILTER_OP_V3_IN_VSID_VALUE_WIDTH 24
	#define MC_CMD_FILTER_OP_V3_IN_VSID_TYPE_LBN 24
	#define MC_CMD_FILTER_OP_V3_IN_VSID_TYPE_WIDTH 8
	/* enum: Match NVGRE traffic with this VSID */
	-#define MC_CMD_FILTER_OP_V3_IN_VSID_TYPE_NVGRE 0x0
	+#define MC_CMD_FILTER_OP_V3_IN_VSID_TYPE_NVGRE 0x0
	/* source IP address to match (as bytes in network order; set last 12 bytes to
	* 0 for IPv4 address)
	*/
	@@ -8593,17 +8686,17 @@
	#define MC_CMD_FILTER_OP_V3_IN_MATCH_ACTION_OFST 172
	#define MC_CMD_FILTER_OP_V3_IN_MATCH_ACTION_LEN 4
	/* enum: do nothing extra */
	-#define MC_CMD_FILTER_OP_V3_IN_MATCH_ACTION_NONE 0x0
	+#define MC_CMD_FILTER_OP_V3_IN_MATCH_ACTION_NONE 0x0
	/* enum: Set the match flag in the packet prefix for packets matching the
	* filter (only with dpdk firmware, otherwise fails with ENOTSUP). Used to
	* support the DPDK rte_flow "FLAG" action.
	*/
	-#define MC_CMD_FILTER_OP_V3_IN_MATCH_ACTION_FLAG 0x1
	+#define MC_CMD_FILTER_OP_V3_IN_MATCH_ACTION_FLAG 0x1
	/* enum: Insert MATCH_MARK_VALUE into the packet prefix for packets matching
	* the filter (only with dpdk firmware, otherwise fails with ENOTSUP). Used to
	* support the DPDK rte_flow "MARK" action.
	*/
	-#define MC_CMD_FILTER_OP_V3_IN_MATCH_ACTION_MARK 0x2
	+#define MC_CMD_FILTER_OP_V3_IN_MATCH_ACTION_MARK 0x2
	/* the mark value for MATCH_ACTION_MARK */
	#define MC_CMD_FILTER_OP_V3_IN_MATCH_MARK_VALUE_OFST 176
	#define MC_CMD_FILTER_OP_V3_IN_MATCH_MARK_VALUE_LEN 4
	@@ -8624,9 +8717,9 @@
	#define MC_CMD_FILTER_OP_OUT_HANDLE_LO_OFST 4
	#define MC_CMD_FILTER_OP_OUT_HANDLE_HI_OFST 8
	/* enum: guaranteed invalid filter handle (low 32 bits) */
	-#define MC_CMD_FILTER_OP_OUT_HANDLE_LO_INVALID 0xffffffff
	+#define MC_CMD_FILTER_OP_OUT_HANDLE_LO_INVALID 0xffffffff
	/* enum: guaranteed invalid filter handle (high 32 bits) */
	-#define MC_CMD_FILTER_OP_OUT_HANDLE_HI_INVALID 0xffffffff
	+#define MC_CMD_FILTER_OP_OUT_HANDLE_HI_INVALID 0xffffffff

	/* MC_CMD_FILTER_OP_EXT_OUT msgresponse */
	#define MC_CMD_FILTER_OP_EXT_OUT_LEN 12
	@@ -8662,20 +8755,20 @@
	#define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_OFST 0
	#define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_LEN 4
	/* enum: read the list of supported RX filter matches */
	-#define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_RX_MATCHES 0x1
	+#define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_RX_MATCHES 0x1
	/* enum: read flags indicating restrictions on filter insertion for the calling
	* client
	*/
	-#define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_RESTRICTIONS 0x2
	+#define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_RESTRICTIONS 0x2
	/* enum: read properties relating to security rules (Medford-only; for use by
	* SolarSecure apps, not directly by drivers. See SF-114946-SW.)
	*/
	-#define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SECURITY_RULE_INFO 0x3
	+#define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SECURITY_RULE_INFO 0x3
	/* enum: read the list of supported RX filter matches for VXLAN/NVGRE
	* encapsulated frames, which follow a different match sequence to normal
	* frames (Medford only)
	*/
	-#define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_ENCAP_RX_MATCHES 0x4
	+#define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_ENCAP_RX_MATCHES 0x4

	/* MC_CMD_GET_PARSER_DISP_INFO_OUT msgresponse */
	#define MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMIN 8
	@@ -8729,7 +8822,7 @@
	#define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_RULES_VERSION_OFST 4
	#define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_RULES_VERSION_LEN 4
	/* enum: implements lookup sequences described in SF-114946-SW draft C */
	-#define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_RULES_VERSION_SF_114946_SW_C 0x0
	+#define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_RULES_VERSION_SF_114946_SW_C 0x0
	/* the number of nodes in the subnet map */
	#define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_SUBNET_MAP_NUM_NODES_OFST 8
	#define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_SUBNET_MAP_NUM_NODES_LEN 4
	@@ -8773,36 +8866,36 @@
	#define MC_CMD_PARSER_DISP_RW_IN_TARGET_OFST 0
	#define MC_CMD_PARSER_DISP_RW_IN_TARGET_LEN 4
	/* enum: RX dispatcher CPU */
	-#define MC_CMD_PARSER_DISP_RW_IN_RX_DICPU 0x0
	+#define MC_CMD_PARSER_DISP_RW_IN_RX_DICPU 0x0
	/* enum: TX dispatcher CPU */
	-#define MC_CMD_PARSER_DISP_RW_IN_TX_DICPU 0x1
	+#define MC_CMD_PARSER_DISP_RW_IN_TX_DICPU 0x1
	/* enum: Lookup engine (with original metadata format). Deprecated; used only
	* by cmdclient as a fallback for very old Huntington firmware, and not
	* supported in firmware beyond v6.4.0.1005. Use LUE_VERSIONED_METADATA
	* instead.
	*/
	-#define MC_CMD_PARSER_DISP_RW_IN_LUE 0x2
	+#define MC_CMD_PARSER_DISP_RW_IN_LUE 0x2
	/* enum: Lookup engine (with requested metadata format) */
	-#define MC_CMD_PARSER_DISP_RW_IN_LUE_VERSIONED_METADATA 0x3
	+#define MC_CMD_PARSER_DISP_RW_IN_LUE_VERSIONED_METADATA 0x3
	/* enum: RX0 dispatcher CPU (alias for RX_DICPU; Medford has 2 RX DICPUs) */
	-#define MC_CMD_PARSER_DISP_RW_IN_RX0_DICPU 0x0
	+#define MC_CMD_PARSER_DISP_RW_IN_RX0_DICPU 0x0
	/* enum: RX1 dispatcher CPU (only valid for Medford) */
	-#define MC_CMD_PARSER_DISP_RW_IN_RX1_DICPU 0x4
	+#define MC_CMD_PARSER_DISP_RW_IN_RX1_DICPU 0x4
	/* enum: Miscellaneous other state (only valid for Medford) */
	-#define MC_CMD_PARSER_DISP_RW_IN_MISC_STATE 0x5
	+#define MC_CMD_PARSER_DISP_RW_IN_MISC_STATE 0x5
	/* identifies the type of operation requested */
	#define MC_CMD_PARSER_DISP_RW_IN_OP_OFST 4
	#define MC_CMD_PARSER_DISP_RW_IN_OP_LEN 4
	/* enum: Read a word of DICPU DMEM or a LUE entry */
	-#define MC_CMD_PARSER_DISP_RW_IN_READ 0x0
	+#define MC_CMD_PARSER_DISP_RW_IN_READ 0x0
	/* enum: Write a word of DICPU DMEM or a LUE entry. Not permitted on
	* tamperproof adapters.
	*/
	-#define MC_CMD_PARSER_DISP_RW_IN_WRITE 0x1
	+#define MC_CMD_PARSER_DISP_RW_IN_WRITE 0x1
	/* enum: Read-modify-write a word of DICPU DMEM (not valid for LUE). Not
	* permitted on tamperproof adapters.
	*/
	-#define MC_CMD_PARSER_DISP_RW_IN_RMW 0x2
	+#define MC_CMD_PARSER_DISP_RW_IN_RMW 0x2
	/* data memory address (DICPU targets) or LUE index (LUE targets) */
	#define MC_CMD_PARSER_DISP_RW_IN_ADDRESS_OFST 8
	#define MC_CMD_PARSER_DISP_RW_IN_ADDRESS_LEN 4
	@@ -8810,7 +8903,7 @@
	#define MC_CMD_PARSER_DISP_RW_IN_SELECTOR_OFST 8
	#define MC_CMD_PARSER_DISP_RW_IN_SELECTOR_LEN 4
	/* enum: Port to datapath mapping */
	-#define MC_CMD_PARSER_DISP_RW_IN_PORT_DP_MAPPING 0x1
	+#define MC_CMD_PARSER_DISP_RW_IN_PORT_DP_MAPPING 0x1
	/* value to write (for DMEM writes) */
	#define MC_CMD_PARSER_DISP_RW_IN_DMEM_WRITE_VALUE_OFST 12
	#define MC_CMD_PARSER_DISP_RW_IN_DMEM_WRITE_VALUE_LEN 4
	@@ -8844,8 +8937,8 @@
	#define MC_CMD_PARSER_DISP_RW_OUT_PORT_DP_MAPPING_OFST 0
	#define MC_CMD_PARSER_DISP_RW_OUT_PORT_DP_MAPPING_LEN 4
	#define MC_CMD_PARSER_DISP_RW_OUT_PORT_DP_MAPPING_NUM 4
	-#define MC_CMD_PARSER_DISP_RW_OUT_DP0 0x1 /* enum */
	-#define MC_CMD_PARSER_DISP_RW_OUT_DP1 0x2 /* enum */
	+#define MC_CMD_PARSER_DISP_RW_OUT_DP0 0x1 /* enum */
	+#define MC_CMD_PARSER_DISP_RW_OUT_DP1 0x2 /* enum */


	/***********************************/
	@@ -9324,13 +9417,13 @@
	#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_OFST 0
	#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_LEN 4
	/* enum: MISC. */
	-#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_MISC 0x0
	+#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_MISC 0x0
	/* enum: IDO. */
	-#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_IDO 0x1
	+#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_IDO 0x1
	/* enum: RO. */
	-#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_RO 0x2
	+#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_RO 0x2
	/* enum: TPH Type. */
	-#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_TPH_TYPE 0x3
	+#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_TPH_TYPE 0x3

	/* MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT msgresponse */
	#define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_LEN 8
	@@ -9435,7 +9528,7 @@
	#define MC_CMD_SATELLITE_DOWNLOAD 0x91
	#undef MC_CMD_0x91_PRIVILEGE_CTG

	-#define MC_CMD_0x91_PRIVILEGE_CTG SRIOV_CTG_ADMIN
	+#define MC_CMD_0x91_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND

	/* MC_CMD_SATELLITE_DOWNLOAD_IN msgrequest: The reset requirements for the CPUs
	* are subtle, and so downloads must proceed in a number of phases.
	@@ -9463,57 +9556,57 @@
	*/
	#define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_OFST 0
	#define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_LEN 4
	-#define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_IDLE 0x0 /* enum */
	-#define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_RESET 0x1 /* enum */
	-#define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_IMEMS 0x2 /* enum */
	-#define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_VECTORS 0x3 /* enum */
	-#define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_READY 0x4 /* enum */
	+#define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_IDLE 0x0 /* enum */
	+#define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_RESET 0x1 /* enum */
	+#define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_IMEMS 0x2 /* enum */
	+#define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_VECTORS 0x3 /* enum */
	+#define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_READY 0x4 /* enum */
	/* Target for download. (These match the blob numbers defined in
	* mc_flash_layout.h.)
	*/
	#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_OFST 4
	#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_LEN 4
	/* enum: Valid in phase 2 (PHASE_IMEMS) only */
	-#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDI_TEXT 0x0
	+#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDI_TEXT 0x0
	/* enum: Valid in phase 2 (PHASE_IMEMS) only */
	-#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDI_TEXT 0x1
	+#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDI_TEXT 0x1
	/* enum: Valid in phase 2 (PHASE_IMEMS) only */
	-#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDP_TEXT 0x2
	+#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDP_TEXT 0x2
	/* enum: Valid in phase 2 (PHASE_IMEMS) only */
	-#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDP_TEXT 0x3
	+#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDP_TEXT 0x3
	/* enum: Valid in phase 2 (PHASE_IMEMS) only */
	-#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_HR_LUT 0x4
	+#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_HR_LUT 0x4
	/* enum: Valid in phase 2 (PHASE_IMEMS) only */
	-#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_HR_LUT_CFG 0x5
	+#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_HR_LUT_CFG 0x5
	/* enum: Valid in phase 2 (PHASE_IMEMS) only */
	-#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_HR_LUT 0x6
	+#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_HR_LUT 0x6
	/* enum: Valid in phase 2 (PHASE_IMEMS) only */
	-#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_HR_LUT_CFG 0x7
	+#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_HR_LUT_CFG 0x7
	/* enum: Valid in phase 2 (PHASE_IMEMS) only */
	-#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_HR_PGM 0x8
	+#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_HR_PGM 0x8
	/* enum: Valid in phase 2 (PHASE_IMEMS) only */
	-#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_SL_PGM 0x9
	+#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_SL_PGM 0x9
	/* enum: Valid in phase 2 (PHASE_IMEMS) only */
	-#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_HR_PGM 0xa
	+#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_HR_PGM 0xa
	/* enum: Valid in phase 2 (PHASE_IMEMS) only */
	-#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_SL_PGM 0xb
	+#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_SL_PGM 0xb
	/* enum: Valid in phase 3 (PHASE_VECTORS) only */
	-#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDI_VTBL0 0xc
	+#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDI_VTBL0 0xc
	/* enum: Valid in phase 3 (PHASE_VECTORS) only */
	-#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDI_VTBL0 0xd
	+#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDI_VTBL0 0xd
	/* enum: Valid in phase 3 (PHASE_VECTORS) only */
	-#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDI_VTBL1 0xe
	+#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDI_VTBL1 0xe
	/* enum: Valid in phase 3 (PHASE_VECTORS) only */
	-#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDI_VTBL1 0xf
	+#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDI_VTBL1 0xf
	/* enum: Valid in phases 1 (PHASE_RESET) and 4 (PHASE_READY) only */
	-#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_ALL 0xffffffff
	+#define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_ALL 0xffffffff
	/* Chunk ID, or CHUNK_ID_LAST or CHUNK_ID_ABORT */
	#define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_ID_OFST 8
	#define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_ID_LEN 4
	/* enum: Last chunk, containing checksum rather than data */
	-#define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_ID_LAST 0xffffffff
	+#define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_ID_LAST 0xffffffff
	/* enum: Abort download of this item */
	-#define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_ID_ABORT 0xfffffffe
	+#define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_ID_ABORT 0xfffffffe
	/* Length of this chunk in bytes */
	#define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_LEN_OFST 12
	#define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_LEN_LEN 4
	@@ -9532,21 +9625,21 @@
	#define MC_CMD_SATELLITE_DOWNLOAD_OUT_INFO_OFST 4
	#define MC_CMD_SATELLITE_DOWNLOAD_OUT_INFO_LEN 4
	/* enum: Code download OK, completed. */
	-#define MC_CMD_SATELLITE_DOWNLOAD_OUT_OK_COMPLETE 0x0
	+#define MC_CMD_SATELLITE_DOWNLOAD_OUT_OK_COMPLETE 0x0
	/* enum: Code download aborted as requested. */
	-#define MC_CMD_SATELLITE_DOWNLOAD_OUT_OK_ABORTED 0x1
	+#define MC_CMD_SATELLITE_DOWNLOAD_OUT_OK_ABORTED 0x1
	/* enum: Code download OK so far, send next chunk. */
	-#define MC_CMD_SATELLITE_DOWNLOAD_OUT_OK_NEXT_CHUNK 0x2
	+#define MC_CMD_SATELLITE_DOWNLOAD_OUT_OK_NEXT_CHUNK 0x2
	/* enum: Download phases out of sequence */
	-#define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_PHASE 0x100
	+#define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_PHASE 0x100
	/* enum: Bad target for this phase */
	-#define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_TARGET 0x101
	+#define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_TARGET 0x101
	/* enum: Chunk ID out of sequence */
	-#define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_CHUNK_ID 0x200
	+#define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_CHUNK_ID 0x200
	/* enum: Chunk length zero or too large */
	-#define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_CHUNK_LEN 0x201
	+#define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_CHUNK_LEN 0x201
	/* enum: Checksum was incorrect */
	-#define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_CHECKSUM 0x300
	+#define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_CHECKSUM 0x300


	/***********************************/
	@@ -9631,58 +9724,58 @@
	#define MC_CMD_GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID_OFST 4
	#define MC_CMD_GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID_LEN 2
	/* enum: Standard RXDP firmware */
	-#define MC_CMD_GET_CAPABILITIES_OUT_RXDP 0x0
	+#define MC_CMD_GET_CAPABILITIES_OUT_RXDP 0x0
	/* enum: Low latency RXDP firmware */
	-#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_LOW_LATENCY 0x1
	+#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_LOW_LATENCY 0x1
	/* enum: Packed stream RXDP firmware */
	-#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_PACKED_STREAM 0x2
	+#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_PACKED_STREAM 0x2
	/* enum: Rules engine RXDP firmware */
	-#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_RULES_ENGINE 0x5
	-/* enum: Packet rate RXDP firmware */
	-#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_DPDK 0x6
	+#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_RULES_ENGINE 0x5
	+/* enum: DPDK RXDP firmware */
	+#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_DPDK 0x6
	/* enum: BIST RXDP firmware */
	-#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_BIST 0x10a
	+#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_BIST 0x10a
	/* enum: RXDP Test firmware image 1 */
	-#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101
	+#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101
	/* enum: RXDP Test firmware image 2 */
	-#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102
	+#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102
	/* enum: RXDP Test firmware image 3 */
	-#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103
	+#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103
	/* enum: RXDP Test firmware image 4 */
	-#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104
	+#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104
	/* enum: RXDP Test firmware image 5 */
	-#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_BACKPRESSURE 0x105
	+#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_BACKPRESSURE 0x105
	/* enum: RXDP Test firmware image 6 */
	-#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106
	+#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106
	/* enum: RXDP Test firmware image 7 */
	-#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107
	+#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107
	/* enum: RXDP Test firmware image 8 */
	-#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_DISABLE_DL 0x108
	+#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_DISABLE_DL 0x108
	/* enum: RXDP Test firmware image 9 */
	-#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b
	+#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b
	/* enum: RXDP Test firmware image 10 */
	-#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_SLOW 0x10c
	+#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_SLOW 0x10c
	/* TxDPCPU firmware id. */
	#define MC_CMD_GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID_OFST 6
	#define MC_CMD_GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID_LEN 2
	/* enum: Standard TXDP firmware */
	-#define MC_CMD_GET_CAPABILITIES_OUT_TXDP 0x0
	+#define MC_CMD_GET_CAPABILITIES_OUT_TXDP 0x0
	/* enum: Low latency TXDP firmware */
	-#define MC_CMD_GET_CAPABILITIES_OUT_TXDP_LOW_LATENCY 0x1
	+#define MC_CMD_GET_CAPABILITIES_OUT_TXDP_LOW_LATENCY 0x1
	/* enum: High packet rate TXDP firmware */
	-#define MC_CMD_GET_CAPABILITIES_OUT_TXDP_HIGH_PACKET_RATE 0x3
	+#define MC_CMD_GET_CAPABILITIES_OUT_TXDP_HIGH_PACKET_RATE 0x3
	/* enum: Rules engine TXDP firmware */
	-#define MC_CMD_GET_CAPABILITIES_OUT_TXDP_RULES_ENGINE 0x5
	-/* enum: Packet rate TXDP firmware */
	-#define MC_CMD_GET_CAPABILITIES_OUT_TXDP_DPDK 0x6
	+#define MC_CMD_GET_CAPABILITIES_OUT_TXDP_RULES_ENGINE 0x5
	+/* enum: DPDK TXDP firmware */
	+#define MC_CMD_GET_CAPABILITIES_OUT_TXDP_DPDK 0x6
	/* enum: BIST TXDP firmware */
	-#define MC_CMD_GET_CAPABILITIES_OUT_TXDP_BIST 0x12d
	+#define MC_CMD_GET_CAPABILITIES_OUT_TXDP_BIST 0x12d
	/* enum: TXDP Test firmware image 1 */
	-#define MC_CMD_GET_CAPABILITIES_OUT_TXDP_TEST_FW_TSO_EDIT 0x101
	+#define MC_CMD_GET_CAPABILITIES_OUT_TXDP_TEST_FW_TSO_EDIT 0x101
	/* enum: TXDP Test firmware image 2 */
	-#define MC_CMD_GET_CAPABILITIES_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102
	+#define MC_CMD_GET_CAPABILITIES_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102
	/* enum: TXDP CSR bus test firmware */
	-#define MC_CMD_GET_CAPABILITIES_OUT_TXDP_TEST_FW_CSR 0x103
	+#define MC_CMD_GET_CAPABILITIES_OUT_TXDP_TEST_FW_CSR 0x103
	#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_OFST 8
	#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_LEN 2
	#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_REV_LBN 0
	@@ -9692,43 +9785,43 @@
	/* enum: reserved value - do not use (may indicate alternative interpretation
	* of REV field in future)
	*/
	-#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_RESERVED 0x0
	+#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_RESERVED 0x0
	/* enum: Trivial RX PD firmware for early Huntington development (Huntington
	* development only)
	*/
	-#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1
	+#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1
	/* enum: RX PD firmware with approximately Siena-compatible behaviour
	* (Huntington development only)
	*/
	-#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2
	+#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2
	/* enum: Full featured RX PD production firmware */
	-#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3
	+#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3
	/* enum: (deprecated original name for the FULL_FEATURED variant) */
	-#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_VSWITCH 0x3
	+#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_VSWITCH 0x3
	/* enum: siena_compat variant RX PD firmware using PM rather than MAC
	* (Huntington development only)
	*/
	-#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
	+#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
	/* enum: Low latency RX PD production firmware */
	-#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5
	+#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5
	/* enum: Packed stream RX PD production firmware */
	-#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6
	+#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6
	/* enum: RX PD firmware handling layer 2 only for high packet rate performance
	* tests (Medford development only)
	*/
	-#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7
	+#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7
	/* enum: Rules engine RX PD production firmware */
	-#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8
	-/* enum: reserved value - do not use (bug69716) */
	-#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_RESERVED_9 0x9
	-/* enum: Packet rate RX PD production firmware */
	-#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_DPDK 0xa
	+#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8
	+/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
	+#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_L3XUDP 0x9
	+/* enum: DPDK RX PD production firmware */
	+#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_DPDK 0xa
	/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
	-#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
	+#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
	/* enum: RX PD firmware parsing but not filtering network overlay tunnel
	* encapsulations (Medford development only)
	*/
	-#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf
	+#define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf
	#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_OFST 10
	#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_LEN 2
	#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_REV_LBN 0
	@@ -9738,36 +9831,36 @@
	/* enum: reserved value - do not use (may indicate alternative interpretation
	* of REV field in future)
	*/
	-#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_RESERVED 0x0
	+#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_RESERVED 0x0
	/* enum: Trivial TX PD firmware for early Huntington development (Huntington
	* development only)
	*/
	-#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1
	+#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1
	/* enum: TX PD firmware with approximately Siena-compatible behaviour
	* (Huntington development only)
	*/
	-#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2
	+#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2
	/* enum: Full featured TX PD production firmware */
	-#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3
	+#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3
	/* enum: (deprecated original name for the FULL_FEATURED variant) */
	-#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_VSWITCH 0x3
	+#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_VSWITCH 0x3
	/* enum: siena_compat variant TX PD firmware using PM rather than MAC
	* (Huntington development only)
	*/
	-#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
	-#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */
	+#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
	+#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */
	/* enum: TX PD firmware handling layer 2 only for high packet rate performance
	* tests (Medford development only)
	*/
	-#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7
	+#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7
	/* enum: Rules engine TX PD production firmware */
	-#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8
	-/* enum: reserved value - do not use (bug69716) */
	-#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_RESERVED_9 0x9
	-/* enum: Packet rate TX PD production firmware */
	-#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_DPDK 0xa
	+#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8
	+/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
	+#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_L3XUDP 0x9
	+/* enum: DPDK TX PD production firmware */
	+#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_DPDK 0xa
	/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
	-#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
	+#define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
	/* Hardware capabilities of NIC */
	#define MC_CMD_GET_CAPABILITIES_OUT_HW_CAPABILITIES_OFST 12
	#define MC_CMD_GET_CAPABILITIES_OUT_HW_CAPABILITIES_LEN 4
	@@ -9845,58 +9938,58 @@
	#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DPCPU_FW_ID_OFST 4
	#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DPCPU_FW_ID_LEN 2
	/* enum: Standard RXDP firmware */
	-#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP 0x0
	+#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP 0x0
	/* enum: Low latency RXDP firmware */
	-#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_LOW_LATENCY 0x1
	+#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_LOW_LATENCY 0x1
	/* enum: Packed stream RXDP firmware */
	-#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_PACKED_STREAM 0x2
	+#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_PACKED_STREAM 0x2
	/* enum: Rules engine RXDP firmware */
	-#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_RULES_ENGINE 0x5
	-/* enum: Packet rate RXDP firmware */
	-#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_DPDK 0x6
	+#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_RULES_ENGINE 0x5
	+/* enum: DPDK RXDP firmware */
	+#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_DPDK 0x6
	/* enum: BIST RXDP firmware */
	-#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_BIST 0x10a
	+#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_BIST 0x10a
	/* enum: RXDP Test firmware image 1 */
	-#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101
	+#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101
	/* enum: RXDP Test firmware image 2 */
	-#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102
	+#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102
	/* enum: RXDP Test firmware image 3 */
	-#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103
	+#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103
	/* enum: RXDP Test firmware image 4 */
	-#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104
	+#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104
	/* enum: RXDP Test firmware image 5 */
	-#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_BACKPRESSURE 0x105
	+#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_BACKPRESSURE 0x105
	/* enum: RXDP Test firmware image 6 */
	-#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106
	+#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106
	/* enum: RXDP Test firmware image 7 */
	-#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107
	+#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107
	/* enum: RXDP Test firmware image 8 */
	-#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_DISABLE_DL 0x108
	+#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_DISABLE_DL 0x108
	/* enum: RXDP Test firmware image 9 */
	-#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b
	+#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b
	/* enum: RXDP Test firmware image 10 */
	-#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_SLOW 0x10c
	+#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_SLOW 0x10c
	/* TxDPCPU firmware id. */
	#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_DPCPU_FW_ID_OFST 6
	#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_DPCPU_FW_ID_LEN 2
	/* enum: Standard TXDP firmware */
	-#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP 0x0
	+#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP 0x0
	/* enum: Low latency TXDP firmware */
	-#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_LOW_LATENCY 0x1
	+#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_LOW_LATENCY 0x1
	/* enum: High packet rate TXDP firmware */
	-#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_HIGH_PACKET_RATE 0x3
	+#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_HIGH_PACKET_RATE 0x3
	/* enum: Rules engine TXDP firmware */
	-#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_RULES_ENGINE 0x5
	-/* enum: Packet rate TXDP firmware */
	-#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_DPDK 0x6
	+#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_RULES_ENGINE 0x5
	+/* enum: DPDK TXDP firmware */
	+#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_DPDK 0x6
	/* enum: BIST TXDP firmware */
	-#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_BIST 0x12d
	+#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_BIST 0x12d
	/* enum: TXDP Test firmware image 1 */
	-#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_TEST_FW_TSO_EDIT 0x101
	+#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_TEST_FW_TSO_EDIT 0x101
	/* enum: TXDP Test firmware image 2 */
	-#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102
	+#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102
	/* enum: TXDP CSR bus test firmware */
	-#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_TEST_FW_CSR 0x103
	+#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_TEST_FW_CSR 0x103
	#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_OFST 8
	#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_LEN 2
	#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_REV_LBN 0
	@@ -9906,43 +9999,43 @@
	/* enum: reserved value - do not use (may indicate alternative interpretation
	* of REV field in future)
	*/
	-#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_RESERVED 0x0
	+#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_RESERVED 0x0
	/* enum: Trivial RX PD firmware for early Huntington development (Huntington
	* development only)
	*/
	-#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1
	+#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1
	/* enum: RX PD firmware with approximately Siena-compatible behaviour
	* (Huntington development only)
	*/
	-#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2
	+#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2
	/* enum: Full featured RX PD production firmware */
	-#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3
	+#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3
	/* enum: (deprecated original name for the FULL_FEATURED variant) */
	-#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_VSWITCH 0x3
	+#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_VSWITCH 0x3
	/* enum: siena_compat variant RX PD firmware using PM rather than MAC
	* (Huntington development only)
	*/
	-#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
	+#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
	/* enum: Low latency RX PD production firmware */
	-#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5
	+#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5
	/* enum: Packed stream RX PD production firmware */
	-#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6
	+#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6
	/* enum: RX PD firmware handling layer 2 only for high packet rate performance
	* tests (Medford development only)
	*/
	-#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7
	+#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7
	/* enum: Rules engine RX PD production firmware */
	-#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8
	-/* enum: reserved value - do not use (bug69716) */
	-#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_RESERVED_9 0x9
	-/* enum: Packet rate RX PD production firmware */
	-#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_DPDK 0xa
	+#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8
	+/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
	+#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_L3XUDP 0x9
	+/* enum: DPDK RX PD production firmware */
	+#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_DPDK 0xa
	/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
	-#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
	+#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
	/* enum: RX PD firmware parsing but not filtering network overlay tunnel
	* encapsulations (Medford development only)
	*/
	-#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf
	+#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf
	#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_OFST 10
	#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_LEN 2
	#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_REV_LBN 0
	@@ -9952,36 +10045,36 @@
	/* enum: reserved value - do not use (may indicate alternative interpretation
	* of REV field in future)
	*/
	-#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_RESERVED 0x0
	+#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_RESERVED 0x0
	/* enum: Trivial TX PD firmware for early Huntington development (Huntington
	* development only)
	*/
	-#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1
	+#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1
	/* enum: TX PD firmware with approximately Siena-compatible behaviour
	* (Huntington development only)
	*/
	-#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2
	+#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2
	/* enum: Full featured TX PD production firmware */
	-#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3
	+#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3
	/* enum: (deprecated original name for the FULL_FEATURED variant) */
	-#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_VSWITCH 0x3
	+#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_VSWITCH 0x3
	/* enum: siena_compat variant TX PD firmware using PM rather than MAC
	* (Huntington development only)
	*/
	-#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
	-#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */
	+#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
	+#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */
	/* enum: TX PD firmware handling layer 2 only for high packet rate performance
	* tests (Medford development only)
	*/
	-#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7
	+#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7
	/* enum: Rules engine TX PD production firmware */
	-#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8
	-/* enum: reserved value - do not use (bug69716) */
	-#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_RESERVED_9 0x9
	-/* enum: Packet rate TX PD production firmware */
	-#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_DPDK 0xa
	+#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8
	+/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
	+#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_L3XUDP 0x9
	+/* enum: DPDK TX PD production firmware */
	+#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_DPDK 0xa
	/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
	-#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
	+#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
	/* Hardware capabilities of NIC */
	#define MC_CMD_GET_CAPABILITIES_V2_OUT_HW_CAPABILITIES_OFST 12
	#define MC_CMD_GET_CAPABILITIES_V2_OUT_HW_CAPABILITIES_LEN 4
	@@ -10035,6 +10128,10 @@
	#define MC_CMD_GET_CAPABILITIES_V2_OUT_FILTER_ACTION_MARK_WIDTH 1
	#define MC_CMD_GET_CAPABILITIES_V2_OUT_EQUAL_STRIDE_PACKED_STREAM_LBN 21
	#define MC_CMD_GET_CAPABILITIES_V2_OUT_EQUAL_STRIDE_PACKED_STREAM_WIDTH 1
	+#define MC_CMD_GET_CAPABILITIES_V2_OUT_L3XUDP_SUPPORT_LBN 22
	+#define MC_CMD_GET_CAPABILITIES_V2_OUT_L3XUDP_SUPPORT_WIDTH 1
	+#define MC_CMD_GET_CAPABILITIES_V2_OUT_FW_SUBVARIANT_NO_TX_CSUM_LBN 23
	+#define MC_CMD_GET_CAPABILITIES_V2_OUT_FW_SUBVARIANT_NO_TX_CSUM_WIDTH 1
	/* Number of FATSOv2 contexts per datapath supported by this NIC. Not present
	* on older firmware (check the length).
	*/
	@@ -10048,18 +10145,18 @@
	#define MC_CMD_GET_CAPABILITIES_V2_OUT_PFS_TO_PORTS_ASSIGNMENT_LEN 1
	#define MC_CMD_GET_CAPABILITIES_V2_OUT_PFS_TO_PORTS_ASSIGNMENT_NUM 16
	/* enum: The caller is not permitted to access information on this PF. */
	-#define MC_CMD_GET_CAPABILITIES_V2_OUT_ACCESS_NOT_PERMITTED 0xff
	+#define MC_CMD_GET_CAPABILITIES_V2_OUT_ACCESS_NOT_PERMITTED 0xff
	/* enum: PF does not exist. */
	-#define MC_CMD_GET_CAPABILITIES_V2_OUT_PF_NOT_PRESENT 0xfe
	+#define MC_CMD_GET_CAPABILITIES_V2_OUT_PF_NOT_PRESENT 0xfe
	/* enum: PF does exist but is not assigned to any external port. */
	-#define MC_CMD_GET_CAPABILITIES_V2_OUT_PF_NOT_ASSIGNED 0xfd
	+#define MC_CMD_GET_CAPABILITIES_V2_OUT_PF_NOT_ASSIGNED 0xfd
	/* enum: This value indicates that PF is assigned, but it cannot be expressed
	* in this field. It is intended for a possible future situation where a more
	* complex scheme of PFs to ports mapping is being used. The future driver
	* should look for a new field supporting the new scheme. The current/old
	* driver should treat this value as PF_NOT_ASSIGNED.
	*/
	-#define MC_CMD_GET_CAPABILITIES_V2_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc
	+#define MC_CMD_GET_CAPABILITIES_V2_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc
	/* One byte per PF containing the number of its VFs, indexed by PF number. A
	* special value indicates that a PF is not present.
	*/
	@@ -10067,9 +10164,9 @@
	#define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VFS_PER_PF_LEN 1
	#define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VFS_PER_PF_NUM 16
	/* enum: The caller is not permitted to access information on this PF. */
	-/* MC_CMD_GET_CAPABILITIES_V2_OUT_ACCESS_NOT_PERMITTED 0xff */
	+/* MC_CMD_GET_CAPABILITIES_V2_OUT_ACCESS_NOT_PERMITTED 0xff */
	/* enum: PF does not exist. */
	-/* MC_CMD_GET_CAPABILITIES_V2_OUT_PF_NOT_PRESENT 0xfe */
	+/* MC_CMD_GET_CAPABILITIES_V2_OUT_PF_NOT_PRESENT 0xfe */
	/* Number of VIs available for each external port */
	#define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VIS_PER_PORT_OFST 58
	#define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VIS_PER_PORT_LEN 2
	@@ -10158,58 +10255,58 @@
	#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_DPCPU_FW_ID_OFST 4
	#define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_DPCPU_FW_ID_LEN 2
	/* enum: Standard RXDP firmware */
	-#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP 0x0
	+#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP 0x0
	/* enum: Low latency RXDP firmware */
	-#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_LOW_LATENCY 0x1
	+#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_LOW_LATENCY 0x1
	/* enum: Packed stream RXDP firmware */
	-#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_PACKED_STREAM 0x2
	+#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_PACKED_STREAM 0x2
	/* enum: Rules engine RXDP firmware */
	-#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_RULES_ENGINE 0x5
	-/* enum: Packet rate RXDP firmware */
	-#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_DPDK 0x6
	+#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_RULES_ENGINE 0x5
	+/* enum: DPDK RXDP firmware */
	+#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_DPDK 0x6
	/* enum: BIST RXDP firmware */
	-#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_BIST 0x10a
	+#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_BIST 0x10a
	/* enum: RXDP Test firmware image 1 */
	-#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101
	+#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101
	/* enum: RXDP Test firmware image 2 */
	-#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102
	+#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102
	/* enum: RXDP Test firmware image 3 */
	-#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103
	+#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103
	/* enum: RXDP Test firmware image 4 */
	-#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104
	+#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104
	/* enum: RXDP Test firmware image 5 */
	-#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_BACKPRESSURE 0x105
	+#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_BACKPRESSURE 0x105
	/* enum: RXDP Test firmware image 6 */
	-#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106
	+#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106
	/* enum: RXDP Test firmware image 7 */
	-#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107
	+#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107
	/* enum: RXDP Test firmware image 8 */
	-#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_DISABLE_DL 0x108
	+#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_DISABLE_DL 0x108
	/* enum: RXDP Test firmware image 9 */
	-#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b
	+#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b
	/* enum: RXDP Test firmware image 10 */
	-#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_SLOW 0x10c
	+#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_SLOW 0x10c
	/* TxDPCPU firmware id. */
	#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_DPCPU_FW_ID_OFST 6
	#define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_DPCPU_FW_ID_LEN 2
	/* enum: Standard TXDP firmware */
	-#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP 0x0
	+#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP 0x0
	/* enum: Low latency TXDP firmware */
	-#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_LOW_LATENCY 0x1
	+#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_LOW_LATENCY 0x1
	/* enum: High packet rate TXDP firmware */
	-#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_HIGH_PACKET_RATE 0x3
	+#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_HIGH_PACKET_RATE 0x3
	/* enum: Rules engine TXDP firmware */
	-#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_RULES_ENGINE 0x5
	-/* enum: Packet rate TXDP firmware */
	-#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_DPDK 0x6
	+#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_RULES_ENGINE 0x5
	+/* enum: DPDK TXDP firmware */
	+#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_DPDK 0x6
	/* enum: BIST TXDP firmware */
	-#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_BIST 0x12d
	+#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_BIST 0x12d
	/* enum: TXDP Test firmware image 1 */
	-#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_TEST_FW_TSO_EDIT 0x101
	+#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_TEST_FW_TSO_EDIT 0x101
	/* enum: TXDP Test firmware image 2 */
	-#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102
	+#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102
	/* enum: TXDP CSR bus test firmware */
	-#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_TEST_FW_CSR 0x103
	+#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_TEST_FW_CSR 0x103
	#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_OFST 8
	#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_LEN 2
	#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_REV_LBN 0
	@@ -10219,43 +10316,43 @@
	/* enum: reserved value - do not use (may indicate alternative interpretation
	* of REV field in future)
	*/
	-#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_RESERVED 0x0
	+#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_RESERVED 0x0
	/* enum: Trivial RX PD firmware for early Huntington development (Huntington
	* development only)
	*/
	-#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1
	+#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1
	/* enum: RX PD firmware with approximately Siena-compatible behaviour
	* (Huntington development only)
	*/
	-#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2
	+#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2
	/* enum: Full featured RX PD production firmware */
	-#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3
	+#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3
	/* enum: (deprecated original name for the FULL_FEATURED variant) */
	-#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_VSWITCH 0x3
	+#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_VSWITCH 0x3
	/* enum: siena_compat variant RX PD firmware using PM rather than MAC
	* (Huntington development only)
	*/
	-#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
	+#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
	/* enum: Low latency RX PD production firmware */
	-#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5
	+#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5
	/* enum: Packed stream RX PD production firmware */
	-#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6
	+#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6
	/* enum: RX PD firmware handling layer 2 only for high packet rate performance
	* tests (Medford development only)
	*/
	-#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7
	+#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7
	/* enum: Rules engine RX PD production firmware */
	-#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8
	-/* enum: reserved value - do not use (bug69716) */
	-#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_RESERVED_9 0x9
	-/* enum: Packet rate RX PD production firmware */
	-#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_DPDK 0xa
	+#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8
	+/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
	+#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_L3XUDP 0x9
	+/* enum: DPDK RX PD production firmware */
	+#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_DPDK 0xa
	/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
	-#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
	+#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
	/* enum: RX PD firmware parsing but not filtering network overlay tunnel
	* encapsulations (Medford development only)
	*/
	-#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf
	+#define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf
	#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_OFST 10
	#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_LEN 2
	#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_REV_LBN 0
	@@ -10265,36 +10362,36 @@
	/* enum: reserved value - do not use (may indicate alternative interpretation
	* of REV field in future)
	*/
	-#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_RESERVED 0x0
	+#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_RESERVED 0x0
	/* enum: Trivial TX PD firmware for early Huntington development (Huntington
	* development only)
	*/
	-#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1
	+#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1
	/* enum: TX PD firmware with approximately Siena-compatible behaviour
	* (Huntington development only)
	*/
	-#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2
	+#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2
	/* enum: Full featured TX PD production firmware */
	-#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3
	+#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3
	/* enum: (deprecated original name for the FULL_FEATURED variant) */
	-#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_VSWITCH 0x3
	+#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_VSWITCH 0x3
	/* enum: siena_compat variant TX PD firmware using PM rather than MAC
	* (Huntington development only)
	*/
	-#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
	-#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */
	+#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
	+#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */
	/* enum: TX PD firmware handling layer 2 only for high packet rate performance
	* tests (Medford development only)
	*/
	-#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7
	+#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7
	/* enum: Rules engine TX PD production firmware */
	-#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8
	-/* enum: reserved value - do not use (bug69716) */
	-#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_RESERVED_9 0x9
	-/* enum: Packet rate TX PD production firmware */
	-#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_DPDK 0xa
	+#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8
	+/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
	+#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_L3XUDP 0x9
	+/* enum: DPDK TX PD production firmware */
	+#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_DPDK 0xa
	/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
	-#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
	+#define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
	/* Hardware capabilities of NIC */
	#define MC_CMD_GET_CAPABILITIES_V3_OUT_HW_CAPABILITIES_OFST 12
	#define MC_CMD_GET_CAPABILITIES_V3_OUT_HW_CAPABILITIES_LEN 4
	@@ -10348,6 +10445,10 @@
	#define MC_CMD_GET_CAPABILITIES_V3_OUT_FILTER_ACTION_MARK_WIDTH 1
	#define MC_CMD_GET_CAPABILITIES_V3_OUT_EQUAL_STRIDE_PACKED_STREAM_LBN 21
	#define MC_CMD_GET_CAPABILITIES_V3_OUT_EQUAL_STRIDE_PACKED_STREAM_WIDTH 1
	+#define MC_CMD_GET_CAPABILITIES_V3_OUT_L3XUDP_SUPPORT_LBN 22
	+#define MC_CMD_GET_CAPABILITIES_V3_OUT_L3XUDP_SUPPORT_WIDTH 1
	+#define MC_CMD_GET_CAPABILITIES_V3_OUT_FW_SUBVARIANT_NO_TX_CSUM_LBN 23
	+#define MC_CMD_GET_CAPABILITIES_V3_OUT_FW_SUBVARIANT_NO_TX_CSUM_WIDTH 1
	/* Number of FATSOv2 contexts per datapath supported by this NIC. Not present
	* on older firmware (check the length).
	*/
	@@ -10361,18 +10462,18 @@
	#define MC_CMD_GET_CAPABILITIES_V3_OUT_PFS_TO_PORTS_ASSIGNMENT_LEN 1
	#define MC_CMD_GET_CAPABILITIES_V3_OUT_PFS_TO_PORTS_ASSIGNMENT_NUM 16
	/* enum: The caller is not permitted to access information on this PF. */
	-#define MC_CMD_GET_CAPABILITIES_V3_OUT_ACCESS_NOT_PERMITTED 0xff
	+#define MC_CMD_GET_CAPABILITIES_V3_OUT_ACCESS_NOT_PERMITTED 0xff
	/* enum: PF does not exist. */
	-#define MC_CMD_GET_CAPABILITIES_V3_OUT_PF_NOT_PRESENT 0xfe
	+#define MC_CMD_GET_CAPABILITIES_V3_OUT_PF_NOT_PRESENT 0xfe
	/* enum: PF does exist but is not assigned to any external port. */
	-#define MC_CMD_GET_CAPABILITIES_V3_OUT_PF_NOT_ASSIGNED 0xfd
	+#define MC_CMD_GET_CAPABILITIES_V3_OUT_PF_NOT_ASSIGNED 0xfd
	/* enum: This value indicates that PF is assigned, but it cannot be expressed
	* in this field. It is intended for a possible future situation where a more
	* complex scheme of PFs to ports mapping is being used. The future driver
	* should look for a new field supporting the new scheme. The current/old
	* driver should treat this value as PF_NOT_ASSIGNED.
	*/
	-#define MC_CMD_GET_CAPABILITIES_V3_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc
	+#define MC_CMD_GET_CAPABILITIES_V3_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc
	/* One byte per PF containing the number of its VFs, indexed by PF number. A
	* special value indicates that a PF is not present.
	*/
	@@ -10380,9 +10481,9 @@
	#define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_VFS_PER_PF_LEN 1
	#define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_VFS_PER_PF_NUM 16
	/* enum: The caller is not permitted to access information on this PF. */
	-/* MC_CMD_GET_CAPABILITIES_V3_OUT_ACCESS_NOT_PERMITTED 0xff */
	+/* MC_CMD_GET_CAPABILITIES_V3_OUT_ACCESS_NOT_PERMITTED 0xff */
	/* enum: PF does not exist. */
	-/* MC_CMD_GET_CAPABILITIES_V3_OUT_PF_NOT_PRESENT 0xfe */
	+/* MC_CMD_GET_CAPABILITIES_V3_OUT_PF_NOT_PRESENT 0xfe */
	/* Number of VIs available for each external port */
	#define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_VIS_PER_PORT_OFST 58
	#define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_VIS_PER_PORT_LEN 2
	@@ -10413,11 +10514,11 @@
	/* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k.
	* CTPIO is not mapped.
	*/
	-#define MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_8K 0x0
	+#define MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_8K 0x0
	/* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */
	-#define MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_16K 0x1
	+#define MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_16K 0x1
	/* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */
	-#define MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_64K 0x2
	+#define MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_64K 0x2
	/* Number of vFIFOs per adapter that can be used for VFIFO Stuffing
	* (SF-115995-SW) in the present configuration of firmware and port mode.
	*/
	@@ -10496,58 +10597,58 @@
	#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_DPCPU_FW_ID_OFST 4
	#define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_DPCPU_FW_ID_LEN 2
	/* enum: Standard RXDP firmware */
	-#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP 0x0
	+#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP 0x0
	/* enum: Low latency RXDP firmware */
	-#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_LOW_LATENCY 0x1
	+#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_LOW_LATENCY 0x1
	/* enum: Packed stream RXDP firmware */
	-#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_PACKED_STREAM 0x2
	+#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_PACKED_STREAM 0x2
	/* enum: Rules engine RXDP firmware */
	-#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_RULES_ENGINE 0x5
	-/* enum: Packet rate RXDP firmware */
	-#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_DPDK 0x6
	+#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_RULES_ENGINE 0x5
	+/* enum: DPDK RXDP firmware */
	+#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_DPDK 0x6
	/* enum: BIST RXDP firmware */
	-#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_BIST 0x10a
	+#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_BIST 0x10a
	/* enum: RXDP Test firmware image 1 */
	-#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101
	+#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101
	/* enum: RXDP Test firmware image 2 */
	-#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102
	+#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102
	/* enum: RXDP Test firmware image 3 */
	-#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103
	+#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103
	/* enum: RXDP Test firmware image 4 */
	-#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104
	+#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104
	/* enum: RXDP Test firmware image 5 */
	-#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_BACKPRESSURE 0x105
	+#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_BACKPRESSURE 0x105
	/* enum: RXDP Test firmware image 6 */
	-#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106
	+#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106
	/* enum: RXDP Test firmware image 7 */
	-#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107
	+#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107
	/* enum: RXDP Test firmware image 8 */
	-#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_DISABLE_DL 0x108
	+#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_DISABLE_DL 0x108
	/* enum: RXDP Test firmware image 9 */
	-#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b
	+#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b
	/* enum: RXDP Test firmware image 10 */
	-#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_SLOW 0x10c
	+#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_SLOW 0x10c
	/* TxDPCPU firmware id. */
	#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_DPCPU_FW_ID_OFST 6
	#define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_DPCPU_FW_ID_LEN 2
	/* enum: Standard TXDP firmware */
	-#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP 0x0
	+#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP 0x0
	/* enum: Low latency TXDP firmware */
	-#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_LOW_LATENCY 0x1
	+#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_LOW_LATENCY 0x1
	/* enum: High packet rate TXDP firmware */
	-#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_HIGH_PACKET_RATE 0x3
	+#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_HIGH_PACKET_RATE 0x3
	/* enum: Rules engine TXDP firmware */
	-#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_RULES_ENGINE 0x5
	-/* enum: Packet rate TXDP firmware */
	-#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_DPDK 0x6
	+#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_RULES_ENGINE 0x5
	+/* enum: DPDK TXDP firmware */
	+#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_DPDK 0x6
	/* enum: BIST TXDP firmware */
	-#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_BIST 0x12d
	+#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_BIST 0x12d
	/* enum: TXDP Test firmware image 1 */
	-#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_TEST_FW_TSO_EDIT 0x101
	+#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_TEST_FW_TSO_EDIT 0x101
	/* enum: TXDP Test firmware image 2 */
	-#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102
	+#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102
	/* enum: TXDP CSR bus test firmware */
	-#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_TEST_FW_CSR 0x103
	+#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_TEST_FW_CSR 0x103
	#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_VERSION_OFST 8
	#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_VERSION_LEN 2
	#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_VERSION_REV_LBN 0
	@@ -10557,43 +10658,43 @@
	/* enum: reserved value - do not use (may indicate alternative interpretation
	* of REV field in future)
	*/
	-#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_RESERVED 0x0
	+#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_RESERVED 0x0
	/* enum: Trivial RX PD firmware for early Huntington development (Huntington
	* development only)
	*/
	-#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1
	+#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1
	/* enum: RX PD firmware with approximately Siena-compatible behaviour
	* (Huntington development only)
	*/
	-#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2
	+#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2
	/* enum: Full featured RX PD production firmware */
	-#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3
	+#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3
	/* enum: (deprecated original name for the FULL_FEATURED variant) */
	-#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_VSWITCH 0x3
	+#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_VSWITCH 0x3
	/* enum: siena_compat variant RX PD firmware using PM rather than MAC
	* (Huntington development only)
	*/
	-#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
	+#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
	/* enum: Low latency RX PD production firmware */
	-#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5
	+#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5
	/* enum: Packed stream RX PD production firmware */
	-#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6
	+#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6
	/* enum: RX PD firmware handling layer 2 only for high packet rate performance
	* tests (Medford development only)
	*/
	-#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7
	+#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7
	/* enum: Rules engine RX PD production firmware */
	-#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8
	-/* enum: reserved value - do not use (bug69716) */
	-#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_RESERVED_9 0x9
	-/* enum: Packet rate RX PD production firmware */
	-#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_DPDK 0xa
	+#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8
	+/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
	+#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_L3XUDP 0x9
	+/* enum: DPDK RX PD production firmware */
	+#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_DPDK 0xa
	/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
	-#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
	+#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
	/* enum: RX PD firmware parsing but not filtering network overlay tunnel
	* encapsulations (Medford development only)
	*/
	-#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf
	+#define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf
	#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_VERSION_OFST 10
	#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_VERSION_LEN 2
	#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_VERSION_REV_LBN 0
	@@ -10603,36 +10704,36 @@
	/* enum: reserved value - do not use (may indicate alternative interpretation
	* of REV field in future)
	*/
	-#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_RESERVED 0x0
	+#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_RESERVED 0x0
	/* enum: Trivial TX PD firmware for early Huntington development (Huntington
	* development only)
	*/
	-#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1
	+#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1
	/* enum: TX PD firmware with approximately Siena-compatible behaviour
	* (Huntington development only)
	*/
	-#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2
	+#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2
	/* enum: Full featured TX PD production firmware */
	-#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3
	+#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3
	/* enum: (deprecated original name for the FULL_FEATURED variant) */
	-#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_VSWITCH 0x3
	+#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_VSWITCH 0x3
	/* enum: siena_compat variant TX PD firmware using PM rather than MAC
	* (Huntington development only)
	*/
	-#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
	-#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */
	+#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
	+#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */
	/* enum: TX PD firmware handling layer 2 only for high packet rate performance
	* tests (Medford development only)
	*/
	-#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7
	+#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7
	/* enum: Rules engine TX PD production firmware */
	-#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8
	-/* enum: reserved value - do not use (bug69716) */
	-#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_RESERVED_9 0x9
	-/* enum: Packet rate TX PD production firmware */
	-#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_DPDK 0xa
	+#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8
	+/* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
	+#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_L3XUDP 0x9
	+/* enum: DPDK TX PD production firmware */
	+#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_DPDK 0xa
	/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */
	-#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
	+#define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
	/* Hardware capabilities of NIC */
	#define MC_CMD_GET_CAPABILITIES_V4_OUT_HW_CAPABILITIES_OFST 12
	#define MC_CMD_GET_CAPABILITIES_V4_OUT_HW_CAPABILITIES_LEN 4
	@@ -10686,6 +10787,10 @@
	#define MC_CMD_GET_CAPABILITIES_V4_OUT_FILTER_ACTION_MARK_WIDTH 1
	#define MC_CMD_GET_CAPABILITIES_V4_OUT_EQUAL_STRIDE_PACKED_STREAM_LBN 21
	#define MC_CMD_GET_CAPABILITIES_V4_OUT_EQUAL_STRIDE_PACKED_STREAM_WIDTH 1
	+#define MC_CMD_GET_CAPABILITIES_V4_OUT_L3XUDP_SUPPORT_LBN 22
	+#define MC_CMD_GET_CAPABILITIES_V4_OUT_L3XUDP_SUPPORT_WIDTH 1
	+#define MC_CMD_GET_CAPABILITIES_V4_OUT_FW_SUBVARIANT_NO_TX_CSUM_LBN 23
	+#define MC_CMD_GET_CAPABILITIES_V4_OUT_FW_SUBVARIANT_NO_TX_CSUM_WIDTH 1
	/* Number of FATSOv2 contexts per datapath supported by this NIC. Not present
	* on older firmware (check the length).
	*/
	@@ -10699,18 +10804,18 @@
	#define MC_CMD_GET_CAPABILITIES_V4_OUT_PFS_TO_PORTS_ASSIGNMENT_LEN 1
	#define MC_CMD_GET_CAPABILITIES_V4_OUT_PFS_TO_PORTS_ASSIGNMENT_NUM 16
	/* enum: The caller is not permitted to access information on this PF. */
	-#define MC_CMD_GET_CAPABILITIES_V4_OUT_ACCESS_NOT_PERMITTED 0xff
	+#define MC_CMD_GET_CAPABILITIES_V4_OUT_ACCESS_NOT_PERMITTED 0xff
	/* enum: PF does not exist. */
	-#define MC_CMD_GET_CAPABILITIES_V4_OUT_PF_NOT_PRESENT 0xfe
	+#define MC_CMD_GET_CAPABILITIES_V4_OUT_PF_NOT_PRESENT 0xfe
	/* enum: PF does exist but is not assigned to any external port. */
	-#define MC_CMD_GET_CAPABILITIES_V4_OUT_PF_NOT_ASSIGNED 0xfd
	+#define MC_CMD_GET_CAPABILITIES_V4_OUT_PF_NOT_ASSIGNED 0xfd
	/* enum: This value indicates that PF is assigned, but it cannot be expressed
	* in this field. It is intended for a possible future situation where a more
	* complex scheme of PFs to ports mapping is being used. The future driver
	* should look for a new field supporting the new scheme. The current/old
	* driver should treat this value as PF_NOT_ASSIGNED.
	*/
	-#define MC_CMD_GET_CAPABILITIES_V4_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc
	+#define MC_CMD_GET_CAPABILITIES_V4_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc
	/* One byte per PF containing the number of its VFs, indexed by PF number. A
	* special value indicates that a PF is not present.
	*/
	@@ -10718,9 +10823,9 @@
	#define MC_CMD_GET_CAPABILITIES_V4_OUT_NUM_VFS_PER_PF_LEN 1
	#define MC_CMD_GET_CAPABILITIES_V4_OUT_NUM_VFS_PER_PF_NUM 16
	/* enum: The caller is not permitted to access information on this PF. */
	-/* MC_CMD_GET_CAPABILITIES_V4_OUT_ACCESS_NOT_PERMITTED 0xff */
	+/* MC_CMD_GET_CAPABILITIES_V4_OUT_ACCESS_NOT_PERMITTED 0xff */
	/* enum: PF does not exist. */
	-/* MC_CMD_GET_CAPABILITIES_V4_OUT_PF_NOT_PRESENT 0xfe */
	+/* MC_CMD_GET_CAPABILITIES_V4_OUT_PF_NOT_PRESENT 0xfe */
	/* Number of VIs available for each external port */
	#define MC_CMD_GET_CAPABILITIES_V4_OUT_NUM_VIS_PER_PORT_OFST 58
	#define MC_CMD_GET_CAPABILITIES_V4_OUT_NUM_VIS_PER_PORT_LEN 2
	@@ -10751,11 +10856,11 @@
	/* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k.
	* CTPIO is not mapped.
	*/
	-#define MC_CMD_GET_CAPABILITIES_V4_OUT_VI_WINDOW_MODE_8K 0x0
	+#define MC_CMD_GET_CAPABILITIES_V4_OUT_VI_WINDOW_MODE_8K 0x0
	/* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */
	-#define MC_CMD_GET_CAPABILITIES_V4_OUT_VI_WINDOW_MODE_16K 0x1
	+#define MC_CMD_GET_CAPABILITIES_V4_OUT_VI_WINDOW_MODE_16K 0x1
	/* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */
	-#define MC_CMD_GET_CAPABILITIES_V4_OUT_VI_WINDOW_MODE_64K 0x2
	+#define MC_CMD_GET_CAPABILITIES_V4_OUT_VI_WINDOW_MODE_64K 0x2
	/* Number of vFIFOs per adapter that can be used for VFIFO Stuffing
	* (SF-115995-SW) in the present configuration of firmware and port mode.
	*/
	@@ -10800,11 +10905,11 @@
	#define MC_CMD_V2_EXTN_IN_MESSAGE_TYPE_LBN 28
	#define MC_CMD_V2_EXTN_IN_MESSAGE_TYPE_WIDTH 4
	/* enum: MCDI command directed to or response originating from the MC. */
	-#define MC_CMD_V2_EXTN_IN_MCDI_MESSAGE_TYPE_MC 0x0
	+#define MC_CMD_V2_EXTN_IN_MCDI_MESSAGE_TYPE_MC 0x0
	/* enum: MCDI command directed to a TSA controller. MCDI responses of this type
	* are not defined.
	*/
	-#define MC_CMD_V2_EXTN_IN_MCDI_MESSAGE_TYPE_TSA 0x1
	+#define MC_CMD_V2_EXTN_IN_MCDI_MESSAGE_TYPE_TSA 0x1


	/***********************************/
	@@ -11022,15 +11127,15 @@
	#define MC_CMD_VSWITCH_ALLOC_IN_TYPE_OFST 4
	#define MC_CMD_VSWITCH_ALLOC_IN_TYPE_LEN 4
	/* enum: VLAN */
	-#define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_VLAN 0x1
	+#define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_VLAN 0x1
	/* enum: VEB */
	-#define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_VEB 0x2
	+#define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_VEB 0x2
	/* enum: VEPA (obsolete) */
	-#define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_VEPA 0x3
	+#define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_VEPA 0x3
	/* enum: MUX */
	-#define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_MUX 0x4
	+#define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_MUX 0x4
	/* enum: Snapper specific; semantics TBD */
	-#define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_TEST 0x5
	+#define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_TEST 0x5
	/* Flags controlling v-port creation */
	#define MC_CMD_VSWITCH_ALLOC_IN_FLAGS_OFST 8
	#define MC_CMD_VSWITCH_ALLOC_IN_FLAGS_LEN 4
	@@ -11108,23 +11213,23 @@
	#define MC_CMD_VPORT_ALLOC_IN_TYPE_OFST 4
	#define MC_CMD_VPORT_ALLOC_IN_TYPE_LEN 4
	/* enum: VLAN (obsolete) */
	-#define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_VLAN 0x1
	+#define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_VLAN 0x1
	/* enum: VEB (obsolete) */
	-#define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_VEB 0x2
	+#define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_VEB 0x2
	/* enum: VEPA (obsolete) */
	-#define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_VEPA 0x3
	+#define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_VEPA 0x3
	/* enum: A normal v-port receives packets which match a specified MAC and/or
	* VLAN.
	*/
	-#define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_NORMAL 0x4
	+#define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_NORMAL 0x4
	/* enum: An expansion v-port packets traffic which don't match any other
	* v-port.
	*/
	-#define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_EXPANSION 0x5
	+#define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_EXPANSION 0x5
	/* enum: An test v-port receives packets which match any filters installed by
	* its downstream components.
	*/
	-#define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_TEST 0x6
	+#define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_TEST 0x6
	/* Flags controlling v-port creation */
	#define MC_CMD_VPORT_ALLOC_IN_FLAGS_OFST 8
	#define MC_CMD_VPORT_ALLOC_IN_FLAGS_LEN 4
	@@ -11210,7 +11315,7 @@
	#define MC_CMD_VADAPTOR_ALLOC_IN_MACADDR_OFST 24
	#define MC_CMD_VADAPTOR_ALLOC_IN_MACADDR_LEN 6
	/* enum: Derive the MAC address from the upstream port */
	-#define MC_CMD_VADAPTOR_ALLOC_IN_AUTO_MAC 0x0
	+#define MC_CMD_VADAPTOR_ALLOC_IN_AUTO_MAC 0x0

	/* MC_CMD_VADAPTOR_ALLOC_OUT msgresponse */
	#define MC_CMD_VADAPTOR_ALLOC_OUT_LEN 0
	@@ -11433,12 +11538,12 @@
	/* enum: Allocate a context for exclusive use. The key and indirection table
	* must be explicitly configured.
	*/
	-#define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_EXCLUSIVE 0x0
	+#define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_EXCLUSIVE 0x0
	/* enum: Allocate a context for shared use; this will spread across a range of
	* queues, but the key and indirection table are pre-configured and may not be
	* changed. For this mode, NUM_QUEUES must 2, 4, 8, 16, 32 or 64.
	*/
	-#define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_SHARED 0x1
	+#define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_SHARED 0x1
	/* Number of queues spanned by this context, in the range 1-64; valid offsets
	* in the indirection table will be in the range 0 to NUM_QUEUES-1.
	*/
	@@ -11454,7 +11559,7 @@
	#define MC_CMD_RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID_OFST 0
	#define MC_CMD_RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID_LEN 4
	/* enum: guaranteed invalid RSS context handle value */
	-#define MC_CMD_RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID_INVALID 0xffffffff
	+#define MC_CMD_RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID_INVALID 0xffffffff


	/***********************************/
	@@ -11705,7 +11810,7 @@
	#define MC_CMD_DOT1P_MAPPING_ALLOC_OUT_DOT1P_MAPPING_ID_OFST 0
	#define MC_CMD_DOT1P_MAPPING_ALLOC_OUT_DOT1P_MAPPING_ID_LEN 4
	/* enum: guaranteed invalid .1p mapping handle value */
	-#define MC_CMD_DOT1P_MAPPING_ALLOC_OUT_DOT1P_MAPPING_ID_INVALID 0xffffffff
	+#define MC_CMD_DOT1P_MAPPING_ALLOC_OUT_DOT1P_MAPPING_ID_INVALID 0xffffffff


	/***********************************/
	@@ -12029,11 +12134,11 @@
	#define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_LEN_LBN 1
	#define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_LEN_WIDTH 2
	/* enum: pad to 64 bytes */
	-#define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_64 0x0
	+#define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_64 0x0
	/* enum: pad to 128 bytes (Medford only) */
	-#define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_128 0x1
	+#define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_128 0x1
	/* enum: pad to 256 bytes (Medford only) */
	-#define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_256 0x2
	+#define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_256 0x2

	/* MC_CMD_SET_RXDP_CONFIG_OUT msgresponse */
	#define MC_CMD_SET_RXDP_CONFIG_OUT_LEN 0
	@@ -12100,37 +12205,37 @@
	#define MC_CMD_SET_CLOCK_IN_SYS_FREQ_OFST 0
	#define MC_CMD_SET_CLOCK_IN_SYS_FREQ_LEN 4
	/* enum: Leave the system clock domain frequency unchanged */
	-#define MC_CMD_SET_CLOCK_IN_SYS_DOMAIN_DONT_CHANGE 0x0
	+#define MC_CMD_SET_CLOCK_IN_SYS_DOMAIN_DONT_CHANGE 0x0
	/* Requested frequency in MHz for inter-core clock domain */
	#define MC_CMD_SET_CLOCK_IN_ICORE_FREQ_OFST 4
	#define MC_CMD_SET_CLOCK_IN_ICORE_FREQ_LEN 4
	/* enum: Leave the inter-core clock domain frequency unchanged */
	-#define MC_CMD_SET_CLOCK_IN_ICORE_DOMAIN_DONT_CHANGE 0x0
	+#define MC_CMD_SET_CLOCK_IN_ICORE_DOMAIN_DONT_CHANGE 0x0
	/* Requested frequency in MHz for DPCPU clock domain */
	#define MC_CMD_SET_CLOCK_IN_DPCPU_FREQ_OFST 8
	#define MC_CMD_SET_CLOCK_IN_DPCPU_FREQ_LEN 4
	/* enum: Leave the DPCPU clock domain frequency unchanged */
	-#define MC_CMD_SET_CLOCK_IN_DPCPU_DOMAIN_DONT_CHANGE 0x0
	+#define MC_CMD_SET_CLOCK_IN_DPCPU_DOMAIN_DONT_CHANGE 0x0
	/* Requested frequency in MHz for PCS clock domain */
	#define MC_CMD_SET_CLOCK_IN_PCS_FREQ_OFST 12
	#define MC_CMD_SET_CLOCK_IN_PCS_FREQ_LEN 4
	/* enum: Leave the PCS clock domain frequency unchanged */
	-#define MC_CMD_SET_CLOCK_IN_PCS_DOMAIN_DONT_CHANGE 0x0
	+#define MC_CMD_SET_CLOCK_IN_PCS_DOMAIN_DONT_CHANGE 0x0
	/* Requested frequency in MHz for MC clock domain */
	#define MC_CMD_SET_CLOCK_IN_MC_FREQ_OFST 16
	#define MC_CMD_SET_CLOCK_IN_MC_FREQ_LEN 4
	/* enum: Leave the MC clock domain frequency unchanged */
	-#define MC_CMD_SET_CLOCK_IN_MC_DOMAIN_DONT_CHANGE 0x0
	+#define MC_CMD_SET_CLOCK_IN_MC_DOMAIN_DONT_CHANGE 0x0
	/* Requested frequency in MHz for rmon clock domain */
	#define MC_CMD_SET_CLOCK_IN_RMON_FREQ_OFST 20
	#define MC_CMD_SET_CLOCK_IN_RMON_FREQ_LEN 4
	/* enum: Leave the rmon clock domain frequency unchanged */
	-#define MC_CMD_SET_CLOCK_IN_RMON_DOMAIN_DONT_CHANGE 0x0
	+#define MC_CMD_SET_CLOCK_IN_RMON_DOMAIN_DONT_CHANGE 0x0
	/* Requested frequency in MHz for vswitch clock domain */
	#define MC_CMD_SET_CLOCK_IN_VSWITCH_FREQ_OFST 24
	#define MC_CMD_SET_CLOCK_IN_VSWITCH_FREQ_LEN 4
	/* enum: Leave the vswitch clock domain frequency unchanged */
	-#define MC_CMD_SET_CLOCK_IN_VSWITCH_DOMAIN_DONT_CHANGE 0x0
	+#define MC_CMD_SET_CLOCK_IN_VSWITCH_DOMAIN_DONT_CHANGE 0x0

	/* MC_CMD_SET_CLOCK_OUT msgresponse */
	#define MC_CMD_SET_CLOCK_OUT_LEN 28
	@@ -12138,37 +12243,37 @@
	#define MC_CMD_SET_CLOCK_OUT_SYS_FREQ_OFST 0
	#define MC_CMD_SET_CLOCK_OUT_SYS_FREQ_LEN 4
	/* enum: The system clock domain doesn't exist */
	-#define MC_CMD_SET_CLOCK_OUT_SYS_DOMAIN_UNSUPPORTED 0x0
	+#define MC_CMD_SET_CLOCK_OUT_SYS_DOMAIN_UNSUPPORTED 0x0
	/* Resulting inter-core frequency in MHz */
	#define MC_CMD_SET_CLOCK_OUT_ICORE_FREQ_OFST 4
	#define MC_CMD_SET_CLOCK_OUT_ICORE_FREQ_LEN 4
	/* enum: The inter-core clock domain doesn't exist / isn't used */
	-#define MC_CMD_SET_CLOCK_OUT_ICORE_DOMAIN_UNSUPPORTED 0x0
	+#define MC_CMD_SET_CLOCK_OUT_ICORE_DOMAIN_UNSUPPORTED 0x0
	/* Resulting DPCPU frequency in MHz */
	#define MC_CMD_SET_CLOCK_OUT_DPCPU_FREQ_OFST 8
	#define MC_CMD_SET_CLOCK_OUT_DPCPU_FREQ_LEN 4
	/* enum: The dpcpu clock domain doesn't exist */
	-#define MC_CMD_SET_CLOCK_OUT_DPCPU_DOMAIN_UNSUPPORTED 0x0
	+#define MC_CMD_SET_CLOCK_OUT_DPCPU_DOMAIN_UNSUPPORTED 0x0
	/* Resulting PCS frequency in MHz */
	#define MC_CMD_SET_CLOCK_OUT_PCS_FREQ_OFST 12
	#define MC_CMD_SET_CLOCK_OUT_PCS_FREQ_LEN 4
	/* enum: The PCS clock domain doesn't exist / isn't controlled */
	-#define MC_CMD_SET_CLOCK_OUT_PCS_DOMAIN_UNSUPPORTED 0x0
	+#define MC_CMD_SET_CLOCK_OUT_PCS_DOMAIN_UNSUPPORTED 0x0
	/* Resulting MC frequency in MHz */
	#define MC_CMD_SET_CLOCK_OUT_MC_FREQ_OFST 16
	#define MC_CMD_SET_CLOCK_OUT_MC_FREQ_LEN 4
	/* enum: The MC clock domain doesn't exist / isn't controlled */
	-#define MC_CMD_SET_CLOCK_OUT_MC_DOMAIN_UNSUPPORTED 0x0
	+#define MC_CMD_SET_CLOCK_OUT_MC_DOMAIN_UNSUPPORTED 0x0
	/* Resulting rmon frequency in MHz */
	#define MC_CMD_SET_CLOCK_OUT_RMON_FREQ_OFST 20
	#define MC_CMD_SET_CLOCK_OUT_RMON_FREQ_LEN 4
	/* enum: The rmon clock domain doesn't exist / isn't controlled */
	-#define MC_CMD_SET_CLOCK_OUT_RMON_DOMAIN_UNSUPPORTED 0x0
	+#define MC_CMD_SET_CLOCK_OUT_RMON_DOMAIN_UNSUPPORTED 0x0
	/* Resulting vswitch frequency in MHz */
	#define MC_CMD_SET_CLOCK_OUT_VSWITCH_FREQ_OFST 24
	#define MC_CMD_SET_CLOCK_OUT_VSWITCH_FREQ_LEN 4
	/* enum: The vswitch clock domain doesn't exist / isn't controlled */
	-#define MC_CMD_SET_CLOCK_OUT_VSWITCH_DOMAIN_UNSUPPORTED 0x0
	+#define MC_CMD_SET_CLOCK_OUT_VSWITCH_DOMAIN_UNSUPPORTED 0x0


	/***********************************/
	@@ -12185,21 +12290,21 @@
	#define MC_CMD_DPCPU_RPC_IN_CPU_OFST 0
	#define MC_CMD_DPCPU_RPC_IN_CPU_LEN 4
	/* enum: RxDPCPU0 */
	-#define MC_CMD_DPCPU_RPC_IN_DPCPU_RX0 0x0
	+#define MC_CMD_DPCPU_RPC_IN_DPCPU_RX0 0x0
	/* enum: TxDPCPU0 */
	-#define MC_CMD_DPCPU_RPC_IN_DPCPU_TX0 0x1
	+#define MC_CMD_DPCPU_RPC_IN_DPCPU_TX0 0x1
	/* enum: TxDPCPU1 */
	-#define MC_CMD_DPCPU_RPC_IN_DPCPU_TX1 0x2
	+#define MC_CMD_DPCPU_RPC_IN_DPCPU_TX1 0x2
	/* enum: RxDPCPU1 (Medford only) */
	-#define MC_CMD_DPCPU_RPC_IN_DPCPU_RX1 0x3
	+#define MC_CMD_DPCPU_RPC_IN_DPCPU_RX1 0x3
	/* enum: RxDPCPU (will be for the calling function; for now, just an alias of
	* DPCPU_RX0)
	*/
	-#define MC_CMD_DPCPU_RPC_IN_DPCPU_RX 0x80
	+#define MC_CMD_DPCPU_RPC_IN_DPCPU_RX 0x80
	/* enum: TxDPCPU (will be for the calling function; for now, just an alias of
	* DPCPU_TX0)
	*/
	-#define MC_CMD_DPCPU_RPC_IN_DPCPU_TX 0x81
	+#define MC_CMD_DPCPU_RPC_IN_DPCPU_TX 0x81
	/* First 8 bits [39:32] of DATA are consumed by MC-DPCPU protocol and must be
	* initialised to zero
	*/
	@@ -12207,15 +12312,15 @@
	#define MC_CMD_DPCPU_RPC_IN_DATA_LEN 32
	#define MC_CMD_DPCPU_RPC_IN_HDR_CMD_CMDNUM_LBN 8
	#define MC_CMD_DPCPU_RPC_IN_HDR_CMD_CMDNUM_WIDTH 8
	-#define MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_READ 0x6 /* enum */
	-#define MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_WRITE 0x7 /* enum */
	-#define MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_SELF_TEST 0xc /* enum */
	-#define MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_CSR_ACCESS 0xe /* enum */
	-#define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_READ 0x46 /* enum */
	-#define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_WRITE 0x47 /* enum */
	-#define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_SELF_TEST 0x4a /* enum */
	-#define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_CSR_ACCESS 0x4c /* enum */
	-#define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_SET_MC_REPLAY_CNTXT 0x4d /* enum */
	+#define MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_READ 0x6 /* enum */
	+#define MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_WRITE 0x7 /* enum */
	+#define MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_SELF_TEST 0xc /* enum */
	+#define MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_CSR_ACCESS 0xe /* enum */
	+#define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_READ 0x46 /* enum */
	+#define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_WRITE 0x47 /* enum */
	+#define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_SELF_TEST 0x4a /* enum */
	+#define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_CSR_ACCESS 0x4c /* enum */
	+#define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_SET_MC_REPLAY_CNTXT 0x4d /* enum */
	#define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_OBJID_LBN 16
	#define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_OBJID_WIDTH 16
	#define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_ADDR_LBN 16
	@@ -12226,11 +12331,11 @@
	#define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_INFO_WIDTH 240
	#define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_LBN 16
	#define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_WIDTH 16
	-#define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_STOP_RETURN_RESULT 0x0 /* enum */
	-#define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_READ 0x1 /* enum */
	-#define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_WRITE 0x2 /* enum */
	-#define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_WRITE_READ 0x3 /* enum */
	-#define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_PIPELINED_READ 0x4 /* enum */
	+#define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_STOP_RETURN_RESULT 0x0 /* enum */
	+#define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_READ 0x1 /* enum */
	+#define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_WRITE 0x2 /* enum */
	+#define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_WRITE_READ 0x3 /* enum */
	+#define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_PIPELINED_READ 0x4 /* enum */
	#define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_START_DELAY_LBN 48
	#define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_START_DELAY_WIDTH 16
	#define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_RPT_COUNT_LBN 64
	@@ -12239,9 +12344,9 @@
	#define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_GAP_DELAY_WIDTH 16
	#define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_LBN 16
	#define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_WIDTH 16
	-#define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_CUT_THROUGH 0x1 /* enum */
	-#define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_STORE_FORWARD 0x2 /* enum */
	-#define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_STORE_FORWARD_FIRST 0x3 /* enum */
	+#define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_CUT_THROUGH 0x1 /* enum */
	+#define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_STORE_FORWARD 0x2 /* enum */
	+#define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_STORE_FORWARD_FIRST 0x3 /* enum */
	#define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_CNTXT_LBN 64
	#define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_CNTXT_WIDTH 16
	#define MC_CMD_DPCPU_RPC_IN_WDATA_OFST 12
	@@ -12302,7 +12407,7 @@
	#define MC_CMD_SHMBOOT_OP 0xe6
	#undef MC_CMD_0xe6_PRIVILEGE_CTG

	-#define MC_CMD_0xe6_PRIVILEGE_CTG SRIOV_CTG_ADMIN
	+#define MC_CMD_0xe6_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND

	/* MC_CMD_SHMBOOT_OP_IN msgrequest */
	#define MC_CMD_SHMBOOT_OP_IN_LEN 4
	@@ -12310,7 +12415,7 @@
	#define MC_CMD_SHMBOOT_OP_IN_SHMBOOT_OP_OFST 0
	#define MC_CMD_SHMBOOT_OP_IN_SHMBOOT_OP_LEN 4
	/* enum: Copy slave_data section to the slave core. (Greenport only) */
	-#define MC_CMD_SHMBOOT_OP_IN_PUSH_SLAVE_DATA 0x0
	+#define MC_CMD_SHMBOOT_OP_IN_PUSH_SLAVE_DATA 0x0

	/* MC_CMD_SHMBOOT_OP_OUT msgresponse */
	#define MC_CMD_SHMBOOT_OP_OUT_LEN 0
	@@ -12361,14 +12466,14 @@
	#define MC_CMD_DUMP_DO_IN_PADDING_LEN 4
	#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_OFST 4
	#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_LEN 4
	-#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM 0x0 /* enum */
	-#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_DEFAULT 0x1 /* enum */
	+#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM 0x0 /* enum */
	+#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_DEFAULT 0x1 /* enum */
	#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_TYPE_OFST 8
	#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_TYPE_LEN 4
	-#define MC_CMD_DUMP_DO_IN_DUMP_LOCATION_NVRAM 0x1 /* enum */
	-#define MC_CMD_DUMP_DO_IN_DUMP_LOCATION_HOST_MEMORY 0x2 /* enum */
	-#define MC_CMD_DUMP_DO_IN_DUMP_LOCATION_HOST_MEMORY_MLI 0x3 /* enum */
	-#define MC_CMD_DUMP_DO_IN_DUMP_LOCATION_UART 0x4 /* enum */
	+#define MC_CMD_DUMP_DO_IN_DUMP_LOCATION_NVRAM 0x1 /* enum */
	+#define MC_CMD_DUMP_DO_IN_DUMP_LOCATION_HOST_MEMORY 0x2 /* enum */
	+#define MC_CMD_DUMP_DO_IN_DUMP_LOCATION_HOST_MEMORY_MLI 0x3 /* enum */
	+#define MC_CMD_DUMP_DO_IN_DUMP_LOCATION_UART 0x4 /* enum */
	#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_PARTITION_TYPE_ID_OFST 12
	#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_PARTITION_TYPE_ID_LEN 4
	#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_OFFSET_OFST 16
	@@ -12379,24 +12484,24 @@
	#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_HI_LEN 4
	#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_OFST 12
	#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_LEN 4
	-#define MC_CMD_DUMP_DO_IN_HOST_MEMORY_MLI_PAGE_SIZE 0x1000 /* enum */
	+#define MC_CMD_DUMP_DO_IN_HOST_MEMORY_MLI_PAGE_SIZE 0x1000 /* enum */
	#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_OFST 16
	#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_LEN 4
	#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_DEPTH_OFST 20
	#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_DEPTH_LEN 4
	-#define MC_CMD_DUMP_DO_IN_HOST_MEMORY_MLI_MAX_DEPTH 0x2 /* enum */
	+#define MC_CMD_DUMP_DO_IN_HOST_MEMORY_MLI_MAX_DEPTH 0x2 /* enum */
	#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_UART_PORT_OFST 12
	#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_UART_PORT_LEN 4
	/* enum: The uart port this command was received over (if using a uart
	* transport)
	*/
	-#define MC_CMD_DUMP_DO_IN_UART_PORT_SRC 0xff
	+#define MC_CMD_DUMP_DO_IN_UART_PORT_SRC 0xff
	#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_SIZE_OFST 24
	#define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_SIZE_LEN 4
	#define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_OFST 28
	#define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_LEN 4
	-#define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM 0x0 /* enum */
	-#define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_NVRAM_DUMP_PARTITION 0x1 /* enum */
	+#define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM 0x0 /* enum */
	+#define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_NVRAM_DUMP_PARTITION 0x1 /* enum */
	#define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_TYPE_OFST 32
	#define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_TYPE_LEN 4
	/* Enum values, see field(s): */
	@@ -12508,11 +12613,11 @@
	#define MC_CMD_SET_PSU_IN_LEN 12
	#define MC_CMD_SET_PSU_IN_PARAM_OFST 0
	#define MC_CMD_SET_PSU_IN_PARAM_LEN 4
	-#define MC_CMD_SET_PSU_IN_PARAM_SUPPLY_VOLTAGE 0x0 /* enum */
	+#define MC_CMD_SET_PSU_IN_PARAM_SUPPLY_VOLTAGE 0x0 /* enum */
	#define MC_CMD_SET_PSU_IN_RAIL_OFST 4
	#define MC_CMD_SET_PSU_IN_RAIL_LEN 4
	-#define MC_CMD_SET_PSU_IN_RAIL_0V9 0x0 /* enum */
	-#define MC_CMD_SET_PSU_IN_RAIL_1V2 0x1 /* enum */
	+#define MC_CMD_SET_PSU_IN_RAIL_0V9 0x0 /* enum */
	+#define MC_CMD_SET_PSU_IN_RAIL_1V2 0x1 /* enum */
	/* desired value, eg voltage in mV */
	#define MC_CMD_SET_PSU_IN_VALUE_OFST 8
	#define MC_CMD_SET_PSU_IN_VALUE_LEN 4
	@@ -12550,7 +12655,7 @@
	#define MC_CMD_ENABLE_OFFLINE_BIST 0xed
	#undef MC_CMD_0xed_PRIVILEGE_CTG

	-#define MC_CMD_0xed_PRIVILEGE_CTG SRIOV_CTG_ADMIN
	+#define MC_CMD_0xed_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND

	/* MC_CMD_ENABLE_OFFLINE_BIST_IN msgrequest */
	#define MC_CMD_ENABLE_OFFLINE_BIST_IN_LEN 0
	@@ -12681,7 +12786,7 @@
	#define MC_CMD_KR_TUNE 0xf1
	#undef MC_CMD_0xf1_PRIVILEGE_CTG

	-#define MC_CMD_0xf1_PRIVILEGE_CTG SRIOV_CTG_ADMIN
	+#define MC_CMD_0xf1_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND

	/* MC_CMD_KR_TUNE_IN msgrequest */
	#define MC_CMD_KR_TUNE_IN_LENMIN 4
	@@ -12691,30 +12796,30 @@
	#define MC_CMD_KR_TUNE_IN_KR_TUNE_OP_OFST 0
	#define MC_CMD_KR_TUNE_IN_KR_TUNE_OP_LEN 1
	/* enum: Get current RXEQ settings */
	-#define MC_CMD_KR_TUNE_IN_RXEQ_GET 0x0
	+#define MC_CMD_KR_TUNE_IN_RXEQ_GET 0x0
	/* enum: Override RXEQ settings */
	-#define MC_CMD_KR_TUNE_IN_RXEQ_SET 0x1
	+#define MC_CMD_KR_TUNE_IN_RXEQ_SET 0x1
	/* enum: Get current TX Driver settings */
	-#define MC_CMD_KR_TUNE_IN_TXEQ_GET 0x2
	+#define MC_CMD_KR_TUNE_IN_TXEQ_GET 0x2
	/* enum: Override TX Driver settings */
	-#define MC_CMD_KR_TUNE_IN_TXEQ_SET 0x3
	+#define MC_CMD_KR_TUNE_IN_TXEQ_SET 0x3
	/* enum: Force KR Serdes reset / recalibration */
	-#define MC_CMD_KR_TUNE_IN_RECAL 0x4
	+#define MC_CMD_KR_TUNE_IN_RECAL 0x4
	/* enum: Start KR Serdes Eye diagram plot on a given lane. Lane must have valid
	* signal.
	*/
	-#define MC_CMD_KR_TUNE_IN_START_EYE_PLOT 0x5
	+#define MC_CMD_KR_TUNE_IN_START_EYE_PLOT 0x5
	/* enum: Poll KR Serdes Eye diagram plot. Returns one row of BER data. The
	* caller should call this command repeatedly after starting eye plot, until no
	* more data is returned.
	*/
	-#define MC_CMD_KR_TUNE_IN_POLL_EYE_PLOT 0x6
	+#define MC_CMD_KR_TUNE_IN_POLL_EYE_PLOT 0x6
	/* enum: Read Figure Of Merit (eye quality, higher is better). */
	-#define MC_CMD_KR_TUNE_IN_READ_FOM 0x7
	+#define MC_CMD_KR_TUNE_IN_READ_FOM 0x7
	/* enum: Start/stop link training frames */
	-#define MC_CMD_KR_TUNE_IN_LINK_TRAIN_RUN 0x8
	+#define MC_CMD_KR_TUNE_IN_LINK_TRAIN_RUN 0x8
	/* enum: Issue KR link training command (control training coefficients) */
	-#define MC_CMD_KR_TUNE_IN_LINK_TRAIN_CMD 0x9
	+#define MC_CMD_KR_TUNE_IN_LINK_TRAIN_CMD 0x9
	/* Align the arguments to 32 bits */
	#define MC_CMD_KR_TUNE_IN_KR_TUNE_RSVD_OFST 1
	#define MC_CMD_KR_TUNE_IN_KR_TUNE_RSVD_LEN 3
	@@ -12748,98 +12853,98 @@
	#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_ID_LBN 0
	#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_ID_WIDTH 8
	/* enum: Attenuation (0-15, Huntington) */
	-#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_ATT 0x0
	+#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_ATT 0x0
	/* enum: CTLE Boost (0-15, Huntington) */
	-#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_BOOST 0x1
	+#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_BOOST 0x1
	/* enum: Edge DFE Tap1 (Huntington - 0 - max negative, 64 - zero, 127 - max
	* positive, Medford - 0-31)
	*/
	-#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP1 0x2
	+#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP1 0x2
	/* enum: Edge DFE Tap2 (Huntington - 0 - max negative, 32 - zero, 63 - max
	* positive, Medford - 0-31)
	*/
	-#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP2 0x3
	+#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP2 0x3
	/* enum: Edge DFE Tap3 (Huntington - 0 - max negative, 32 - zero, 63 - max
	* positive, Medford - 0-16)
	*/
	-#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP3 0x4
	+#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP3 0x4
	/* enum: Edge DFE Tap4 (Huntington - 0 - max negative, 32 - zero, 63 - max
	* positive, Medford - 0-16)
	*/
	-#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP4 0x5
	+#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP4 0x5
	/* enum: Edge DFE Tap5 (Huntington - 0 - max negative, 32 - zero, 63 - max
	* positive, Medford - 0-16)
	*/
	-#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP5 0x6
	+#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP5 0x6
	/* enum: Edge DFE DLEV (0-128 for Medford) */
	-#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_DLEV 0x7
	+#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_DLEV 0x7
	/* enum: Variable Gain Amplifier (0-15, Medford) */
	-#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_VGA 0x8
	+#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_VGA 0x8
	/* enum: CTLE EQ Capacitor (0-15, Medford) */
	-#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_CTLE_EQC 0x9
	+#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_CTLE_EQC 0x9
	/* enum: CTLE EQ Resistor (0-7, Medford) */
	-#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_CTLE_EQRES 0xa
	+#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_CTLE_EQRES 0xa
	/* enum: CTLE gain (0-31, Medford2) */
	-#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_CTLE_GAIN 0xb
	+#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_CTLE_GAIN 0xb
	/* enum: CTLE pole (0-31, Medford2) */
	-#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_CTLE_POLE 0xc
	+#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_CTLE_POLE 0xc
	/* enum: CTLE peaking (0-31, Medford2) */
	-#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_CTLE_PEAK 0xd
	+#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_CTLE_PEAK 0xd
	/* enum: DFE Tap1 - even path (Medford2 - 6 bit signed (-29 - +29)) */
	-#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP1_EVEN 0xe
	+#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP1_EVEN 0xe
	/* enum: DFE Tap1 - odd path (Medford2 - 6 bit signed (-29 - +29)) */
	-#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP1_ODD 0xf
	+#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP1_ODD 0xf
	/* enum: DFE Tap2 (Medford2 - 6 bit signed (-20 - +20)) */
	-#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP2 0x10
	+#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP2 0x10
	/* enum: DFE Tap3 (Medford2 - 6 bit signed (-20 - +20)) */
	-#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP3 0x11
	+#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP3 0x11
	/* enum: DFE Tap4 (Medford2 - 6 bit signed (-20 - +20)) */
	-#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP4 0x12
	+#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP4 0x12
	/* enum: DFE Tap5 (Medford2 - 6 bit signed (-24 - +24)) */
	-#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP5 0x13
	+#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP5 0x13
	/* enum: DFE Tap6 (Medford2 - 6 bit signed (-24 - +24)) */
	-#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP6 0x14
	+#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP6 0x14
	/* enum: DFE Tap7 (Medford2 - 6 bit signed (-24 - +24)) */
	-#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP7 0x15
	+#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP7 0x15
	/* enum: DFE Tap8 (Medford2 - 6 bit signed (-24 - +24)) */
	-#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP8 0x16
	+#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP8 0x16
	/* enum: DFE Tap9 (Medford2 - 6 bit signed (-24 - +24)) */
	-#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP9 0x17
	+#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP9 0x17
	/* enum: DFE Tap10 (Medford2 - 6 bit signed (-24 - +24)) */
	-#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP10 0x18
	+#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP10 0x18
	/* enum: DFE Tap11 (Medford2 - 6 bit signed (-24 - +24)) */
	-#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP11 0x19
	+#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP11 0x19
	/* enum: DFE Tap12 (Medford2 - 6 bit signed (-24 - +24)) */
	-#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP12 0x1a
	+#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP12 0x1a
	/* enum: I/Q clk offset (Medford2 - 4 bit signed (-5 - +5))) */
	-#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_IQ_OFF 0x1b
	+#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_IQ_OFF 0x1b
	/* enum: Negative h1 polarity data sampler offset calibration code, even path
	* (Medford2 - 6 bit signed (-29 - +29)))
	*/
	-#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_H1N_OFF_EVEN 0x1c
	+#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_H1N_OFF_EVEN 0x1c
	/* enum: Negative h1 polarity data sampler offset calibration code, odd path
	* (Medford2 - 6 bit signed (-29 - +29)))
	*/
	-#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_H1N_OFF_ODD 0x1d
	+#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_H1N_OFF_ODD 0x1d
	/* enum: Positive h1 polarity data sampler offset calibration code, even path
	* (Medford2 - 6 bit signed (-29 - +29)))
	*/
	-#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_H1P_OFF_EVEN 0x1e
	+#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_H1P_OFF_EVEN 0x1e
	/* enum: Positive h1 polarity data sampler offset calibration code, odd path
	* (Medford2 - 6 bit signed (-29 - +29)))
	*/
	-#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_H1P_OFF_ODD 0x1f
	+#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_H1P_OFF_ODD 0x1f
	/* enum: CDR calibration loop code (Medford2) */
	-#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_CDR_PVT 0x20
	+#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_CDR_PVT 0x20
	/* enum: CDR integral loop code (Medford2) */
	-#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_CDR_INTEG 0x21
	+#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_CDR_INTEG 0x21
	#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_LANE_LBN 8
	#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_LANE_WIDTH 3
	-#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_0 0x0 /* enum */
	-#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_1 0x1 /* enum */
	-#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_2 0x2 /* enum */
	-#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_3 0x3 /* enum */
	-#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_ALL 0x4 /* enum */
	+#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_0 0x0 /* enum */
	+#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_1 0x1 /* enum */
	+#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_2 0x2 /* enum */
	+#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_3 0x3 /* enum */
	+#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_ALL 0x4 /* enum */
	#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_LBN 11
	#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_WIDTH 1
	#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_RESERVED_LBN 12
	@@ -12905,38 +13010,38 @@
	#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_ID_LBN 0
	#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_ID_WIDTH 8
	/* enum: TX Amplitude (Huntington, Medford, Medford2) */
	-#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_LEV 0x0
	+#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_LEV 0x0
	/* enum: De-Emphasis Tap1 Magnitude (0-7) (Huntington) */
	-#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_MODE 0x1
	+#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_MODE 0x1
	/* enum: De-Emphasis Tap1 Fine */
	-#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_DTLEV 0x2
	+#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_DTLEV 0x2
	/* enum: De-Emphasis Tap2 Magnitude (0-6) (Huntington) */
	-#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_D2 0x3
	+#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_D2 0x3
	/* enum: De-Emphasis Tap2 Fine (Huntington) */
	-#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_D2TLEV 0x4
	+#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_D2TLEV 0x4
	/* enum: Pre-Emphasis Magnitude (Huntington) */
	-#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_E 0x5
	+#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_E 0x5
	/* enum: Pre-Emphasis Fine (Huntington) */
	-#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_ETLEV 0x6
	+#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_ETLEV 0x6
	/* enum: TX Slew Rate Coarse control (Huntington) */
	-#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_PREDRV_DLY 0x7
	+#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_PREDRV_DLY 0x7
	/* enum: TX Slew Rate Fine control (Huntington) */
	-#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_SR_SET 0x8
	+#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_SR_SET 0x8
	/* enum: TX Termination Impedance control (Huntington) */
	-#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_RT_SET 0x9
	+#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_RT_SET 0x9
	/* enum: TX Amplitude Fine control (Medford) */
	-#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_LEV_FINE 0xa
	+#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_LEV_FINE 0xa
	/* enum: Pre-shoot Tap (Medford, Medford2) */
	-#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TAP_ADV 0xb
	+#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TAP_ADV 0xb
	/* enum: De-emphasis Tap (Medford, Medford2) */
	-#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TAP_DLY 0xc
	+#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TAP_DLY 0xc
	#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_LANE_LBN 8
	#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_LANE_WIDTH 3
	-#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_0 0x0 /* enum */
	-#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_1 0x1 /* enum */
	-#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_2 0x2 /* enum */
	-#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_3 0x3 /* enum */
	-#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_ALL 0x4 /* enum */
	+#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_0 0x0 /* enum */
	+#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_1 0x1 /* enum */
	+#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_2 0x2 /* enum */
	+#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_3 0x3 /* enum */
	+#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_ALL 0x4 /* enum */
	#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_RESERVED_LBN 11
	#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_RESERVED_WIDTH 5
	#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_INITIAL_LBN 16
	@@ -13070,8 +13175,8 @@
	#define MC_CMD_KR_TUNE_LINK_TRAIN_RUN_IN_KR_TUNE_RSVD_LEN 3
	#define MC_CMD_KR_TUNE_LINK_TRAIN_RUN_IN_RUN_OFST 4
	#define MC_CMD_KR_TUNE_LINK_TRAIN_RUN_IN_RUN_LEN 4
	-#define MC_CMD_KR_TUNE_LINK_TRAIN_RUN_IN_STOP 0x0 /* enum */
	-#define MC_CMD_KR_TUNE_LINK_TRAIN_RUN_IN_START 0x1 /* enum */
	+#define MC_CMD_KR_TUNE_LINK_TRAIN_RUN_IN_STOP 0x0 /* enum */
	+#define MC_CMD_KR_TUNE_LINK_TRAIN_RUN_IN_START 0x1 /* enum */

	/* MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN msgrequest */
	#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_LEN 28
	@@ -13092,9 +13197,9 @@
	/* C(-1) request */
	#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_CM1_OFST 16
	#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_CM1_LEN 4
	-#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_REQ_HOLD 0x0 /* enum */
	-#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_REQ_INCREMENT 0x1 /* enum */
	-#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_REQ_DECREMENT 0x2 /* enum */
	+#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_REQ_HOLD 0x0 /* enum */
	+#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_REQ_INCREMENT 0x1 /* enum */
	+#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_REQ_DECREMENT 0x2 /* enum */
	/* C(0) request */
	#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_C0_OFST 20
	#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_C0_LEN 4
	@@ -13111,10 +13216,10 @@
	/* C(-1) status */
	#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_CM1_STATUS_OFST 0
	#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_CM1_STATUS_LEN 4
	-#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_STATUS_NOT_UPDATED 0x0 /* enum */
	-#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_STATUS_UPDATED 0x1 /* enum */
	-#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_STATUS_MINIMUM 0x2 /* enum */
	-#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_STATUS_MAXIMUM 0x3 /* enum */
	+#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_STATUS_NOT_UPDATED 0x0 /* enum */
	+#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_STATUS_UPDATED 0x1 /* enum */
	+#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_STATUS_MINIMUM 0x2 /* enum */
	+#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_STATUS_MAXIMUM 0x3 /* enum */
	/* C(0) status */
	#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_C0_STATUS_OFST 4
	#define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_C0_STATUS_LEN 4
	@@ -13143,7 +13248,7 @@
	#define MC_CMD_PCIE_TUNE 0xf2
	#undef MC_CMD_0xf2_PRIVILEGE_CTG

	-#define MC_CMD_0xf2_PRIVILEGE_CTG SRIOV_CTG_ADMIN
	+#define MC_CMD_0xf2_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND

	/* MC_CMD_PCIE_TUNE_IN msgrequest */
	#define MC_CMD_PCIE_TUNE_IN_LENMIN 4
	@@ -13153,22 +13258,22 @@
	#define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_OP_OFST 0
	#define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_OP_LEN 1
	/* enum: Get current RXEQ settings */
	-#define MC_CMD_PCIE_TUNE_IN_RXEQ_GET 0x0
	+#define MC_CMD_PCIE_TUNE_IN_RXEQ_GET 0x0
	/* enum: Override RXEQ settings */
	-#define MC_CMD_PCIE_TUNE_IN_RXEQ_SET 0x1
	+#define MC_CMD_PCIE_TUNE_IN_RXEQ_SET 0x1
	/* enum: Get current TX Driver settings */
	-#define MC_CMD_PCIE_TUNE_IN_TXEQ_GET 0x2
	+#define MC_CMD_PCIE_TUNE_IN_TXEQ_GET 0x2
	/* enum: Override TX Driver settings */
	-#define MC_CMD_PCIE_TUNE_IN_TXEQ_SET 0x3
	+#define MC_CMD_PCIE_TUNE_IN_TXEQ_SET 0x3
	/* enum: Start PCIe Serdes Eye diagram plot on a given lane. */
	-#define MC_CMD_PCIE_TUNE_IN_START_EYE_PLOT 0x5
	+#define MC_CMD_PCIE_TUNE_IN_START_EYE_PLOT 0x5
	/* enum: Poll PCIe Serdes Eye diagram plot. Returns one row of BER data. The
	* caller should call this command repeatedly after starting eye plot, until no
	* more data is returned.
	*/
	-#define MC_CMD_PCIE_TUNE_IN_POLL_EYE_PLOT 0x6
	+#define MC_CMD_PCIE_TUNE_IN_POLL_EYE_PLOT 0x6
	/* enum: Enable the SERDES BIST and set it to generate a 200MHz square wave */
	-#define MC_CMD_PCIE_TUNE_IN_BIST_SQUARE_WAVE 0x7
	+#define MC_CMD_PCIE_TUNE_IN_BIST_SQUARE_WAVE 0x7
	/* Align the arguments to 32 bits */
	#define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_RSVD_OFST 1
	#define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_RSVD_LEN 3
	@@ -13202,46 +13307,46 @@
	#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_ID_LBN 0
	#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_ID_WIDTH 8
	/* enum: Attenuation (0-15) */
	-#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_ATT 0x0
	+#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_ATT 0x0
	/* enum: CTLE Boost (0-15) */
	-#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_BOOST 0x1
	+#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_BOOST 0x1
	/* enum: DFE Tap1 (0 - max negative, 64 - zero, 127 - max positive) */
	-#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP1 0x2
	+#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP1 0x2
	/* enum: DFE Tap2 (0 - max negative, 32 - zero, 63 - max positive) */
	-#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP2 0x3
	+#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP2 0x3
	/* enum: DFE Tap3 (0 - max negative, 32 - zero, 63 - max positive) */
	-#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP3 0x4
	+#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP3 0x4
	/* enum: DFE Tap4 (0 - max negative, 32 - zero, 63 - max positive) */
	-#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP4 0x5
	+#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP4 0x5
	/* enum: DFE Tap5 (0 - max negative, 32 - zero, 63 - max positive) */
	-#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP5 0x6
	+#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP5 0x6
	/* enum: DFE DLev */
	-#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_DLEV 0x7
	+#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_DLEV 0x7
	/* enum: Figure of Merit */
	-#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_FOM 0x8
	+#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_FOM 0x8
	/* enum: CTLE EQ Capacitor (HF Gain) */
	-#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_CTLE_EQC 0x9
	+#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_CTLE_EQC 0x9
	/* enum: CTLE EQ Resistor (DC Gain) */
	-#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_CTLE_EQRES 0xa
	+#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_CTLE_EQRES 0xa
	#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_LANE_LBN 8
	#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_LANE_WIDTH 5
	-#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_0 0x0 /* enum */
	-#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_1 0x1 /* enum */
	-#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_2 0x2 /* enum */
	-#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_3 0x3 /* enum */
	-#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_4 0x4 /* enum */
	-#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_5 0x5 /* enum */
	-#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_6 0x6 /* enum */
	-#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_7 0x7 /* enum */
	-#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_8 0x8 /* enum */
	-#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_9 0x9 /* enum */
	-#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_10 0xa /* enum */
	-#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_11 0xb /* enum */
	-#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_12 0xc /* enum */
	-#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_13 0xd /* enum */
	-#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_14 0xe /* enum */
	-#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_15 0xf /* enum */
	-#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_ALL 0x10 /* enum */
	+#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_0 0x0 /* enum */
	+#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_1 0x1 /* enum */
	+#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_2 0x2 /* enum */
	+#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_3 0x3 /* enum */
	+#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_4 0x4 /* enum */
	+#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_5 0x5 /* enum */
	+#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_6 0x6 /* enum */
	+#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_7 0x7 /* enum */
	+#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_8 0x8 /* enum */
	+#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_9 0x9 /* enum */
	+#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_10 0xa /* enum */
	+#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_11 0xb /* enum */
	+#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_12 0xc /* enum */
	+#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_13 0xd /* enum */
	+#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_14 0xe /* enum */
	+#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_15 0xf /* enum */
	+#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_ALL 0x10 /* enum */
	#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_LBN 13
	#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_WIDTH 1
	#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_RESERVED_LBN 14
	@@ -13305,15 +13410,15 @@
	#define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_ID_LBN 0
	#define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_ID_WIDTH 8
	/* enum: TxMargin (PIPE) */
	-#define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_TXMARGIN 0x0
	+#define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_TXMARGIN 0x0
	/* enum: TxSwing (PIPE) */
	-#define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_TXSWING 0x1
	+#define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_TXSWING 0x1
	/* enum: De-emphasis coefficient C(-1) (PIPE) */
	-#define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_CM1 0x2
	+#define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_CM1 0x2
	/* enum: De-emphasis coefficient C(0) (PIPE) */
	-#define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_C0 0x3
	+#define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_C0 0x3
	/* enum: De-emphasis coefficient C(+1) (PIPE) */
	-#define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_CP1 0x4
	+#define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_CP1 0x4
	#define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_LANE_LBN 8
	#define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_LANE_WIDTH 4
	/* Enum values, see field(s): */
	@@ -13380,9 +13485,9 @@
	/* enum: re-read and apply licenses after a license key partition update; note
	* that this operation returns a zero-length response
	*/
	-#define MC_CMD_LICENSING_IN_OP_UPDATE_LICENSE 0x0
	+#define MC_CMD_LICENSING_IN_OP_UPDATE_LICENSE 0x0
	/* enum: report counts of installed licenses */
	-#define MC_CMD_LICENSING_IN_OP_GET_KEY_STATS 0x1
	+#define MC_CMD_LICENSING_IN_OP_GET_KEY_STATS 0x1

	/* MC_CMD_LICENSING_OUT msgresponse */
	#define MC_CMD_LICENSING_OUT_LEN 28
	@@ -13413,9 +13518,9 @@
	#define MC_CMD_LICENSING_OUT_LICENSING_SELF_TEST_OFST 24
	#define MC_CMD_LICENSING_OUT_LICENSING_SELF_TEST_LEN 4
	/* enum: licensing subsystem self-test failed */
	-#define MC_CMD_LICENSING_OUT_SELF_TEST_FAIL 0x0
	+#define MC_CMD_LICENSING_OUT_SELF_TEST_FAIL 0x0
	/* enum: licensing subsystem self-test passed */
	-#define MC_CMD_LICENSING_OUT_SELF_TEST_PASS 0x1
	+#define MC_CMD_LICENSING_OUT_SELF_TEST_PASS 0x1


	/***********************************/
	@@ -13436,11 +13541,11 @@
	/* enum: re-read and apply licenses after a license key partition update; note
	* that this operation returns a zero-length response
	*/
	-#define MC_CMD_LICENSING_V3_IN_OP_UPDATE_LICENSE 0x0
	+#define MC_CMD_LICENSING_V3_IN_OP_UPDATE_LICENSE 0x0
	/* enum: report counts of installed licenses Returns EAGAIN if license
	* processing (updating) has been started but not yet completed.
	*/
	-#define MC_CMD_LICENSING_V3_IN_OP_REPORT_LICENSE 0x1
	+#define MC_CMD_LICENSING_V3_IN_OP_REPORT_LICENSE 0x1

	/* MC_CMD_LICENSING_V3_OUT msgresponse */
	#define MC_CMD_LICENSING_V3_OUT_LEN 88
	@@ -13467,9 +13572,9 @@
	#define MC_CMD_LICENSING_V3_OUT_LICENSING_SELF_TEST_OFST 20
	#define MC_CMD_LICENSING_V3_OUT_LICENSING_SELF_TEST_LEN 4
	/* enum: licensing subsystem self-test failed */
	-#define MC_CMD_LICENSING_V3_OUT_SELF_TEST_FAIL 0x0
	+#define MC_CMD_LICENSING_V3_OUT_SELF_TEST_FAIL 0x0
	/* enum: licensing subsystem self-test passed */
	-#define MC_CMD_LICENSING_V3_OUT_SELF_TEST_PASS 0x1
	+#define MC_CMD_LICENSING_V3_OUT_SELF_TEST_PASS 0x1
	/* bitmask of licensed applications */
	#define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_OFST 24
	#define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_LEN 8
	@@ -13558,9 +13663,9 @@
	#define MC_CMD_GET_LICENSED_APP_STATE_OUT_STATE_OFST 0
	#define MC_CMD_GET_LICENSED_APP_STATE_OUT_STATE_LEN 4
	/* enum: no (or invalid) license is present for the application */
	-#define MC_CMD_GET_LICENSED_APP_STATE_OUT_NOT_LICENSED 0x0
	+#define MC_CMD_GET_LICENSED_APP_STATE_OUT_NOT_LICENSED 0x0
	/* enum: a valid license is present for the application */
	-#define MC_CMD_GET_LICENSED_APP_STATE_OUT_LICENSED 0x1
	+#define MC_CMD_GET_LICENSED_APP_STATE_OUT_LICENSED 0x1


	/***********************************/
	@@ -13590,9 +13695,9 @@
	#define MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_STATE_OFST 0
	#define MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_STATE_LEN 4
	/* enum: no (or invalid) license is present for the application */
	-#define MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_NOT_LICENSED 0x0
	+#define MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_NOT_LICENSED 0x0
	/* enum: a valid license is present for the application */
	-#define MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_LICENSED 0x1
	+#define MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_LICENSED 0x1


	/***********************************/
	@@ -13646,9 +13751,9 @@
	#define MC_CMD_LICENSED_APP_OP_IN_OP_OFST 4
	#define MC_CMD_LICENSED_APP_OP_IN_OP_LEN 4
	/* enum: validate application */
	-#define MC_CMD_LICENSED_APP_OP_IN_OP_VALIDATE 0x0
	+#define MC_CMD_LICENSED_APP_OP_IN_OP_VALIDATE 0x0
	/* enum: mask application */
	-#define MC_CMD_LICENSED_APP_OP_IN_OP_MASK 0x1
	+#define MC_CMD_LICENSED_APP_OP_IN_OP_MASK 0x1
	/* arguments specific to this particular operation */
	#define MC_CMD_LICENSED_APP_OP_IN_ARGS_OFST 8
	#define MC_CMD_LICENSED_APP_OP_IN_ARGS_LEN 4
	@@ -13740,9 +13845,9 @@
	#define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_UNITS_OFST 100
	#define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_UNITS_LEN 4
	/* enum: expiry units are accounting units */
	-#define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_UNIT_ACC 0x0
	+#define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_UNIT_ACC 0x0
	/* enum: expiry units are calendar days */
	-#define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_UNIT_DAYS 0x1
	+#define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_UNIT_DAYS 0x1
	/* base MAC address of the NIC stored in NVRAM (note that this is a constant
	* value for a given NIC regardless which function is calling, effectively this
	* is PF0 base MAC address)
	@@ -13776,9 +13881,9 @@
	#define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_FLAG_OFST 8
	#define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_FLAG_LEN 4
	/* enum: turn the features off */
	-#define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_OFF 0x0
	+#define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_OFF 0x0
	/* enum: turn the features back on */
	-#define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_ON 0x1
	+#define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_ON 0x1

	/* MC_CMD_LICENSED_V3_MASK_FEATURES_OUT msgresponse */
	#define MC_CMD_LICENSED_V3_MASK_FEATURES_OUT_LEN 0
	@@ -13795,7 +13900,7 @@
	#define MC_CMD_LICENSING_V3_TEMPORARY 0xd6
	#undef MC_CMD_0xd6_PRIVILEGE_CTG

	-#define MC_CMD_0xd6_PRIVILEGE_CTG SRIOV_CTG_ADMIN
	+#define MC_CMD_0xd6_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND

	/* MC_CMD_LICENSING_V3_TEMPORARY_IN msgrequest */
	#define MC_CMD_LICENSING_V3_TEMPORARY_IN_LEN 4
	@@ -13806,15 +13911,15 @@
	* This is an asynchronous operation owing to the time taken to validate an
	* ECDSA license
	*/
	-#define MC_CMD_LICENSING_V3_TEMPORARY_SET 0x0
	+#define MC_CMD_LICENSING_V3_TEMPORARY_SET 0x0
	/* enum: clear the license immediately rather than waiting for the next power
	* cycle
	*/
	-#define MC_CMD_LICENSING_V3_TEMPORARY_CLEAR 0x1
	+#define MC_CMD_LICENSING_V3_TEMPORARY_CLEAR 0x1
	/* enum: get the status of the asynchronous MC_CMD_LICENSING_V3_TEMPORARY_SET
	* operation
	*/
	-#define MC_CMD_LICENSING_V3_TEMPORARY_STATUS 0x2
	+#define MC_CMD_LICENSING_V3_TEMPORARY_STATUS 0x2

	/* MC_CMD_LICENSING_V3_TEMPORARY_IN_SET msgrequest */
	#define MC_CMD_LICENSING_V3_TEMPORARY_IN_SET_LEN 164
	@@ -13840,13 +13945,13 @@
	#define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_STATUS_OFST 0
	#define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_STATUS_LEN 4
	/* enum: finished validating and installing license */
	-#define MC_CMD_LICENSING_V3_TEMPORARY_STATUS_OK 0x0
	+#define MC_CMD_LICENSING_V3_TEMPORARY_STATUS_OK 0x0
	/* enum: license validation and installation in progress */
	-#define MC_CMD_LICENSING_V3_TEMPORARY_STATUS_IN_PROGRESS 0x1
	+#define MC_CMD_LICENSING_V3_TEMPORARY_STATUS_IN_PROGRESS 0x1
	/* enum: licensing error. More specific error messages are not provided to
	* avoid exposing details of the licensing system to the client
	*/
	-#define MC_CMD_LICENSING_V3_TEMPORARY_STATUS_ERROR 0x2
	+#define MC_CMD_LICENSING_V3_TEMPORARY_STATUS_ERROR 0x2
	/* bitmask of licensed features */
	#define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_OFST 4
	#define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_LEN 8
	@@ -13883,9 +13988,9 @@
	#define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_MODE_OFST 8
	#define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_MODE_LEN 4
	/* enum: receive to just the specified queue */
	-#define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_MODE_SIMPLE 0x0
	+#define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_MODE_SIMPLE 0x0
	/* enum: receive to multiple queues using RSS context */
	-#define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_MODE_RSS 0x1
	+#define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_MODE_RSS 0x1
	/* RSS context (for RX_MODE_RSS) as returned by MC_CMD_RSS_CONTEXT_ALLOC. Note
	* that these handles should be considered opaque to the host, although a value
	* of 0xFFFFFFFF is guaranteed never to be a valid handle.
	@@ -13906,7 +14011,7 @@
	#define MC_CMD_GET_PORT_SNIFF_CONFIG 0xf8
	#undef MC_CMD_0xf8_PRIVILEGE_CTG

	-#define MC_CMD_0xf8_PRIVILEGE_CTG SRIOV_CTG_ADMIN
	+#define MC_CMD_0xf8_PRIVILEGE_CTG SRIOV_CTG_GENERAL

	/* MC_CMD_GET_PORT_SNIFF_CONFIG_IN msgrequest */
	#define MC_CMD_GET_PORT_SNIFF_CONFIG_IN_LEN 0
	@@ -13927,9 +14032,9 @@
	#define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_MODE_OFST 8
	#define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_MODE_LEN 4
	/* enum: receiving to just the specified queue */
	-#define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_MODE_SIMPLE 0x0
	+#define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_MODE_SIMPLE 0x0
	/* enum: receiving to multiple queues using RSS context */
	-#define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_MODE_RSS 0x1
	+#define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_MODE_RSS 0x1
	/* RSS context (for RX_MODE_RSS) */
	#define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_CONTEXT_OFST 12
	#define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_CONTEXT_LEN 4
	@@ -13954,12 +14059,12 @@
	/* enum: Per-TXQ enable for multicast UDP destination lookup for possible
	* internal loopback. (ENTITY is a queue handle, VALUE is a single boolean.)
	*/
	-#define MC_CMD_SET_PARSER_DISP_CONFIG_IN_TXQ_MCAST_UDP_DST_LOOKUP_EN 0x0
	+#define MC_CMD_SET_PARSER_DISP_CONFIG_IN_TXQ_MCAST_UDP_DST_LOOKUP_EN 0x0
	/* enum: Per-v-adaptor enable for suppression of self-transmissions on the
	* internal loopback path. (ENTITY is an EVB_PORT_ID, VALUE is a single
	* boolean.)
	*/
	-#define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VADAPTOR_SUPPRESS_SELF_TX 0x1
	+#define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VADAPTOR_SUPPRESS_SELF_TX 0x1
	/* handle for the entity to update: queue handle, EVB port ID, etc. depending
	* on the type of configuration setting being changed
	*/
	@@ -14041,9 +14146,9 @@
	#define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_MODE_OFST 8
	#define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_MODE_LEN 4
	/* enum: receive to just the specified queue */
	-#define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_MODE_SIMPLE 0x0
	+#define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_MODE_SIMPLE 0x0
	/* enum: receive to multiple queues using RSS context */
	-#define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_MODE_RSS 0x1
	+#define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_MODE_RSS 0x1
	/* RSS context (for RX_MODE_RSS) as returned by MC_CMD_RSS_CONTEXT_ALLOC. Note
	* that these handles should be considered opaque to the host, although a value
	* of 0xFFFFFFFF is guaranteed never to be a valid handle.
	@@ -14064,7 +14169,7 @@
	#define MC_CMD_GET_TX_PORT_SNIFF_CONFIG 0xfc
	#undef MC_CMD_0xfc_PRIVILEGE_CTG

	-#define MC_CMD_0xfc_PRIVILEGE_CTG SRIOV_CTG_ADMIN
	+#define MC_CMD_0xfc_PRIVILEGE_CTG SRIOV_CTG_GENERAL

	/* MC_CMD_GET_TX_PORT_SNIFF_CONFIG_IN msgrequest */
	#define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_IN_LEN 0
	@@ -14083,9 +14188,9 @@
	#define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_MODE_OFST 8
	#define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_MODE_LEN 4
	/* enum: receiving to just the specified queue */
	-#define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_MODE_SIMPLE 0x0
	+#define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_MODE_SIMPLE 0x0
	/* enum: receiving to multiple queues using RSS context */
	-#define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_MODE_RSS 0x1
	+#define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_MODE_RSS 0x1
	/* RSS context (for RX_MODE_RSS) */
	#define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_CONTEXT_OFST 12
	#define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_CONTEXT_LEN 4
	@@ -14199,9 +14304,9 @@
	#define MC_CMD_READ_ATB_IN_LEN 16
	#define MC_CMD_READ_ATB_IN_SIGNAL_BUS_OFST 0
	#define MC_CMD_READ_ATB_IN_SIGNAL_BUS_LEN 4
	-#define MC_CMD_READ_ATB_IN_BUS_CCOM 0x0 /* enum */
	-#define MC_CMD_READ_ATB_IN_BUS_CKR 0x1 /* enum */
	-#define MC_CMD_READ_ATB_IN_BUS_CPCIE 0x8 /* enum */
	+#define MC_CMD_READ_ATB_IN_BUS_CCOM 0x0 /* enum */
	+#define MC_CMD_READ_ATB_IN_BUS_CKR 0x1 /* enum */
	+#define MC_CMD_READ_ATB_IN_BUS_CPCIE 0x8 /* enum */
	#define MC_CMD_READ_ATB_IN_SIGNAL_EN_BITNO_OFST 4
	#define MC_CMD_READ_ATB_IN_SIGNAL_EN_BITNO_LEN 4
	#define MC_CMD_READ_ATB_IN_SIGNAL_SEL_OFST 8
	@@ -14273,46 +14378,52 @@
	#define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_PF_WIDTH 16
	#define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_VF_LBN 16
	#define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_VF_WIDTH 16
	-#define MC_CMD_PRIVILEGE_MASK_IN_VF_NULL 0xffff /* enum */
	+#define MC_CMD_PRIVILEGE_MASK_IN_VF_NULL 0xffff /* enum */
	/* New privilege mask to be set. The mask will only be changed if the MSB is
	* set to 1.
	*/
	#define MC_CMD_PRIVILEGE_MASK_IN_NEW_MASK_OFST 4
	#define MC_CMD_PRIVILEGE_MASK_IN_NEW_MASK_LEN 4
	-#define MC_CMD_PRIVILEGE_MASK_IN_GRP_ADMIN 0x1 /* enum */
	-#define MC_CMD_PRIVILEGE_MASK_IN_GRP_LINK 0x2 /* enum */
	-#define MC_CMD_PRIVILEGE_MASK_IN_GRP_ONLOAD 0x4 /* enum */
	-#define MC_CMD_PRIVILEGE_MASK_IN_GRP_PTP 0x8 /* enum */
	-#define MC_CMD_PRIVILEGE_MASK_IN_GRP_INSECURE_FILTERS 0x10 /* enum */
	+#define MC_CMD_PRIVILEGE_MASK_IN_GRP_ADMIN 0x1 /* enum */
	+#define MC_CMD_PRIVILEGE_MASK_IN_GRP_LINK 0x2 /* enum */
	+#define MC_CMD_PRIVILEGE_MASK_IN_GRP_ONLOAD 0x4 /* enum */
	+#define MC_CMD_PRIVILEGE_MASK_IN_GRP_PTP 0x8 /* enum */
	+#define MC_CMD_PRIVILEGE_MASK_IN_GRP_INSECURE_FILTERS 0x10 /* enum */
	/* enum: Deprecated. Equivalent to MAC_SPOOFING_TX combined with CHANGE_MAC. */
	-#define MC_CMD_PRIVILEGE_MASK_IN_GRP_MAC_SPOOFING 0x20
	-#define MC_CMD_PRIVILEGE_MASK_IN_GRP_UNICAST 0x40 /* enum */
	-#define MC_CMD_PRIVILEGE_MASK_IN_GRP_MULTICAST 0x80 /* enum */
	-#define MC_CMD_PRIVILEGE_MASK_IN_GRP_BROADCAST 0x100 /* enum */
	-#define MC_CMD_PRIVILEGE_MASK_IN_GRP_ALL_MULTICAST 0x200 /* enum */
	-#define MC_CMD_PRIVILEGE_MASK_IN_GRP_PROMISCUOUS 0x400 /* enum */
	+#define MC_CMD_PRIVILEGE_MASK_IN_GRP_MAC_SPOOFING 0x20
	+#define MC_CMD_PRIVILEGE_MASK_IN_GRP_UNICAST 0x40 /* enum */
	+#define MC_CMD_PRIVILEGE_MASK_IN_GRP_MULTICAST 0x80 /* enum */
	+#define MC_CMD_PRIVILEGE_MASK_IN_GRP_BROADCAST 0x100 /* enum */
	+#define MC_CMD_PRIVILEGE_MASK_IN_GRP_ALL_MULTICAST 0x200 /* enum */
	+#define MC_CMD_PRIVILEGE_MASK_IN_GRP_PROMISCUOUS 0x400 /* enum */
	/* enum: Allows to set the TX packets' source MAC address to any arbitrary MAC
	* adress.
	*/
	-#define MC_CMD_PRIVILEGE_MASK_IN_GRP_MAC_SPOOFING_TX 0x800
	+#define MC_CMD_PRIVILEGE_MASK_IN_GRP_MAC_SPOOFING_TX 0x800
	/* enum: Privilege that allows a Function to change the MAC address configured
	* in its associated vAdapter/vPort.
	*/
	-#define MC_CMD_PRIVILEGE_MASK_IN_GRP_CHANGE_MAC 0x1000
	+#define MC_CMD_PRIVILEGE_MASK_IN_GRP_CHANGE_MAC 0x1000
	/* enum: Privilege that allows a Function to install filters that specify VLANs
	* that are not in the permit list for the associated vPort. This privilege is
	* primarily to support ESX where vPorts are created that restrict traffic to
	* only a set of permitted VLANs. See the vPort flag FLAG_VLAN_RESTRICT.
	*/
	-#define MC_CMD_PRIVILEGE_MASK_IN_GRP_UNRESTRICTED_VLAN 0x2000
	+#define MC_CMD_PRIVILEGE_MASK_IN_GRP_UNRESTRICTED_VLAN 0x2000
	/* enum: Privilege for insecure commands. Commands that belong to this group
	* are not permitted on secure adapters regardless of the privilege mask.
	*/
	-#define MC_CMD_PRIVILEGE_MASK_IN_GRP_INSECURE 0x4000
	+#define MC_CMD_PRIVILEGE_MASK_IN_GRP_INSECURE 0x4000
	+/* enum: Trusted Server Adapter (TSA) / ServerLock. Privilege for
	+ * administrator-level operations that are not allowed from the local host once
	+ * an adapter has Bound to a remote ServerLock Controller (see doxbox
	+ * SF-117064-DG for background).
	+ */
	+#define MC_CMD_PRIVILEGE_MASK_IN_GRP_ADMIN_TSA_UNBOUND 0x8000
	/* enum: Set this bit to indicate that a new privilege mask is to be set,
	* otherwise the command will only read the existing mask.
	*/
	-#define MC_CMD_PRIVILEGE_MASK_IN_DO_CHANGE 0x80000000
	+#define MC_CMD_PRIVILEGE_MASK_IN_DO_CHANGE 0x80000000

	/* MC_CMD_PRIVILEGE_MASK_OUT msgresponse */
	#define MC_CMD_PRIVILEGE_MASK_OUT_LEN 4
	@@ -14344,12 +14455,12 @@
	/* New link state mode to be set */
	#define MC_CMD_LINK_STATE_MODE_IN_NEW_MODE_OFST 4
	#define MC_CMD_LINK_STATE_MODE_IN_NEW_MODE_LEN 4
	-#define MC_CMD_LINK_STATE_MODE_IN_LINK_STATE_AUTO 0x0 /* enum */
	-#define MC_CMD_LINK_STATE_MODE_IN_LINK_STATE_UP 0x1 /* enum */
	-#define MC_CMD_LINK_STATE_MODE_IN_LINK_STATE_DOWN 0x2 /* enum */
	+#define MC_CMD_LINK_STATE_MODE_IN_LINK_STATE_AUTO 0x0 /* enum */
	+#define MC_CMD_LINK_STATE_MODE_IN_LINK_STATE_UP 0x1 /* enum */
	+#define MC_CMD_LINK_STATE_MODE_IN_LINK_STATE_DOWN 0x2 /* enum */
	/* enum: Use this value to just read the existing setting without modifying it.
	*/
	-#define MC_CMD_LINK_STATE_MODE_IN_DO_NOT_CHANGE 0xffffffff
	+#define MC_CMD_LINK_STATE_MODE_IN_DO_NOT_CHANGE 0xffffffff

	/* MC_CMD_LINK_STATE_MODE_OUT msgresponse */
	#define MC_CMD_LINK_STATE_MODE_OUT_LEN 4
	@@ -14448,12 +14559,12 @@
	/* The groups of functions to have their privilege masks modified. */
	#define MC_CMD_PRIVILEGE_MODIFY_IN_FN_GROUP_OFST 0
	#define MC_CMD_PRIVILEGE_MODIFY_IN_FN_GROUP_LEN 4
	-#define MC_CMD_PRIVILEGE_MODIFY_IN_NONE 0x0 /* enum */
	-#define MC_CMD_PRIVILEGE_MODIFY_IN_ALL 0x1 /* enum */
	-#define MC_CMD_PRIVILEGE_MODIFY_IN_PFS_ONLY 0x2 /* enum */
	-#define MC_CMD_PRIVILEGE_MODIFY_IN_VFS_ONLY 0x3 /* enum */
	-#define MC_CMD_PRIVILEGE_MODIFY_IN_VFS_OF_PF 0x4 /* enum */
	-#define MC_CMD_PRIVILEGE_MODIFY_IN_ONE 0x5 /* enum */
	+#define MC_CMD_PRIVILEGE_MODIFY_IN_NONE 0x0 /* enum */
	+#define MC_CMD_PRIVILEGE_MODIFY_IN_ALL 0x1 /* enum */
	+#define MC_CMD_PRIVILEGE_MODIFY_IN_PFS_ONLY 0x2 /* enum */
	+#define MC_CMD_PRIVILEGE_MODIFY_IN_VFS_ONLY 0x3 /* enum */
	+#define MC_CMD_PRIVILEGE_MODIFY_IN_VFS_OF_PF 0x4 /* enum */
	+#define MC_CMD_PRIVILEGE_MODIFY_IN_ONE 0x5 /* enum */
	/* For VFS_OF_PF specify the PF, for ONE specify the target function */
	#define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_OFST 4
	#define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_LEN 4
	@@ -14559,11 +14670,11 @@
	/* Sector type */
	#define MC_CMD_XPM_READ_SECTOR_OUT_TYPE_OFST 0
	#define MC_CMD_XPM_READ_SECTOR_OUT_TYPE_LEN 4
	-#define MC_CMD_XPM_READ_SECTOR_OUT_BLANK 0x0 /* enum */
	-#define MC_CMD_XPM_READ_SECTOR_OUT_CRYPTO_KEY_128 0x1 /* enum */
	-#define MC_CMD_XPM_READ_SECTOR_OUT_CRYPTO_KEY_256 0x2 /* enum */
	-#define MC_CMD_XPM_READ_SECTOR_OUT_CRYPTO_DATA 0x3 /* enum */
	-#define MC_CMD_XPM_READ_SECTOR_OUT_INVALID 0xff /* enum */
	+#define MC_CMD_XPM_READ_SECTOR_OUT_BLANK 0x0 /* enum */
	+#define MC_CMD_XPM_READ_SECTOR_OUT_CRYPTO_KEY_128 0x1 /* enum */
	+#define MC_CMD_XPM_READ_SECTOR_OUT_CRYPTO_KEY_256 0x2 /* enum */
	+#define MC_CMD_XPM_READ_SECTOR_OUT_CRYPTO_DATA 0x3 /* enum */
	+#define MC_CMD_XPM_READ_SECTOR_OUT_INVALID 0xff /* enum */
	/* Sector data */
	#define MC_CMD_XPM_READ_SECTOR_OUT_DATA_OFST 4
	#define MC_CMD_XPM_READ_SECTOR_OUT_DATA_LEN 1
	@@ -14738,7 +14849,7 @@
	#define MC_CMD_EXEC_SIGNED 0x10c
	#undef MC_CMD_0x10c_PRIVILEGE_CTG

	-#define MC_CMD_0x10c_PRIVILEGE_CTG SRIOV_CTG_ADMIN
	+#define MC_CMD_0x10c_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND

	/* MC_CMD_EXEC_SIGNED_IN msgrequest */
	#define MC_CMD_EXEC_SIGNED_IN_LEN 28
	@@ -14768,7 +14879,7 @@
	#define MC_CMD_PREPARE_SIGNED 0x10d
	#undef MC_CMD_0x10d_PRIVILEGE_CTG

	-#define MC_CMD_0x10d_PRIVILEGE_CTG SRIOV_CTG_ADMIN
	+#define MC_CMD_0x10d_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND

	/* MC_CMD_PREPARE_SIGNED_IN msgrequest */
	#define MC_CMD_PREPARE_SIGNED_IN_LEN 4
	@@ -14791,7 +14902,7 @@
	#define MC_CMD_SET_SECURITY_RULE 0x10f
	#undef MC_CMD_0x10f_PRIVILEGE_CTG

	-#define MC_CMD_0x10f_PRIVILEGE_CTG SRIOV_CTG_ADMIN
	+#define MC_CMD_0x10f_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND

	/* MC_CMD_SET_SECURITY_RULE_IN msgrequest */
	#define MC_CMD_SET_SECURITY_RULE_IN_LEN 92
	@@ -14893,45 +15004,45 @@
	#define MC_CMD_SET_SECURITY_RULE_IN_TX_ACTION_OFST 80
	#define MC_CMD_SET_SECURITY_RULE_IN_TX_ACTION_LEN 4
	/* enum: make no decision */
	-#define MC_CMD_SET_SECURITY_RULE_IN_TX_ACTION_NONE 0x0
	+#define MC_CMD_SET_SECURITY_RULE_IN_TX_ACTION_NONE 0x0
	/* enum: decide to accept the packet */
	-#define MC_CMD_SET_SECURITY_RULE_IN_TX_ACTION_WHITELIST 0x1
	+#define MC_CMD_SET_SECURITY_RULE_IN_TX_ACTION_WHITELIST 0x1
	/* enum: decide to drop the packet */
	-#define MC_CMD_SET_SECURITY_RULE_IN_TX_ACTION_BLACKLIST 0x2
	+#define MC_CMD_SET_SECURITY_RULE_IN_TX_ACTION_BLACKLIST 0x2
	/* enum: inform the TSA controller about some sample of packets matching this
	* rule (via MC_CMD_TSA_INFO_IN_PKT_SAMPLE messages); may be bitwise-ORed with
	* either the WHITELIST or BLACKLIST action
	*/
	-#define MC_CMD_SET_SECURITY_RULE_IN_TX_ACTION_SAMPLE 0x4
	+#define MC_CMD_SET_SECURITY_RULE_IN_TX_ACTION_SAMPLE 0x4
	/* enum: do not change the current TX action */
	-#define MC_CMD_SET_SECURITY_RULE_IN_TX_ACTION_UNCHANGED 0xffffffff
	+#define MC_CMD_SET_SECURITY_RULE_IN_TX_ACTION_UNCHANGED 0xffffffff
	/* set the action for received packets matching this rule */
	#define MC_CMD_SET_SECURITY_RULE_IN_RX_ACTION_OFST 84
	#define MC_CMD_SET_SECURITY_RULE_IN_RX_ACTION_LEN 4
	/* enum: make no decision */
	-#define MC_CMD_SET_SECURITY_RULE_IN_RX_ACTION_NONE 0x0
	+#define MC_CMD_SET_SECURITY_RULE_IN_RX_ACTION_NONE 0x0
	/* enum: decide to accept the packet */
	-#define MC_CMD_SET_SECURITY_RULE_IN_RX_ACTION_WHITELIST 0x1
	+#define MC_CMD_SET_SECURITY_RULE_IN_RX_ACTION_WHITELIST 0x1
	/* enum: decide to drop the packet */
	-#define MC_CMD_SET_SECURITY_RULE_IN_RX_ACTION_BLACKLIST 0x2
	+#define MC_CMD_SET_SECURITY_RULE_IN_RX_ACTION_BLACKLIST 0x2
	/* enum: inform the TSA controller about some sample of packets matching this
	* rule (via MC_CMD_TSA_INFO_IN_PKT_SAMPLE messages); may be bitwise-ORed with
	* either the WHITELIST or BLACKLIST action
	*/
	-#define MC_CMD_SET_SECURITY_RULE_IN_RX_ACTION_SAMPLE 0x4
	+#define MC_CMD_SET_SECURITY_RULE_IN_RX_ACTION_SAMPLE 0x4
	/* enum: do not change the current RX action */
	-#define MC_CMD_SET_SECURITY_RULE_IN_RX_ACTION_UNCHANGED 0xffffffff
	+#define MC_CMD_SET_SECURITY_RULE_IN_RX_ACTION_UNCHANGED 0xffffffff
	/* counter ID to associate with this rule; IDs are allocated using
	* MC_CMD_SECURITY_RULE_COUNTER_ALLOC
	*/
	#define MC_CMD_SET_SECURITY_RULE_IN_COUNTER_ID_OFST 88
	#define MC_CMD_SET_SECURITY_RULE_IN_COUNTER_ID_LEN 4
	/* enum: special value for the null counter ID */
	-#define MC_CMD_SET_SECURITY_RULE_IN_COUNTER_ID_NONE 0x0
	+#define MC_CMD_SET_SECURITY_RULE_IN_COUNTER_ID_NONE 0x0
	/* enum: special value to tell the MC to allocate an available counter */
	-#define MC_CMD_SET_SECURITY_RULE_IN_COUNTER_ID_SW_AUTO 0xeeeeeeee
	+#define MC_CMD_SET_SECURITY_RULE_IN_COUNTER_ID_SW_AUTO 0xeeeeeeee
	/* enum: special value to request use of hardware counter (Medford2 only) */
	-#define MC_CMD_SET_SECURITY_RULE_IN_COUNTER_ID_HW 0xffffffff
	+#define MC_CMD_SET_SECURITY_RULE_IN_COUNTER_ID_HW 0xffffffff

	/* MC_CMD_SET_SECURITY_RULE_OUT msgresponse */
	#define MC_CMD_SET_SECURITY_RULE_OUT_LEN 32
	@@ -14966,7 +15077,7 @@
	#define MC_CMD_RESET_SECURITY_RULES 0x110
	#undef MC_CMD_0x110_PRIVILEGE_CTG

	-#define MC_CMD_0x110_PRIVILEGE_CTG SRIOV_CTG_ADMIN
	+#define MC_CMD_0x110_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND

	/* MC_CMD_RESET_SECURITY_RULES_IN msgrequest */
	#define MC_CMD_RESET_SECURITY_RULES_IN_LEN 4
	@@ -14974,7 +15085,7 @@
	#define MC_CMD_RESET_SECURITY_RULES_IN_PHYSICAL_PORT_OFST 0
	#define MC_CMD_RESET_SECURITY_RULES_IN_PHYSICAL_PORT_LEN 4
	/* enum: special value to reset all physical ports */
	-#define MC_CMD_RESET_SECURITY_RULES_IN_ALL_PHYSICAL_PORTS 0xffffffff
	+#define MC_CMD_RESET_SECURITY_RULES_IN_ALL_PHYSICAL_PORTS 0xffffffff

	/* MC_CMD_RESET_SECURITY_RULES_OUT msgresponse */
	#define MC_CMD_RESET_SECURITY_RULES_OUT_LEN 0
	@@ -15019,7 +15130,7 @@
	#define MC_CMD_SECURITY_RULE_COUNTER_ALLOC 0x112
	#undef MC_CMD_0x112_PRIVILEGE_CTG

	-#define MC_CMD_0x112_PRIVILEGE_CTG SRIOV_CTG_ADMIN
	+#define MC_CMD_0x112_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND

	/* MC_CMD_SECURITY_RULE_COUNTER_ALLOC_IN msgrequest */
	#define MC_CMD_SECURITY_RULE_COUNTER_ALLOC_IN_LEN 4
	@@ -15054,7 +15165,7 @@
	#define MC_CMD_SECURITY_RULE_COUNTER_FREE 0x113
	#undef MC_CMD_0x113_PRIVILEGE_CTG

	-#define MC_CMD_0x113_PRIVILEGE_CTG SRIOV_CTG_ADMIN
	+#define MC_CMD_0x113_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND

	/* MC_CMD_SECURITY_RULE_COUNTER_FREE_IN msgrequest */
	#define MC_CMD_SECURITY_RULE_COUNTER_FREE_IN_LENMIN 4
	@@ -15086,7 +15197,7 @@
	#define MC_CMD_SUBNET_MAP_SET_NODE 0x114
	#undef MC_CMD_0x114_PRIVILEGE_CTG

	-#define MC_CMD_0x114_PRIVILEGE_CTG SRIOV_CTG_ADMIN
	+#define MC_CMD_0x114_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND

	/* MC_CMD_SUBNET_MAP_SET_NODE_IN msgrequest */
	#define MC_CMD_SUBNET_MAP_SET_NODE_IN_LENMIN 6
	@@ -15115,7 +15226,7 @@
	*/
	#define PORTRANGE_TREE_ENTRY_BRANCH_KEY_OFST 0
	#define PORTRANGE_TREE_ENTRY_BRANCH_KEY_LEN 2
	-#define PORTRANGE_TREE_ENTRY_LEAF_NODE_KEY 0xffff /* enum */
	+#define PORTRANGE_TREE_ENTRY_LEAF_NODE_KEY 0xffff /* enum */
	#define PORTRANGE_TREE_ENTRY_BRANCH_KEY_LBN 0
	#define PORTRANGE_TREE_ENTRY_BRANCH_KEY_WIDTH 16
	/* final portrange ID for leaf nodes (don't care for branch nodes) */
	@@ -15138,7 +15249,7 @@
	#define MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE 0x115
	#undef MC_CMD_0x115_PRIVILEGE_CTG

	-#define MC_CMD_0x115_PRIVILEGE_CTG SRIOV_CTG_ADMIN
	+#define MC_CMD_0x115_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND

	/* MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE_IN msgrequest */
	#define MC_CMD_REMOTE_PORTRANGE_MAP_SET_TREE_IN_LENMIN 4
	@@ -15169,7 +15280,7 @@
	#define MC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE 0x116
	#undef MC_CMD_0x116_PRIVILEGE_CTG

	-#define MC_CMD_0x116_PRIVILEGE_CTG SRIOV_CTG_ADMIN
	+#define MC_CMD_0x116_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND

	/* MC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE_IN msgrequest */
	#define MC_CMD_LOCAL_PORTRANGE_MAP_SET_TREE_IN_LENMIN 4
	@@ -15192,18 +15303,18 @@
	#define TUNNEL_ENCAP_UDP_PORT_ENTRY_UDP_PORT_OFST 0
	#define TUNNEL_ENCAP_UDP_PORT_ENTRY_UDP_PORT_LEN 2
	/* enum: the IANA allocated UDP port for VXLAN */
	-#define TUNNEL_ENCAP_UDP_PORT_ENTRY_IANA_VXLAN_UDP_PORT 0x12b5
	+#define TUNNEL_ENCAP_UDP_PORT_ENTRY_IANA_VXLAN_UDP_PORT 0x12b5
	/* enum: the IANA allocated UDP port for Geneve */
	-#define TUNNEL_ENCAP_UDP_PORT_ENTRY_IANA_GENEVE_UDP_PORT 0x17c1
	+#define TUNNEL_ENCAP_UDP_PORT_ENTRY_IANA_GENEVE_UDP_PORT 0x17c1
	#define TUNNEL_ENCAP_UDP_PORT_ENTRY_UDP_PORT_LBN 0
	#define TUNNEL_ENCAP_UDP_PORT_ENTRY_UDP_PORT_WIDTH 16
	/* tunnel encapsulation protocol (only those named below are supported) */
	#define TUNNEL_ENCAP_UDP_PORT_ENTRY_PROTOCOL_OFST 2
	#define TUNNEL_ENCAP_UDP_PORT_ENTRY_PROTOCOL_LEN 2
	/* enum: This port will be used for VXLAN on both IPv4 and IPv6 */
	-#define TUNNEL_ENCAP_UDP_PORT_ENTRY_VXLAN 0x0
	+#define TUNNEL_ENCAP_UDP_PORT_ENTRY_VXLAN 0x0
	/* enum: This port will be used for Geneve on both IPv4 and IPv6 */
	-#define TUNNEL_ENCAP_UDP_PORT_ENTRY_GENEVE 0x1
	+#define TUNNEL_ENCAP_UDP_PORT_ENTRY_GENEVE 0x1
	#define TUNNEL_ENCAP_UDP_PORT_ENTRY_PROTOCOL_LBN 16
	#define TUNNEL_ENCAP_UDP_PORT_ENTRY_PROTOCOL_WIDTH 16

	@@ -15260,7 +15371,7 @@
	#define MC_CMD_RX_BALANCING 0x118
	#undef MC_CMD_0x118_PRIVILEGE_CTG

	-#define MC_CMD_0x118_PRIVILEGE_CTG SRIOV_CTG_ADMIN
	+#define MC_CMD_0x118_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND

	/* MC_CMD_RX_BALANCING_IN msgrequest */
	#define MC_CMD_RX_BALANCING_IN_LEN 16
	@@ -15284,12 +15395,7 @@
	/***********************************/
	/* MC_CMD_TSA_BIND
	* TSAN - TSAC binding communication protocol. Refer to SF-115479-TC for more
	- * info in respect to the binding protocol. This MCDI command is only available
	- * over a TLS secure connection between the TSAN and TSAC, and is not available
	- * to host software. Note- The messages definitions that do comprise this MCDI
	- * command deemed as provisional. This MCDI command has not yet been used in
	- * any released code and may change during development. This note will be
	- * removed once it is regarded as stable.
	+ * info in respect to the binding protocol.
	*/
	#define MC_CMD_TSA_BIND 0x119
	#undef MC_CMD_0x119_PRIVILEGE_CTG
	@@ -15300,15 +15406,12 @@
	#define MC_CMD_TSA_BIND_IN_LEN 4
	#define MC_CMD_TSA_BIND_IN_OP_OFST 0
	#define MC_CMD_TSA_BIND_IN_OP_LEN 4
	-/* enum: Retrieve the TSAN ID from a TSAN. TSAN ID is a unique identifier for
	- * the network adapter. More specifically, TSAN ID equals the MAC address of
	- * the network adapter. TSAN ID is used as part of the TSAN authentication
	- * protocol. Refer to SF-114946-SW for more information.
	- */
	+/* enum: Obsolete. Use MC_CMD_SECURE_NIC_INFO_IN_STATUS. */
	#define MC_CMD_TSA_BIND_OP_GET_ID 0x1
	/* enum: Get a binding ticket from the TSAN. The binding ticket is used as part
	* of the binding procedure to authorize the binding of an adapter to a TSAID.
	- * Refer to SF-114946-SW for more information.
	+ * Refer to SF-114946-SW for more information. This sub-command is only
	+ * available over a TLS secure connection between the TSAN and TSAC.
	*/
	#define MC_CMD_TSA_BIND_OP_GET_TICKET 0x2
	/* enum: Opcode associated with the propagation of a private key that TSAN uses
	@@ -15316,36 +15419,43 @@
	* uses this key for a signing operation. TSAC uses the counterpart public key
	* to verify the signature. Note - The post-binding authentication occurs when
	* the TSAN-TSAC connection terminates and TSAN tries to reconnect. Refer to
	- * SF-114946-SW for more information.
	+ * SF-114946-SW for more information. This sub-command is only available over a
	+ * TLS secure connection between the TSAN and TSAC.
	*/
	#define MC_CMD_TSA_BIND_OP_SET_KEY 0x3
	-/* enum: Request an unbinding operation. Note- TSAN clears the binding ticket
	- * from the Nvram section. Deprecated. Use MC_CMD_TSA_BIND_OP_UNBIND_EXT opcode
	- * as indicated below.
	+/* enum: Request an insecure unbinding operation. This sub-command is available
	+ * for any privileged client.
	*/
	#define MC_CMD_TSA_BIND_OP_UNBIND 0x4
	-/* enum: Opcode associated with the propagation of the unbinding ticket data
	- * blob. The latest SF-115479-TC spec requires a more secure unbinding
	- * procedure based on unbinding ticket. Note- The previous unbind operation
	- * based on MC_CMD_TSA_BIND_OP_UNBIND remains in place but now deprecated.
	- */
	+/* enum: Obsolete. Use MC_CMD_TSA_BIND_OP_SECURE_UNBIND. */
	#define MC_CMD_TSA_BIND_OP_UNBIND_EXT 0x5
	/* enum: Opcode associated with the propagation of the unbinding secret token.
	* TSAN persists the unbinding secret token. Refer to SF-115479-TC for more
	- * information.
	+ * information. This sub-command is only available over a TLS secure connection
	+ * between the TSAN and TSAC.
	*/
	#define MC_CMD_TSA_BIND_OP_SET_UNBINDTOKEN 0x6
	-/* enum: Request a decommissioning operation. This is to force unbinding the
	- * adapter. Note- This type of operation comes handy when keys other attributes
	- * get corrupted at the database level on the controller side and not able to
	- * unbind the adapter as part of a normal unbind procedure. Note- Refer to
	- * SF-115479-TC for more information.
	- */
	+/* enum: Obsolete. Use MC_CMD_TSA_BIND_OP_SECURE_DECOMMISSION. */
	#define MC_CMD_TSA_BIND_OP_DECOMMISSION 0x7
	-/* enum: Request a certificate. */
	+/* enum: Obsolete. Use MC_CMD_GET_CERTIFICATE. */
	#define MC_CMD_TSA_BIND_OP_GET_CERTIFICATE 0x8
	+/* enum: Request a secure unbinding operation using unbinding token. This sub-
	+ * command is available for any privileged client.
	+ */
	+#define MC_CMD_TSA_BIND_OP_SECURE_UNBIND 0x9
	+/* enum: Request a secure decommissioning operation. This sub-command is
	+ * available for any privileged client.
	+ */
	+#define MC_CMD_TSA_BIND_OP_SECURE_DECOMMISSION 0xa
	+/* enum: Test facility that allows an adapter to be configured to behave as if
	+ * Bound to a TSA controller with restricted MCDI administrator operations.
	+ * This operation is primarily intended to aid host driver development.
	+ */
	+#define MC_CMD_TSA_BIND_OP_TEST_MCDI 0xb

	-/* MC_CMD_TSA_BIND_IN_GET_ID msgrequest */
	+/* MC_CMD_TSA_BIND_IN_GET_ID msgrequest: Obsolete. Use
	+ * MC_CMD_SECURE_NIC_INFO_IN_STATUS.
	+ */
	#define MC_CMD_TSA_BIND_IN_GET_ID_LEN 20
	/* The operation requested. */
	#define MC_CMD_TSA_BIND_IN_GET_ID_OP_OFST 0
	@@ -15382,8 +15492,8 @@
	#define MC_CMD_TSA_BIND_IN_SET_KEY_DATKEY_MINNUM 1
	#define MC_CMD_TSA_BIND_IN_SET_KEY_DATKEY_MAXNUM 248

	-/* MC_CMD_TSA_BIND_IN_UNBIND msgrequest: Asks for the un-binding procedure
	- * Deprecated. Use MC_CMD_TSA_BIND_IN_UNBIND_EXT msgrequest as indicated below.
	+/* MC_CMD_TSA_BIND_IN_UNBIND msgrequest: Request an insecure unbinding
	+ * operation.
	*/
	#define MC_CMD_TSA_BIND_IN_UNBIND_LEN 10
	/* The operation requested. */
	@@ -15393,7 +15503,8 @@
	#define MC_CMD_TSA_BIND_IN_UNBIND_TSANID_OFST 4
	#define MC_CMD_TSA_BIND_IN_UNBIND_TSANID_LEN 6

	-/* MC_CMD_TSA_BIND_IN_UNBIND_EXT msgrequest: Asks for the un-binding procedure
	+/* MC_CMD_TSA_BIND_IN_UNBIND_EXT msgrequest: Obsolete. Use
	+ * MC_CMD_TSA_BIND_IN_SECURE_UNBIND.
	*/
	#define MC_CMD_TSA_BIND_IN_UNBIND_EXT_LENMIN 93
	#define MC_CMD_TSA_BIND_IN_UNBIND_EXT_LENMAX 252
	@@ -15453,8 +15564,8 @@
	*/
	#define MC_CMD_TSA_BIND_IN_SET_UNBINDTOKEN_ADAPTER_BINDING_FAILURE 0x1

	-/* MC_CMD_TSA_BIND_IN_DECOMMISSION msgrequest: Asks for the decommissioning
	- * procedure
	+/* MC_CMD_TSA_BIND_IN_DECOMMISSION msgrequest: Obsolete. Use
	+ * MC_CMD_TSA_BIND_IN_SECURE_DECOMMISSION.
	*/
	#define MC_CMD_TSA_BIND_IN_DECOMMISSION_LENMIN 109
	#define MC_CMD_TSA_BIND_IN_DECOMMISSION_LENMAX 252
	@@ -15497,7 +15608,9 @@
	#define MC_CMD_TSA_BIND_IN_DECOMMISSION_REASON_OFST 104
	#define MC_CMD_TSA_BIND_IN_DECOMMISSION_REASON_LEN 4

	-/* MC_CMD_TSA_BIND_IN_GET_CERTIFICATE msgrequest: Request a certificate. */
	+/* MC_CMD_TSA_BIND_IN_GET_CERTIFICATE msgrequest: Obsolete. Use
	+ * MC_CMD_GET_CERTIFICATE.
	+ */
	#define MC_CMD_TSA_BIND_IN_GET_CERTIFICATE_LEN 8
	/* The operation requested, must be MC_CMD_TSA_BIND_OP_GET_CERTIFICATE. */
	#define MC_CMD_TSA_BIND_IN_GET_CERTIFICATE_OP_OFST 0
	@@ -15505,17 +15618,120 @@
	/* Type of the certificate to be retrieved. */
	#define MC_CMD_TSA_BIND_IN_GET_CERTIFICATE_TYPE_OFST 4
	#define MC_CMD_TSA_BIND_IN_GET_CERTIFICATE_TYPE_LEN 4
	-#define MC_CMD_TSA_BIND_IN_GET_CERTIFICATE_UNUSED 0x0 /* enum */
	+#define MC_CMD_TSA_BIND_IN_GET_CERTIFICATE_UNUSED 0x0 /* enum */
	/* enum: Adapter Authentication Certificate (AAC). The AAC is used by the
	* controller to verify the authenticity of the adapter.
	*/
	-#define MC_CMD_TSA_BIND_IN_GET_CERTIFICATE_AAC 0x1
	+#define MC_CMD_TSA_BIND_IN_GET_CERTIFICATE_AAC 0x1
	/* enum: Adapter Authentication Signing Certificate (AASC). The AASC is used by
	* the controller to verify the validity of AAC.
	*/
	-#define MC_CMD_TSA_BIND_IN_GET_CERTIFICATE_AASC 0x2
	+#define MC_CMD_TSA_BIND_IN_GET_CERTIFICATE_AASC 0x2

	-/* MC_CMD_TSA_BIND_OUT_GET_ID msgresponse */
	+/* MC_CMD_TSA_BIND_IN_SECURE_UNBIND msgrequest: Request a secure unbinding
	+ * operation using unbinding token.
	+ */
	+#define MC_CMD_TSA_BIND_IN_SECURE_UNBIND_LENMIN 97
	+#define MC_CMD_TSA_BIND_IN_SECURE_UNBIND_LENMAX 200
	+#define MC_CMD_TSA_BIND_IN_SECURE_UNBIND_LEN(num) (96+1*(num))
	+/* The operation requested, must be MC_CMD_TSA_BIND_OP_SECURE_UNBIND. */
	+#define MC_CMD_TSA_BIND_IN_SECURE_UNBIND_OP_OFST 0
	+#define MC_CMD_TSA_BIND_IN_SECURE_UNBIND_OP_LEN 4
	+/* Type of the message. (MESSAGE_TYPE_xxx) Must be
	+ * MESSAGE_TYPE_TSA_SECURE_UNBIND.
	+ */
	+#define MC_CMD_TSA_BIND_IN_SECURE_UNBIND_MESSAGE_TYPE_OFST 4
	+#define MC_CMD_TSA_BIND_IN_SECURE_UNBIND_MESSAGE_TYPE_LEN 4
	+/* TSAN unique identifier for the network adapter */
	+#define MC_CMD_TSA_BIND_IN_SECURE_UNBIND_TSANID_OFST 8
	+#define MC_CMD_TSA_BIND_IN_SECURE_UNBIND_TSANID_LEN 6
	+/* Align the arguments to 32 bits */
	+#define MC_CMD_TSA_BIND_IN_SECURE_UNBIND_TSANID_RSVD_OFST 14
	+#define MC_CMD_TSA_BIND_IN_SECURE_UNBIND_TSANID_RSVD_LEN 2
	+/* A NUL padded US-ASCII string identifying the TSA infrastructure domain. This
	+ * field is for information only, and not used by the firmware. Note- The TSAID
	+ * is the Organizational Unit Name field as part of the root and server
	+ * certificates.
	+ */
	+#define MC_CMD_TSA_BIND_IN_SECURE_UNBIND_TSAID_OFST 16
	+#define MC_CMD_TSA_BIND_IN_SECURE_UNBIND_TSAID_LEN 1
	+#define MC_CMD_TSA_BIND_IN_SECURE_UNBIND_TSAID_NUM 64
	+/* Unbinding secret token. The adapter validates this unbinding token by
	+ * comparing it against the one stored on the adapter as part of the
	+ * MC_CMD_TSA_BIND_IN_SET_UNBINDTOKEN msgrequest. Refer to SF-115479-TC for
	+ * more information.
	+ */
	+#define MC_CMD_TSA_BIND_IN_SECURE_UNBIND_UNBINDTOKEN_OFST 80
	+#define MC_CMD_TSA_BIND_IN_SECURE_UNBIND_UNBINDTOKEN_LEN 16
	+/* The signature computed and encoded as specified by MESSAGE_TYPE. */
	+#define MC_CMD_TSA_BIND_IN_SECURE_UNBIND_SIG_OFST 96
	+#define MC_CMD_TSA_BIND_IN_SECURE_UNBIND_SIG_LEN 1
	+#define MC_CMD_TSA_BIND_IN_SECURE_UNBIND_SIG_MINNUM 1
	+#define MC_CMD_TSA_BIND_IN_SECURE_UNBIND_SIG_MAXNUM 104
	+
	+/* MC_CMD_TSA_BIND_IN_SECURE_DECOMMISSION msgrequest: Request a secure
	+ * decommissioning operation.
	+ */
	+#define MC_CMD_TSA_BIND_IN_SECURE_DECOMMISSION_LENMIN 113
	+#define MC_CMD_TSA_BIND_IN_SECURE_DECOMMISSION_LENMAX 216
	+#define MC_CMD_TSA_BIND_IN_SECURE_DECOMMISSION_LEN(num) (112+1*(num))
	+/* The operation requested, must be MC_CMD_TSA_BIND_OP_SECURE_DECOMMISSION. */
	+#define MC_CMD_TSA_BIND_IN_SECURE_DECOMMISSION_OP_OFST 0
	+#define MC_CMD_TSA_BIND_IN_SECURE_DECOMMISSION_OP_LEN 4
	+/* Type of the message. (MESSAGE_TYPE_xxx) Must be
	+ * MESSAGE_TYPE_SECURE_DECOMMISSION.
	+ */
	+#define MC_CMD_TSA_BIND_IN_SECURE_DECOMMISSION_MESSAGE_TYPE_OFST 4
	+#define MC_CMD_TSA_BIND_IN_SECURE_DECOMMISSION_MESSAGE_TYPE_LEN 4
	+/* A NUL padded US-ASCII string identifying the TSA infrastructure domain. This
	+ * field is for information only, and not used by the firmware. Note- The TSAID
	+ * is the Organizational Unit Name field as part of the root and server
	+ * certificates.
	+ */
	+#define MC_CMD_TSA_BIND_IN_SECURE_DECOMMISSION_TSAID_OFST 8
	+#define MC_CMD_TSA_BIND_IN_SECURE_DECOMMISSION_TSAID_LEN 1
	+#define MC_CMD_TSA_BIND_IN_SECURE_DECOMMISSION_TSAID_NUM 64
	+/* A NUL padded US-ASCII string containing user name of the creator of the
	+ * decommissioning ticket. This field is for information only, and not used by
	+ * the firmware.
	+ */
	+#define MC_CMD_TSA_BIND_IN_SECURE_DECOMMISSION_USER_OFST 72
	+#define MC_CMD_TSA_BIND_IN_SECURE_DECOMMISSION_USER_LEN 1
	+#define MC_CMD_TSA_BIND_IN_SECURE_DECOMMISSION_USER_NUM 36
	+/* Reason of why decommissioning happens */
	+#define MC_CMD_TSA_BIND_IN_SECURE_DECOMMISSION_REASON_OFST 108
	+#define MC_CMD_TSA_BIND_IN_SECURE_DECOMMISSION_REASON_LEN 4
	+/* enum: There are situations when the binding process does not complete
	+ * successfully due to key, other attributes corruption at the database level
	+ * (Controller). Adapter can't connect to the controller anymore. To recover,
	+ * use the decommission command to force the adapter into unbound state.
	+ */
	+#define MC_CMD_TSA_BIND_IN_SECURE_DECOMMISSION_ADAPTER_BINDING_FAILURE 0x1
	+/* The signature computed and encoded as specified by MESSAGE_TYPE. */
	+#define MC_CMD_TSA_BIND_IN_SECURE_DECOMMISSION_SIG_OFST 112
	+#define MC_CMD_TSA_BIND_IN_SECURE_DECOMMISSION_SIG_LEN 1
	+#define MC_CMD_TSA_BIND_IN_SECURE_DECOMMISSION_SIG_MINNUM 1
	+#define MC_CMD_TSA_BIND_IN_SECURE_DECOMMISSION_SIG_MAXNUM 104
	+
	+/* MC_CMD_TSA_BIND_IN_TEST_MCDI msgrequest: Test mode that emulates MCDI
	+ * interface restrictions of a bound adapter. This operation is intended for
	+ * test use on adapters that are not deployed and bound to a TSA Controller.
	+ * Using it on a Bound adapter will succeed but will not alter the MCDI
	+ * privileges as MCDI operations will already be restricted.
	+ */
	+#define MC_CMD_TSA_BIND_IN_TEST_MCDI_LEN 8
	+/* The operation requested must be MC_CMD_TSA_BIND_OP_TEST_MCDI. */
	+#define MC_CMD_TSA_BIND_IN_TEST_MCDI_OP_OFST 0
	+#define MC_CMD_TSA_BIND_IN_TEST_MCDI_OP_LEN 4
	+/* Enable or disable emulation of bound adapter */
	+#define MC_CMD_TSA_BIND_IN_TEST_MCDI_CTRL_OFST 4
	+#define MC_CMD_TSA_BIND_IN_TEST_MCDI_CTRL_LEN 4
	+#define MC_CMD_TSA_BIND_IN_TEST_MCDI_DISABLE 0x0 /* enum */
	+#define MC_CMD_TSA_BIND_IN_TEST_MCDI_ENABLE 0x1 /* enum */
	+
	+/* MC_CMD_TSA_BIND_OUT_GET_ID msgresponse: Obsolete. Use
	+ * MC_CMD_SECURE_NIC_INFO_OUT_STATUS.
	+ */
	#define MC_CMD_TSA_BIND_OUT_GET_ID_LENMIN 15
	#define MC_CMD_TSA_BIND_OUT_GET_ID_LENMAX 252
	#define MC_CMD_TSA_BIND_OUT_GET_ID_LEN(num) (14+1*(num))
	@@ -15586,17 +15802,16 @@
	#define MC_CMD_TSA_BIND_OUT_UNBIND_INFO_OFST 4
	#define MC_CMD_TSA_BIND_OUT_UNBIND_INFO_LEN 4
	/* enum: Unbind successful. */
	-#define MC_CMD_TSA_BIND_OUT_UNBIND_OK_UNBOUND 0x0
	+#define MC_CMD_TSA_BIND_OUT_UNBIND_OK_UNBOUND 0x0
	/* enum: TSANID mismatch */
	-#define MC_CMD_TSA_BIND_OUT_UNBIND_ERR_BAD_TSANID 0x1
	+#define MC_CMD_TSA_BIND_OUT_UNBIND_ERR_BAD_TSANID 0x1
	/* enum: Unable to remove the binding ticket from persistent storage. */
	-#define MC_CMD_TSA_BIND_OUT_UNBIND_ERR_REMOVE_TICKET 0x2
	+#define MC_CMD_TSA_BIND_OUT_UNBIND_ERR_REMOVE_TICKET 0x2
	/* enum: TSAN is not bound to a binding ticket. */
	-#define MC_CMD_TSA_BIND_OUT_UNBIND_ERR_NOT_BOUND 0x3
	+#define MC_CMD_TSA_BIND_OUT_UNBIND_ERR_NOT_BOUND 0x3

	-/* MC_CMD_TSA_BIND_OUT_UNBIND_EXT msgresponse: Response to secure unbind
	- * request. (Note! This has same fields as insecure unbind response but is a
	- * response to a different command.)
	+/* MC_CMD_TSA_BIND_OUT_UNBIND_EXT msgresponse: Obsolete. Use
	+ * MC_CMD_TSA_BIND_OUT_SECURE_UNBIND.
	*/
	#define MC_CMD_TSA_BIND_OUT_UNBIND_EXT_LEN 8
	/* Same as MC_CMD_ERR field, but included as 0 in success cases */
	@@ -15606,17 +15821,17 @@
	#define MC_CMD_TSA_BIND_OUT_UNBIND_EXT_INFO_OFST 4
	#define MC_CMD_TSA_BIND_OUT_UNBIND_EXT_INFO_LEN 4
	/* enum: Unbind successful. */
	-#define MC_CMD_TSA_BIND_OUT_UNBIND_EXT_OK_UNBOUND 0x0
	+#define MC_CMD_TSA_BIND_OUT_UNBIND_EXT_OK_UNBOUND 0x0
	/* enum: TSANID mismatch */
	-#define MC_CMD_TSA_BIND_OUT_UNBIND_EXT_ERR_BAD_TSANID 0x1
	+#define MC_CMD_TSA_BIND_OUT_UNBIND_EXT_ERR_BAD_TSANID 0x1
	/* enum: Unable to remove the binding ticket from persistent storage. */
	-#define MC_CMD_TSA_BIND_OUT_UNBIND_EXT_ERR_REMOVE_TICKET 0x2
	+#define MC_CMD_TSA_BIND_OUT_UNBIND_EXT_ERR_REMOVE_TICKET 0x2
	/* enum: TSAN is not bound to a binding ticket. */
	-#define MC_CMD_TSA_BIND_OUT_UNBIND_EXT_ERR_NOT_BOUND 0x3
	+#define MC_CMD_TSA_BIND_OUT_UNBIND_EXT_ERR_NOT_BOUND 0x3
	/* enum: Invalid unbind token */
	-#define MC_CMD_TSA_BIND_OUT_UNBIND_EXT_ERR_BAD_TOKEN 0x4
	+#define MC_CMD_TSA_BIND_OUT_UNBIND_EXT_ERR_BAD_TOKEN 0x4
	/* enum: Invalid signature */
	-#define MC_CMD_TSA_BIND_OUT_UNBIND_EXT_ERR_BAD_SIGNATURE 0x5
	+#define MC_CMD_TSA_BIND_OUT_UNBIND_EXT_ERR_BAD_SIGNATURE 0x5

	/* MC_CMD_TSA_BIND_OUT_SET_UNBINDTOKEN msgresponse */
	#define MC_CMD_TSA_BIND_OUT_SET_UNBINDTOKEN_LEN 4
	@@ -15626,7 +15841,9 @@
	#define MC_CMD_TSA_BIND_OUT_SET_UNBINDTOKEN_OP_OFST 0
	#define MC_CMD_TSA_BIND_OUT_SET_UNBINDTOKEN_OP_LEN 4

	-/* MC_CMD_TSA_BIND_OUT_DECOMMISSION msgresponse */
	+/* MC_CMD_TSA_BIND_OUT_DECOMMISSION msgresponse: Obsolete. Use
	+ * MC_CMD_TSA_BIND_OUT_SECURE_DECOMMISSION.
	+ */
	#define MC_CMD_TSA_BIND_OUT_DECOMMISSION_LEN 4
	/* The protocol operation code MC_CMD_TSA_BIND_OP_DECOMMISSION that is sent
	* back to the caller.
	@@ -15654,7 +15871,59 @@
	#define MC_CMD_TSA_BIND_OUT_GET_CERTIFICATE_DATA_MINNUM 1
	#define MC_CMD_TSA_BIND_OUT_GET_CERTIFICATE_DATA_MAXNUM 244

	+/* MC_CMD_TSA_BIND_OUT_SECURE_UNBIND msgresponse: Response to secure unbind
	+ * request.
	+ */
	+#define MC_CMD_TSA_BIND_OUT_SECURE_UNBIND_LEN 8
	+/* The protocol operation code that is sent back to the caller. */
	+#define MC_CMD_TSA_BIND_OUT_SECURE_UNBIND_OP_OFST 0
	+#define MC_CMD_TSA_BIND_OUT_SECURE_UNBIND_OP_LEN 4
	+#define MC_CMD_TSA_BIND_OUT_SECURE_UNBIND_RESULT_OFST 4
	+#define MC_CMD_TSA_BIND_OUT_SECURE_UNBIND_RESULT_LEN 4
	+/* enum: Unbind successful. */
	+#define MC_CMD_TSA_BIND_OUT_SECURE_UNBIND_OK_UNBOUND 0x0
	+/* enum: TSANID mismatch */
	+#define MC_CMD_TSA_BIND_OUT_SECURE_UNBIND_ERR_BAD_TSANID 0x1
	+/* enum: Unable to remove the binding ticket from persistent storage. */
	+#define MC_CMD_TSA_BIND_OUT_SECURE_UNBIND_ERR_REMOVE_TICKET 0x2
	+/* enum: TSAN is not bound to a domain. */
	+#define MC_CMD_TSA_BIND_OUT_SECURE_UNBIND_ERR_NOT_BOUND 0x3
	+/* enum: Invalid unbind token */
	+#define MC_CMD_TSA_BIND_OUT_SECURE_UNBIND_ERR_BAD_TOKEN 0x4
	+/* enum: Invalid signature */
	+#define MC_CMD_TSA_BIND_OUT_SECURE_UNBIND_ERR_BAD_SIGNATURE 0x5

	+/* MC_CMD_TSA_BIND_OUT_SECURE_DECOMMISSION msgresponse: Response to secure
	+ * decommission request.
	+ */
	+#define MC_CMD_TSA_BIND_OUT_SECURE_DECOMMISSION_LEN 8
	+/* The protocol operation code that is sent back to the caller. */
	+#define MC_CMD_TSA_BIND_OUT_SECURE_DECOMMISSION_OP_OFST 0
	+#define MC_CMD_TSA_BIND_OUT_SECURE_DECOMMISSION_OP_LEN 4
	+#define MC_CMD_TSA_BIND_OUT_SECURE_DECOMMISSION_RESULT_OFST 4
	+#define MC_CMD_TSA_BIND_OUT_SECURE_DECOMMISSION_RESULT_LEN 4
	+/* enum: Unbind successful. */
	+#define MC_CMD_TSA_BIND_OUT_SECURE_DECOMMISSION_OK_UNBOUND 0x0
	+/* enum: TSANID mismatch */
	+#define MC_CMD_TSA_BIND_OUT_SECURE_DECOMMISSION_ERR_BAD_TSANID 0x1
	+/* enum: Unable to remove the binding ticket from persistent storage. */
	+#define MC_CMD_TSA_BIND_OUT_SECURE_DECOMMISSION_ERR_REMOVE_TICKET 0x2
	+/* enum: TSAN is not bound to a domain. */
	+#define MC_CMD_TSA_BIND_OUT_SECURE_DECOMMISSION_ERR_NOT_BOUND 0x3
	+/* enum: Invalid unbind token */
	+#define MC_CMD_TSA_BIND_OUT_SECURE_DECOMMISSION_ERR_BAD_TOKEN 0x4
	+/* enum: Invalid signature */
	+#define MC_CMD_TSA_BIND_OUT_SECURE_DECOMMISSION_ERR_BAD_SIGNATURE 0x5
	+
	+/* MC_CMD_TSA_BIND_OUT_TEST_MCDI msgrequest */
	+#define MC_CMD_TSA_BIND_OUT_TEST_MCDI_LEN 4
	+/* The protocol operation code MC_CMD_TSA_BIND_OP_TEST_MCDI that is sent back
	+ * to the caller.
	+ */
	+#define MC_CMD_TSA_BIND_OUT_TEST_MCDI_OP_OFST 0
	+#define MC_CMD_TSA_BIND_OUT_TEST_MCDI_OP_LEN 4
	+
	+
	/***********************************/
	/* MC_CMD_MANAGE_SECURITY_RULESET_CACHE
	* Manage the persistent NVRAM cache of security rules created with
	@@ -15665,9 +15934,9 @@
	* will be loaded at power on or MC reboot, instead of the default ruleset.
	* Rollback of the currently active ruleset to the cached version (when it is
	* valid) is also supported. (Medford-only; for use by SolarSecure apps, not
	- * directly by drivers. See SF-114946-SW.) NOTE - this message definition is
	- * provisional. It has not yet been used in any released code and may change
	- * during development. This note will be removed once it is regarded as stable.
	+ * directly by drivers. See SF-114946-SW.) NOTE - The only sub-operation
	+ * allowed in an adapter bound to a TSA controller from the local host is
	+ * OP_GET_CACHED_VERSION. All other sub-operations are prohibited.
	*/
	#define MC_CMD_MANAGE_SECURITY_RULESET_CACHE 0x11a
	#undef MC_CMD_0x11a_PRIVILEGE_CTG
	@@ -15682,15 +15951,15 @@
	/* enum: reports the ruleset version that is cached in persistent storage but
	* performs no other action
	*/
	-#define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_IN_OP_GET_CACHED_VERSION 0x0
	+#define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_IN_OP_GET_CACHED_VERSION 0x0
	/* enum: rolls back the active state to the cached version. (May fail with
	* ENOENT if there is no valid cached version.)
	*/
	-#define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_IN_OP_ROLLBACK 0x1
	+#define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_IN_OP_ROLLBACK 0x1
	/* enum: commits the active state to the persistent cache */
	-#define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_IN_OP_COMMIT 0x2
	+#define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_IN_OP_COMMIT 0x2
	/* enum: invalidates the persistent cache without affecting the active state */
	-#define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_IN_OP_INVALIDATE 0x3
	+#define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_IN_OP_INVALIDATE 0x3

	/* MC_CMD_MANAGE_SECURITY_RULESET_CACHE_OUT msgresponse */
	#define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_OUT_LENMIN 5
	@@ -15704,9 +15973,9 @@
	/* enum: persistent cache is invalid (the VERSION field will be empty in this
	* case)
	*/
	-#define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_OUT_STATE_INVALID 0x0
	+#define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_OUT_STATE_INVALID 0x0
	/* enum: persistent cache is valid */
	-#define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_OUT_STATE_VALID 0x1
	+#define MC_CMD_MANAGE_SECURITY_RULESET_CACHE_OUT_STATE_VALID 0x1
	/* cached ruleset version (after completion of the requested operation, in the
	* case of rollback, commit, or invalidate) as an opaque hash value in the same
	* form as MC_CMD_GET_SECURITY_RULESET_VERSION_OUT_VERSION
	@@ -15725,7 +15994,7 @@
	#define MC_CMD_NVRAM_PRIVATE_APPEND 0x11c
	#undef MC_CMD_0x11c_PRIVILEGE_CTG

	-#define MC_CMD_0x11c_PRIVILEGE_CTG SRIOV_CTG_ADMIN
	+#define MC_CMD_0x11c_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND

	/* MC_CMD_NVRAM_PRIVATE_APPEND_IN msgrequest */
	#define MC_CMD_NVRAM_PRIVATE_APPEND_IN_LENMIN 9
	@@ -15812,10 +16081,10 @@
	/* Timer mode. Meanings as per EVQ_TMR_REG.TC_TIMER_VAL */
	#define MC_CMD_SET_EVQ_TMR_IN_TMR_MODE_OFST 12
	#define MC_CMD_SET_EVQ_TMR_IN_TMR_MODE_LEN 4
	-#define MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_DIS 0x0 /* enum */
	-#define MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_IMMED_START 0x1 /* enum */
	-#define MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_TRIG_START 0x2 /* enum */
	-#define MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_INT_HLDOFF 0x3 /* enum */
	+#define MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_DIS 0x0 /* enum */
	+#define MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_IMMED_START 0x1 /* enum */
	+#define MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_TRIG_START 0x2 /* enum */
	+#define MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_INT_HLDOFF 0x3 /* enum */

	/* MC_CMD_SET_EVQ_TMR_OUT msgresponse */
	#define MC_CMD_SET_EVQ_TMR_OUT_LEN 8
	@@ -15903,7 +16172,7 @@
	#define MC_CMD_ALLOCATE_TX_VFIFO_CP 0x11d
	#undef MC_CMD_0x11d_PRIVILEGE_CTG

	-#define MC_CMD_0x11d_PRIVILEGE_CTG SRIOV_CTG_ADMIN
	+#define MC_CMD_0x11d_PRIVILEGE_CTG SRIOV_CTG_GENERAL

	/* MC_CMD_ALLOCATE_TX_VFIFO_CP_IN msgrequest */
	#define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_LEN 20
	@@ -15915,9 +16184,9 @@
	/* Will the common pool be used as TX_vFIFO_ULL (1) */
	#define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_MODE_OFST 4
	#define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_MODE_LEN 4
	-#define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_ENABLED 0x1 /* enum */
	+#define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_ENABLED 0x1 /* enum */
	/* enum: Using this interface without TX_vFIFO_ULL is not supported for now */
	-#define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_DISABLED 0x0
	+#define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_DISABLED 0x0
	/* Number of buffers to reserve for the common pool */
	#define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_SIZE_OFST 8
	#define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_SIZE_LEN 4
	@@ -15925,20 +16194,20 @@
	#define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_INGRESS_OFST 12
	#define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_INGRESS_LEN 4
	/* enum: Extracts information from function */
	-#define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_USE_FUNCTION_VALUE -0x1
	+#define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_USE_FUNCTION_VALUE -0x1
	/* Network port or RX Engine to which the common pool connects. */
	#define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_EGRESS_OFST 16
	#define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_EGRESS_LEN 4
	/* enum: Extracts information from function */
	-/* MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_USE_FUNCTION_VALUE -0x1 */
	-#define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_PORT0 0x0 /* enum */
	-#define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_PORT1 0x1 /* enum */
	-#define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_PORT2 0x2 /* enum */
	-#define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_PORT3 0x3 /* enum */
	+/* MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_USE_FUNCTION_VALUE -0x1 */
	+#define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_PORT0 0x0 /* enum */
	+#define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_PORT1 0x1 /* enum */
	+#define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_PORT2 0x2 /* enum */
	+#define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_PORT3 0x3 /* enum */
	/* enum: To enable Switch loopback with Rx engine 0 */
	-#define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_RX_ENGINE0 0x4
	+#define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_RX_ENGINE0 0x4
	/* enum: To enable Switch loopback with Rx engine 1 */
	-#define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_RX_ENGINE1 0x5
	+#define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_RX_ENGINE1 0x5

	/* MC_CMD_ALLOCATE_TX_VFIFO_CP_OUT msgresponse */
	#define MC_CMD_ALLOCATE_TX_VFIFO_CP_OUT_LEN 4
	@@ -15955,7 +16224,7 @@
	#define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO 0x11e
	#undef MC_CMD_0x11e_PRIVILEGE_CTG

	-#define MC_CMD_0x11e_PRIVILEGE_CTG SRIOV_CTG_ADMIN
	+#define MC_CMD_0x11e_PRIVILEGE_CTG SRIOV_CTG_GENERAL

	/* MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN msgrequest */
	#define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_LEN 20
	@@ -15967,20 +16236,20 @@
	#define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_EGRESS_OFST 4
	#define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_EGRESS_LEN 4
	/* enum: Extracts information from common pool */
	-#define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_USE_CP_VALUE -0x1
	-#define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_PORT0 0x0 /* enum */
	-#define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_PORT1 0x1 /* enum */
	-#define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_PORT2 0x2 /* enum */
	-#define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_PORT3 0x3 /* enum */
	+#define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_USE_CP_VALUE -0x1
	+#define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_PORT0 0x0 /* enum */
	+#define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_PORT1 0x1 /* enum */
	+#define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_PORT2 0x2 /* enum */
	+#define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_PORT3 0x3 /* enum */
	/* enum: To enable Switch loopback with Rx engine 0 */
	-#define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_RX_ENGINE0 0x4
	+#define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_RX_ENGINE0 0x4
	/* enum: To enable Switch loopback with Rx engine 1 */
	-#define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_RX_ENGINE1 0x5
	+#define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_RX_ENGINE1 0x5
	/* Minimum number of buffers that the pool must have */
	#define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_SIZE_OFST 8
	#define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_SIZE_LEN 4
	/* enum: Do not check the space available */
	-#define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_NO_MINIMUM 0x0
	+#define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_NO_MINIMUM 0x0
	/* Will the vFIFO be used as TX_vFIFO_ULL */
	#define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_MODE_OFST 12
	#define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_MODE_LEN 4
	@@ -15988,7 +16257,7 @@
	#define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_PRIORITY_OFST 16
	#define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_PRIORITY_LEN 4
	/* enum: Search for the lowest unused priority */
	-#define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_LOWEST_AVAILABLE -0x1
	+#define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_LOWEST_AVAILABLE -0x1

	/* MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_OUT msgresponse */
	#define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_OUT_LEN 8
	@@ -16008,7 +16277,7 @@
	#define MC_CMD_TEARDOWN_TX_VFIFO_VF 0x11f
	#undef MC_CMD_0x11f_PRIVILEGE_CTG

	-#define MC_CMD_0x11f_PRIVILEGE_CTG SRIOV_CTG_ADMIN
	+#define MC_CMD_0x11f_PRIVILEGE_CTG SRIOV_CTG_GENERAL

	/* MC_CMD_TEARDOWN_TX_VFIFO_VF_IN msgrequest */
	#define MC_CMD_TEARDOWN_TX_VFIFO_VF_IN_LEN 4
	@@ -16028,7 +16297,7 @@
	#define MC_CMD_DEALLOCATE_TX_VFIFO_CP 0x121
	#undef MC_CMD_0x121_PRIVILEGE_CTG

	-#define MC_CMD_0x121_PRIVILEGE_CTG SRIOV_CTG_ADMIN
	+#define MC_CMD_0x121_PRIVILEGE_CTG SRIOV_CTG_GENERAL

	/* MC_CMD_DEALLOCATE_TX_VFIFO_CP_IN msgrequest */
	#define MC_CMD_DEALLOCATE_TX_VFIFO_CP_IN_LEN 4
	@@ -16056,7 +16325,7 @@
	#define MC_CMD_REKEY 0x123
	#undef MC_CMD_0x123_PRIVILEGE_CTG

	-#define MC_CMD_0x123_PRIVILEGE_CTG SRIOV_CTG_ADMIN
	+#define MC_CMD_0x123_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND

	/* MC_CMD_REKEY_IN msgrequest */
	#define MC_CMD_REKEY_IN_LEN 4
	@@ -16064,9 +16333,9 @@
	#define MC_CMD_REKEY_IN_OP_OFST 0
	#define MC_CMD_REKEY_IN_OP_LEN 4
	/* enum: Start the rekeying operation */
	-#define MC_CMD_REKEY_IN_OP_REKEY 0x0
	+#define MC_CMD_REKEY_IN_OP_REKEY 0x0
	/* enum: Poll for completion of the rekeying operation */
	-#define MC_CMD_REKEY_IN_OP_POLL 0x1
	+#define MC_CMD_REKEY_IN_OP_POLL 0x1

	/* MC_CMD_REKEY_OUT msgresponse */
	#define MC_CMD_REKEY_OUT_LEN 0
	@@ -16080,7 +16349,7 @@
	#define MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS 0x124
	#undef MC_CMD_0x124_PRIVILEGE_CTG

	-#define MC_CMD_0x124_PRIVILEGE_CTG SRIOV_CTG_ADMIN
	+#define MC_CMD_0x124_PRIVILEGE_CTG SRIOV_CTG_GENERAL

	/* MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_IN msgrequest */
	#define MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_IN_LEN 0
	@@ -16108,7 +16377,7 @@
	#define MC_CMD_SET_SECURITY_FUSES 0x126
	#undef MC_CMD_0x126_PRIVILEGE_CTG

	-#define MC_CMD_0x126_PRIVILEGE_CTG SRIOV_CTG_ADMIN
	+#define MC_CMD_0x126_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND

	/* MC_CMD_SET_SECURITY_FUSES_IN msgrequest */
	#define MC_CMD_SET_SECURITY_FUSES_IN_LEN 4
	@@ -16147,7 +16416,7 @@
	#define MC_CMD_TSA_INFO 0x127
	#undef MC_CMD_0x127_PRIVILEGE_CTG

	-#define MC_CMD_0x127_PRIVILEGE_CTG SRIOV_CTG_ADMIN
	+#define MC_CMD_0x127_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND

	/* MC_CMD_TSA_INFO_IN msgrequest */
	#define MC_CMD_TSA_INFO_IN_LEN 4
	@@ -16437,7 +16706,7 @@
	#define MC_CMD_TSA_STATISTICS 0x130
	#undef MC_CMD_0x130_PRIVILEGE_CTG

	-#define MC_CMD_0x130_PRIVILEGE_CTG SRIOV_CTG_ADMIN
	+#define MC_CMD_0x130_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND

	/* MC_CMD_TSA_STATISTICS_IN msgrequest */
	#define MC_CMD_TSA_STATISTICS_IN_LEN 4
	@@ -16447,9 +16716,9 @@
	/* enum: Get the configuration parameters that describe the TSA statistics
	* layout on the adapter.
	*/
	-#define MC_CMD_TSA_STATISTICS_OP_GET_CONFIG 0x0
	+#define MC_CMD_TSA_STATISTICS_OP_GET_CONFIG 0x0
	/* enum: Read and/or clear TSA statistics counters. */
	-#define MC_CMD_TSA_STATISTICS_OP_READ_CLEAR 0x1
	+#define MC_CMD_TSA_STATISTICS_OP_READ_CLEAR 0x1

	/* MC_CMD_TSA_STATISTICS_IN_GET_CONFIG msgrequest */
	#define MC_CMD_TSA_STATISTICS_IN_GET_CONFIG_LEN 4
	@@ -16492,11 +16761,11 @@
	/* enum: The statistics counters are specified as an unordered list of
	* individual counter ID.
	*/
	-#define MC_CMD_TSA_STATISTICS_IN_READ_CLEAR_LIST 0x0
	+#define MC_CMD_TSA_STATISTICS_IN_READ_CLEAR_LIST 0x0
	/* enum: The statistics counters are specified as a range of consecutive
	* counter IDs.
	*/
	-#define MC_CMD_TSA_STATISTICS_IN_READ_CLEAR_RANGE 0x1
	+#define MC_CMD_TSA_STATISTICS_IN_READ_CLEAR_RANGE 0x1
	/* Number of statistics counters */
	#define MC_CMD_TSA_STATISTICS_IN_READ_CLEAR_NUM_STATS_OFST 12
	#define MC_CMD_TSA_STATISTICS_IN_READ_CLEAR_NUM_STATS_LEN 4
	@@ -16553,7 +16822,7 @@
	#define MC_CMD_ERASE_INITIAL_NIC_SECRET 0x131
	#undef MC_CMD_0x131_PRIVILEGE_CTG

	-#define MC_CMD_0x131_PRIVILEGE_CTG SRIOV_CTG_ADMIN
	+#define MC_CMD_0x131_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND

	/* MC_CMD_ERASE_INITIAL_NIC_SECRET_IN msgrequest */
	#define MC_CMD_ERASE_INITIAL_NIC_SECRET_IN_LEN 0
	@@ -16581,14 +16850,14 @@
	* encrypted unless they are declared as non-sensitive. Returns
	* MC_CMD_ERR_EEXIST if the tag is already present.
	*/
	-#define MC_CMD_TSA_CONFIG_OP_APPEND 0x1
	+#define MC_CMD_TSA_CONFIG_OP_APPEND 0x1
	/* enum: Reset the tsa_config partition to a clean state. */
	-#define MC_CMD_TSA_CONFIG_OP_RESET 0x2
	+#define MC_CMD_TSA_CONFIG_OP_RESET 0x2
	/* enum: Read back a configured item from tsa_config partition. Returns
	* MC_CMD_ERR_ENOENT if the item doesn't exist, or MC_CMD_ERR_EPERM if the item
	* is declared as sensitive (i.e. is encrypted).
	*/
	-#define MC_CMD_TSA_CONFIG_OP_READ 0x3
	+#define MC_CMD_TSA_CONFIG_OP_READ 0x3

	/* MC_CMD_TSA_CONFIG_IN_APPEND msgrequest */
	#define MC_CMD_TSA_CONFIG_IN_APPEND_LENMIN 12
	@@ -16680,7 +16949,7 @@
	#define MC_CMD_TSA_IPADDR 0x65
	#undef MC_CMD_0x65_PRIVILEGE_CTG

	-#define MC_CMD_0x65_PRIVILEGE_CTG SRIOV_CTG_ADMIN
	+#define MC_CMD_0x65_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND

	/* MC_CMD_TSA_IPADDR_IN msgrequest */
	#define MC_CMD_TSA_IPADDR_IN_LEN 4
	@@ -16699,12 +16968,12 @@
	* probes (if there are any) will be forwarded to the controller using
	* MC_CMD_TSA_INFO alerts.
	*/
	-#define MC_CMD_TSA_IPADDR_OP_VALIDATE_IPV4 0x1
	+#define MC_CMD_TSA_IPADDR_OP_VALIDATE_IPV4 0x1
	/* enum: Notify the adapter that one or more IPv4 addresses are no longer valid
	* for the host of the adapter. The adapter should remove the IPv4 addresses
	* from its local cache.
	*/
	-#define MC_CMD_TSA_IPADDR_OP_REMOVE_IPV4 0x2
	+#define MC_CMD_TSA_IPADDR_OP_REMOVE_IPV4 0x2

	/* MC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4 msgrequest */
	#define MC_CMD_TSA_IPADDR_IN_VALIDATE_IPV4_LENMIN 16
	@@ -16768,7 +17037,7 @@
	#define MC_CMD_SECURE_NIC_INFO 0x132
	#undef MC_CMD_0x132_PRIVILEGE_CTG

	-#define MC_CMD_0x132_PRIVILEGE_CTG SRIOV_CTG_ADMIN
	+#define MC_CMD_0x132_PRIVILEGE_CTG SRIOV_CTG_GENERAL

	/* MC_CMD_SECURE_NIC_INFO_IN msgrequest */
	#define MC_CMD_SECURE_NIC_INFO_IN_LEN 4
	@@ -16780,7 +17049,7 @@
	/* enum: Get the status of various security settings, all signed along with a
	* challenge chosen by the host.
	*/
	-#define MC_CMD_SECURE_NIC_INFO_OP_STATUS 0x0
	+#define MC_CMD_SECURE_NIC_INFO_OP_STATUS 0x0

	/* MC_CMD_SECURE_NIC_INFO_IN_STATUS msgrequest */
	#define MC_CMD_SECURE_NIC_INFO_IN_STATUS_LEN 24
	@@ -16790,17 +17059,17 @@
	/* Type of key to be used to sign response. */
	#define MC_CMD_SECURE_NIC_INFO_IN_STATUS_KEY_TYPE_OFST 4
	#define MC_CMD_SECURE_NIC_INFO_IN_STATUS_KEY_TYPE_LEN 4
	-#define MC_CMD_SECURE_NIC_INFO_IN_STATUS_UNUSED 0x0 /* enum */
	+#define MC_CMD_SECURE_NIC_INFO_IN_STATUS_UNUSED 0x0 /* enum */
	/* enum: Solarflare adapter authentication key, installed by Manftest. */
	-#define MC_CMD_SECURE_NIC_INFO_IN_STATUS_SF_ADAPTER_AUTH 0x1
	+#define MC_CMD_SECURE_NIC_INFO_IN_STATUS_SF_ADAPTER_AUTH 0x1
	/* enum: TSA binding key, installed after adapter is bound to a TSA controller.
	* This is not supported in firmware which does not support TSA.
	*/
	-#define MC_CMD_SECURE_NIC_INFO_IN_STATUS_TSA_BINDING 0x2
	+#define MC_CMD_SECURE_NIC_INFO_IN_STATUS_TSA_BINDING 0x2
	/* enum: Customer adapter authentication key. Installed by the customer in the
	* field, but otherwise similar to the Solarflare adapter authentication key.
	*/
	-#define MC_CMD_SECURE_NIC_INFO_IN_STATUS_CUSTOMER_ADAPTER_AUTH 0x3
	+#define MC_CMD_SECURE_NIC_INFO_IN_STATUS_CUSTOMER_ADAPTER_AUTH 0x3
	/* Random challenge generated by the host. */
	#define MC_CMD_SECURE_NIC_INFO_IN_STATUS_CHALLENGE_OFST 8
	#define MC_CMD_SECURE_NIC_INFO_IN_STATUS_CHALLENGE_LEN 16
	@@ -16827,7 +17096,7 @@
	/* enum: Message type value for the response to a
	* MC_CMD_SECURE_NIC_INFO_IN_STATUS message.
	*/
	-#define MC_CMD_SECURE_NIC_INFO_STATUS 0xdb4
	+#define MC_CMD_SECURE_NIC_INFO_STATUS 0xdb4
	/* The challenge provided by the host in the MC_CMD_SECURE_NIC_INFO_IN_STATUS
	* message
	*/
	@@ -16860,7 +17129,7 @@
	#define MC_CMD_TSA_TEST 0x125
	#undef MC_CMD_0x125_PRIVILEGE_CTG

	-#define MC_CMD_0x125_PRIVILEGE_CTG SRIOV_CTG_ADMIN
	+#define MC_CMD_0x125_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND

	/* MC_CMD_TSA_TEST_IN msgrequest */
	#define MC_CMD_TSA_TEST_IN_LEN 0
	@@ -16881,7 +17150,7 @@
	#define MC_CMD_TSA_RULESET_OVERRIDE 0x12a
	#undef MC_CMD_0x12a_PRIVILEGE_CTG

	-#define MC_CMD_0x12a_PRIVILEGE_CTG SRIOV_CTG_ADMIN
	+#define MC_CMD_0x12a_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND

	/* MC_CMD_TSA_RULESET_OVERRIDE_IN msgrequest */
	#define MC_CMD_TSA_RULESET_OVERRIDE_IN_LEN 4
	@@ -16889,17 +17158,17 @@
	#define MC_CMD_TSA_RULESET_OVERRIDE_IN_STATE_OFST 0
	#define MC_CMD_TSA_RULESET_OVERRIDE_IN_STATE_LEN 4
	/* enum: No override in place - the existing ruleset is in operation. */
	-#define MC_CMD_TSA_RULESET_OVERRIDE_NONE 0x0
	+#define MC_CMD_TSA_RULESET_OVERRIDE_NONE 0x0
	/* enum: Block all packets seen on all datapath channel except those packets
	* required for basic configuration of the TSA NIC such as ARPs and TSA-
	* communication traffic. Such exceptional traffic is handled differently
	* compared to TSA rulesets.
	*/
	-#define MC_CMD_TSA_RULESET_OVERRIDE_BLOCK 0x1
	+#define MC_CMD_TSA_RULESET_OVERRIDE_BLOCK 0x1
	/* enum: Allow all packets through all datapath channel. The TSA adapter
	* behaves like a normal NIC without any firewalls.
	*/
	-#define MC_CMD_TSA_RULESET_OVERRIDE_ALLOW 0x2
	+#define MC_CMD_TSA_RULESET_OVERRIDE_ALLOW 0x2

	/* MC_CMD_TSA_RULESET_OVERRIDE_OUT msgresponse */
	#define MC_CMD_TSA_RULESET_OVERRIDE_OUT_LEN 0
	@@ -16913,7 +17182,7 @@
	#define MC_CMD_TSAC_REQUEST 0x12b
	#undef MC_CMD_0x12b_PRIVILEGE_CTG

	-#define MC_CMD_0x12b_PRIVILEGE_CTG SRIOV_CTG_ADMIN
	+#define MC_CMD_0x12b_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND

	/* MC_CMD_TSAC_REQUEST_IN msgrequest */
	#define MC_CMD_TSAC_REQUEST_IN_LEN 4
	@@ -16924,7 +17193,7 @@
	* command does not return any IP address information; IP addresses are sent as
	* TSA notifications as descibed in MC_CMD_TSA_INFO_IN_LOCAL_IP.
	*/
	-#define MC_CMD_TSAC_REQUEST_LOCALIP 0x0
	+#define MC_CMD_TSAC_REQUEST_LOCALIP 0x0

	/* MC_CMD_TSAC_REQUEST_OUT msgresponse */
	#define MC_CMD_TSAC_REQUEST_OUT_LEN 0
	@@ -16937,7 +17206,7 @@
	#define MC_CMD_SUC_VERSION 0x134
	#undef MC_CMD_0x134_PRIVILEGE_CTG

	-#define MC_CMD_0x134_PRIVILEGE_CTG SRIOV_CTG_ADMIN
	+#define MC_CMD_0x134_PRIVILEGE_CTG SRIOV_CTG_GENERAL

	/* MC_CMD_SUC_VERSION_IN msgrequest */
	#define MC_CMD_SUC_VERSION_IN_LEN 0
	@@ -16982,7 +17251,7 @@
	#define MC_CMD_SUC_MANFTEST 0x135
	#undef MC_CMD_0x135_PRIVILEGE_CTG

	-#define MC_CMD_0x135_PRIVILEGE_CTG SRIOV_CTG_ADMIN
	+#define MC_CMD_0x135_PRIVILEGE_CTG SRIOV_CTG_ADMIN_TSA_UNBOUND

	/* MC_CMD_SUC_MANFTEST_IN msgrequest */
	#define MC_CMD_SUC_MANFTEST_IN_LEN 4
	@@ -16990,19 +17259,23 @@
	#define MC_CMD_SUC_MANFTEST_IN_OP_OFST 0
	#define MC_CMD_SUC_MANFTEST_IN_OP_LEN 4
	/* enum: Read serial number and use count. */
	-#define MC_CMD_SUC_MANFTEST_WEAROUT_READ 0x0
	+#define MC_CMD_SUC_MANFTEST_WEAROUT_READ 0x0
	/* enum: Update use count on wearout adapter. */
	-#define MC_CMD_SUC_MANFTEST_WEAROUT_UPDATE 0x1
	+#define MC_CMD_SUC_MANFTEST_WEAROUT_UPDATE 0x1
	/* enum: Start an ADC calibration. */
	-#define MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_START 0x2
	+#define MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_START 0x2
	/* enum: Read the status of an ADC calibration. */
	-#define MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_STATUS 0x3
	+#define MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_STATUS 0x3
	/* enum: Read the results of an ADC calibration. */
	-#define MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_RESULT 0x4
	+#define MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_RESULT 0x4
	/* enum: Read the PCIe configuration. */
	-#define MC_CMD_SUC_MANFTEST_CONFIG_PCIE_READ 0x5
	+#define MC_CMD_SUC_MANFTEST_CONFIG_PCIE_READ 0x5
	/* enum: Write the PCIe configuration. */
	-#define MC_CMD_SUC_MANFTEST_CONFIG_PCIE_WRITE 0x6
	+#define MC_CMD_SUC_MANFTEST_CONFIG_PCIE_WRITE 0x6
	+/* enum: Write FRU information to SUC. The FRU information is taken from the
	+ * FRU_INFORMATION partition. Attempts to write to read-only FRUs are rejected.
	+ */
	+#define MC_CMD_SUC_MANFTEST_FRU_WRITE 0x7

	/* MC_CMD_SUC_MANFTEST_OUT msgresponse */
	#define MC_CMD_SUC_MANFTEST_OUT_LEN 0
	@@ -17076,12 +17349,12 @@
	#define MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_RESULT_IN_OP_OFST 0
	#define MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_RESULT_IN_OP_LEN 4

	-/* MC_CMD_SUC_WEAROUT_ADC_CALIBRATE_RESULT_OUT msgresponse */
	-#define MC_CMD_SUC_WEAROUT_ADC_CALIBRATE_RESULT_OUT_LEN 12
	+/* MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_RESULT_OUT msgresponse */
	+#define MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_RESULT_OUT_LEN 12
	/* The set of calibration results. */
	-#define MC_CMD_SUC_WEAROUT_ADC_CALIBRATE_RESULT_OUT_VALUE_OFST 0
	-#define MC_CMD_SUC_WEAROUT_ADC_CALIBRATE_RESULT_OUT_VALUE_LEN 4
	-#define MC_CMD_SUC_WEAROUT_ADC_CALIBRATE_RESULT_OUT_VALUE_NUM 3
	+#define MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_RESULT_OUT_VALUE_OFST 0
	+#define MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_RESULT_OUT_VALUE_LEN 4
	+#define MC_CMD_SUC_MANFTEST_ADC_CALIBRATE_RESULT_OUT_VALUE_NUM 3

	/* MC_CMD_SUC_MANFTEST_CONFIG_PCIE_READ_IN msgrequest */
	#define MC_CMD_SUC_MANFTEST_CONFIG_PCIE_READ_IN_LEN 4
	@@ -17091,14 +17364,14 @@
	#define MC_CMD_SUC_MANFTEST_CONFIG_PCIE_READ_IN_OP_OFST 0
	#define MC_CMD_SUC_MANFTEST_CONFIG_PCIE_READ_IN_OP_LEN 4

	-/* MC_CMD_SUC_WEAROUT_CONFIG_PCIE_READ_OUT msgresponse */
	-#define MC_CMD_SUC_WEAROUT_CONFIG_PCIE_READ_OUT_LEN 4
	+/* MC_CMD_SUC_MANFTEST_CONFIG_PCIE_READ_OUT msgresponse */
	+#define MC_CMD_SUC_MANFTEST_CONFIG_PCIE_READ_OUT_LEN 4
	/* The PCIe vendor ID. */
	-#define MC_CMD_SUC_WEAROUT_CONFIG_PCIE_READ_OUT_VENDOR_ID_OFST 0
	-#define MC_CMD_SUC_WEAROUT_CONFIG_PCIE_READ_OUT_VENDOR_ID_LEN 2
	+#define MC_CMD_SUC_MANFTEST_CONFIG_PCIE_READ_OUT_VENDOR_ID_OFST 0
	+#define MC_CMD_SUC_MANFTEST_CONFIG_PCIE_READ_OUT_VENDOR_ID_LEN 2
	/* The PCIe device ID. */
	-#define MC_CMD_SUC_WEAROUT_CONFIG_PCIE_READ_OUT_DEVICE_ID_OFST 2
	-#define MC_CMD_SUC_WEAROUT_CONFIG_PCIE_READ_OUT_DEVICE_ID_LEN 2
	+#define MC_CMD_SUC_MANFTEST_CONFIG_PCIE_READ_OUT_DEVICE_ID_OFST 2
	+#define MC_CMD_SUC_MANFTEST_CONFIG_PCIE_READ_OUT_DEVICE_ID_LEN 2

	/* MC_CMD_SUC_MANFTEST_CONFIG_PCIE_WRITE_IN msgrequest */
	#define MC_CMD_SUC_MANFTEST_CONFIG_PCIE_WRITE_IN_LEN 8
	@@ -17116,5 +17389,158 @@

	/* MC_CMD_SUC_MANFTEST_CONFIG_PCIE_WRITE_OUT msgresponse */
	#define MC_CMD_SUC_MANFTEST_CONFIG_PCIE_WRITE_OUT_LEN 0
	+
	+/* MC_CMD_SUC_MANFTEST_FRU_WRITE_IN msgrequest */
	+#define MC_CMD_SUC_MANFTEST_FRU_WRITE_IN_LEN 4
	+/* The manftest operation to be performed. This must be
	+ * MC_CMD_SUC_MANFTEST_FRU_WRITE
	+ */
	+#define MC_CMD_SUC_MANFTEST_FRU_WRITE_IN_OP_OFST 0
	+#define MC_CMD_SUC_MANFTEST_FRU_WRITE_IN_OP_LEN 4
	+
	+/* MC_CMD_SUC_MANFTEST_FRU_WRITE_OUT msgresponse */
	+#define MC_CMD_SUC_MANFTEST_FRU_WRITE_OUT_LEN 0
	+
	+
	+/***********************************/
	+/* MC_CMD_GET_CERTIFICATE
	+ * Request a certificate.
	+ */
	+#define MC_CMD_GET_CERTIFICATE 0x12c
	+#undef MC_CMD_0x12c_PRIVILEGE_CTG
	+
	+#define MC_CMD_0x12c_PRIVILEGE_CTG SRIOV_CTG_GENERAL
	+
	+/* MC_CMD_GET_CERTIFICATE_IN msgrequest */
	+#define MC_CMD_GET_CERTIFICATE_IN_LEN 8
	+/* Type of the certificate to be retrieved. */
	+#define MC_CMD_GET_CERTIFICATE_IN_TYPE_OFST 0
	+#define MC_CMD_GET_CERTIFICATE_IN_TYPE_LEN 4
	+#define MC_CMD_GET_CERTIFICATE_IN_UNUSED 0x0 /* enum */
	+#define MC_CMD_GET_CERTIFICATE_IN_AAC 0x1 /* enum */
	+/* enum: Adapter Authentication Certificate (AAC). The AAC is unique to each
	+ * adapter and is used to verify its authenticity. It is installed by Manftest.
	+ */
	+#define MC_CMD_GET_CERTIFICATE_IN_ADAPTER_AUTH 0x1
	+#define MC_CMD_GET_CERTIFICATE_IN_AASC 0x2 /* enum */
	+/* enum: Adapter Authentication Signing Certificate (AASC). The AASC is shared
	+ * by a group of adapters (typically a purchase order) and is used to verify
	+ * the validity of AAC along with the SF root certificate. It is installed by
	+ * Manftest.
	+ */
	+#define MC_CMD_GET_CERTIFICATE_IN_ADAPTER_AUTH_SIGNING 0x2
	+#define MC_CMD_GET_CERTIFICATE_IN_CUSTOMER_AAC 0x3 /* enum */
	+/* enum: Customer Adapter Authentication Certificate. The Customer AAC is
	+ * unique to each adapter and is used to verify its authenticity in cases where
	+ * either the AAC is not installed or a customer desires to use their own
	+ * certificate chain. It is installed by the customer.
	+ */
	+#define MC_CMD_GET_CERTIFICATE_IN_CUSTOMER_ADAPTER_AUTH 0x3
	+#define MC_CMD_GET_CERTIFICATE_IN_CUSTOMER_AASC 0x4 /* enum */
	+/* enum: Customer Adapter Authentication Certificate. The Customer AASC is
	+ * shared by a group of adapters and is used to verify the validity of the
	+ * Customer AAC along with the customers root certificate. It is installed by
	+ * the customer.
	+ */
	+#define MC_CMD_GET_CERTIFICATE_IN_CUSTOMER_ADAPTER_AUTH_SIGNING 0x4
	+/* Offset, measured in bytes, relative to the start of the certificate data
	+ * from which the certificate is to be retrieved.
	+ */
	+#define MC_CMD_GET_CERTIFICATE_IN_OFFSET_OFST 4
	+#define MC_CMD_GET_CERTIFICATE_IN_OFFSET_LEN 4
	+
	+/* MC_CMD_GET_CERTIFICATE_OUT msgresponse */
	+#define MC_CMD_GET_CERTIFICATE_OUT_LENMIN 13
	+#define MC_CMD_GET_CERTIFICATE_OUT_LENMAX 252
	+#define MC_CMD_GET_CERTIFICATE_OUT_LEN(num) (12+1*(num))
	+/* Type of the certificate. */
	+#define MC_CMD_GET_CERTIFICATE_OUT_TYPE_OFST 0
	+#define MC_CMD_GET_CERTIFICATE_OUT_TYPE_LEN 4
	+/* Enum values, see field(s): */
	+/* MC_CMD_GET_CERTIFICATE_IN/TYPE */
	+/* Offset, measured in bytes, relative to the start of the certificate data
	+ * from which data in this message starts.
	+ */
	+#define MC_CMD_GET_CERTIFICATE_OUT_OFFSET_OFST 4
	+#define MC_CMD_GET_CERTIFICATE_OUT_OFFSET_LEN 4
	+/* Total length of the certificate data. */
	+#define MC_CMD_GET_CERTIFICATE_OUT_TOTAL_LENGTH_OFST 8
	+#define MC_CMD_GET_CERTIFICATE_OUT_TOTAL_LENGTH_LEN 4
	+/* The certificate data. */
	+#define MC_CMD_GET_CERTIFICATE_OUT_DATA_OFST 12
	+#define MC_CMD_GET_CERTIFICATE_OUT_DATA_LEN 1
	+#define MC_CMD_GET_CERTIFICATE_OUT_DATA_MINNUM 1
	+#define MC_CMD_GET_CERTIFICATE_OUT_DATA_MAXNUM 240
	+
	+
	+/***********************************/
	+/* MC_CMD_GET_NIC_GLOBAL
	+ * Get a global value which applies to all PCI functions
	+ */
	+#define MC_CMD_GET_NIC_GLOBAL 0x12d
	+#undef MC_CMD_0x12d_PRIVILEGE_CTG
	+
	+#define MC_CMD_0x12d_PRIVILEGE_CTG SRIOV_CTG_GENERAL
	+
	+/* MC_CMD_GET_NIC_GLOBAL_IN msgrequest */
	+#define MC_CMD_GET_NIC_GLOBAL_IN_LEN 4
	+/* Key to request value for, see enum values in MC_CMD_SET_NIC_GLOBAL. If the
	+ * given key is unknown to the current firmware, the call will fail with
	+ * ENOENT.
	+ */
	+#define MC_CMD_GET_NIC_GLOBAL_IN_KEY_OFST 0
	+#define MC_CMD_GET_NIC_GLOBAL_IN_KEY_LEN 4
	+
	+/* MC_CMD_GET_NIC_GLOBAL_OUT msgresponse */
	+#define MC_CMD_GET_NIC_GLOBAL_OUT_LEN 4
	+/* Value of requested key, see key descriptions below. */
	+#define MC_CMD_GET_NIC_GLOBAL_OUT_VALUE_OFST 0
	+#define MC_CMD_GET_NIC_GLOBAL_OUT_VALUE_LEN 4
	+
	+
	+/***********************************/
	+/* MC_CMD_SET_NIC_GLOBAL
	+ * Set a global value which applies to all PCI functions. Most global values
	+ * can only be changed under specific conditions, and this call will return an
	+ * appropriate error otherwise (see key descriptions).
	+ */
	+#define MC_CMD_SET_NIC_GLOBAL 0x12e
	+#undef MC_CMD_0x12e_PRIVILEGE_CTG
	+
	+#define MC_CMD_0x12e_PRIVILEGE_CTG SRIOV_CTG_ADMIN
	+
	+/* MC_CMD_SET_NIC_GLOBAL_IN msgrequest */
	+#define MC_CMD_SET_NIC_GLOBAL_IN_LEN 8
	+/* Key to change value of. Firmware will return ENOENT for keys it doesn't know
	+ * about.
	+ */
	+#define MC_CMD_SET_NIC_GLOBAL_IN_KEY_OFST 0
	+#define MC_CMD_SET_NIC_GLOBAL_IN_KEY_LEN 4
	+/* enum: Request switching the datapath firmware sub-variant. Currently only
	+ * useful when running the DPDK f/w variant. See key values below, and the DPDK
	+ * section of the EF10 Driver Writers Guide. Note that any driver attaching
	+ * with the SUBVARIANT_AWARE flag cleared is implicitly considered as a request
	+ * to switch back to the default sub-variant, and will thus reset this value.
	+ * If a sub-variant switch happens, all other PCI functions will get their
	+ * resources reset (they will see an MC reboot).
	+ */
	+#define MC_CMD_SET_NIC_GLOBAL_IN_FIRMWARE_SUBVARIANT 0x1
	+/* New value to set, see key descriptions above. */
	+#define MC_CMD_SET_NIC_GLOBAL_IN_VALUE_OFST 4
	+#define MC_CMD_SET_NIC_GLOBAL_IN_VALUE_LEN 4
	+/* enum: Only if KEY = FIRMWARE_SUBVARIANT. Default sub-variant with support
	+ * for maximum features for the current f/w variant. A request from a
	+ * privileged function to set this particular value will always succeed.
	+ */
	+#define MC_CMD_SET_NIC_GLOBAL_IN_FW_SUBVARIANT_DEFAULT 0x0
	+/* enum: Only if KEY = FIRMWARE_SUBVARIANT. Increases packet rate at the cost
	+ * of not supporting any TX checksum offloads. Only supported when running some
	+ * f/w variants, others will return ENOTSUP (as reported by the homonymous bit
	+ * in MC_CMD_GET_CAPABILITIES_V2). Can only be set when no other drivers are
	+ * attached, and the calling driver must have no resources allocated. See the
	+ * DPDK section of the EF10 Driver Writers Guide for a more detailed
	+ * description with possible error codes.
	+ */
	+#define MC_CMD_SET_NIC_GLOBAL_IN_FW_SUBVARIANT_NO_TX_CSUM 0x1

	#endif /* _SIENA_MC_DRIVER_PCOL_H */
	Index: head/sys/dev/sfxge/common/efx_regs_mcdi_aoe.h
	===================================================================
	--- head/sys/dev/sfxge/common/efx_regs_mcdi_aoe.h
	+++ head/sys/dev/sfxge/common/efx_regs_mcdi_aoe.h
	@@ -717,8 +717,8 @@
	/* MC_CMD_FC_IN_CMD_LEN 4 */
	#define MC_CMD_FC_IN_DMA_OP_OFST 4
	#define MC_CMD_FC_IN_DMA_OP_LEN 4
	-#define MC_CMD_FC_IN_DMA_STOP 0x0 /* enum */
	-#define MC_CMD_FC_IN_DMA_READ 0x1 /* enum */
	+#define MC_CMD_FC_IN_DMA_STOP 0x0 /* enum */
	+#define MC_CMD_FC_IN_DMA_READ 0x1 /* enum */

	/* MC_CMD_FC_IN_DMA_STOP msgrequest */
	#define MC_CMD_FC_IN_DMA_STOP_LEN 12
	@@ -747,9 +747,9 @@
	/* MC_CMD_FC_IN_CMD_LEN 4 */
	#define MC_CMD_FC_IN_TIMED_READ_OP_OFST 4
	#define MC_CMD_FC_IN_TIMED_READ_OP_LEN 4
	-#define MC_CMD_FC_IN_TIMED_READ_SET 0x0 /* enum */
	-#define MC_CMD_FC_IN_TIMED_READ_GET 0x1 /* enum */
	-#define MC_CMD_FC_IN_TIMED_READ_CLEAR 0x2 /* enum */
	+#define MC_CMD_FC_IN_TIMED_READ_SET 0x0 /* enum */
	+#define MC_CMD_FC_IN_TIMED_READ_GET 0x1 /* enum */
	+#define MC_CMD_FC_IN_TIMED_READ_CLEAR 0x2 /* enum */

	/* MC_CMD_FC_IN_TIMED_READ_SET msgrequest */
	#define MC_CMD_FC_IN_TIMED_READ_SET_LEN 52
	@@ -792,10 +792,10 @@
	#define MC_CMD_FC_IN_TIMED_READ_SET_EVENT_WIDTH 1
	#define MC_CMD_FC_IN_TIMED_READ_SET_PREREAD_LBN 3
	#define MC_CMD_FC_IN_TIMED_READ_SET_PREREAD_WIDTH 2
	-#define MC_CMD_FC_IN_TIMED_READ_SET_NONE 0x0 /* enum */
	-#define MC_CMD_FC_IN_TIMED_READ_SET_READ 0x1 /* enum */
	-#define MC_CMD_FC_IN_TIMED_READ_SET_WRITE 0x2 /* enum */
	-#define MC_CMD_FC_IN_TIMED_READ_SET_READWRITE 0x3 /* enum */
	+#define MC_CMD_FC_IN_TIMED_READ_SET_NONE 0x0 /* enum */
	+#define MC_CMD_FC_IN_TIMED_READ_SET_READ 0x1 /* enum */
	+#define MC_CMD_FC_IN_TIMED_READ_SET_WRITE 0x2 /* enum */
	+#define MC_CMD_FC_IN_TIMED_READ_SET_READWRITE 0x3 /* enum */
	/* Period at which reads are performed (100ms units) */
	#define MC_CMD_FC_IN_TIMED_READ_SET_PERIOD_OFST 48
	#define MC_CMD_FC_IN_TIMED_READ_SET_PERIOD_LEN 4
	@@ -826,8 +826,8 @@
	/* MC_CMD_FC_IN_CMD_LEN 4 */
	#define MC_CMD_FC_IN_LOG_OP_OFST 4
	#define MC_CMD_FC_IN_LOG_OP_LEN 4
	-#define MC_CMD_FC_IN_LOG_ADDR_RANGE 0x0 /* enum */
	-#define MC_CMD_FC_IN_LOG_JTAG_UART 0x1 /* enum */
	+#define MC_CMD_FC_IN_LOG_ADDR_RANGE 0x0 /* enum */
	+#define MC_CMD_FC_IN_LOG_JTAG_UART 0x1 /* enum */

	/* MC_CMD_FC_IN_LOG_ADDR_RANGE msgrequest */
	#define MC_CMD_FC_IN_LOG_ADDR_RANGE_LEN 20
	@@ -855,31 +855,33 @@
	#define MC_CMD_FC_IN_LOG_JTAG_UART_ENABLE_OFST 8
	#define MC_CMD_FC_IN_LOG_JTAG_UART_ENABLE_LEN 4

	-/* MC_CMD_FC_IN_CLOCK msgrequest */
	+/* MC_CMD_FC_IN_CLOCK msgrequest: Perform a clock operation */
	#define MC_CMD_FC_IN_CLOCK_LEN 12
	/* MC_CMD_FC_IN_CMD_OFST 0 */
	/* MC_CMD_FC_IN_CMD_LEN 4 */
	#define MC_CMD_FC_IN_CLOCK_OP_OFST 4
	#define MC_CMD_FC_IN_CLOCK_OP_LEN 4
	-#define MC_CMD_FC_IN_CLOCK_GET_TIME 0x0 /* enum */
	-#define MC_CMD_FC_IN_CLOCK_SET_TIME 0x1 /* enum */
	-/* Perform a clock operation */
	+#define MC_CMD_FC_IN_CLOCK_GET_TIME 0x0 /* enum */
	+#define MC_CMD_FC_IN_CLOCK_SET_TIME 0x1 /* enum */
	#define MC_CMD_FC_IN_CLOCK_ID_OFST 8
	#define MC_CMD_FC_IN_CLOCK_ID_LEN 4
	-#define MC_CMD_FC_IN_CLOCK_STATS 0x0 /* enum */
	-#define MC_CMD_FC_IN_CLOCK_MAC 0x1 /* enum */
	+#define MC_CMD_FC_IN_CLOCK_STATS 0x0 /* enum */
	+#define MC_CMD_FC_IN_CLOCK_MAC 0x1 /* enum */

	-/* MC_CMD_FC_IN_CLOCK_GET_TIME msgrequest */
	+/* MC_CMD_FC_IN_CLOCK_GET_TIME msgrequest: Retrieve the clock value of the
	+ * specified clock
	+ */
	#define MC_CMD_FC_IN_CLOCK_GET_TIME_LEN 12
	/* MC_CMD_FC_IN_CMD_OFST 0 */
	/* MC_CMD_FC_IN_CMD_LEN 4 */
	/* MC_CMD_FC_IN_CLOCK_OP_OFST 4 */
	/* MC_CMD_FC_IN_CLOCK_OP_LEN 4 */
	-/* Retrieve the clock value of the specified clock */
	/* MC_CMD_FC_IN_CLOCK_ID_OFST 8 */
	/* MC_CMD_FC_IN_CLOCK_ID_LEN 4 */

	-/* MC_CMD_FC_IN_CLOCK_SET_TIME msgrequest */
	+/* MC_CMD_FC_IN_CLOCK_SET_TIME msgrequest: Set the clock value of the specified
	+ * clock
	+ */
	#define MC_CMD_FC_IN_CLOCK_SET_TIME_LEN 24
	/* MC_CMD_FC_IN_CMD_OFST 0 */
	/* MC_CMD_FC_IN_CMD_LEN 4 */
	@@ -891,7 +893,6 @@
	#define MC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_LEN 8
	#define MC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_LO_OFST 12
	#define MC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_HI_OFST 16
	-/* Set the clock value of the specified clock */
	#define MC_CMD_FC_IN_CLOCK_SET_TIME_NANOSECONDS_OFST 20
	#define MC_CMD_FC_IN_CLOCK_SET_TIME_NANOSECONDS_LEN 4

	@@ -901,16 +902,16 @@
	/* MC_CMD_FC_IN_CMD_LEN 4 */
	#define MC_CMD_FC_IN_DDR_OP_OFST 4
	#define MC_CMD_FC_IN_DDR_OP_LEN 4
	-#define MC_CMD_FC_IN_DDR_SET_SPD 0x0 /* enum */
	-#define MC_CMD_FC_IN_DDR_GET_STATUS 0x1 /* enum */
	-#define MC_CMD_FC_IN_DDR_SET_INFO 0x2 /* enum */
	+#define MC_CMD_FC_IN_DDR_SET_SPD 0x0 /* enum */
	+#define MC_CMD_FC_IN_DDR_GET_STATUS 0x1 /* enum */
	+#define MC_CMD_FC_IN_DDR_SET_INFO 0x2 /* enum */
	#define MC_CMD_FC_IN_DDR_BANK_OFST 8
	#define MC_CMD_FC_IN_DDR_BANK_LEN 4
	-#define MC_CMD_FC_IN_DDR_BANK_B0 0x0 /* enum */
	-#define MC_CMD_FC_IN_DDR_BANK_B1 0x1 /* enum */
	-#define MC_CMD_FC_IN_DDR_BANK_T0 0x2 /* enum */
	-#define MC_CMD_FC_IN_DDR_BANK_T1 0x3 /* enum */
	-#define MC_CMD_FC_IN_DDR_NUM_BANKS 0x4 /* enum */
	+#define MC_CMD_FC_IN_DDR_BANK_B0 0x0 /* enum */
	+#define MC_CMD_FC_IN_DDR_BANK_B1 0x1 /* enum */
	+#define MC_CMD_FC_IN_DDR_BANK_T0 0x2 /* enum */
	+#define MC_CMD_FC_IN_DDR_BANK_T1 0x3 /* enum */
	+#define MC_CMD_FC_IN_DDR_NUM_BANKS 0x4 /* enum */

	/* MC_CMD_FC_IN_DDR_SET_SPD msgrequest */
	#define MC_CMD_FC_IN_DDR_SET_SPD_LEN 148
	@@ -924,7 +925,7 @@
	/* Flags */
	#define MC_CMD_FC_IN_DDR_FLAGS_OFST 12
	#define MC_CMD_FC_IN_DDR_FLAGS_LEN 4
	-#define MC_CMD_FC_IN_DDR_SET_SPD_ACTIVE 0x1 /* enum */
	+#define MC_CMD_FC_IN_DDR_SET_SPD_ACTIVE 0x1 /* enum */
	/* 128-byte page of serial presence detect data read from module's EEPROM */
	#define MC_CMD_FC_IN_DDR_SPD_OFST 16
	#define MC_CMD_FC_IN_DDR_SPD_LEN 1
	@@ -1318,33 +1319,33 @@
	#define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_LO_OFST 0
	#define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_HI_OFST 4
	#define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_NUM MC_CMD_FC_MAC_RX_NSTATS
	-#define MC_CMD_FC_MAC_RX_STATS_OCTETS 0x0 /* enum */
	-#define MC_CMD_FC_MAC_RX_OCTETS_OK 0x1 /* enum */
	-#define MC_CMD_FC_MAC_RX_ALIGNMENT_ERRORS 0x2 /* enum */
	-#define MC_CMD_FC_MAC_RX_PAUSE_MAC_CTRL_FRAMES 0x3 /* enum */
	-#define MC_CMD_FC_MAC_RX_FRAMES_OK 0x4 /* enum */
	-#define MC_CMD_FC_MAC_RX_CRC_ERRORS 0x5 /* enum */
	-#define MC_CMD_FC_MAC_RX_VLAN_OK 0x6 /* enum */
	-#define MC_CMD_FC_MAC_RX_ERRORS 0x7 /* enum */
	-#define MC_CMD_FC_MAC_RX_UCAST_PKTS 0x8 /* enum */
	-#define MC_CMD_FC_MAC_RX_MULTICAST_PKTS 0x9 /* enum */
	-#define MC_CMD_FC_MAC_RX_BROADCAST_PKTS 0xa /* enum */
	-#define MC_CMD_FC_MAC_RX_STATS_DROP_EVENTS 0xb /* enum */
	-#define MC_CMD_FC_MAC_RX_STATS_PKTS 0xc /* enum */
	-#define MC_CMD_FC_MAC_RX_STATS_UNDERSIZE_PKTS 0xd /* enum */
	-#define MC_CMD_FC_MAC_RX_STATS_PKTS_64 0xe /* enum */
	-#define MC_CMD_FC_MAC_RX_STATS_PKTS_65_127 0xf /* enum */
	-#define MC_CMD_FC_MAC_RX_STATS_PKTS_128_255 0x10 /* enum */
	-#define MC_CMD_FC_MAC_RX_STATS_PKTS_256_511 0x11 /* enum */
	-#define MC_CMD_FC_MAC_RX_STATS_PKTS_512_1023 0x12 /* enum */
	-#define MC_CMD_FC_MAC_RX_STATS_PKTS_1024_1518 0x13 /* enum */
	-#define MC_CMD_FC_MAC_RX_STATS_PKTS_1519_MAX 0x14 /* enum */
	-#define MC_CMD_FC_MAC_RX_STATS_OVERSIZE_PKTS 0x15 /* enum */
	-#define MC_CMD_FC_MAC_RX_STATS_JABBERS 0x16 /* enum */
	-#define MC_CMD_FC_MAC_RX_STATS_FRAGMENTS 0x17 /* enum */
	-#define MC_CMD_FC_MAC_RX_MAC_CONTROL_FRAMES 0x18 /* enum */
	+#define MC_CMD_FC_MAC_RX_STATS_OCTETS 0x0 /* enum */
	+#define MC_CMD_FC_MAC_RX_OCTETS_OK 0x1 /* enum */
	+#define MC_CMD_FC_MAC_RX_ALIGNMENT_ERRORS 0x2 /* enum */
	+#define MC_CMD_FC_MAC_RX_PAUSE_MAC_CTRL_FRAMES 0x3 /* enum */
	+#define MC_CMD_FC_MAC_RX_FRAMES_OK 0x4 /* enum */
	+#define MC_CMD_FC_MAC_RX_CRC_ERRORS 0x5 /* enum */
	+#define MC_CMD_FC_MAC_RX_VLAN_OK 0x6 /* enum */
	+#define MC_CMD_FC_MAC_RX_ERRORS 0x7 /* enum */
	+#define MC_CMD_FC_MAC_RX_UCAST_PKTS 0x8 /* enum */
	+#define MC_CMD_FC_MAC_RX_MULTICAST_PKTS 0x9 /* enum */
	+#define MC_CMD_FC_MAC_RX_BROADCAST_PKTS 0xa /* enum */
	+#define MC_CMD_FC_MAC_RX_STATS_DROP_EVENTS 0xb /* enum */
	+#define MC_CMD_FC_MAC_RX_STATS_PKTS 0xc /* enum */
	+#define MC_CMD_FC_MAC_RX_STATS_UNDERSIZE_PKTS 0xd /* enum */
	+#define MC_CMD_FC_MAC_RX_STATS_PKTS_64 0xe /* enum */
	+#define MC_CMD_FC_MAC_RX_STATS_PKTS_65_127 0xf /* enum */
	+#define MC_CMD_FC_MAC_RX_STATS_PKTS_128_255 0x10 /* enum */
	+#define MC_CMD_FC_MAC_RX_STATS_PKTS_256_511 0x11 /* enum */
	+#define MC_CMD_FC_MAC_RX_STATS_PKTS_512_1023 0x12 /* enum */
	+#define MC_CMD_FC_MAC_RX_STATS_PKTS_1024_1518 0x13 /* enum */
	+#define MC_CMD_FC_MAC_RX_STATS_PKTS_1519_MAX 0x14 /* enum */
	+#define MC_CMD_FC_MAC_RX_STATS_OVERSIZE_PKTS 0x15 /* enum */
	+#define MC_CMD_FC_MAC_RX_STATS_JABBERS 0x16 /* enum */
	+#define MC_CMD_FC_MAC_RX_STATS_FRAGMENTS 0x17 /* enum */
	+#define MC_CMD_FC_MAC_RX_MAC_CONTROL_FRAMES 0x18 /* enum */
	/* enum: (Last entry) */
	-#define MC_CMD_FC_MAC_RX_NSTATS 0x19
	+#define MC_CMD_FC_MAC_RX_NSTATS 0x19

	/* MC_CMD_FC_OUT_MAC_GET_TX_STATS msgresponse */
	#define MC_CMD_FC_OUT_MAC_GET_TX_STATS_LEN ((((0-1+(64*MC_CMD_FC_MAC_TX_NSTATS))+1))>>3)
	@@ -1353,30 +1354,30 @@
	#define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_LO_OFST 0
	#define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_HI_OFST 4
	#define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_NUM MC_CMD_FC_MAC_TX_NSTATS
	-#define MC_CMD_FC_MAC_TX_STATS_OCTETS 0x0 /* enum */
	-#define MC_CMD_FC_MAC_TX_OCTETS_OK 0x1 /* enum */
	-#define MC_CMD_FC_MAC_TX_ALIGNMENT_ERRORS 0x2 /* enum */
	-#define MC_CMD_FC_MAC_TX_PAUSE_MAC_CTRL_FRAMES 0x3 /* enum */
	-#define MC_CMD_FC_MAC_TX_FRAMES_OK 0x4 /* enum */
	-#define MC_CMD_FC_MAC_TX_CRC_ERRORS 0x5 /* enum */
	-#define MC_CMD_FC_MAC_TX_VLAN_OK 0x6 /* enum */
	-#define MC_CMD_FC_MAC_TX_ERRORS 0x7 /* enum */
	-#define MC_CMD_FC_MAC_TX_UCAST_PKTS 0x8 /* enum */
	-#define MC_CMD_FC_MAC_TX_MULTICAST_PKTS 0x9 /* enum */
	-#define MC_CMD_FC_MAC_TX_BROADCAST_PKTS 0xa /* enum */
	-#define MC_CMD_FC_MAC_TX_STATS_DROP_EVENTS 0xb /* enum */
	-#define MC_CMD_FC_MAC_TX_STATS_PKTS 0xc /* enum */
	-#define MC_CMD_FC_MAC_TX_STATS_UNDERSIZE_PKTS 0xd /* enum */
	-#define MC_CMD_FC_MAC_TX_STATS_PKTS_64 0xe /* enum */
	-#define MC_CMD_FC_MAC_TX_STATS_PKTS_65_127 0xf /* enum */
	-#define MC_CMD_FC_MAC_TX_STATS_PKTS_128_255 0x10 /* enum */
	-#define MC_CMD_FC_MAC_TX_STATS_PKTS_256_511 0x11 /* enum */
	-#define MC_CMD_FC_MAC_TX_STATS_PKTS_512_1023 0x12 /* enum */
	-#define MC_CMD_FC_MAC_TX_STATS_PKTS_1024_1518 0x13 /* enum */
	-#define MC_CMD_FC_MAC_TX_STATS_PKTS_1519_TX_MTU 0x14 /* enum */
	-#define MC_CMD_FC_MAC_TX_MAC_CONTROL_FRAMES 0x15 /* enum */
	+#define MC_CMD_FC_MAC_TX_STATS_OCTETS 0x0 /* enum */
	+#define MC_CMD_FC_MAC_TX_OCTETS_OK 0x1 /* enum */
	+#define MC_CMD_FC_MAC_TX_ALIGNMENT_ERRORS 0x2 /* enum */
	+#define MC_CMD_FC_MAC_TX_PAUSE_MAC_CTRL_FRAMES 0x3 /* enum */
	+#define MC_CMD_FC_MAC_TX_FRAMES_OK 0x4 /* enum */
	+#define MC_CMD_FC_MAC_TX_CRC_ERRORS 0x5 /* enum */
	+#define MC_CMD_FC_MAC_TX_VLAN_OK 0x6 /* enum */
	+#define MC_CMD_FC_MAC_TX_ERRORS 0x7 /* enum */
	+#define MC_CMD_FC_MAC_TX_UCAST_PKTS 0x8 /* enum */
	+#define MC_CMD_FC_MAC_TX_MULTICAST_PKTS 0x9 /* enum */
	+#define MC_CMD_FC_MAC_TX_BROADCAST_PKTS 0xa /* enum */
	+#define MC_CMD_FC_MAC_TX_STATS_DROP_EVENTS 0xb /* enum */
	+#define MC_CMD_FC_MAC_TX_STATS_PKTS 0xc /* enum */
	+#define MC_CMD_FC_MAC_TX_STATS_UNDERSIZE_PKTS 0xd /* enum */
	+#define MC_CMD_FC_MAC_TX_STATS_PKTS_64 0xe /* enum */
	+#define MC_CMD_FC_MAC_TX_STATS_PKTS_65_127 0xf /* enum */
	+#define MC_CMD_FC_MAC_TX_STATS_PKTS_128_255 0x10 /* enum */
	+#define MC_CMD_FC_MAC_TX_STATS_PKTS_256_511 0x11 /* enum */
	+#define MC_CMD_FC_MAC_TX_STATS_PKTS_512_1023 0x12 /* enum */
	+#define MC_CMD_FC_MAC_TX_STATS_PKTS_1024_1518 0x13 /* enum */
	+#define MC_CMD_FC_MAC_TX_STATS_PKTS_1519_TX_MTU 0x14 /* enum */
	+#define MC_CMD_FC_MAC_TX_MAC_CONTROL_FRAMES 0x15 /* enum */
	/* enum: (Last entry) */
	-#define MC_CMD_FC_MAC_TX_NSTATS 0x16
	+#define MC_CMD_FC_MAC_TX_NSTATS 0x16

	/* MC_CMD_FC_OUT_MAC_GET_STATS msgresponse */
	#define MC_CMD_FC_OUT_MAC_GET_STATS_LEN ((((0-1+(64*MC_CMD_FC_MAC_NSTATS_PER_BLOCK))+1))>>3)
	@@ -1812,17 +1813,17 @@
	/* Options for the map */
	#define MC_CMD_FC_OUT_READ_MAP_INDEX_OPTIONS_OFST 4
	#define MC_CMD_FC_OUT_READ_MAP_INDEX_OPTIONS_LEN 4
	-#define MC_CMD_FC_OUT_READ_MAP_INDEX_ALIGN_8 0x0 /* enum */
	-#define MC_CMD_FC_OUT_READ_MAP_INDEX_ALIGN_16 0x1 /* enum */
	-#define MC_CMD_FC_OUT_READ_MAP_INDEX_ALIGN_32 0x2 /* enum */
	-#define MC_CMD_FC_OUT_READ_MAP_INDEX_ALIGN_64 0x3 /* enum */
	-#define MC_CMD_FC_OUT_READ_MAP_INDEX_ALIGN_MASK 0x3 /* enum */
	-#define MC_CMD_FC_OUT_READ_MAP_INDEX_PATH_FC 0x4 /* enum */
	-#define MC_CMD_FC_OUT_READ_MAP_INDEX_PATH_MEM 0x8 /* enum */
	-#define MC_CMD_FC_OUT_READ_MAP_INDEX_PERM_READ 0x10 /* enum */
	-#define MC_CMD_FC_OUT_READ_MAP_INDEX_PERM_WRITE 0x20 /* enum */
	-#define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_FREE 0x0 /* enum */
	-#define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_LICENSED 0x40 /* enum */
	+#define MC_CMD_FC_OUT_READ_MAP_INDEX_ALIGN_8 0x0 /* enum */
	+#define MC_CMD_FC_OUT_READ_MAP_INDEX_ALIGN_16 0x1 /* enum */
	+#define MC_CMD_FC_OUT_READ_MAP_INDEX_ALIGN_32 0x2 /* enum */
	+#define MC_CMD_FC_OUT_READ_MAP_INDEX_ALIGN_64 0x3 /* enum */
	+#define MC_CMD_FC_OUT_READ_MAP_INDEX_ALIGN_MASK 0x3 /* enum */
	+#define MC_CMD_FC_OUT_READ_MAP_INDEX_PATH_FC 0x4 /* enum */
	+#define MC_CMD_FC_OUT_READ_MAP_INDEX_PATH_MEM 0x8 /* enum */
	+#define MC_CMD_FC_OUT_READ_MAP_INDEX_PERM_READ 0x10 /* enum */
	+#define MC_CMD_FC_OUT_READ_MAP_INDEX_PERM_WRITE 0x20 /* enum */
	+#define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_FREE 0x0 /* enum */
	+#define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_LICENSED 0x40 /* enum */
	/* Address of start of map */
	#define MC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_OFST 8
	#define MC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_LEN 8
	@@ -2346,21 +2347,21 @@
	#define MC_CMD_AOE_IN_POWER_OP_OFST 4
	#define MC_CMD_AOE_IN_POWER_OP_LEN 4
	/* enum: Turn off FPGA power */
	-#define MC_CMD_AOE_IN_POWER_OFF 0x0
	+#define MC_CMD_AOE_IN_POWER_OFF 0x0
	/* enum: Turn on FPGA power */
	-#define MC_CMD_AOE_IN_POWER_ON 0x1
	+#define MC_CMD_AOE_IN_POWER_ON 0x1
	/* enum: Clear peak power measurement */
	-#define MC_CMD_AOE_IN_POWER_CLEAR 0x2
	+#define MC_CMD_AOE_IN_POWER_CLEAR 0x2
	/* enum: Show current power in sensors output */
	-#define MC_CMD_AOE_IN_POWER_SHOW_CURRENT 0x3
	+#define MC_CMD_AOE_IN_POWER_SHOW_CURRENT 0x3
	/* enum: Show peak power in sensors output */
	-#define MC_CMD_AOE_IN_POWER_SHOW_PEAK 0x4
	+#define MC_CMD_AOE_IN_POWER_SHOW_PEAK 0x4
	/* enum: Show current DDR current */
	-#define MC_CMD_AOE_IN_POWER_DDR_LAST 0x5
	+#define MC_CMD_AOE_IN_POWER_DDR_LAST 0x5
	/* enum: Show peak DDR current */
	-#define MC_CMD_AOE_IN_POWER_DDR_PEAK 0x6
	+#define MC_CMD_AOE_IN_POWER_DDR_PEAK 0x6
	/* enum: Clear peak DDR current */
	-#define MC_CMD_AOE_IN_POWER_DDR_CLEAR 0x7
	+#define MC_CMD_AOE_IN_POWER_DDR_CLEAR 0x7

	/* MC_CMD_AOE_IN_LOAD msgrequest */
	#define MC_CMD_AOE_IN_LOAD_LEN 8
	@@ -2475,21 +2476,21 @@
	#define MC_CMD_AOE_IN_LINK_STATE_CONFIG_MODE_LBN 0
	#define MC_CMD_AOE_IN_LINK_STATE_CONFIG_MODE_WIDTH 8
	/* enum: AOE and associated external port */
	-#define MC_CMD_AOE_IN_LINK_STATE_SIMPLE_SEPARATE 0x0
	+#define MC_CMD_AOE_IN_LINK_STATE_SIMPLE_SEPARATE 0x0
	/* enum: AOE and OR of all external ports */
	-#define MC_CMD_AOE_IN_LINK_STATE_SIMPLE_COMBINED 0x1
	+#define MC_CMD_AOE_IN_LINK_STATE_SIMPLE_COMBINED 0x1
	/* enum: Individual ports */
	-#define MC_CMD_AOE_IN_LINK_STATE_DIAGNOSTIC 0x2
	+#define MC_CMD_AOE_IN_LINK_STATE_DIAGNOSTIC 0x2
	/* enum: Configure link state mode on given AOE port */
	-#define MC_CMD_AOE_IN_LINK_STATE_CUSTOM 0x3
	+#define MC_CMD_AOE_IN_LINK_STATE_CUSTOM 0x3
	#define MC_CMD_AOE_IN_LINK_STATE_OPERATION_LBN 8
	#define MC_CMD_AOE_IN_LINK_STATE_OPERATION_WIDTH 8
	/* enum: No-op */
	-#define MC_CMD_AOE_IN_LINK_STATE_OP_NONE 0x0
	+#define MC_CMD_AOE_IN_LINK_STATE_OP_NONE 0x0
	/* enum: logical OR of all SFP ports link status */
	-#define MC_CMD_AOE_IN_LINK_STATE_OP_OR 0x1
	+#define MC_CMD_AOE_IN_LINK_STATE_OP_OR 0x1
	/* enum: logical AND of all SFP ports link status */
	-#define MC_CMD_AOE_IN_LINK_STATE_OP_AND 0x2
	+#define MC_CMD_AOE_IN_LINK_STATE_OP_AND 0x2
	#define MC_CMD_AOE_IN_LINK_STATE_SFP_MASK_LBN 16
	#define MC_CMD_AOE_IN_LINK_STATE_SFP_MASK_WIDTH 16

	@@ -2511,9 +2512,9 @@
	#define MC_CMD_AOE_IN_SIENA_STATS_MODE_OFST 4
	#define MC_CMD_AOE_IN_SIENA_STATS_MODE_LEN 4
	/* enum: Statistics from Siena (default) */
	-#define MC_CMD_AOE_IN_SIENA_STATS_STATS_SIENA 0x0
	+#define MC_CMD_AOE_IN_SIENA_STATS_STATS_SIENA 0x0
	/* enum: Statistics from AOE external ports */
	-#define MC_CMD_AOE_IN_SIENA_STATS_STATS_AOE 0x1
	+#define MC_CMD_AOE_IN_SIENA_STATS_STATS_AOE 0x1

	/* MC_CMD_AOE_IN_ASIC_STATS msgrequest */
	#define MC_CMD_AOE_IN_ASIC_STATS_LEN 8
	@@ -2523,9 +2524,9 @@
	#define MC_CMD_AOE_IN_ASIC_STATS_MODE_OFST 4
	#define MC_CMD_AOE_IN_ASIC_STATS_MODE_LEN 4
	/* enum: Statistics from the ASIC (default) */
	-#define MC_CMD_AOE_IN_ASIC_STATS_STATS_ASIC 0x0
	+#define MC_CMD_AOE_IN_ASIC_STATS_STATS_ASIC 0x0
	/* enum: Statistics from AOE external ports */
	-#define MC_CMD_AOE_IN_ASIC_STATS_STATS_AOE 0x1
	+#define MC_CMD_AOE_IN_ASIC_STATS_STATS_AOE 0x1

	/* MC_CMD_AOE_IN_DDR msgrequest */
	#define MC_CMD_AOE_IN_DDR_LEN 12
	@@ -2650,8 +2651,8 @@
	/* FPGA type - read from CPLD straps */
	#define MC_CMD_AOE_OUT_INFO_FPGA_TYPE_OFST 16
	#define MC_CMD_AOE_OUT_INFO_FPGA_TYPE_LEN 4
	-#define MC_CMD_AOE_OUT_INFO_FPGA_TYPE_A5_C2 0x1 /* enum */
	-#define MC_CMD_AOE_OUT_INFO_FPGA_TYPE_A7_C2 0x2 /* enum */
	+#define MC_CMD_AOE_OUT_INFO_FPGA_TYPE_A5_C2 0x1 /* enum */
	+#define MC_CMD_AOE_OUT_INFO_FPGA_TYPE_A7_C2 0x2 /* enum */
	/* FPGA state (debug) */
	#define MC_CMD_AOE_OUT_INFO_FPGA_STATE_OFST 20
	#define MC_CMD_AOE_OUT_INFO_FPGA_STATE_LEN 4
	@@ -2669,29 +2670,29 @@
	#define MC_CMD_AOE_OUT_INFO_FLAGS_OFST 32
	#define MC_CMD_AOE_OUT_INFO_FLAGS_LEN 4
	/* enum: Power to FPGA supplied by PEG connector, not PCIe bus */
	-#define MC_CMD_AOE_OUT_INFO_PEG_POWER 0x1
	+#define MC_CMD_AOE_OUT_INFO_PEG_POWER 0x1
	/* enum: CPLD apparently good */
	-#define MC_CMD_AOE_OUT_INFO_CPLD_GOOD 0x2
	+#define MC_CMD_AOE_OUT_INFO_CPLD_GOOD 0x2
	/* enum: FPGA working normally */
	-#define MC_CMD_AOE_OUT_INFO_FPGA_GOOD 0x4
	+#define MC_CMD_AOE_OUT_INFO_FPGA_GOOD 0x4
	/* enum: FPGA is powered */
	-#define MC_CMD_AOE_OUT_INFO_FPGA_POWER 0x8
	+#define MC_CMD_AOE_OUT_INFO_FPGA_POWER 0x8
	/* enum: Board has incompatible SODIMMs fitted */
	-#define MC_CMD_AOE_OUT_INFO_BAD_SODIMM 0x10
	+#define MC_CMD_AOE_OUT_INFO_BAD_SODIMM 0x10
	/* enum: Board has ByteBlaster connected */
	-#define MC_CMD_AOE_OUT_INFO_HAS_BYTEBLASTER 0x20
	+#define MC_CMD_AOE_OUT_INFO_HAS_BYTEBLASTER 0x20
	/* enum: FPGA Boot flash has an invalid header. */
	-#define MC_CMD_AOE_OUT_INFO_FPGA_BAD_BOOT_HDR 0x40
	+#define MC_CMD_AOE_OUT_INFO_FPGA_BAD_BOOT_HDR 0x40
	/* enum: FPGA Application flash is accessible. */
	-#define MC_CMD_AOE_OUT_INFO_FPGA_APP_FLASH_GOOD 0x80
	+#define MC_CMD_AOE_OUT_INFO_FPGA_APP_FLASH_GOOD 0x80
	/* Revision of Modena and Sorrento boards. Sorrento can be R1_2 or R1_3. */
	#define MC_CMD_AOE_OUT_INFO_BOARD_REVISION_OFST 36
	#define MC_CMD_AOE_OUT_INFO_BOARD_REVISION_LEN 4
	-#define MC_CMD_AOE_OUT_INFO_UNKNOWN 0x0 /* enum */
	-#define MC_CMD_AOE_OUT_INFO_R1_0 0x10 /* enum */
	-#define MC_CMD_AOE_OUT_INFO_R1_1 0x11 /* enum */
	-#define MC_CMD_AOE_OUT_INFO_R1_2 0x12 /* enum */
	-#define MC_CMD_AOE_OUT_INFO_R1_3 0x13 /* enum */
	+#define MC_CMD_AOE_OUT_INFO_UNKNOWN 0x0 /* enum */
	+#define MC_CMD_AOE_OUT_INFO_R1_0 0x10 /* enum */
	+#define MC_CMD_AOE_OUT_INFO_R1_1 0x11 /* enum */
	+#define MC_CMD_AOE_OUT_INFO_R1_2 0x12 /* enum */
	+#define MC_CMD_AOE_OUT_INFO_R1_3 0x13 /* enum */
	/* Result of FC booting - not valid while a ByteBlaster is connected. */
	#define MC_CMD_AOE_OUT_INFO_FC_BOOT_RESULT_OFST 40
	#define MC_CMD_AOE_OUT_INFO_FC_BOOT_RESULT_LEN 4

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