D55081.1793645365.diff
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	diff --git a/lib/libpmc/pmu-events/arch/x86/graniterapids/cache.json b/lib/libpmc/pmu-events/arch/x86/graniterapids/cache.json
	new file mode 100644
	--- /dev/null
	+++ b/lib/libpmc/pmu-events/arch/x86/graniterapids/cache.json
	@@ -0,0 +1,1230 @@
	+[
	+ {
	+ "BriefDescription": "L1D.HWPF_MISS",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x51",
	+ "EventName": "L1D.HWPF_MISS",
	+ "SampleAfterValue": "1000003",
	+ "UMask": "0x20"
	+ },
	+ {
	+ "BriefDescription": "Counts the number of cache lines replaced in L1 data cache.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x51",
	+ "EventName": "L1D.REPLACEMENT",
	+ "PublicDescription": "Counts L1D data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x1"
	+ },
	+ {
	+ "BriefDescription": "Number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailability.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x48",
	+ "EventName": "L1D_PEND_MISS.FB_FULL",
	+ "PublicDescription": "Counts number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.",
	+ "SampleAfterValue": "1000003",
	+ "UMask": "0x2"
	+ },
	+ {
	+ "BriefDescription": "Number of phases a demand request has waited due to L1D Fill Buffer (FB) unavailability.",
	+ "Counter": "0,1,2,3",
	+ "CounterMask": "1",
	+ "EdgeDetect": "1",
	+ "EventCode": "0x48",
	+ "EventName": "L1D_PEND_MISS.FB_FULL_PERIODS",
	+ "PublicDescription": "Counts number of phases a demand request has waited due to L1D Fill Buffer (FB) unavailability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.",
	+ "SampleAfterValue": "1000003",
	+ "UMask": "0x2"
	+ },
	+ {
	+ "BriefDescription": "Number of cycles a demand request has waited due to L1D due to lack of L2 resources.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x48",
	+ "EventName": "L1D_PEND_MISS.L2_STALLS",
	+ "PublicDescription": "Counts number of cycles a demand request has waited due to L1D due to lack of L2 resources. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.",
	+ "SampleAfterValue": "1000003",
	+ "UMask": "0x4"
	+ },
	+ {
	+ "BriefDescription": "Number of L1D misses that are outstanding",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x48",
	+ "EventName": "L1D_PEND_MISS.PENDING",
	+ "PublicDescription": "Counts number of L1D misses that are outstanding in each cycle, that is each cycle the number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand from the demand Hit FB, if it is allocated by hardware or software prefetch. Note: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type.",
	+ "SampleAfterValue": "1000003",
	+ "UMask": "0x1"
	+ },
	+ {
	+ "BriefDescription": "Cycles with L1D load Misses outstanding.",
	+ "Counter": "0,1,2,3",
	+ "CounterMask": "1",
	+ "EventCode": "0x48",
	+ "EventName": "L1D_PEND_MISS.PENDING_CYCLES",
	+ "PublicDescription": "Counts duration of L1D miss outstanding in cycles.",
	+ "SampleAfterValue": "1000003",
	+ "UMask": "0x1"
	+ },
	+ {
	+ "BriefDescription": "L2 cache lines filling L2",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x25",
	+ "EventName": "L2_LINES_IN.ALL",
	+ "PublicDescription": "Counts the number of L2 cache lines filling the L2. Counting does not cover rejects.",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x1f"
	+ },
	+ {
	+ "BriefDescription": "Modified cache lines that are evicted by L2 cache when triggered by an L2 cache fill.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x26",
	+ "EventName": "L2_LINES_OUT.NON_SILENT",
	+ "PublicDescription": "Counts the number of lines that are evicted by L2 cache when triggered by an L2 cache fill. Those lines are in Modified state. Modified lines are written back to L3",
	+ "SampleAfterValue": "200003",
	+ "UMask": "0x2"
	+ },
	+ {
	+ "BriefDescription": "Non-modified cache lines that are silently dropped by L2 cache.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x26",
	+ "EventName": "L2_LINES_OUT.SILENT",
	+ "PublicDescription": "Counts the number of lines that are silently dropped by L2 cache. These lines are typically in Shared or Exclusive state. A non-threaded event.",
	+ "SampleAfterValue": "200003",
	+ "UMask": "0x1"
	+ },
	+ {
	+ "BriefDescription": "Cache lines that have been L2 hardware prefetched but not used by demand accesses",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x26",
	+ "EventName": "L2_LINES_OUT.USELESS_HWPF",
	+ "PublicDescription": "Counts the number of cache lines that have been prefetched by the L2 hardware prefetcher but not used by demand access when evicted from the L2 cache",
	+ "SampleAfterValue": "200003",
	+ "UMask": "0x4"
	+ },
	+ {
	+ "BriefDescription": "All accesses to L2 cache [This event is alias to L2_RQSTS.REFERENCES]",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x24",
	+ "EventName": "L2_REQUEST.ALL",
	+ "PublicDescription": "Counts all requests that were hit or true misses in L2 cache. True-miss excludes misses that were merged with ongoing L2 misses. [This event is alias to L2_RQSTS.REFERENCES]",
	+ "SampleAfterValue": "200003",
	+ "UMask": "0xff"
	+ },
	+ {
	+ "BriefDescription": "All requests that hit L2 cache. [This event is alias to L2_RQSTS.HIT]",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x24",
	+ "EventName": "L2_REQUEST.HIT",
	+ "PublicDescription": "Counts all requests that hit L2 cache. [This event is alias to L2_RQSTS.HIT]",
	+ "SampleAfterValue": "200003",
	+ "UMask": "0xdf"
	+ },
	+ {
	+ "BriefDescription": "Read requests with true-miss in L2 cache [This event is alias to L2_RQSTS.MISS]",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x24",
	+ "EventName": "L2_REQUEST.MISS",
	+ "PublicDescription": "Counts read requests of any type with true-miss in the L2 cache. True-miss excludes L2 misses that were merged with ongoing L2 misses. [This event is alias to L2_RQSTS.MISS]",
	+ "SampleAfterValue": "200003",
	+ "UMask": "0x3f"
	+ },
	+ {
	+ "BriefDescription": "L2 code requests",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x24",
	+ "EventName": "L2_RQSTS.ALL_CODE_RD",
	+ "PublicDescription": "Counts the total number of L2 code requests.",
	+ "SampleAfterValue": "200003",
	+ "UMask": "0xe4"
	+ },
	+ {
	+ "BriefDescription": "Demand Data Read access L2 cache",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x24",
	+ "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD",
	+ "PublicDescription": "Counts Demand Data Read requests accessing the L2 cache. These requests may hit or miss L2 cache. True-miss exclude misses that were merged with ongoing L2 misses. An access is counted once.",
	+ "SampleAfterValue": "200003",
	+ "UMask": "0xe1"
	+ },
	+ {
	+ "BriefDescription": "Demand requests that miss L2 cache",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x24",
	+ "EventName": "L2_RQSTS.ALL_DEMAND_MISS",
	+ "PublicDescription": "Counts demand requests that miss L2 cache.",
	+ "SampleAfterValue": "200003",
	+ "UMask": "0x27"
	+ },
	+ {
	+ "BriefDescription": "Demand requests to L2 cache",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x24",
	+ "EventName": "L2_RQSTS.ALL_DEMAND_REFERENCES",
	+ "PublicDescription": "Counts demand requests to L2 cache.",
	+ "SampleAfterValue": "200003",
	+ "UMask": "0xe7"
	+ },
	+ {
	+ "BriefDescription": "L2_RQSTS.ALL_HWPF",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x24",
	+ "EventName": "L2_RQSTS.ALL_HWPF",
	+ "SampleAfterValue": "200003",
	+ "UMask": "0xf0"
	+ },
	+ {
	+ "BriefDescription": "RFO requests to L2 cache",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x24",
	+ "EventName": "L2_RQSTS.ALL_RFO",
	+ "PublicDescription": "Counts the total number of RFO (read for ownership) requests to L2 cache. L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetches.",
	+ "SampleAfterValue": "200003",
	+ "UMask": "0xe2"
	+ },
	+ {
	+ "BriefDescription": "L2 cache hits when fetching instructions, code reads.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x24",
	+ "EventName": "L2_RQSTS.CODE_RD_HIT",
	+ "PublicDescription": "Counts L2 cache hits when fetching instructions, code reads.",
	+ "SampleAfterValue": "200003",
	+ "UMask": "0xc4"
	+ },
	+ {
	+ "BriefDescription": "L2 cache misses when fetching instructions",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x24",
	+ "EventName": "L2_RQSTS.CODE_RD_MISS",
	+ "PublicDescription": "Counts L2 cache misses when fetching instructions.",
	+ "SampleAfterValue": "200003",
	+ "UMask": "0x24"
	+ },
	+ {
	+ "BriefDescription": "Demand Data Read requests that hit L2 cache",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x24",
	+ "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT",
	+ "PublicDescription": "Counts the number of demand Data Read requests initiated by load instructions that hit L2 cache.",
	+ "SampleAfterValue": "200003",
	+ "UMask": "0xc1"
	+ },
	+ {
	+ "BriefDescription": "Demand Data Read miss L2 cache",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x24",
	+ "EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS",
	+ "PublicDescription": "Counts demand Data Read requests with true-miss in the L2 cache. True-miss excludes misses that were merged with ongoing L2 misses. An access is counted once.",
	+ "SampleAfterValue": "200003",
	+ "UMask": "0x21"
	+ },
	+ {
	+ "BriefDescription": "All requests that hit L2 cache. [This event is alias to L2_REQUEST.HIT]",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x24",
	+ "EventName": "L2_RQSTS.HIT",
	+ "PublicDescription": "Counts all requests that hit L2 cache. [This event is alias to L2_REQUEST.HIT]",
	+ "SampleAfterValue": "200003",
	+ "UMask": "0xdf"
	+ },
	+ {
	+ "BriefDescription": "L2_RQSTS.HWPF_MISS",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x24",
	+ "EventName": "L2_RQSTS.HWPF_MISS",
	+ "SampleAfterValue": "200003",
	+ "UMask": "0x30"
	+ },
	+ {
	+ "BriefDescription": "Read requests with true-miss in L2 cache [This event is alias to L2_REQUEST.MISS]",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x24",
	+ "EventName": "L2_RQSTS.MISS",
	+ "PublicDescription": "Counts read requests of any type with true-miss in the L2 cache. True-miss excludes L2 misses that were merged with ongoing L2 misses. [This event is alias to L2_REQUEST.MISS]",
	+ "SampleAfterValue": "200003",
	+ "UMask": "0x3f"
	+ },
	+ {
	+ "BriefDescription": "All accesses to L2 cache [This event is alias to L2_REQUEST.ALL]",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x24",
	+ "EventName": "L2_RQSTS.REFERENCES",
	+ "PublicDescription": "Counts all requests that were hit or true misses in L2 cache. True-miss excludes misses that were merged with ongoing L2 misses. [This event is alias to L2_REQUEST.ALL]",
	+ "SampleAfterValue": "200003",
	+ "UMask": "0xff"
	+ },
	+ {
	+ "BriefDescription": "RFO requests that hit L2 cache",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x24",
	+ "EventName": "L2_RQSTS.RFO_HIT",
	+ "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that hit L2 cache.",
	+ "SampleAfterValue": "200003",
	+ "UMask": "0xc2"
	+ },
	+ {
	+ "BriefDescription": "RFO requests that miss L2 cache",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x24",
	+ "EventName": "L2_RQSTS.RFO_MISS",
	+ "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that miss L2 cache.",
	+ "SampleAfterValue": "200003",
	+ "UMask": "0x22"
	+ },
	+ {
	+ "BriefDescription": "SW prefetch requests that hit L2 cache.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x24",
	+ "EventName": "L2_RQSTS.SWPF_HIT",
	+ "PublicDescription": "Counts Software prefetch requests that hit the L2 cache. Accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions when FB is not full.",
	+ "SampleAfterValue": "200003",
	+ "UMask": "0xc8"
	+ },
	+ {
	+ "BriefDescription": "SW prefetch requests that miss L2 cache.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x24",
	+ "EventName": "L2_RQSTS.SWPF_MISS",
	+ "PublicDescription": "Counts Software prefetch requests that miss the L2 cache. Accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions when FB is not full.",
	+ "SampleAfterValue": "200003",
	+ "UMask": "0x28"
	+ },
	+ {
	+ "BriefDescription": "L2 writebacks that access L2 cache",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x23",
	+ "EventName": "L2_TRANS.L2_WB",
	+ "PublicDescription": "Counts L2 writebacks that access L2 cache.",
	+ "SampleAfterValue": "200003",
	+ "UMask": "0x40"
	+ },
	+ {
	+ "BriefDescription": "Core-originated cacheable requests that missed L3 (Except hardware prefetches to the L3)",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0x2e",
	+ "EventName": "LONGEST_LAT_CACHE.MISS",
	+ "PublicDescription": "Counts core-originated cacheable requests that miss the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches to the L1 and L2. It does not include hardware prefetches to the L3, and may not count other types of requests to the L3.",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x41"
	+ },
	+ {
	+ "BriefDescription": "Core-originated cacheable requests that refer to L3 (Except hardware prefetches to the L3)",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0x2e",
	+ "EventName": "LONGEST_LAT_CACHE.REFERENCE",
	+ "PublicDescription": "Counts core-originated cacheable requests to the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches to the L1 and L2. It does not include hardware prefetches to the L3, and may not count other types of requests to the L3.",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x4f"
	+ },
	+ {
	+ "BriefDescription": "Retired load instructions.",
	+ "Counter": "0,1,2,3",
	+ "Data_LA": "1",
	+ "EventCode": "0xd0",
	+ "EventName": "MEM_INST_RETIRED.ALL_LOADS",
	+ "PublicDescription": "Counts all retired load instructions. This event accounts for SW prefetch instructions of PREFETCHNTA or PREFETCHT0/1/2 or PREFETCHW. Available PDIST counters: 0",
	+ "SampleAfterValue": "1000003",
	+ "UMask": "0x81"
	+ },
	+ {
	+ "BriefDescription": "Retired store instructions.",
	+ "Counter": "0,1,2,3",
	+ "Data_LA": "1",
	+ "EventCode": "0xd0",
	+ "EventName": "MEM_INST_RETIRED.ALL_STORES",
	+ "PublicDescription": "Counts all retired store instructions. Available PDIST counters: 0",
	+ "SampleAfterValue": "1000003",
	+ "UMask": "0x82"
	+ },
	+ {
	+ "BriefDescription": "All retired memory instructions.",
	+ "Counter": "0,1,2,3",
	+ "Data_LA": "1",
	+ "EventCode": "0xd0",
	+ "EventName": "MEM_INST_RETIRED.ANY",
	+ "PublicDescription": "Counts all retired memory instructions - loads and stores. Available PDIST counters: 0",
	+ "SampleAfterValue": "1000003",
	+ "UMask": "0x83"
	+ },
	+ {
	+ "BriefDescription": "Retired load instructions with locked access.",
	+ "Counter": "0,1,2,3",
	+ "Data_LA": "1",
	+ "EventCode": "0xd0",
	+ "EventName": "MEM_INST_RETIRED.LOCK_LOADS",
	+ "PublicDescription": "Counts retired load instructions with locked access. Available PDIST counters: 0",
	+ "RetirementLatencyMax": "5156",
	+ "RetirementLatencyMean": "63.76",
	+ "RetirementLatencyMin": "15",
	+ "SampleAfterValue": "100007",
	+ "UMask": "0x21"
	+ },
	+ {
	+ "BriefDescription": "Retired load instructions that split across a cacheline boundary.",
	+ "Counter": "0,1,2,3",
	+ "Data_LA": "1",
	+ "EventCode": "0xd0",
	+ "EventName": "MEM_INST_RETIRED.SPLIT_LOADS",
	+ "PublicDescription": "Counts retired load instructions that split across a cacheline boundary. Available PDIST counters: 0",
	+ "RetirementLatencyMax": "4704",
	+ "RetirementLatencyMean": "3.97",
	+ "RetirementLatencyMin": "0",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x41"
	+ },
	+ {
	+ "BriefDescription": "Retired store instructions that split across a cacheline boundary.",
	+ "Counter": "0,1,2,3",
	+ "Data_LA": "1",
	+ "EventCode": "0xd0",
	+ "EventName": "MEM_INST_RETIRED.SPLIT_STORES",
	+ "PublicDescription": "Counts retired store instructions that split across a cacheline boundary. Available PDIST counters: 0",
	+ "RetirementLatencyMax": "65535",
	+ "RetirementLatencyMean": "19.0",
	+ "RetirementLatencyMin": "0",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x42"
	+ },
	+ {
	+ "BriefDescription": "Retired load instructions that hit the STLB.",
	+ "Counter": "0,1,2,3",
	+ "Data_LA": "1",
	+ "EventCode": "0xd0",
	+ "EventName": "MEM_INST_RETIRED.STLB_HIT_LOADS",
	+ "PublicDescription": "Number of retired load instructions with a clean hit in the 2nd-level TLB (STLB). Available PDIST counters: 0",
	+ "RetirementLatencyMax": "3424",
	+ "RetirementLatencyMean": "1.57",
	+ "RetirementLatencyMin": "0",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x9"
	+ },
	+ {
	+ "BriefDescription": "Retired store instructions that hit the STLB.",
	+ "Counter": "0,1,2,3",
	+ "Data_LA": "1",
	+ "EventCode": "0xd0",
	+ "EventName": "MEM_INST_RETIRED.STLB_HIT_STORES",
	+ "PublicDescription": "Number of retired store instructions that hit in the 2nd-level TLB (STLB). Available PDIST counters: 0",
	+ "RetirementLatencyMax": "65535",
	+ "RetirementLatencyMean": "5.24",
	+ "RetirementLatencyMin": "0",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0xa"
	+ },
	+ {
	+ "BriefDescription": "Retired load instructions that miss the STLB.",
	+ "Counter": "0,1,2,3",
	+ "Data_LA": "1",
	+ "EventCode": "0xd0",
	+ "EventName": "MEM_INST_RETIRED.STLB_MISS_LOADS",
	+ "PublicDescription": "Number of retired load instructions that (start a) miss in the 2nd-level TLB (STLB). Available PDIST counters: 0",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x11"
	+ },
	+ {
	+ "BriefDescription": "Retired store instructions that miss the STLB.",
	+ "Counter": "0,1,2,3",
	+ "Data_LA": "1",
	+ "EventCode": "0xd0",
	+ "EventName": "MEM_INST_RETIRED.STLB_MISS_STORES",
	+ "PublicDescription": "Number of retired store instructions that (start a) miss in the 2nd-level TLB (STLB). Available PDIST counters: 0",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x12"
	+ },
	+ {
	+ "BriefDescription": "Completed demand load uops that miss the L1 d-cache.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x43",
	+ "EventName": "MEM_LOAD_COMPLETED.L1_MISS_ANY",
	+ "PublicDescription": "Number of completed demand load requests that missed the L1 data cache including shadow misses (FB hits, merge to an ongoing L1D miss)",
	+ "SampleAfterValue": "1000003",
	+ "UMask": "0xfd"
	+ },
	+ {
	+ "BriefDescription": "Retired load instructions whose data sources were HitM responses from shared L3",
	+ "Counter": "0,1,2,3",
	+ "Data_LA": "1",
	+ "EventCode": "0xd2",
	+ "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD",
	+ "PublicDescription": "Counts retired load instructions whose data sources were HitM responses from shared L3. Available PDIST counters: 0",
	+ "RetirementLatencyMax": "4472",
	+ "RetirementLatencyMean": "353.04",
	+ "RetirementLatencyMin": "0",
	+ "SampleAfterValue": "20011",
	+ "UMask": "0x4"
	+ },
	+ {
	+ "BriefDescription": "Retired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core cache.",
	+ "Counter": "0,1,2,3",
	+ "Data_LA": "1",
	+ "EventCode": "0xd2",
	+ "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS",
	+ "PublicDescription": "Counts the retired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core cache. Available PDIST counters: 0",
	+ "RetirementLatencyMax": "830",
	+ "RetirementLatencyMean": "125.27",
	+ "RetirementLatencyMin": "0",
	+ "SampleAfterValue": "20011",
	+ "UMask": "0x1"
	+ },
	+ {
	+ "BriefDescription": "Retired load instructions whose data sources were hits in L3 without snoops required",
	+ "Counter": "0,1,2,3",
	+ "Data_LA": "1",
	+ "EventCode": "0xd2",
	+ "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NONE",
	+ "PublicDescription": "Counts retired load instructions whose data sources were hits in L3 without snoops required. Available PDIST counters: 0",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x8"
	+ },
	+ {
	+ "BriefDescription": "Retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache",
	+ "Counter": "0,1,2,3",
	+ "Data_LA": "1",
	+ "EventCode": "0xd2",
	+ "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD",
	+ "PublicDescription": "Counts retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache. Available PDIST counters: 0",
	+ "RetirementLatencyMax": "3939",
	+ "RetirementLatencyMean": "289.9",
	+ "RetirementLatencyMin": "0",
	+ "SampleAfterValue": "20011",
	+ "UMask": "0x2"
	+ },
	+ {
	+ "BriefDescription": "Retired load instructions which data sources missed L3 but serviced from dram homed in the local socket",
	+ "Counter": "0,1,2,3",
	+ "Data_LA": "1",
	+ "EventCode": "0xd3",
	+ "EventName": "MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM",
	+ "PublicDescription": "Retired load instructions which data sources missed L3 but serviced from DRAM homed in the local socket. Available PDIST counters: 0",
	+ "RetirementLatencyMax": "4146",
	+ "RetirementLatencyMean": "115.83",
	+ "RetirementLatencyMin": "0",
	+ "SampleAfterValue": "100007",
	+ "UMask": "0x1"
	+ },
	+ {
	+ "BriefDescription": "Retired load instructions with remote cxl mem as the data source where the data request missed all caches.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0xd3",
	+ "EventName": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_CXL_MEM",
	+ "PublicDescription": "Counts retired load instructions with remote cxl mem as the data source and the data request missed L3. Available PDIST counters: 0",
	+ "SampleAfterValue": "100007",
	+ "UMask": "0x10"
	+ },
	+ {
	+ "BriefDescription": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM",
	+ "Counter": "0,1,2,3",
	+ "Data_LA": "1",
	+ "EventCode": "0xd3",
	+ "EventName": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM",
	+ "PublicDescription": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM Available PDIST counters: 0",
	+ "RetirementLatencyMax": "3572",
	+ "RetirementLatencyMean": "430.22",
	+ "RetirementLatencyMin": "0",
	+ "SampleAfterValue": "1000003",
	+ "UMask": "0x2"
	+ },
	+ {
	+ "BriefDescription": "Retired load instructions whose data sources was forwarded from a remote cache",
	+ "Counter": "0,1,2,3",
	+ "Data_LA": "1",
	+ "EventCode": "0xd3",
	+ "EventName": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD",
	+ "PublicDescription": "Retired load instructions whose data sources was forwarded from a remote cache. Available PDIST counters: 0",
	+ "RetirementLatencyMax": "8552",
	+ "RetirementLatencyMean": "125.36",
	+ "RetirementLatencyMin": "0",
	+ "SampleAfterValue": "100007",
	+ "UMask": "0x8"
	+ },
	+ {
	+ "BriefDescription": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM",
	+ "Counter": "0,1,2,3",
	+ "Data_LA": "1",
	+ "EventCode": "0xd3",
	+ "EventName": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM",
	+ "PublicDescription": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM Available PDIST counters: 0",
	+ "RetirementLatencyMax": "2580",
	+ "RetirementLatencyMean": "135.29",
	+ "RetirementLatencyMin": "0",
	+ "SampleAfterValue": "1000003",
	+ "UMask": "0x4"
	+ },
	+ {
	+ "BriefDescription": "Retired instructions with at least 1 uncacheable load or lock.",
	+ "Counter": "0,1,2,3",
	+ "Data_LA": "1",
	+ "EventCode": "0xd4",
	+ "EventName": "MEM_LOAD_MISC_RETIRED.UC",
	+ "PublicDescription": "Retired instructions with at least one load to uncacheable memory-type, or at least one cache-line split locked access (Bus Lock). Available PDIST counters: 0",
	+ "SampleAfterValue": "100007",
	+ "UMask": "0x4"
	+ },
	+ {
	+ "BriefDescription": "Number of completed demand load requests that missed the L1, but hit the FB(fill buffer), because a preceding miss to the same cacheline initiated the line to be brought into L1, but data is not yet ready in L1.",
	+ "Counter": "0,1,2,3",
	+ "Data_LA": "1",
	+ "EventCode": "0xd1",
	+ "EventName": "MEM_LOAD_RETIRED.FB_HIT",
	+ "PublicDescription": "Counts retired load instructions with at least one uop was load missed in L1 but hit FB (Fill Buffers) due to preceding miss to the same cache line with data not ready. Available PDIST counters: 0",
	+ "SampleAfterValue": "100007",
	+ "UMask": "0x40"
	+ },
	+ {
	+ "BriefDescription": "Retired load instructions with L1 cache hits as data sources",
	+ "Counter": "0,1,2,3",
	+ "Data_LA": "1",
	+ "EventCode": "0xd1",
	+ "EventName": "MEM_LOAD_RETIRED.L1_HIT",
	+ "PublicDescription": "Counts retired load instructions with at least one uop that hit in the L1 data cache. This event includes all SW prefetches and lock instructions regardless of the data source. Available PDIST counters: 0",
	+ "SampleAfterValue": "1000003",
	+ "UMask": "0x1"
	+ },
	+ {
	+ "BriefDescription": "Retired load instructions missed L1 cache as data sources",
	+ "Counter": "0,1,2,3",
	+ "Data_LA": "1",
	+ "EventCode": "0xd1",
	+ "EventName": "MEM_LOAD_RETIRED.L1_MISS",
	+ "PublicDescription": "Counts retired load instructions with at least one uop that missed in the L1 cache. Available PDIST counters: 0",
	+ "SampleAfterValue": "200003",
	+ "UMask": "0x8"
	+ },
	+ {
	+ "BriefDescription": "Retired load instructions with L2 cache hits as data sources",
	+ "Counter": "0,1,2,3",
	+ "Data_LA": "1",
	+ "EventCode": "0xd1",
	+ "EventName": "MEM_LOAD_RETIRED.L2_HIT",
	+ "PublicDescription": "Counts retired load instructions with L2 cache hits as data sources. Available PDIST counters: 0",
	+ "RetirementLatencyMax": "7140",
	+ "RetirementLatencyMean": "5.71",
	+ "RetirementLatencyMin": "0",
	+ "SampleAfterValue": "200003",
	+ "UMask": "0x2"
	+ },
	+ {
	+ "BriefDescription": "Retired load instructions missed L2 cache as data sources",
	+ "Counter": "0,1,2,3",
	+ "Data_LA": "1",
	+ "EventCode": "0xd1",
	+ "EventName": "MEM_LOAD_RETIRED.L2_MISS",
	+ "PublicDescription": "Counts retired load instructions missed L2 cache as data sources. Available PDIST counters: 0",
	+ "SampleAfterValue": "100021",
	+ "UMask": "0x10"
	+ },
	+ {
	+ "BriefDescription": "Retired load instructions with L3 cache hits as data sources",
	+ "Counter": "0,1,2,3",
	+ "Data_LA": "1",
	+ "EventCode": "0xd1",
	+ "EventName": "MEM_LOAD_RETIRED.L3_HIT",
	+ "PublicDescription": "Counts retired load instructions with at least one uop that hit in the L3 cache. Available PDIST counters: 0",
	+ "RetirementLatencyMax": "5630",
	+ "RetirementLatencyMean": "57.64",
	+ "RetirementLatencyMin": "0",
	+ "SampleAfterValue": "100021",
	+ "UMask": "0x4"
	+ },
	+ {
	+ "BriefDescription": "Retired load instructions missed L3 cache as data sources",
	+ "Counter": "0,1,2,3",
	+ "Data_LA": "1",
	+ "EventCode": "0xd1",
	+ "EventName": "MEM_LOAD_RETIRED.L3_MISS",
	+ "PublicDescription": "Counts retired load instructions with at least one uop that missed in the L3 cache. Available PDIST counters: 0",
	+ "SampleAfterValue": "50021",
	+ "UMask": "0x20"
	+ },
	+ {
	+ "BriefDescription": "Retired load instructions with local cxl mem as the data source where the data request missed all caches.",
	+ "Counter": "0,1,2,3",
	+ "Data_LA": "1",
	+ "EventCode": "0xd1",
	+ "EventName": "MEM_LOAD_RETIRED.LOCAL_CXL_MEM",
	+ "PublicDescription": "Counts retired load instructions with local cxl mem as the data source and the data request missed L3. Available PDIST counters: 0",
	+ "SampleAfterValue": "1000003",
	+ "UMask": "0x80"
	+ },
	+ {
	+ "BriefDescription": "MEM_STORE_RETIRED.L2_HIT",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x44",
	+ "EventName": "MEM_STORE_RETIRED.L2_HIT",
	+ "SampleAfterValue": "200003",
	+ "UMask": "0x1"
	+ },
	+ {
	+ "BriefDescription": "Retired memory uops for any access",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xe5",
	+ "EventName": "MEM_UOP_RETIRED.ANY",
	+ "PublicDescription": "Number of retired micro-operations (uops) for load or store memory accesses",
	+ "SampleAfterValue": "1000003",
	+ "UMask": "0x3"
	+ },
	+ {
	+ "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that have any type of response.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x2A,0x2B",
	+ "EventName": "OCR.DEMAND_CODE_RD.ANY_RESPONSE",
	+ "MSRIndex": "0x1a6,0x1a7",
	+ "MSRValue": "0x10004",
	+ "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that have any type of response. Available PDIST counters: 0",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x1"
	+ },
	+ {
	+ "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit in the L3 or were snooped from another core's caches on the same socket.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x2A,0x2B",
	+ "EventName": "OCR.DEMAND_CODE_RD.L3_HIT",
	+ "MSRIndex": "0x1a6,0x1a7",
	+ "MSRValue": "0x3F803C0004",
	+ "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit in the L3 or were snooped from another core's caches on the same socket. Available PDIST counters: 0",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x1"
	+ },
	+ {
	+ "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that resulted in a snoop hit a modified line in another core's caches which forwarded the data.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x2A,0x2B",
	+ "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HITM",
	+ "MSRIndex": "0x1a6,0x1a7",
	+ "MSRValue": "0x10003C0004",
	+ "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that resulted in a snoop hit a modified line in another core's caches which forwarded the data. Available PDIST counters: 0",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x1"
	+ },
	+ {
	+ "BriefDescription": "Counts demand data reads that have any type of response.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x2A,0x2B",
	+ "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE",
	+ "MSRIndex": "0x1a6,0x1a7",
	+ "MSRValue": "0x10001",
	+ "PublicDescription": "Counts demand data reads that have any type of response. Available PDIST counters: 0",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x1"
	+ },
	+ {
	+ "BriefDescription": "Counts demand data reads that were supplied by CXL MEM (Type 2 or Type 3).",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x2A,0x2B",
	+ "EventName": "OCR.DEMAND_DATA_RD.CXL_MEM",
	+ "MSRIndex": "0x1a6,0x1a7",
	+ "MSRValue": "0x703C00001",
	+ "PublicDescription": "Counts demand data reads that were supplied by CXL MEM (Type 2 or Type 3). Available PDIST counters: 0",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x1"
	+ },
	+ {
	+ "BriefDescription": "Counts demand data reads that hit in the L3 or were snooped from another core's caches on the same socket.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x2A,0x2B",
	+ "EventName": "OCR.DEMAND_DATA_RD.L3_HIT",
	+ "MSRIndex": "0x1a6,0x1a7",
	+ "MSRValue": "0x3F803C0001",
	+ "PublicDescription": "Counts demand data reads that hit in the L3 or were snooped from another core's caches on the same socket. Available PDIST counters: 0",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x1"
	+ },
	+ {
	+ "BriefDescription": "Counts demand data reads that resulted in a snoop hit a modified line in another core's caches which forwarded the data.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x2A,0x2B",
	+ "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM",
	+ "MSRIndex": "0x1a6,0x1a7",
	+ "MSRValue": "0x10003C0001",
	+ "PublicDescription": "Counts demand data reads that resulted in a snoop hit a modified line in another core's caches which forwarded the data. Available PDIST counters: 0",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x1"
	+ },
	+ {
	+ "BriefDescription": "Counts demand data reads that resulted in a snoop that hit in another core, which did not forward the data.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x2A,0x2B",
	+ "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD",
	+ "MSRIndex": "0x1a6,0x1a7",
	+ "MSRValue": "0x4003C0001",
	+ "PublicDescription": "Counts demand data reads that resulted in a snoop that hit in another core, which did not forward the data. Available PDIST counters: 0",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x1"
	+ },
	+ {
	+ "BriefDescription": "Counts demand data reads that resulted in a snoop hit in another core's caches which forwarded the unmodified data to the requesting core.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x2A,0x2B",
	+ "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
	+ "MSRIndex": "0x1a6,0x1a7",
	+ "MSRValue": "0x8003C0001",
	+ "PublicDescription": "Counts demand data reads that resulted in a snoop hit in another core's caches which forwarded the unmodified data to the requesting core. Available PDIST counters: 0",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x1"
	+ },
	+ {
	+ "BriefDescription": "Counts demand data reads that were supplied by CXL MEM (Type 2 and Type 3) attached to local socket.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x2A,0x2B",
	+ "EventName": "OCR.DEMAND_DATA_RD.LOCAL_CXL_MEM",
	+ "MSRIndex": "0x1a6,0x1a7",
	+ "MSRValue": "0x700C00001",
	+ "PublicDescription": "Counts demand data reads that were supplied by CXL MEM (Type 2 and Type 3) attached to local socket. Available PDIST counters: 0",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x1"
	+ },
	+ {
	+ "BriefDescription": "Counts demand data reads that were supplied by a cache on a remote socket where a snoop hit a modified line in another core's caches which forwarded the data.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x2A,0x2B",
	+ "EventName": "OCR.DEMAND_DATA_RD.REMOTE_CACHE.SNOOP_HITM",
	+ "MSRIndex": "0x1a6,0x1a7",
	+ "MSRValue": "0x1030000001",
	+ "PublicDescription": "Counts demand data reads that were supplied by a cache on a remote socket where a snoop hit a modified line in another core's caches which forwarded the data. Available PDIST counters: 0",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x1"
	+ },
	+ {
	+ "BriefDescription": "Counts demand data reads that were supplied by a cache on a remote socket where a snoop hit in another core's caches which forwarded the unmodified data to the requesting core.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x2A,0x2B",
	+ "EventName": "OCR.DEMAND_DATA_RD.REMOTE_CACHE.SNOOP_HIT_WITH_FWD",
	+ "MSRIndex": "0x1a6,0x1a7",
	+ "MSRValue": "0x830000001",
	+ "PublicDescription": "Counts demand data reads that were supplied by a cache on a remote socket where a snoop hit in another core's caches which forwarded the unmodified data to the requesting core. Available PDIST counters: 0",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x1"
	+ },
	+ {
	+ "BriefDescription": "Counts demand data reads that were supplied by CXL MEM (Type 2 or Type 3) attached to another socket.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x2A,0x2B",
	+ "EventName": "OCR.DEMAND_DATA_RD.REMOTE_CXL_MEM",
	+ "MSRIndex": "0x1a6,0x1a7",
	+ "MSRValue": "0x703000001",
	+ "PublicDescription": "Counts demand data reads that were supplied by CXL MEM (Type 2 or Type 3) attached to another socket. Available PDIST counters: 0",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x1"
	+ },
	+ {
	+ "BriefDescription": "Counts demand data reads that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x2A,0x2B",
	+ "EventName": "OCR.DEMAND_DATA_RD.SNC_CACHE.HITM",
	+ "MSRIndex": "0x1a6,0x1a7",
	+ "MSRValue": "0x1008000001",
	+ "PublicDescription": "Counts demand data reads that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode. Available PDIST counters: 0",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x1"
	+ },
	+ {
	+ "BriefDescription": "Counts demand data reads that either hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x2A,0x2B",
	+ "EventName": "OCR.DEMAND_DATA_RD.SNC_CACHE.HIT_WITH_FWD",
	+ "MSRIndex": "0x1a6,0x1a7",
	+ "MSRValue": "0x808000001",
	+ "PublicDescription": "Counts demand data reads that either hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode. Available PDIST counters: 0",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x1"
	+ },
	+ {
	+ "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x2A,0x2B",
	+ "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE",
	+ "MSRIndex": "0x1a6,0x1a7",
	+ "MSRValue": "0x3F3FFC0002",
	+ "PublicDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that have any type of response. Available PDIST counters: 0",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x1"
	+ },
	+ {
	+ "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by CXL MEM (Type 2 or Type 3).",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x2A,0x2B",
	+ "EventName": "OCR.DEMAND_RFO.CXL_MEM",
	+ "MSRIndex": "0x1a6,0x1a7",
	+ "MSRValue": "0x703C00002",
	+ "PublicDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by CXL MEM (Type 2 or Type 3). Available PDIST counters: 0",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x1"
	+ },
	+ {
	+ "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit in the L3 or were snooped from another core's caches on the same socket.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x2A,0x2B",
	+ "EventName": "OCR.DEMAND_RFO.L3_HIT",
	+ "MSRIndex": "0x1a6,0x1a7",
	+ "MSRValue": "0x3F803C0002",
	+ "PublicDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit in the L3 or were snooped from another core's caches on the same socket. Available PDIST counters: 0",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x1"
	+ },
	+ {
	+ "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that resulted in a snoop hit a modified line in another core's caches which forwarded the data.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x2A,0x2B",
	+ "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM",
	+ "MSRIndex": "0x1a6,0x1a7",
	+ "MSRValue": "0x10003C0002",
	+ "PublicDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that resulted in a snoop hit a modified line in another core's caches which forwarded the data. Available PDIST counters: 0",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x1"
	+ },
	+ {
	+ "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by CXL MEM (Type 2 and Type 3) attached to local socket.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x2A,0x2B",
	+ "EventName": "OCR.DEMAND_RFO.LOCAL_CXL_MEM",
	+ "MSRIndex": "0x1a6,0x1a7",
	+ "MSRValue": "0x700C00002",
	+ "PublicDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by CXL MEM (Type 2 and Type 3) attached to local socket. Available PDIST counters: 0",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x1"
	+ },
	+ {
	+ "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by CXL MEM (Type 2 or Type 3) attached to another socket.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x2A,0x2B",
	+ "EventName": "OCR.DEMAND_RFO.REMOTE_CXL_MEM",
	+ "MSRIndex": "0x1a6,0x1a7",
	+ "MSRValue": "0x703000002",
	+ "PublicDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by CXL MEM (Type 2 or Type 3) attached to another socket. Available PDIST counters: 0",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x1"
	+ },
	+ {
	+ "BriefDescription": "Counts writebacks of modified cachelines and streaming stores that have any type of response.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x2A,0x2B",
	+ "EventName": "OCR.MODIFIED_WRITE.ANY_RESPONSE",
	+ "MSRIndex": "0x1a6,0x1a7",
	+ "MSRValue": "0x10808",
	+ "PublicDescription": "Counts writebacks of modified cachelines and streaming stores that have any type of response. Available PDIST counters: 0",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x1"
	+ },
	+ {
	+ "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that have any type of response.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x2A,0x2B",
	+ "EventName": "OCR.READS_TO_CORE.ANY_RESPONSE",
	+ "MSRIndex": "0x1a6,0x1a7",
	+ "MSRValue": "0x3F3FFC4477",
	+ "PublicDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that have any type of response. Available PDIST counters: 0",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x1"
	+ },
	+ {
	+ "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by CXL MEM (Type 2 or Type 3).",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x2A,0x2B",
	+ "EventName": "OCR.READS_TO_CORE.CXL_MEM",
	+ "MSRIndex": "0x1a6,0x1a7",
	+ "MSRValue": "0x703C04477",
	+ "PublicDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by CXL MEM (Type 2 or Type 3). Available PDIST counters: 0",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x1"
	+ },
	+ {
	+ "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that hit in the L3 or were snooped from another core's caches on the same socket.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x2A,0x2B",
	+ "EventName": "OCR.READS_TO_CORE.L3_HIT",
	+ "MSRIndex": "0x1a6,0x1a7",
	+ "MSRValue": "0x3F003C4477",
	+ "PublicDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that hit in the L3 or were snooped from another core's caches on the same socket. Available PDIST counters: 0",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x1"
	+ },
	+ {
	+ "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that resulted in a snoop hit a modified line in another core's caches which forwarded the data.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x2A,0x2B",
	+ "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HITM",
	+ "MSRIndex": "0x1a6,0x1a7",
	+ "MSRValue": "0x10003C4477",
	+ "PublicDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that resulted in a snoop hit a modified line in another core's caches which forwarded the data. Available PDIST counters: 0",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x1"
	+ },
	+ {
	+ "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by CXL MEM (Type 2 and Type 3) attached to local socket.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x2A,0x2B",
	+ "EventName": "OCR.READS_TO_CORE.LOCAL_CXL_MEM",
	+ "MSRIndex": "0x1a6,0x1a7",
	+ "MSRValue": "0x700C04477",
	+ "PublicDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by CXL MEM (Type 2 and Type 3) attached to local socket. Available PDIST counters: 0",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x1"
	+ },
	+ {
	+ "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the local socket's L1, L2, or L3 caches and were supplied by a remote socket.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x2A,0x2B",
	+ "EventName": "OCR.READS_TO_CORE.REMOTE",
	+ "MSRIndex": "0x1a6,0x1a7",
	+ "MSRValue": "0x3F33004477",
	+ "PublicDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the local socket's L1, L2, or L3 caches and were supplied by a remote socket. Available PDIST counters: 0",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x1"
	+ },
	+ {
	+ "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by a cache on a remote socket where a snoop was sent and data was returned (Modified or Not Modified).",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x2A,0x2B",
	+ "EventName": "OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_FWD",
	+ "MSRIndex": "0x1a6,0x1a7",
	+ "MSRValue": "0x1830004477",
	+ "PublicDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by a cache on a remote socket where a snoop was sent and data was returned (Modified or Not Modified). Available PDIST counters: 0",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x1"
	+ },
	+ {
	+ "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by a cache on a remote socket where a snoop hit a modified line in another core's caches which forwarded the data.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x2A,0x2B",
	+ "EventName": "OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_HITM",
	+ "MSRIndex": "0x1a6,0x1a7",
	+ "MSRValue": "0x1030004477",
	+ "PublicDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by a cache on a remote socket where a snoop hit a modified line in another core's caches which forwarded the data. Available PDIST counters: 0",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x1"
	+ },
	+ {
	+ "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by a cache on a remote socket where a snoop hit in another core's caches which forwarded the unmodified data to the requesting core.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x2A,0x2B",
	+ "EventName": "OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_HIT_WITH_FWD",
	+ "MSRIndex": "0x1a6,0x1a7",
	+ "MSRValue": "0x830004477",
	+ "PublicDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by a cache on a remote socket where a snoop hit in another core's caches which forwarded the unmodified data to the requesting core. Available PDIST counters: 0",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x1"
	+ },
	+ {
	+ "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by CXL MEM (Type 2 or Type 3) attached to another socket.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x2A,0x2B",
	+ "EventName": "OCR.READS_TO_CORE.REMOTE_CXL_MEM",
	+ "MSRIndex": "0x1a6,0x1a7",
	+ "MSRValue": "0x703004477",
	+ "PublicDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by CXL MEM (Type 2 or Type 3) attached to another socket. Available PDIST counters: 0",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x1"
	+ },
	+ {
	+ "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x2A,0x2B",
	+ "EventName": "OCR.READS_TO_CORE.SNC_CACHE.HITM",
	+ "MSRIndex": "0x1a6,0x1a7",
	+ "MSRValue": "0x1008004477",
	+ "PublicDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode. Available PDIST counters: 0",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x1"
	+ },
	+ {
	+ "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that either hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x2A,0x2B",
	+ "EventName": "OCR.READS_TO_CORE.SNC_CACHE.HIT_WITH_FWD",
	+ "MSRIndex": "0x1a6,0x1a7",
	+ "MSRValue": "0x808004477",
	+ "PublicDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that either hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode. Available PDIST counters: 0",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x1"
	+ },
	+ {
	+ "BriefDescription": "Counts demand reads for ownership (RFO), hardware prefetch RFOs (which bring data to L2), and software prefetches for exclusive ownership (PREFETCHW) that hit to a (M)odified cacheline in the L3 or snoop filter.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x2A,0x2B",
	+ "EventName": "OCR.RFO_TO_CORE.L3_HIT_M",
	+ "MSRIndex": "0x1a6,0x1a7",
	+ "MSRValue": "0x1F80040022",
	+ "PublicDescription": "Counts demand reads for ownership (RFO), hardware prefetch RFOs (which bring data to L2), and software prefetches for exclusive ownership (PREFETCHW) that hit to a (M)odified cacheline in the L3 or snoop filter. Available PDIST counters: 0",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x1"
	+ },
	+ {
	+ "BriefDescription": "Any memory transaction that reached the SQ.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x21",
	+ "EventName": "OFFCORE_REQUESTS.ALL_REQUESTS",
	+ "PublicDescription": "Counts memory transactions reached the super queue including requests initiated by the core, all L3 prefetches, page walks, etc..",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x80"
	+ },
	+ {
	+ "BriefDescription": "Demand and prefetch data reads",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x21",
	+ "EventName": "OFFCORE_REQUESTS.DATA_RD",
	+ "PublicDescription": "Counts the demand and prefetch data reads. All Core Data Reads include cacheable 'Demands' and L2 prefetchers (not L3 prefetchers). Counting also covers reads due to page walks resulted from any request type.",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x8"
	+ },
	+ {
	+ "BriefDescription": "Cacheable and Non-Cacheable code read requests",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x21",
	+ "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD",
	+ "PublicDescription": "Counts both cacheable and Non-Cacheable code read requests.",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x2"
	+ },
	+ {
	+ "BriefDescription": "Demand Data Read requests sent to uncore",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x21",
	+ "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD",
	+ "PublicDescription": "Counts the Demand Data Read requests sent to uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determine average latency in the uncore.",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x1"
	+ },
	+ {
	+ "BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x21",
	+ "EventName": "OFFCORE_REQUESTS.DEMAND_RFO",
	+ "PublicDescription": "Counts the demand RFO (read for ownership) requests including regular RFOs, locks, ItoM.",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x4"
	+ },
	+ {
	+ "BriefDescription": "Offcore Uncacheable memory data read transactions.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x21",
	+ "EventName": "OFFCORE_REQUESTS.MEM_UC",
	+ "PublicDescription": "This event counts noncacheable memory data read transactions.",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x20"
	+ },
	+ {
	+ "BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore.",
	+ "Counter": "0,1,2,3",
	+ "CounterMask": "1",
	+ "EventCode": "0x20",
	+ "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD",
	+ "PublicDescription": "Counts cycles when offcore outstanding cacheable Core Data Read transactions are present in the super queue. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS.",
	+ "SampleAfterValue": "1000003",
	+ "UMask": "0x8"
	+ },
	+ {
	+ "BriefDescription": "Cycles with offcore outstanding Code Reads transactions in the SuperQueue (SQ), queue to uncore.",
	+ "Counter": "0,1,2,3",
	+ "CounterMask": "1",
	+ "EventCode": "0x20",
	+ "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_CODE_RD",
	+ "PublicDescription": "Counts the number of offcore outstanding Code Reads transactions in the super queue every cycle. The 'Offcore outstanding' state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS.",
	+ "SampleAfterValue": "1000003",
	+ "UMask": "0x2"
	+ },
	+ {
	+ "BriefDescription": "Cycles where at least 1 outstanding demand data read request is pending.",
	+ "Counter": "0,1,2,3",
	+ "CounterMask": "1",
	+ "EventCode": "0x20",
	+ "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD",
	+ "SampleAfterValue": "2000003",
	+ "UMask": "0x1"
	+ },
	+ {
	+ "BriefDescription": "Cycles with offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore.",
	+ "Counter": "0,1,2,3",
	+ "CounterMask": "1",
	+ "EventCode": "0x20",
	+ "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO",
	+ "PublicDescription": "Counts the number of offcore outstanding demand rfo Reads transactions in the super queue every cycle. The 'Offcore outstanding' state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS.",
	+ "SampleAfterValue": "1000003",
	+ "UMask": "0x4"
	+ },
	+ {
	+ "BriefDescription": "OFFCORE_REQUESTS_OUTSTANDING.DATA_RD",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x20",
	+ "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DATA_RD",
	+ "SampleAfterValue": "1000003",
	+ "UMask": "0x8"
	+ },
	+ {
	+ "BriefDescription": "Offcore outstanding Code Reads transactions in the SuperQueue (SQ), queue to uncore, every cycle.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x20",
	+ "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD",
	+ "PublicDescription": "Counts the number of offcore outstanding Code Reads transactions in the super queue every cycle. The 'Offcore outstanding' state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS.",
	+ "SampleAfterValue": "1000003",
	+ "UMask": "0x2"
	+ },
	+ {
	+ "BriefDescription": "For every cycle, increments by the number of outstanding demand data read requests pending.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x20",
	+ "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD",
	+ "PublicDescription": "For every cycle, increments by the number of outstanding demand data read requests pending. Requests are considered outstanding from the time they miss the core's L2 cache until the transaction completion message is sent to the requestor.",
	+ "SampleAfterValue": "1000003",
	+ "UMask": "0x1"
	+ },
	+ {
	+ "BriefDescription": "Store Read transactions pending for off-core. Highly correlated.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x20",
	+ "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO",
	+ "PublicDescription": "Counts the number of off-core outstanding read-for-ownership (RFO) store transactions every cycle. An RFO transaction is considered to be in the Off-core outstanding state between L2 cache miss and transaction completion.",
	+ "SampleAfterValue": "1000003",
	+ "UMask": "0x4"
	+ },
	+ {
	+ "BriefDescription": "Counts bus locks, accounts for cache line split locks and UC locks.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x2c",
	+ "EventName": "SQ_MISC.BUS_LOCK",
	+ "PublicDescription": "Counts the more expensive bus lock needed to enforce cache coherency for certain memory accesses that need to be done atomically. Can be created by issuing an atomic instruction (via the LOCK prefix) which causes a cache line split or accesses uncacheable memory.",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x10"
	+ },
	+ {
	+ "BriefDescription": "Counts the number of PREFETCHNTA, PREFETCHW, PREFETCHT0, PREFETCHT1 or PREFETCHT2 instructions executed.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x40",
	+ "EventName": "SW_PREFETCH_ACCESS.ANY",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0xf"
	+ },
	+ {
	+ "BriefDescription": "Number of PREFETCHNTA instructions executed.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x40",
	+ "EventName": "SW_PREFETCH_ACCESS.NTA",
	+ "PublicDescription": "Counts the number of PREFETCHNTA instructions executed.",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x1"
	+ },
	+ {
	+ "BriefDescription": "Number of PREFETCHW instructions executed.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x40",
	+ "EventName": "SW_PREFETCH_ACCESS.PREFETCHW",
	+ "PublicDescription": "Counts the number of PREFETCHW instructions executed.",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x8"
	+ },
	+ {
	+ "BriefDescription": "Number of PREFETCHT0 instructions executed.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x40",
	+ "EventName": "SW_PREFETCH_ACCESS.T0",
	+ "PublicDescription": "Counts the number of PREFETCHT0 instructions executed.",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x2"
	+ },
	+ {
	+ "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x40",
	+ "EventName": "SW_PREFETCH_ACCESS.T1_T2",
	+ "PublicDescription": "Counts the number of PREFETCHT1 or PREFETCHT2 instructions executed.",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x4"
	+ }
	+]
	\ No newline at end of file
	diff --git a/lib/libpmc/pmu-events/arch/x86/graniterapids/floating-point.json b/lib/libpmc/pmu-events/arch/x86/graniterapids/floating-point.json
	new file mode 100644
	--- /dev/null
	+++ b/lib/libpmc/pmu-events/arch/x86/graniterapids/floating-point.json
	@@ -0,0 +1,242 @@
	+[
	+ {
	+ "BriefDescription": "This event counts the cycles the floating point divider is busy.",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "CounterMask": "1",
	+ "EventCode": "0xb0",
	+ "EventName": "ARITH.FPDIV_ACTIVE",
	+ "SampleAfterValue": "1000003",
	+ "UMask": "0x1"
	+ },
	+ {
	+ "BriefDescription": "Counts all microcode FP assists.",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xc1",
	+ "EventName": "ASSISTS.FP",
	+ "PublicDescription": "Counts all microcode Floating Point assists.",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x2"
	+ },
	+ {
	+ "BriefDescription": "ASSISTS.SSE_AVX_MIX",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xc1",
	+ "EventName": "ASSISTS.SSE_AVX_MIX",
	+ "SampleAfterValue": "1000003",
	+ "UMask": "0x10"
	+ },
	+ {
	+ "BriefDescription": "FP_ARITH_DISPATCHED.PORT_0 [This event is alias to FP_ARITH_DISPATCHED.V0]",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xb3",
	+ "EventName": "FP_ARITH_DISPATCHED.PORT_0",
	+ "SampleAfterValue": "2000003",
	+ "UMask": "0x1"
	+ },
	+ {
	+ "BriefDescription": "FP_ARITH_DISPATCHED.PORT_1 [This event is alias to FP_ARITH_DISPATCHED.V1]",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xb3",
	+ "EventName": "FP_ARITH_DISPATCHED.PORT_1",
	+ "SampleAfterValue": "2000003",
	+ "UMask": "0x2"
	+ },
	+ {
	+ "BriefDescription": "FP_ARITH_DISPATCHED.PORT_5 [This event is alias to FP_ARITH_DISPATCHED.V2]",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xb3",
	+ "EventName": "FP_ARITH_DISPATCHED.PORT_5",
	+ "SampleAfterValue": "2000003",
	+ "UMask": "0x4"
	+ },
	+ {
	+ "BriefDescription": "FP_ARITH_DISPATCHED.V0 [This event is alias to FP_ARITH_DISPATCHED.PORT_0]",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xb3",
	+ "EventName": "FP_ARITH_DISPATCHED.V0",
	+ "SampleAfterValue": "2000003",
	+ "UMask": "0x1"
	+ },
	+ {
	+ "BriefDescription": "FP_ARITH_DISPATCHED.V1 [This event is alias to FP_ARITH_DISPATCHED.PORT_1]",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xb3",
	+ "EventName": "FP_ARITH_DISPATCHED.V1",
	+ "SampleAfterValue": "2000003",
	+ "UMask": "0x2"
	+ },
	+ {
	+ "BriefDescription": "FP_ARITH_DISPATCHED.V2 [This event is alias to FP_ARITH_DISPATCHED.PORT_5]",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xb3",
	+ "EventName": "FP_ARITH_DISPATCHED.V2",
	+ "SampleAfterValue": "2000003",
	+ "UMask": "0x4"
	+ },
	+ {
	+ "BriefDescription": "Counts number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xc7",
	+ "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE",
	+ "PublicDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x4"
	+ },
	+ {
	+ "BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xc7",
	+ "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE",
	+ "PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x8"
	+ },
	+ {
	+ "BriefDescription": "Counts number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xc7",
	+ "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE",
	+ "PublicDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x10"
	+ },
	+ {
	+ "BriefDescription": "Counts number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xc7",
	+ "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE",
	+ "PublicDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x20"
	+ },
	+ {
	+ "BriefDescription": "Number of SSE/AVX computational 128-bit packed single and 256-bit packed double precision FP instructions retired; some instructions will count twice as noted below. Each count represents 2 or/and 4 computation operations, 1 for each element. Applies to SSE* and AVX* packed single precision and packed double precision FP instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB count twice as they perform 2 calculations per element.",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xc7",
	+ "EventName": "FP_ARITH_INST_RETIRED.4_FLOPS",
	+ "PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision and 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 or/and 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point and packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x18"
	+ },
	+ {
	+ "BriefDescription": "Counts number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xc7",
	+ "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE",
	+ "PublicDescription": "Number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x40"
	+ },
	+ {
	+ "BriefDescription": "Counts number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xc7",
	+ "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE",
	+ "PublicDescription": "Number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x80"
	+ },
	+ {
	+ "BriefDescription": "Number of SSE/AVX computational 256-bit packed single precision and 512-bit packed double precision FP instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, 1 for each element. Applies to SSE* and AVX* packed single precision and double precision FP instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RSQRT14 RCP RCP14 DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB count twice as they perform 2 calculations per element.",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xc7",
	+ "EventName": "FP_ARITH_INST_RETIRED.8_FLOPS",
	+ "PublicDescription": "Number of SSE/AVX computational 256-bit packed single precision and 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision and double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RSQRT14 RCP RCP14 DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x60"
	+ },
	+ {
	+ "BriefDescription": "Number of SSE/AVX computational scalar floating-point instructions retired; some instructions will count twice as noted below. Applies to SSE* and AVX* scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 RANGE SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xc7",
	+ "EventName": "FP_ARITH_INST_RETIRED.SCALAR",
	+ "PublicDescription": "Number of SSE/AVX computational scalar single precision and double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
	+ "SampleAfterValue": "1000003",
	+ "UMask": "0x3"
	+ },
	+ {
	+ "BriefDescription": "Counts number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xc7",
	+ "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE",
	+ "PublicDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x1"
	+ },
	+ {
	+ "BriefDescription": "Counts number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xc7",
	+ "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE",
	+ "PublicDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x2"
	+ },
	+ {
	+ "BriefDescription": "Number of any Vector retired FP arithmetic instructions",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xc7",
	+ "EventName": "FP_ARITH_INST_RETIRED.VECTOR",
	+ "PublicDescription": "Number of any Vector retired FP arithmetic instructions. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
	+ "SampleAfterValue": "1000003",
	+ "UMask": "0xfc"
	+ },
	+ {
	+ "BriefDescription": "FP_ARITH_INST_RETIRED2.128B_PACKED_HALF",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xcf",
	+ "EventName": "FP_ARITH_INST_RETIRED2.128B_PACKED_HALF",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x4"
	+ },
	+ {
	+ "BriefDescription": "FP_ARITH_INST_RETIRED2.256B_PACKED_HALF",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xcf",
	+ "EventName": "FP_ARITH_INST_RETIRED2.256B_PACKED_HALF",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x8"
	+ },
	+ {
	+ "BriefDescription": "FP_ARITH_INST_RETIRED2.512B_PACKED_HALF",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xcf",
	+ "EventName": "FP_ARITH_INST_RETIRED2.512B_PACKED_HALF",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x10"
	+ },
	+ {
	+ "BriefDescription": "FP_ARITH_INST_RETIRED2.COMPLEX_SCALAR_HALF",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xcf",
	+ "EventName": "FP_ARITH_INST_RETIRED2.COMPLEX_SCALAR_HALF",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x2"
	+ },
	+ {
	+ "BriefDescription": "Number of all Scalar Half-Precision FP arithmetic instructions(1) retired - regular and complex.",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xcf",
	+ "EventName": "FP_ARITH_INST_RETIRED2.SCALAR",
	+ "PublicDescription": "FP_ARITH_INST_RETIRED2.SCALAR",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x3"
	+ },
	+ {
	+ "BriefDescription": "FP_ARITH_INST_RETIRED2.SCALAR_HALF",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xcf",
	+ "EventName": "FP_ARITH_INST_RETIRED2.SCALAR_HALF",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x1"
	+ },
	+ {
	+ "BriefDescription": "Number of all Vector (also called packed) Half-Precision FP arithmetic instructions(1) retired.",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xcf",
	+ "EventName": "FP_ARITH_INST_RETIRED2.VECTOR",
	+ "PublicDescription": "FP_ARITH_INST_RETIRED2.VECTOR",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x1c"
	+ }
	+]
	\ No newline at end of file
	diff --git a/lib/libpmc/pmu-events/arch/x86/graniterapids/frontend.json b/lib/libpmc/pmu-events/arch/x86/graniterapids/frontend.json
	new file mode 100644
	--- /dev/null
	+++ b/lib/libpmc/pmu-events/arch/x86/graniterapids/frontend.json
	@@ -0,0 +1,476 @@
	+[
	+ {
	+ "BriefDescription": "Clears due to Unknown Branches.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x60",
	+ "EventName": "BACLEARS.ANY",
	+ "PublicDescription": "Number of times the front-end is resteered when it finds a branch instruction in a fetch line. This is called Unknown Branch which occurs for the first time a branch instruction is fetched or when the branch is not tracked by the BPU (Branch Prediction Unit) anymore.",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x1"
	+ },
	+ {
	+ "BriefDescription": "Stalls caused by changing prefix length of the instruction.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x87",
	+ "EventName": "DECODE.LCP",
	+ "PublicDescription": "Counts cycles that the Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the decoded instruction (by operand size prefix instruction 0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length changing prefix) in a 16-byte chunk.",
	+ "SampleAfterValue": "500009",
	+ "UMask": "0x1"
	+ },
	+ {
	+ "BriefDescription": "Cycles the Microcode Sequencer is busy.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x87",
	+ "EventName": "DECODE.MS_BUSY",
	+ "SampleAfterValue": "500009",
	+ "UMask": "0x2"
	+ },
	+ {
	+ "BriefDescription": "DSB-to-MITE switch true penalty cycles.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x61",
	+ "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES",
	+ "PublicDescription": "Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previously fetched instructions that were decoded by the legacy x86 decode pipeline (MITE). This event counts fetch penalty cycles when a transition occurs from DSB to MITE.",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x2"
	+ },
	+ {
	+ "BriefDescription": "Retired ANT branches",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xc6",
	+ "EventName": "FRONTEND_RETIRED.ANY_ANT",
	+ "MSRIndex": "0x3F7",
	+ "MSRValue": "0x9",
	+ "PublicDescription": "Always Not Taken (ANT) conditional retired branches (no BTB entry and not mispredicted) Available PDIST counters: 0",
	+ "SampleAfterValue": "100007",
	+ "UMask": "0x3"
	+ },
	+ {
	+ "BriefDescription": "Retired Instructions who experienced DSB miss.",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xc6",
	+ "EventName": "FRONTEND_RETIRED.ANY_DSB_MISS",
	+ "MSRIndex": "0x3F7",
	+ "MSRValue": "0x1",
	+ "PublicDescription": "Counts retired Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Available PDIST counters: 0",
	+ "RetirementLatencyMax": "65535",
	+ "RetirementLatencyMean": "2.46",
	+ "RetirementLatencyMin": "0",
	+ "SampleAfterValue": "100007",
	+ "UMask": "0x3"
	+ },
	+ {
	+ "BriefDescription": "Retired Instructions who experienced a critical DSB miss.",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xc6",
	+ "EventName": "FRONTEND_RETIRED.DSB_MISS",
	+ "MSRIndex": "0x3F7",
	+ "MSRValue": "0x11",
	+ "PublicDescription": "Number of retired Instructions that experienced a critical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to the back-end as a result of the DSB miss. Available PDIST counters: 0",
	+ "SampleAfterValue": "100007",
	+ "UMask": "0x3"
	+ },
	+ {
	+ "BriefDescription": "Retired Instructions who experienced iTLB true miss.",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xc6",
	+ "EventName": "FRONTEND_RETIRED.ITLB_MISS",
	+ "MSRIndex": "0x3F7",
	+ "MSRValue": "0x14",
	+ "PublicDescription": "Counts retired Instructions that experienced iTLB (Instruction TLB) true miss. Available PDIST counters: 0",
	+ "RetirementLatencyMax": "980",
	+ "RetirementLatencyMean": "41.96",
	+ "RetirementLatencyMin": "0",
	+ "SampleAfterValue": "100007",
	+ "UMask": "0x3"
	+ },
	+ {
	+ "BriefDescription": "Retired Instructions who experienced Instruction L1 Cache true miss.",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xc6",
	+ "EventName": "FRONTEND_RETIRED.L1I_MISS",
	+ "MSRIndex": "0x3F7",
	+ "MSRValue": "0x12",
	+ "PublicDescription": "Counts retired Instructions who experienced Instruction L1 Cache true miss. Available PDIST counters: 0",
	+ "RetirementLatencyMax": "1785",
	+ "RetirementLatencyMean": "9.83",
	+ "RetirementLatencyMin": "0",
	+ "SampleAfterValue": "100007",
	+ "UMask": "0x3"
	+ },
	+ {
	+ "BriefDescription": "Retired Instructions who experienced Instruction L2 Cache true miss.",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xc6",
	+ "EventName": "FRONTEND_RETIRED.L2_MISS",
	+ "MSRIndex": "0x3F7",
	+ "MSRValue": "0x13",
	+ "PublicDescription": "Counts retired Instructions who experienced Instruction L2 Cache true miss. Available PDIST counters: 0",
	+ "RetirementLatencyMax": "2854",
	+ "RetirementLatencyMean": "137.41",
	+ "RetirementLatencyMin": "0",
	+ "SampleAfterValue": "100007",
	+ "UMask": "0x3"
	+ },
	+ {
	+ "BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xc6",
	+ "EventName": "FRONTEND_RETIRED.LATENCY_GE_1",
	+ "MSRIndex": "0x3F7",
	+ "MSRValue": "0x600106",
	+ "PublicDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of at least 1 cycle which was not interrupted by a back-end stall. Available PDIST counters: 0",
	+ "SampleAfterValue": "100007",
	+ "UMask": "0x3"
	+ },
	+ {
	+ "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall.",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xc6",
	+ "EventName": "FRONTEND_RETIRED.LATENCY_GE_128",
	+ "MSRIndex": "0x3F7",
	+ "MSRValue": "0x608006",
	+ "PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall. Available PDIST counters: 0",
	+ "SampleAfterValue": "100007",
	+ "UMask": "0x3"
	+ },
	+ {
	+ "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 16 cycles which was not interrupted by a back-end stall.",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xc6",
	+ "EventName": "FRONTEND_RETIRED.LATENCY_GE_16",
	+ "MSRIndex": "0x3F7",
	+ "MSRValue": "0x601006",
	+ "PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 16 cycles. During this period the front-end delivered no uops. Available PDIST counters: 0",
	+ "SampleAfterValue": "100007",
	+ "UMask": "0x3"
	+ },
	+ {
	+ "BriefDescription": "Retired instructions after front-end starvation of at least 2 cycles",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xc6",
	+ "EventName": "FRONTEND_RETIRED.LATENCY_GE_2",
	+ "MSRIndex": "0x3F7",
	+ "MSRValue": "0x600206",
	+ "PublicDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of at least 2 cycles which was not interrupted by a back-end stall. Available PDIST counters: 0",
	+ "SampleAfterValue": "100007",
	+ "UMask": "0x3"
	+ },
	+ {
	+ "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall.",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xc6",
	+ "EventName": "FRONTEND_RETIRED.LATENCY_GE_256",
	+ "MSRIndex": "0x3F7",
	+ "MSRValue": "0x610006",
	+ "PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall. Available PDIST counters: 0",
	+ "SampleAfterValue": "100007",
	+ "UMask": "0x3"
	+ },
	+ {
	+ "BriefDescription": "Retired instructions that are fetched after an interval where the front-end had at least 1 bubble-slot for a period of 2 cycles which was not interrupted by a back-end stall.",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xc6",
	+ "EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1",
	+ "MSRIndex": "0x3F7",
	+ "MSRValue": "0x100206",
	+ "PublicDescription": "Counts retired instructions that are delivered to the back-end after the front-end had at least 1 bubble-slot for a period of 2 cycles. A bubble-slot is an empty issue-pipeline slot while there was no RAT stall. Available PDIST counters: 0",
	+ "SampleAfterValue": "100007",
	+ "UMask": "0x3"
	+ },
	+ {
	+ "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 32 cycles which was not interrupted by a back-end stall.",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xc6",
	+ "EventName": "FRONTEND_RETIRED.LATENCY_GE_32",
	+ "MSRIndex": "0x3F7",
	+ "MSRValue": "0x602006",
	+ "PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 32 cycles. During this period the front-end delivered no uops. Available PDIST counters: 0",
	+ "SampleAfterValue": "100007",
	+ "UMask": "0x3"
	+ },
	+ {
	+ "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall.",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xc6",
	+ "EventName": "FRONTEND_RETIRED.LATENCY_GE_4",
	+ "MSRIndex": "0x3F7",
	+ "MSRValue": "0x600406",
	+ "PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall. Available PDIST counters: 0",
	+ "SampleAfterValue": "100007",
	+ "UMask": "0x3"
	+ },
	+ {
	+ "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall.",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xc6",
	+ "EventName": "FRONTEND_RETIRED.LATENCY_GE_512",
	+ "MSRIndex": "0x3F7",
	+ "MSRValue": "0x620006",
	+ "PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall. Available PDIST counters: 0",
	+ "SampleAfterValue": "100007",
	+ "UMask": "0x3"
	+ },
	+ {
	+ "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall.",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xc6",
	+ "EventName": "FRONTEND_RETIRED.LATENCY_GE_64",
	+ "MSRIndex": "0x3F7",
	+ "MSRValue": "0x604006",
	+ "PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall. Available PDIST counters: 0",
	+ "SampleAfterValue": "100007",
	+ "UMask": "0x3"
	+ },
	+ {
	+ "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 8 cycles which was not interrupted by a back-end stall.",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xc6",
	+ "EventName": "FRONTEND_RETIRED.LATENCY_GE_8",
	+ "MSRIndex": "0x3F7",
	+ "MSRValue": "0x600806",
	+ "PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 8 cycles. During this period the front-end delivered no uops. Available PDIST counters: 0",
	+ "SampleAfterValue": "100007",
	+ "UMask": "0x3"
	+ },
	+ {
	+ "BriefDescription": "I-Cache miss too close to Code Prefetch Instruction",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xc6",
	+ "EventName": "FRONTEND_RETIRED.LATE_SWPF",
	+ "MSRIndex": "0x3F7",
	+ "MSRValue": "0xA",
	+ "PublicDescription": "Number of Instruction Cache demand miss in shadow of an on-going i-fetch cache-line triggered by PREFETCHIT0/1 instructions Available PDIST counters: 0",
	+ "SampleAfterValue": "100007",
	+ "UMask": "0x3"
	+ },
	+ {
	+ "BriefDescription": "Mispredicted Retired ANT branches",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xc6",
	+ "EventName": "FRONTEND_RETIRED.MISP_ANT",
	+ "MSRIndex": "0x3F7",
	+ "MSRValue": "0x9",
	+ "PublicDescription": "ANT retired branches that got just mispredicted Available PDIST counters: 0",
	+ "SampleAfterValue": "100007",
	+ "UMask": "0x2"
	+ },
	+ {
	+ "BriefDescription": "FRONTEND_RETIRED.MS_FLOWS",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xc6",
	+ "EventName": "FRONTEND_RETIRED.MS_FLOWS",
	+ "MSRIndex": "0x3F7",
	+ "MSRValue": "0x8",
	+ "PublicDescription": "FRONTEND_RETIRED.MS_FLOWS Available PDIST counters: 0",
	+ "RetirementLatencyMax": "65535",
	+ "RetirementLatencyMean": "77.14",
	+ "RetirementLatencyMin": "0",
	+ "SampleAfterValue": "100007",
	+ "UMask": "0x3"
	+ },
	+ {
	+ "BriefDescription": "Retired Instructions who experienced STLB (2nd level TLB) true miss.",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xc6",
	+ "EventName": "FRONTEND_RETIRED.STLB_MISS",
	+ "MSRIndex": "0x3F7",
	+ "MSRValue": "0x15",
	+ "PublicDescription": "Counts retired Instructions that experienced STLB (2nd level TLB) true miss. Available PDIST counters: 0",
	+ "RetirementLatencyMax": "754",
	+ "RetirementLatencyMean": "206.85",
	+ "RetirementLatencyMin": "0",
	+ "SampleAfterValue": "100007",
	+ "UMask": "0x3"
	+ },
	+ {
	+ "BriefDescription": "FRONTEND_RETIRED.UNKNOWN_BRANCH",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xc6",
	+ "EventName": "FRONTEND_RETIRED.UNKNOWN_BRANCH",
	+ "MSRIndex": "0x3F7",
	+ "MSRValue": "0x17",
	+ "PublicDescription": "FRONTEND_RETIRED.UNKNOWN_BRANCH Available PDIST counters: 0",
	+ "RetirementLatencyMax": "532",
	+ "RetirementLatencyMean": "3.85",
	+ "RetirementLatencyMin": "0",
	+ "SampleAfterValue": "100007",
	+ "UMask": "0x3"
	+ },
	+ {
	+ "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache miss.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x80",
	+ "EventName": "ICACHE_DATA.STALLS",
	+ "PublicDescription": "Counts cycles where a code line fetch is stalled due to an L1 instruction cache miss. The decode pipeline works at a 32 Byte granularity.",
	+ "SampleAfterValue": "500009",
	+ "UMask": "0x4"
	+ },
	+ {
	+ "BriefDescription": "ICACHE_DATA.STALL_PERIODS",
	+ "Counter": "0,1,2,3",
	+ "CounterMask": "1",
	+ "EdgeDetect": "1",
	+ "EventCode": "0x80",
	+ "EventName": "ICACHE_DATA.STALL_PERIODS",
	+ "SampleAfterValue": "500009",
	+ "UMask": "0x4"
	+ },
	+ {
	+ "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache tag miss.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x83",
	+ "EventName": "ICACHE_TAG.STALLS",
	+ "PublicDescription": "Counts cycles where a code fetch is stalled due to L1 instruction cache tag miss.",
	+ "SampleAfterValue": "200003",
	+ "UMask": "0x4"
	+ },
	+ {
	+ "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
	+ "Counter": "0,1,2,3",
	+ "CounterMask": "1",
	+ "EventCode": "0x79",
	+ "EventName": "IDQ.DSB_CYCLES_ANY",
	+ "PublicDescription": "Counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.",
	+ "SampleAfterValue": "2000003",
	+ "UMask": "0x8"
	+ },
	+ {
	+ "BriefDescription": "Cycles DSB is delivering optimal number of Uops",
	+ "Counter": "0,1,2,3",
	+ "CounterMask": "6",
	+ "EventCode": "0x79",
	+ "EventName": "IDQ.DSB_CYCLES_OK",
	+ "PublicDescription": "Counts the number of cycles where optimal number of uops was delivered to the Instruction Decode Queue (IDQ) from the DSB (Decode Stream Buffer) path. Count includes uops that may 'bypass' the IDQ.",
	+ "SampleAfterValue": "2000003",
	+ "UMask": "0x8"
	+ },
	+ {
	+ "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x79",
	+ "EventName": "IDQ.DSB_UOPS",
	+ "PublicDescription": "Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.",
	+ "SampleAfterValue": "2000003",
	+ "UMask": "0x8"
	+ },
	+ {
	+ "BriefDescription": "Cycles MITE is delivering any Uop",
	+ "Counter": "0,1,2,3",
	+ "CounterMask": "1",
	+ "EventCode": "0x79",
	+ "EventName": "IDQ.MITE_CYCLES_ANY",
	+ "PublicDescription": "Counts the number of cycles uops were delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB).",
	+ "SampleAfterValue": "2000003",
	+ "UMask": "0x4"
	+ },
	+ {
	+ "BriefDescription": "Cycles MITE is delivering optimal number of Uops",
	+ "Counter": "0,1,2,3",
	+ "CounterMask": "6",
	+ "EventCode": "0x79",
	+ "EventName": "IDQ.MITE_CYCLES_OK",
	+ "PublicDescription": "Counts the number of cycles where optimal number of uops was delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB).",
	+ "SampleAfterValue": "2000003",
	+ "UMask": "0x4"
	+ },
	+ {
	+ "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x79",
	+ "EventName": "IDQ.MITE_UOPS",
	+ "PublicDescription": "Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
	+ "SampleAfterValue": "2000003",
	+ "UMask": "0x4"
	+ },
	+ {
	+ "BriefDescription": "Cycles when uops are being delivered to IDQ while MS is busy",
	+ "Counter": "0,1,2,3",
	+ "CounterMask": "1",
	+ "EventCode": "0x79",
	+ "EventName": "IDQ.MS_CYCLES_ANY",
	+ "PublicDescription": "Counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE.",
	+ "SampleAfterValue": "2000003",
	+ "UMask": "0x20"
	+ },
	+ {
	+ "BriefDescription": "Number of switches from DSB or MITE to the MS",
	+ "Counter": "0,1,2,3",
	+ "CounterMask": "1",
	+ "EdgeDetect": "1",
	+ "EventCode": "0x79",
	+ "EventName": "IDQ.MS_SWITCHES",
	+ "PublicDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x20"
	+ },
	+ {
	+ "BriefDescription": "Uops initiated by MITE or Decode Stream Buffer (DSB) and delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x79",
	+ "EventName": "IDQ.MS_UOPS",
	+ "PublicDescription": "Counts the number of uops initiated by MITE or Decode Stream Buffer (DSB) and delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may 'bypass' the IDQ.",
	+ "SampleAfterValue": "1000003",
	+ "UMask": "0x20"
	+ },
	+ {
	+ "BriefDescription": "This event counts a subset of the Topdown Slots event that when no operation was delivered to the back-end pipeline due to instruction fetch limitations when the back-end could have accepted more operations. Common examples include instruction cache misses or x86 instruction decode limitations.",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0x9c",
	+ "EventName": "IDQ_BUBBLES.CORE",
	+ "PublicDescription": "This event counts a subset of the Topdown Slots event that when no operation was delivered to the back-end pipeline due to instruction fetch limitations when the back-end could have accepted more operations. Common examples include instruction cache misses or x86 instruction decode limitations. The count may be distributed among unhalted logical processors (hyper-threads) who share the same physical core, in processors that support Intel Hyper-Threading Technology. Software can use this event as the numerator for the Frontend Bound metric (or top-level category) of the Top-down Microarchitecture Analysis method.",
	+ "SampleAfterValue": "1000003",
	+ "UMask": "0x1"
	+ },
	+ {
	+ "BriefDescription": "Cycles when no uops are not delivered by the IDQ when backend of the machine is not stalled [This event is alias to IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE]",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "CounterMask": "6",
	+ "EventCode": "0x9c",
	+ "EventName": "IDQ_BUBBLES.CYCLES_0_UOPS_DELIV.CORE",
	+ "PublicDescription": "Counts the number of cycles when no uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle. [This event is alias to IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE]",
	+ "SampleAfterValue": "1000003",
	+ "UMask": "0x1"
	+ },
	+ {
	+ "BriefDescription": "Cycles when optimal number of uops was delivered to the back-end when the back-end is not stalled [This event is alias to IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK]",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "CounterMask": "1",
	+ "EventCode": "0x9c",
	+ "EventName": "IDQ_BUBBLES.CYCLES_FE_WAS_OK",
	+ "Invert": "1",
	+ "PublicDescription": "Counts the number of cycles when the optimal number of uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle. [This event is alias to IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK]",
	+ "SampleAfterValue": "1000003",
	+ "UMask": "0x1"
	+ },
	+ {
	+ "BriefDescription": "Uops not delivered by IDQ when backend of the machine is not stalled",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0x9c",
	+ "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE",
	+ "PublicDescription": "Counts the number of uops not delivered to by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle.",
	+ "SampleAfterValue": "1000003",
	+ "UMask": "0x1"
	+ },
	+ {
	+ "BriefDescription": "Cycles when no uops are not delivered by the IDQ when backend of the machine is not stalled [This event is alias to IDQ_BUBBLES.CYCLES_0_UOPS_DELIV.CORE]",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "CounterMask": "6",
	+ "EventCode": "0x9c",
	+ "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE",
	+ "PublicDescription": "Counts the number of cycles when no uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle. [This event is alias to IDQ_BUBBLES.CYCLES_0_UOPS_DELIV.CORE]",
	+ "SampleAfterValue": "1000003",
	+ "UMask": "0x1"
	+ },
	+ {
	+ "BriefDescription": "Cycles when optimal number of uops was delivered to the back-end when the back-end is not stalled [This event is alias to IDQ_BUBBLES.CYCLES_FE_WAS_OK]",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "CounterMask": "1",
	+ "EventCode": "0x9c",
	+ "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK",
	+ "Invert": "1",
	+ "PublicDescription": "Counts the number of cycles when the optimal number of uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle. [This event is alias to IDQ_BUBBLES.CYCLES_FE_WAS_OK]",
	+ "SampleAfterValue": "1000003",
	+ "UMask": "0x1"
	+ }
	+]
	\ No newline at end of file
	diff --git a/lib/libpmc/pmu-events/arch/x86/graniterapids/memory.json b/lib/libpmc/pmu-events/arch/x86/graniterapids/memory.json
	new file mode 100644
	--- /dev/null
	+++ b/lib/libpmc/pmu-events/arch/x86/graniterapids/memory.json
	@@ -0,0 +1,523 @@
	+[
	+ {
	+ "BriefDescription": "Cycles while L3 cache miss demand load is outstanding.",
	+ "Counter": "0,1,2,3",
	+ "CounterMask": "2",
	+ "EventCode": "0xa3",
	+ "EventName": "CYCLE_ACTIVITY.CYCLES_L3_MISS",
	+ "SampleAfterValue": "1000003",
	+ "UMask": "0x2"
	+ },
	+ {
	+ "BriefDescription": "Execution stalls while L3 cache miss demand load is outstanding.",
	+ "Counter": "0,1,2,3",
	+ "CounterMask": "6",
	+ "EventCode": "0xa3",
	+ "EventName": "CYCLE_ACTIVITY.STALLS_L3_MISS",
	+ "SampleAfterValue": "1000003",
	+ "UMask": "0x6"
	+ },
	+ {
	+ "BriefDescription": "Number of machine clears due to memory ordering conflicts.",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xc3",
	+ "EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
	+ "PublicDescription": "Counts the number of Machine Clears detected dye to memory ordering. Memory Ordering Machine Clears may apply when a memory read may not conform to the memory ordering rules of the x86 architecture",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x2"
	+ },
	+ {
	+ "BriefDescription": "Cycles while L1 cache miss demand load is outstanding.",
	+ "Counter": "0,1,2,3",
	+ "CounterMask": "2",
	+ "EventCode": "0x47",
	+ "EventName": "MEMORY_ACTIVITY.CYCLES_L1D_MISS",
	+ "SampleAfterValue": "1000003",
	+ "UMask": "0x2"
	+ },
	+ {
	+ "BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.",
	+ "Counter": "0,1,2,3",
	+ "CounterMask": "3",
	+ "EventCode": "0x47",
	+ "EventName": "MEMORY_ACTIVITY.STALLS_L1D_MISS",
	+ "SampleAfterValue": "1000003",
	+ "UMask": "0x3"
	+ },
	+ {
	+ "BriefDescription": "Execution stalls while L2 cache miss demand cacheable load request is outstanding.",
	+ "Counter": "0,1,2,3",
	+ "CounterMask": "5",
	+ "EventCode": "0x47",
	+ "EventName": "MEMORY_ACTIVITY.STALLS_L2_MISS",
	+ "PublicDescription": "Execution stalls while L2 cache miss demand cacheable load request is outstanding (will not count for uncacheable demand requests e.g. bus lock).",
	+ "SampleAfterValue": "1000003",
	+ "UMask": "0x5"
	+ },
	+ {
	+ "BriefDescription": "Execution stalls while L3 cache miss demand cacheable load request is outstanding.",
	+ "Counter": "0,1,2,3",
	+ "CounterMask": "9",
	+ "EventCode": "0x47",
	+ "EventName": "MEMORY_ACTIVITY.STALLS_L3_MISS",
	+ "PublicDescription": "Execution stalls while L3 cache miss demand cacheable load request is outstanding (will not count for uncacheable demand requests e.g. bus lock).",
	+ "SampleAfterValue": "1000003",
	+ "UMask": "0x9"
	+ },
	+ {
	+ "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 1024 cycles.",
	+ "Counter": "1,2,3,4,5,6,7",
	+ "Data_LA": "1",
	+ "EventCode": "0xcd",
	+ "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_1024",
	+ "MSRIndex": "0x3F6",
	+ "MSRValue": "0x400",
	+ "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 1024 cycles. Reported latency may be longer than just the memory latency. Available PDIST counters: 0",
	+ "SampleAfterValue": "53",
	+ "UMask": "0x1"
	+ },
	+ {
	+ "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.",
	+ "Counter": "1,2,3,4,5,6,7",
	+ "Data_LA": "1",
	+ "EventCode": "0xcd",
	+ "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128",
	+ "MSRIndex": "0x3F6",
	+ "MSRValue": "0x80",
	+ "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles. Reported latency may be longer than just the memory latency. Available PDIST counters: 0",
	+ "SampleAfterValue": "1009",
	+ "UMask": "0x1"
	+ },
	+ {
	+ "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.",
	+ "Counter": "1,2,3,4,5,6,7",
	+ "Data_LA": "1",
	+ "EventCode": "0xcd",
	+ "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16",
	+ "MSRIndex": "0x3F6",
	+ "MSRValue": "0x10",
	+ "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles. Reported latency may be longer than just the memory latency. Available PDIST counters: 0",
	+ "SampleAfterValue": "20011",
	+ "UMask": "0x1"
	+ },
	+ {
	+ "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 2048 cycles.",
	+ "Counter": "1,2,3,4,5,6,7",
	+ "Data_LA": "1",
	+ "EventCode": "0xcd",
	+ "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_2048",
	+ "MSRIndex": "0x3F6",
	+ "MSRValue": "0x800",
	+ "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 2048 cycles. Reported latency may be longer than just the memory latency. Available PDIST counters: 0",
	+ "SampleAfterValue": "23",
	+ "UMask": "0x1"
	+ },
	+ {
	+ "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.",
	+ "Counter": "1,2,3,4,5,6,7",
	+ "Data_LA": "1",
	+ "EventCode": "0xcd",
	+ "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256",
	+ "MSRIndex": "0x3F6",
	+ "MSRValue": "0x100",
	+ "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles. Reported latency may be longer than just the memory latency. Available PDIST counters: 0",
	+ "SampleAfterValue": "503",
	+ "UMask": "0x1"
	+ },
	+ {
	+ "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.",
	+ "Counter": "1,2,3,4,5,6,7",
	+ "Data_LA": "1",
	+ "EventCode": "0xcd",
	+ "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32",
	+ "MSRIndex": "0x3F6",
	+ "MSRValue": "0x20",
	+ "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles. Reported latency may be longer than just the memory latency. Available PDIST counters: 0",
	+ "SampleAfterValue": "100007",
	+ "UMask": "0x1"
	+ },
	+ {
	+ "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.",
	+ "Counter": "1,2,3,4,5,6,7",
	+ "Data_LA": "1",
	+ "EventCode": "0xcd",
	+ "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4",
	+ "MSRIndex": "0x3F6",
	+ "MSRValue": "0x4",
	+ "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles. Reported latency may be longer than just the memory latency. Available PDIST counters: 0",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x1"
	+ },
	+ {
	+ "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.",
	+ "Counter": "1,2,3,4,5,6,7",
	+ "Data_LA": "1",
	+ "EventCode": "0xcd",
	+ "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512",
	+ "MSRIndex": "0x3F6",
	+ "MSRValue": "0x200",
	+ "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles. Reported latency may be longer than just the memory latency. Available PDIST counters: 0",
	+ "SampleAfterValue": "101",
	+ "UMask": "0x1"
	+ },
	+ {
	+ "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.",
	+ "Counter": "1,2,3,4,5,6,7",
	+ "Data_LA": "1",
	+ "EventCode": "0xcd",
	+ "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64",
	+ "MSRIndex": "0x3F6",
	+ "MSRValue": "0x40",
	+ "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles. Reported latency may be longer than just the memory latency. Available PDIST counters: 0",
	+ "SampleAfterValue": "2003",
	+ "UMask": "0x1"
	+ },
	+ {
	+ "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.",
	+ "Counter": "1,2,3,4,5,6,7",
	+ "Data_LA": "1",
	+ "EventCode": "0xcd",
	+ "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8",
	+ "MSRIndex": "0x3F6",
	+ "MSRValue": "0x8",
	+ "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles. Reported latency may be longer than just the memory latency. Available PDIST counters: 0",
	+ "SampleAfterValue": "50021",
	+ "UMask": "0x1"
	+ },
	+ {
	+ "BriefDescription": "Retired memory store access operations. A PDist event for PEBS Store Latency Facility.",
	+ "Counter": "0",
	+ "Data_LA": "1",
	+ "EventCode": "0xcd",
	+ "EventName": "MEM_TRANS_RETIRED.STORE_SAMPLE",
	+ "PublicDescription": "Counts Retired memory accesses with at least 1 store operation. This PEBS event is the precisely-distributed (PDist) trigger covering all stores uops for sampling by the PEBS Store Latency Facility. The facility is described in Intel SDM Volume 3 section 19.9.8 Available PDIST counters: 0",
	+ "SampleAfterValue": "1000003",
	+ "UMask": "0x2"
	+ },
	+ {
	+ "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x2A,0x2B",
	+ "EventName": "OCR.DEMAND_CODE_RD.DRAM",
	+ "MSRIndex": "0x1a6,0x1a7",
	+ "MSRValue": "0x73C000004",
	+ "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM. Available PDIST counters: 0",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x1"
	+ },
	+ {
	+ "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the local socket's L1, L2, or L3 caches.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x2A,0x2B",
	+ "EventName": "OCR.DEMAND_CODE_RD.L3_MISS",
	+ "MSRIndex": "0x1a6,0x1a7",
	+ "MSRValue": "0x3FBFC00004",
	+ "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the local socket's L1, L2, or L3 caches. Available PDIST counters: 0",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x1"
	+ },
	+ {
	+ "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x2A,0x2B",
	+ "EventName": "OCR.DEMAND_CODE_RD.LOCAL_DRAM",
	+ "MSRIndex": "0x1a6,0x1a7",
	+ "MSRValue": "0x104000004",
	+ "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster. Available PDIST counters: 0",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x1"
	+ },
	+ {
	+ "BriefDescription": "Counts demand data reads that were supplied by DRAM.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x2A,0x2B",
	+ "EventName": "OCR.DEMAND_DATA_RD.DRAM",
	+ "MSRIndex": "0x1a6,0x1a7",
	+ "MSRValue": "0x73C000001",
	+ "PublicDescription": "Counts demand data reads that were supplied by DRAM. Available PDIST counters: 0",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x1"
	+ },
	+ {
	+ "BriefDescription": "Counts demand data reads that were not supplied by the local socket's L1, L2, or L3 caches.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x2A,0x2B",
	+ "EventName": "OCR.DEMAND_DATA_RD.L3_MISS",
	+ "MSRIndex": "0x1a6,0x1a7",
	+ "MSRValue": "0x3FBFC00001",
	+ "PublicDescription": "Counts demand data reads that were not supplied by the local socket's L1, L2, or L3 caches. Available PDIST counters: 0",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x1"
	+ },
	+ {
	+ "BriefDescription": "Counts demand data reads that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x2A,0x2B",
	+ "EventName": "OCR.DEMAND_DATA_RD.LOCAL_DRAM",
	+ "MSRIndex": "0x1a6,0x1a7",
	+ "MSRValue": "0x104000001",
	+ "PublicDescription": "Counts demand data reads that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster. Available PDIST counters: 0",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x1"
	+ },
	+ {
	+ "BriefDescription": "Counts demand data reads that were supplied by DRAM attached to another socket.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x2A,0x2B",
	+ "EventName": "OCR.DEMAND_DATA_RD.REMOTE_DRAM",
	+ "MSRIndex": "0x1a6,0x1a7",
	+ "MSRValue": "0x730000001",
	+ "PublicDescription": "Counts demand data reads that were supplied by DRAM attached to another socket. Available PDIST counters: 0",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x1"
	+ },
	+ {
	+ "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x2A,0x2B",
	+ "EventName": "OCR.DEMAND_RFO.DRAM",
	+ "MSRIndex": "0x1a6,0x1a7",
	+ "MSRValue": "0x73C000002",
	+ "PublicDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM. Available PDIST counters: 0",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x1"
	+ },
	+ {
	+ "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x2A,0x2B",
	+ "EventName": "OCR.DEMAND_RFO.L3_MISS",
	+ "MSRIndex": "0x1a6,0x1a7",
	+ "MSRValue": "0x3F3FC00002",
	+ "PublicDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches. Available PDIST counters: 0",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x1"
	+ },
	+ {
	+ "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x2A,0x2B",
	+ "EventName": "OCR.DEMAND_RFO.LOCAL_DRAM",
	+ "MSRIndex": "0x1a6,0x1a7",
	+ "MSRValue": "0x104000002",
	+ "PublicDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster. Available PDIST counters: 0",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x1"
	+ },
	+ {
	+ "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x2A,0x2B",
	+ "EventName": "OCR.READS_TO_CORE.DRAM",
	+ "MSRIndex": "0x1a6,0x1a7",
	+ "MSRValue": "0x73C004477",
	+ "PublicDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM. Available PDIST counters: 0",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x1"
	+ },
	+ {
	+ "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the local socket's L1, L2, or L3 caches.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x2A,0x2B",
	+ "EventName": "OCR.READS_TO_CORE.L3_MISS",
	+ "MSRIndex": "0x1a6,0x1a7",
	+ "MSRValue": "0x3F3FC04477",
	+ "PublicDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the local socket's L1, L2, or L3 caches. Available PDIST counters: 0",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x1"
	+ },
	+ {
	+ "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x2A,0x2B",
	+ "EventName": "OCR.READS_TO_CORE.L3_MISS_LOCAL",
	+ "MSRIndex": "0x1a6,0x1a7",
	+ "MSRValue": "0x3F04C04477",
	+ "PublicDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally. Available PDIST counters: 0",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x1"
	+ },
	+ {
	+ "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that missed the L3 Cache and were supplied by the local socket (DRAM or PMM), whether or not in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts PMM or DRAM accesses that are controlled by the close or distant SNC Cluster. It does not count misses to the L3 which go to Local CXL Type 2 Memory or Local Non DRAM.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x2A,0x2B",
	+ "EventName": "OCR.READS_TO_CORE.L3_MISS_LOCAL_SOCKET",
	+ "MSRIndex": "0x1a6,0x1a7",
	+ "MSRValue": "0x70CC04477",
	+ "PublicDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that missed the L3 Cache and were supplied by the local socket (DRAM or PMM), whether or not in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts PMM or DRAM accesses that are controlled by the close or distant SNC Cluster. It does not count misses to the L3 which go to Local CXL Type 2 Memory or Local Non DRAM. Available PDIST counters: 0",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x1"
	+ },
	+ {
	+ "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x2A,0x2B",
	+ "EventName": "OCR.READS_TO_CORE.LOCAL_DRAM",
	+ "MSRIndex": "0x1a6,0x1a7",
	+ "MSRValue": "0x104004477",
	+ "PublicDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster. Available PDIST counters: 0",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x1"
	+ },
	+ {
	+ "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM attached to this socket, whether or not in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts DRAM accesses that are controlled by the close or distant SNC Cluster.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x2A,0x2B",
	+ "EventName": "OCR.READS_TO_CORE.LOCAL_SOCKET_DRAM",
	+ "MSRIndex": "0x1a6,0x1a7",
	+ "MSRValue": "0x70C004477",
	+ "PublicDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM attached to this socket, whether or not in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts DRAM accesses that are controlled by the close or distant SNC Cluster. Available PDIST counters: 0",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x1"
	+ },
	+ {
	+ "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM attached to another socket.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x2A,0x2B",
	+ "EventName": "OCR.READS_TO_CORE.REMOTE_DRAM",
	+ "MSRIndex": "0x1a6,0x1a7",
	+ "MSRValue": "0x730004477",
	+ "PublicDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM attached to another socket. Available PDIST counters: 0",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x1"
	+ },
	+ {
	+ "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM or PMM attached to another socket.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x2A,0x2B",
	+ "EventName": "OCR.READS_TO_CORE.REMOTE_MEMORY",
	+ "MSRIndex": "0x1a6,0x1a7",
	+ "MSRValue": "0x733004477",
	+ "PublicDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM or PMM attached to another socket. Available PDIST counters: 0",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x1"
	+ },
	+ {
	+ "BriefDescription": "Counts Demand RFOs, ItoM's, PREFECTHW's, Hardware RFO Prefetches to the L1/L2 and Streaming stores that likely resulted in a store to Memory (DRAM or PMM)",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x2A,0x2B",
	+ "EventName": "OCR.WRITE_ESTIMATE.MEMORY",
	+ "MSRIndex": "0x1a6,0x1a7",
	+ "MSRValue": "0xFBFF80822",
	+ "PublicDescription": "Counts Demand RFOs, ItoM's, PREFECTHW's, Hardware RFO Prefetches to the L1/L2 and Streaming stores that likely resulted in a store to Memory (DRAM or PMM) Available PDIST counters: 0",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x1"
	+ },
	+ {
	+ "BriefDescription": "Counts demand data read requests that miss the L3 cache.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x21",
	+ "EventName": "OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x10"
	+ },
	+ {
	+ "BriefDescription": "Cycles where data return is pending for a Demand Data Read request who miss L3 cache.",
	+ "Counter": "0,1,2,3",
	+ "CounterMask": "1",
	+ "EventCode": "0x20",
	+ "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_L3_MISS_DEMAND_DATA_RD",
	+ "PublicDescription": "Cycles with at least 1 Demand Data Read requests who miss L3 cache in the superQ.",
	+ "SampleAfterValue": "1000003",
	+ "UMask": "0x10"
	+ },
	+ {
	+ "BriefDescription": "For every cycle, increments by the number of demand data read requests pending that are known to have missed the L3 cache.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x20",
	+ "EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD",
	+ "PublicDescription": "For every cycle, increments by the number of demand data read requests pending that are known to have missed the L3 cache. Note that this does not capture all elapsed cycles while requests are outstanding - only cycles from when the requests were known by the requesting core to have missed the L3 cache.",
	+ "SampleAfterValue": "2000003",
	+ "UMask": "0x10"
	+ },
	+ {
	+ "BriefDescription": "Number of times an RTM execution aborted.",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xc9",
	+ "EventName": "RTM_RETIRED.ABORTED",
	+ "PublicDescription": "Counts the number of times RTM abort was triggered. Available PDIST counters: 0",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x4"
	+ },
	+ {
	+ "BriefDescription": "Number of times an RTM execution aborted due to none of the previous 3 categories (e.g. interrupt)",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xc9",
	+ "EventName": "RTM_RETIRED.ABORTED_EVENTS",
	+ "PublicDescription": "Counts the number of times an RTM execution aborted due to none of the previous 3 categories (e.g. interrupt).",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x80"
	+ },
	+ {
	+ "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xc9",
	+ "EventName": "RTM_RETIRED.ABORTED_MEM",
	+ "PublicDescription": "Counts the number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts).",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x8"
	+ },
	+ {
	+ "BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xc9",
	+ "EventName": "RTM_RETIRED.ABORTED_MEMTYPE",
	+ "PublicDescription": "Counts the number of times an RTM execution aborted due to incompatible memory type.",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x40"
	+ },
	+ {
	+ "BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xc9",
	+ "EventName": "RTM_RETIRED.ABORTED_UNFRIENDLY",
	+ "PublicDescription": "Counts the number of times an RTM execution aborted due to HLE-unfriendly instructions.",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x20"
	+ },
	+ {
	+ "BriefDescription": "Number of times an RTM execution successfully committed",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xc9",
	+ "EventName": "RTM_RETIRED.COMMIT",
	+ "PublicDescription": "Counts the number of times RTM commit succeeded.",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x2"
	+ },
	+ {
	+ "BriefDescription": "Number of times an RTM execution started.",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xc9",
	+ "EventName": "RTM_RETIRED.START",
	+ "PublicDescription": "Counts the number of times we entered an RTM region. Does not count nested transactions.",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x1"
	+ },
	+ {
	+ "BriefDescription": "Speculatively counts the number of TSX aborts due to a data capacity limitation for transactional reads",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x54",
	+ "EventName": "TX_MEM.ABORT_CAPACITY_READ",
	+ "PublicDescription": "Speculatively counts the number of Transactional Synchronization Extensions (TSX) aborts due to a data capacity limitation for transactional reads",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x80"
	+ },
	+ {
	+ "BriefDescription": "Speculatively counts the number of TSX aborts due to a data capacity limitation for transactional writes.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x54",
	+ "EventName": "TX_MEM.ABORT_CAPACITY_WRITE",
	+ "PublicDescription": "Speculatively counts the number of Transactional Synchronization Extensions (TSX) aborts due to a data capacity limitation for transactional writes.",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x2"
	+ },
	+ {
	+ "BriefDescription": "Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x54",
	+ "EventName": "TX_MEM.ABORT_CONFLICT",
	+ "PublicDescription": "Counts the number of times a TSX line had a cache conflict.",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x1"
	+ }
	+]
	\ No newline at end of file
	diff --git a/lib/libpmc/pmu-events/arch/x86/graniterapids/other.json b/lib/libpmc/pmu-events/arch/x86/graniterapids/other.json
	new file mode 100644
	--- /dev/null
	+++ b/lib/libpmc/pmu-events/arch/x86/graniterapids/other.json
	@@ -0,0 +1,65 @@
	+[
	+ {
	+ "BriefDescription": "Count all other hardware assists or traps that are not necessarily architecturally exposed (through a software handler) beyond FP; SSE-AVX mix and A/D assists who are counted by dedicated sub-events. the event also counts for Machine Ordering count.",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xc1",
	+ "EventName": "ASSISTS.HARDWARE",
	+ "PublicDescription": "Count all other hardware assists or traps that are not necessarily architecturally exposed (through a software handler) beyond FP; SSE-AVX mix and A/D assists who are counted by dedicated sub-events. This includes, but not limited to, assists at EXE or MEM uop writeback like AVX* load/store/gather/scatter (non-FP GSSE-assist ) , assists generated by ROB like PEBS and RTIT, Uncore trap, RAR (Remote Action Request) and CET (Control flow Enforcement Technology) assists. the event also counts for Machine Ordering count.",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x4"
	+ },
	+ {
	+ "BriefDescription": "ASSISTS.PAGE_FAULT",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xc1",
	+ "EventName": "ASSISTS.PAGE_FAULT",
	+ "SampleAfterValue": "1000003",
	+ "UMask": "0x8"
	+ },
	+ {
	+ "BriefDescription": "HW_INTERRUPTS.MASKED",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xcb",
	+ "EventName": "HW_INTERRUPTS.MASKED",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x2"
	+ },
	+ {
	+ "BriefDescription": "HW_INTERRUPTS.PENDING_AND_MASKED",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xcb",
	+ "EventName": "HW_INTERRUPTS.PENDING_AND_MASKED",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x4"
	+ },
	+ {
	+ "BriefDescription": "Number of hardware interrupts received by the processor.",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xcb",
	+ "EventName": "HW_INTERRUPTS.RECEIVED",
	+ "PublicDescription": "Counts the number of hardware interruptions received by the processor.",
	+ "SampleAfterValue": "203",
	+ "UMask": "0x1"
	+ },
	+ {
	+ "BriefDescription": "Counts streaming stores that have any type of response.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x2A,0x2B",
	+ "EventName": "OCR.STREAMING_WR.ANY_RESPONSE",
	+ "MSRIndex": "0x1a6,0x1a7",
	+ "MSRValue": "0x10800",
	+ "PublicDescription": "Counts streaming stores that have any type of response. Available PDIST counters: 0",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x1"
	+ },
	+ {
	+ "BriefDescription": "Cycles the uncore cannot take further requests",
	+ "Counter": "0,1,2,3",
	+ "CounterMask": "1",
	+ "EventCode": "0x2d",
	+ "EventName": "XQ.FULL_CYCLES",
	+ "PublicDescription": "number of cycles when the thread is active and the uncore cannot take any further requests (for example prefetches, loads or stores initiated by the Core that miss the L2 cache).",
	+ "SampleAfterValue": "1000003",
	+ "UMask": "0x1"
	+ }
	+]
	\ No newline at end of file
	diff --git a/lib/libpmc/pmu-events/arch/x86/graniterapids/pipeline.json b/lib/libpmc/pmu-events/arch/x86/graniterapids/pipeline.json
	new file mode 100644
	--- /dev/null
	+++ b/lib/libpmc/pmu-events/arch/x86/graniterapids/pipeline.json
	@@ -0,0 +1,1145 @@
	+[
	+ {
	+ "BriefDescription": "Cycles when divide unit is busy executing divide or square root operations.",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "CounterMask": "1",
	+ "EventCode": "0xb0",
	+ "EventName": "ARITH.DIV_ACTIVE",
	+ "PublicDescription": "Counts cycles when divide unit is busy executing divide or square root operations. Accounts for integer and floating-point operations.",
	+ "SampleAfterValue": "1000003",
	+ "UMask": "0x9"
	+ },
	+ {
	+ "BriefDescription": "This event counts the cycles the integer divider is busy.",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "CounterMask": "1",
	+ "EventCode": "0xb0",
	+ "EventName": "ARITH.IDIV_ACTIVE",
	+ "SampleAfterValue": "1000003",
	+ "UMask": "0x8"
	+ },
	+ {
	+ "BriefDescription": "Number of occurrences where a microcode assist is invoked by hardware.",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xc1",
	+ "EventName": "ASSISTS.ANY",
	+ "PublicDescription": "Counts the number of occurrences where a microcode assist is invoked by hardware. Examples include AD (page Access Dirty), FP and AVX related assists.",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x1b"
	+ },
	+ {
	+ "BriefDescription": "All branch instructions retired.",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xc4",
	+ "EventName": "BR_INST_RETIRED.ALL_BRANCHES",
	+ "PublicDescription": "Counts all branch instructions retired. Available PDIST counters: 0",
	+ "SampleAfterValue": "400009"
	+ },
	+ {
	+ "BriefDescription": "Conditional branch instructions retired.",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xc4",
	+ "EventName": "BR_INST_RETIRED.COND",
	+ "PublicDescription": "Counts conditional branch instructions retired. Available PDIST counters: 0",
	+ "SampleAfterValue": "400009",
	+ "UMask": "0x11"
	+ },
	+ {
	+ "BriefDescription": "Not taken branch instructions retired.",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xc4",
	+ "EventName": "BR_INST_RETIRED.COND_NTAKEN",
	+ "PublicDescription": "Counts not taken branch instructions retired. Available PDIST counters: 0",
	+ "SampleAfterValue": "400009",
	+ "UMask": "0x10"
	+ },
	+ {
	+ "BriefDescription": "Taken conditional branch instructions retired.",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xc4",
	+ "EventName": "BR_INST_RETIRED.COND_TAKEN",
	+ "PublicDescription": "Counts taken conditional branch instructions retired. Available PDIST counters: 0",
	+ "SampleAfterValue": "400009",
	+ "UMask": "0x1"
	+ },
	+ {
	+ "BriefDescription": "Far branch instructions retired.",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xc4",
	+ "EventName": "BR_INST_RETIRED.FAR_BRANCH",
	+ "PublicDescription": "Counts far branch instructions retired. Available PDIST counters: 0",
	+ "SampleAfterValue": "100007",
	+ "UMask": "0x40"
	+ },
	+ {
	+ "BriefDescription": "Indirect near branch instructions retired (excluding returns)",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xc4",
	+ "EventName": "BR_INST_RETIRED.INDIRECT",
	+ "PublicDescription": "Counts near indirect branch instructions retired excluding returns. TSX abort is an indirect branch. Available PDIST counters: 0",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x80"
	+ },
	+ {
	+ "BriefDescription": "Direct and indirect near call instructions retired.",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xc4",
	+ "EventName": "BR_INST_RETIRED.NEAR_CALL",
	+ "PublicDescription": "Counts both direct and indirect near call instructions retired. Available PDIST counters: 0",
	+ "SampleAfterValue": "100007",
	+ "UMask": "0x2"
	+ },
	+ {
	+ "BriefDescription": "Return instructions retired.",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xc4",
	+ "EventName": "BR_INST_RETIRED.NEAR_RETURN",
	+ "PublicDescription": "Counts return instructions retired. Available PDIST counters: 0",
	+ "SampleAfterValue": "100007",
	+ "UMask": "0x8"
	+ },
	+ {
	+ "BriefDescription": "Taken branch instructions retired.",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xc4",
	+ "EventName": "BR_INST_RETIRED.NEAR_TAKEN",
	+ "PublicDescription": "Counts taken branch instructions retired. Available PDIST counters: 0",
	+ "SampleAfterValue": "400009",
	+ "UMask": "0x20"
	+ },
	+ {
	+ "BriefDescription": "All mispredicted branch instructions retired.",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xc5",
	+ "EventName": "BR_MISP_RETIRED.ALL_BRANCHES",
	+ "PublicDescription": "Counts all the retired branch instructions that were mispredicted by the processor. A branch misprediction occurs when the processor incorrectly predicts the destination of the branch. When the misprediction is discovered at execution, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path. Available PDIST counters: 0",
	+ "SampleAfterValue": "400009"
	+ },
	+ {
	+ "BriefDescription": "All mispredicted branch instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch.",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xc5",
	+ "EventName": "BR_MISP_RETIRED.ALL_BRANCHES_COST",
	+ "PublicDescription": "All mispredicted branch instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch. Available PDIST counters: 0",
	+ "SampleAfterValue": "400009",
	+ "UMask": "0x44"
	+ },
	+ {
	+ "BriefDescription": "Mispredicted conditional branch instructions retired.",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xc5",
	+ "EventName": "BR_MISP_RETIRED.COND",
	+ "PublicDescription": "Counts mispredicted conditional branch instructions retired. Available PDIST counters: 0",
	+ "SampleAfterValue": "400009",
	+ "UMask": "0x11"
	+ },
	+ {
	+ "BriefDescription": "Mispredicted conditional branch instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch.",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xc5",
	+ "EventName": "BR_MISP_RETIRED.COND_COST",
	+ "PublicDescription": "Mispredicted conditional branch instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch. Available PDIST counters: 0",
	+ "SampleAfterValue": "400009",
	+ "UMask": "0x51"
	+ },
	+ {
	+ "BriefDescription": "Mispredicted non-taken conditional branch instructions retired.",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xc5",
	+ "EventName": "BR_MISP_RETIRED.COND_NTAKEN",
	+ "PublicDescription": "Counts the number of conditional branch instructions retired that were mispredicted and the branch direction was not taken. Available PDIST counters: 0",
	+ "SampleAfterValue": "400009",
	+ "UMask": "0x10"
	+ },
	+ {
	+ "BriefDescription": "Mispredicted non-taken conditional branch instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch.",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xc5",
	+ "EventName": "BR_MISP_RETIRED.COND_NTAKEN_COST",
	+ "PublicDescription": "Mispredicted non-taken conditional branch instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch. Available PDIST counters: 0",
	+ "RetirementLatencyMax": "888",
	+ "RetirementLatencyMean": "6.11",
	+ "RetirementLatencyMin": "0",
	+ "SampleAfterValue": "400009",
	+ "UMask": "0x50"
	+ },
	+ {
	+ "BriefDescription": "number of branch instructions retired that were mispredicted and taken.",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xc5",
	+ "EventName": "BR_MISP_RETIRED.COND_TAKEN",
	+ "PublicDescription": "Counts taken conditional mispredicted branch instructions retired. Available PDIST counters: 0",
	+ "SampleAfterValue": "400009",
	+ "UMask": "0x1"
	+ },
	+ {
	+ "BriefDescription": "Mispredicted taken conditional branch instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch.",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xc5",
	+ "EventName": "BR_MISP_RETIRED.COND_TAKEN_COST",
	+ "PublicDescription": "Mispredicted taken conditional branch instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch. Available PDIST counters: 0",
	+ "RetirementLatencyMax": "2750",
	+ "RetirementLatencyMean": "5.09",
	+ "RetirementLatencyMin": "0",
	+ "SampleAfterValue": "400009",
	+ "UMask": "0x41"
	+ },
	+ {
	+ "BriefDescription": "Miss-predicted near indirect branch instructions retired (excluding returns)",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xc5",
	+ "EventName": "BR_MISP_RETIRED.INDIRECT",
	+ "PublicDescription": "Counts miss-predicted near indirect branch instructions retired excluding returns. TSX abort is an indirect branch. Available PDIST counters: 0",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x80"
	+ },
	+ {
	+ "BriefDescription": "Mispredicted indirect CALL retired.",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xc5",
	+ "EventName": "BR_MISP_RETIRED.INDIRECT_CALL",
	+ "PublicDescription": "Counts retired mispredicted indirect (near taken) CALL instructions, including both register and memory indirect. Available PDIST counters: 0",
	+ "SampleAfterValue": "400009",
	+ "UMask": "0x2"
	+ },
	+ {
	+ "BriefDescription": "Mispredicted indirect CALL retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch.",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xc5",
	+ "EventName": "BR_MISP_RETIRED.INDIRECT_CALL_COST",
	+ "PublicDescription": "Mispredicted indirect CALL retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch. Available PDIST counters: 0",
	+ "RetirementLatencyMax": "703",
	+ "RetirementLatencyMean": "15.56",
	+ "RetirementLatencyMin": "0",
	+ "SampleAfterValue": "400009",
	+ "UMask": "0x42"
	+ },
	+ {
	+ "BriefDescription": "Mispredicted near indirect branch instructions retired (excluding returns). This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch.",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xc5",
	+ "EventName": "BR_MISP_RETIRED.INDIRECT_COST",
	+ "PublicDescription": "Mispredicted near indirect branch instructions retired (excluding returns). This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch. Available PDIST counters: 0",
	+ "RetirementLatencyMax": "1562",
	+ "RetirementLatencyMean": "11.07",
	+ "RetirementLatencyMin": "0",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0xc0"
	+ },
	+ {
	+ "BriefDescription": "Number of near branch instructions retired that were mispredicted and taken.",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xc5",
	+ "EventName": "BR_MISP_RETIRED.NEAR_TAKEN",
	+ "PublicDescription": "Counts number of near branch instructions retired that were mispredicted and taken. Available PDIST counters: 0",
	+ "SampleAfterValue": "400009",
	+ "UMask": "0x20"
	+ },
	+ {
	+ "BriefDescription": "Mispredicted taken near branch instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch.",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xc5",
	+ "EventName": "BR_MISP_RETIRED.NEAR_TAKEN_COST",
	+ "PublicDescription": "Mispredicted taken near branch instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch. Available PDIST counters: 0",
	+ "SampleAfterValue": "400009",
	+ "UMask": "0x60"
	+ },
	+ {
	+ "BriefDescription": "This event counts the number of mispredicted ret instructions retired. Non PEBS",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xc5",
	+ "EventName": "BR_MISP_RETIRED.RET",
	+ "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts mispredicted return instructions retired. Available PDIST counters: 0",
	+ "SampleAfterValue": "100007",
	+ "UMask": "0x8"
	+ },
	+ {
	+ "BriefDescription": "Mispredicted ret instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch.",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xc5",
	+ "EventName": "BR_MISP_RETIRED.RET_COST",
	+ "PublicDescription": "Mispredicted ret instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch. Available PDIST counters: 0",
	+ "RetirementLatencyMax": "1082",
	+ "RetirementLatencyMean": "32.37",
	+ "RetirementLatencyMin": "9",
	+ "SampleAfterValue": "100007",
	+ "UMask": "0x48"
	+ },
	+ {
	+ "BriefDescription": "Core clocks when the thread is in the C0.1 light-weight slower wakeup time but more power saving optimized state.",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xec",
	+ "EventName": "CPU_CLK_UNHALTED.C01",
	+ "PublicDescription": "Counts core clocks when the thread is in the C0.1 light-weight slower wakeup time but more power saving optimized state. This state can be entered via the TPAUSE or UMWAIT instructions.",
	+ "SampleAfterValue": "2000003",
	+ "UMask": "0x10"
	+ },
	+ {
	+ "BriefDescription": "Core clocks when the thread is in the C0.2 light-weight faster wakeup time but less power saving optimized state.",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xec",
	+ "EventName": "CPU_CLK_UNHALTED.C02",
	+ "PublicDescription": "Counts core clocks when the thread is in the C0.2 light-weight faster wakeup time but less power saving optimized state. This state can be entered via the TPAUSE or UMWAIT instructions.",
	+ "SampleAfterValue": "2000003",
	+ "UMask": "0x20"
	+ },
	+ {
	+ "BriefDescription": "Core clocks when the thread is in the C0.1 or C0.2 or running a PAUSE in C0 ACPI state.",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xec",
	+ "EventName": "CPU_CLK_UNHALTED.C0_WAIT",
	+ "PublicDescription": "Counts core clocks when the thread is in the C0.1 or C0.2 power saving optimized states (TPAUSE or UMWAIT instructions) or running the PAUSE instruction.",
	+ "SampleAfterValue": "2000003",
	+ "UMask": "0x70"
	+ },
	+ {
	+ "BriefDescription": "Cycle counts are evenly distributed between active threads in the Core.",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xec",
	+ "EventName": "CPU_CLK_UNHALTED.DISTRIBUTED",
	+ "PublicDescription": "This event distributes cycle counts between active hyperthreads, i.e., those in C0. A hyperthread becomes inactive when it executes the HLT or MWAIT instructions. If all other hyperthreads are inactive (or disabled or do not exist), all counts are attributed to this hyperthread. To obtain the full count when the Core is active, sum the counts from each hyperthread.",
	+ "SampleAfterValue": "2000003",
	+ "UMask": "0x2"
	+ },
	+ {
	+ "BriefDescription": "Core crystal clock cycles when this thread is unhalted and the other thread is halted.",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0x3c",
	+ "EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE",
	+ "PublicDescription": "Counts Core crystal clock cycles when current thread is unhalted and the other thread is halted.",
	+ "SampleAfterValue": "25003",
	+ "UMask": "0x2"
	+ },
	+ {
	+ "BriefDescription": "CPU_CLK_UNHALTED.PAUSE",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xec",
	+ "EventName": "CPU_CLK_UNHALTED.PAUSE",
	+ "SampleAfterValue": "2000003",
	+ "UMask": "0x40"
	+ },
	+ {
	+ "BriefDescription": "CPU_CLK_UNHALTED.PAUSE_INST",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "CounterMask": "1",
	+ "EdgeDetect": "1",
	+ "EventCode": "0xec",
	+ "EventName": "CPU_CLK_UNHALTED.PAUSE_INST",
	+ "SampleAfterValue": "2000003",
	+ "UMask": "0x40"
	+ },
	+ {
	+ "BriefDescription": "Core crystal clock cycles. Cycle counts are evenly distributed between active threads in the Core.",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0x3c",
	+ "EventName": "CPU_CLK_UNHALTED.REF_DISTRIBUTED",
	+ "PublicDescription": "This event distributes Core crystal clock cycle counts between active hyperthreads, i.e., those in C0 sleep-state. A hyperthread becomes inactive when it executes the HLT or MWAIT instructions. If one thread is active in a core, all counts are attributed to this hyperthread. To obtain the full count when the Core is active, sum the counts from each hyperthread.",
	+ "SampleAfterValue": "2000003",
	+ "UMask": "0x8"
	+ },
	+ {
	+ "BriefDescription": "Reference cycles when the core is not in halt state.",
	+ "Counter": "Fixed counter 2",
	+ "EventName": "CPU_CLK_UNHALTED.REF_TSC",
	+ "PublicDescription": "Counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. It is counted on a dedicated fixed counter, leaving the eight programmable counters available for other events. Note: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'. The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'. After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case.",
	+ "SampleAfterValue": "2000003",
	+ "UMask": "0x3"
	+ },
	+ {
	+ "BriefDescription": "Reference cycles when the core is not in halt state.",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0x3c",
	+ "EventName": "CPU_CLK_UNHALTED.REF_TSC_P",
	+ "PublicDescription": "Counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. Note: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'. The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'. After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case.",
	+ "SampleAfterValue": "2000003",
	+ "UMask": "0x1"
	+ },
	+ {
	+ "BriefDescription": "Core cycles when the thread is not in halt state",
	+ "Counter": "Fixed counter 1",
	+ "EventName": "CPU_CLK_UNHALTED.THREAD",
	+ "PublicDescription": "Counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the eight programmable counters available for other events.",
	+ "SampleAfterValue": "2000003",
	+ "UMask": "0x2"
	+ },
	+ {
	+ "BriefDescription": "Thread cycles when thread is not in halt state",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0x3c",
	+ "EventName": "CPU_CLK_UNHALTED.THREAD_P",
	+ "PublicDescription": "This is an architectural event that counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling. For this reason, this event may have a changing ratio with regards to wall clock time.",
	+ "SampleAfterValue": "2000003"
	+ },
	+ {
	+ "BriefDescription": "Cycles while L1 cache miss demand load is outstanding.",
	+ "Counter": "0,1,2,3",
	+ "CounterMask": "8",
	+ "EventCode": "0xa3",
	+ "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS",
	+ "SampleAfterValue": "1000003",
	+ "UMask": "0x8"
	+ },
	+ {
	+ "BriefDescription": "Cycles while L2 cache miss demand load is outstanding.",
	+ "Counter": "0,1,2,3",
	+ "CounterMask": "1",
	+ "EventCode": "0xa3",
	+ "EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS",
	+ "SampleAfterValue": "1000003",
	+ "UMask": "0x1"
	+ },
	+ {
	+ "BriefDescription": "Cycles while memory subsystem has an outstanding load.",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "CounterMask": "16",
	+ "EventCode": "0xa3",
	+ "EventName": "CYCLE_ACTIVITY.CYCLES_MEM_ANY",
	+ "SampleAfterValue": "1000003",
	+ "UMask": "0x10"
	+ },
	+ {
	+ "BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.",
	+ "Counter": "0,1,2,3",
	+ "CounterMask": "12",
	+ "EventCode": "0xa3",
	+ "EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS",
	+ "SampleAfterValue": "1000003",
	+ "UMask": "0xc"
	+ },
	+ {
	+ "BriefDescription": "Execution stalls while L2 cache miss demand load is outstanding.",
	+ "Counter": "0,1,2,3",
	+ "CounterMask": "5",
	+ "EventCode": "0xa3",
	+ "EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS",
	+ "SampleAfterValue": "1000003",
	+ "UMask": "0x5"
	+ },
	+ {
	+ "BriefDescription": "Total execution stalls.",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "CounterMask": "4",
	+ "EventCode": "0xa3",
	+ "EventName": "CYCLE_ACTIVITY.STALLS_TOTAL",
	+ "SampleAfterValue": "1000003",
	+ "UMask": "0x4"
	+ },
	+ {
	+ "BriefDescription": "Counts the cycles where the AMX (Advance Matrix Extension) unit is busy performing an operation.",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xb7",
	+ "EventName": "EXE.AMX_BUSY",
	+ "SampleAfterValue": "2000003",
	+ "UMask": "0x2"
	+ },
	+ {
	+ "BriefDescription": "Cycles total of 1 uop is executed on all ports and Reservation Station was not empty.",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xa6",
	+ "EventName": "EXE_ACTIVITY.1_PORTS_UTIL",
	+ "PublicDescription": "Counts cycles during which a total of 1 uop was executed on all ports and Reservation Station (RS) was not empty.",
	+ "SampleAfterValue": "2000003",
	+ "UMask": "0x2"
	+ },
	+ {
	+ "BriefDescription": "Cycles total of 2 or 3 uops are executed on all ports and Reservation Station (RS) was not empty.",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xa6",
	+ "EventName": "EXE_ACTIVITY.2_3_PORTS_UTIL",
	+ "SampleAfterValue": "2000003",
	+ "UMask": "0xc"
	+ },
	+ {
	+ "BriefDescription": "Cycles total of 2 uops are executed on all ports and Reservation Station was not empty.",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xa6",
	+ "EventName": "EXE_ACTIVITY.2_PORTS_UTIL",
	+ "PublicDescription": "Counts cycles during which a total of 2 uops were executed on all ports and Reservation Station (RS) was not empty.",
	+ "SampleAfterValue": "2000003",
	+ "UMask": "0x4"
	+ },
	+ {
	+ "BriefDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station was not empty.",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xa6",
	+ "EventName": "EXE_ACTIVITY.3_PORTS_UTIL",
	+ "PublicDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station (RS) was not empty.",
	+ "SampleAfterValue": "2000003",
	+ "UMask": "0x8"
	+ },
	+ {
	+ "BriefDescription": "Cycles total of 4 uops are executed on all ports and Reservation Station was not empty.",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xa6",
	+ "EventName": "EXE_ACTIVITY.4_PORTS_UTIL",
	+ "PublicDescription": "Cycles total of 4 uops are executed on all ports and Reservation Station (RS) was not empty.",
	+ "SampleAfterValue": "2000003",
	+ "UMask": "0x10"
	+ },
	+ {
	+ "BriefDescription": "Execution stalls while memory subsystem has an outstanding load.",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "CounterMask": "5",
	+ "EventCode": "0xa6",
	+ "EventName": "EXE_ACTIVITY.BOUND_ON_LOADS",
	+ "SampleAfterValue": "2000003",
	+ "UMask": "0x21"
	+ },
	+ {
	+ "BriefDescription": "Cycles where the Store Buffer was full and no loads caused an execution stall.",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "CounterMask": "2",
	+ "EventCode": "0xa6",
	+ "EventName": "EXE_ACTIVITY.BOUND_ON_STORES",
	+ "PublicDescription": "Counts cycles where the Store Buffer was full and no loads caused an execution stall.",
	+ "SampleAfterValue": "1000003",
	+ "UMask": "0x40"
	+ },
	+ {
	+ "BriefDescription": "Cycles no uop executed while RS was not empty, the SB was not full and there was no outstanding load.",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xa6",
	+ "EventName": "EXE_ACTIVITY.EXE_BOUND_0_PORTS",
	+ "PublicDescription": "Number of cycles total of 0 uops executed on all ports, Reservation Station (RS) was not empty, the Store Buffer (SB) was not full and there was no outstanding load.",
	+ "SampleAfterValue": "1000003",
	+ "UMask": "0x80"
	+ },
	+ {
	+ "BriefDescription": "Instruction decoders utilized in a cycle",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x75",
	+ "EventName": "INST_DECODED.DECODERS",
	+ "PublicDescription": "Number of decoders utilized in a cycle when the MITE (legacy decode pipeline) fetches instructions.",
	+ "SampleAfterValue": "2000003",
	+ "UMask": "0x1"
	+ },
	+ {
	+ "BriefDescription": "Number of instructions retired. Fixed Counter - architectural event",
	+ "Counter": "Fixed counter 0",
	+ "EventName": "INST_RETIRED.ANY",
	+ "PublicDescription": "Counts the number of X86 instructions retired - an Architectural PerfMon event. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter freeing up programmable counters to count other events. INST_RETIRED.ANY_P is counted by a programmable counter. Available PDIST counters: 32",
	+ "SampleAfterValue": "2000003",
	+ "UMask": "0x1"
	+ },
	+ {
	+ "BriefDescription": "Number of instructions retired. General Counter - architectural event",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xc0",
	+ "EventName": "INST_RETIRED.ANY_P",
	+ "PublicDescription": "Counts the number of X86 instructions retired - an Architectural PerfMon event. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter freeing up programmable counters to count other events. INST_RETIRED.ANY_P is counted by a programmable counter.",
	+ "SampleAfterValue": "2000003"
	+ },
	+ {
	+ "BriefDescription": "INST_RETIRED.MACRO_FUSED",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xc0",
	+ "EventName": "INST_RETIRED.MACRO_FUSED",
	+ "SampleAfterValue": "2000003",
	+ "UMask": "0x10"
	+ },
	+ {
	+ "BriefDescription": "Retired NOP instructions.",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xc0",
	+ "EventName": "INST_RETIRED.NOP",
	+ "PublicDescription": "Counts all retired NOP or ENDBR32/64 or PREFETCHIT0/1 instructions",
	+ "SampleAfterValue": "2000003",
	+ "UMask": "0x2"
	+ },
	+ {
	+ "BriefDescription": "Precise instruction retired with PEBS precise-distribution",
	+ "Counter": "Fixed counter 0",
	+ "EventName": "INST_RETIRED.PREC_DIST",
	+ "PublicDescription": "A version of INST_RETIRED that allows for a precise distribution of samples across instructions retired. It utilizes the Precise Distribution of Instructions Retired (PDIR++) feature to fix bias in how retired instructions get sampled. Use on Fixed Counter 0. Available PDIST counters: 32",
	+ "SampleAfterValue": "2000003",
	+ "UMask": "0x1"
	+ },
	+ {
	+ "BriefDescription": "Iterations of Repeat string retired instructions.",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xc0",
	+ "EventName": "INST_RETIRED.REP_ITERATION",
	+ "PublicDescription": "Number of iterations of Repeat (REP) string retired instructions such as MOVS, CMPS, and SCAS. Each has a byte, word, and doubleword version and string instructions can be repeated using a repetition prefix, REP, that allows their architectural execution to be repeated a number of times as specified by the RCX register. Note the number of iterations is implementation-dependent.",
	+ "SampleAfterValue": "2000003",
	+ "UMask": "0x8"
	+ },
	+ {
	+ "BriefDescription": "Clears speculative count",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "CounterMask": "1",
	+ "EdgeDetect": "1",
	+ "EventCode": "0xad",
	+ "EventName": "INT_MISC.CLEARS_COUNT",
	+ "PublicDescription": "Counts the number of speculative clears due to any type of branch misprediction or machine clears",
	+ "SampleAfterValue": "500009",
	+ "UMask": "0x1"
	+ },
	+ {
	+ "BriefDescription": "Counts cycles after recovery from a branch misprediction or machine clear till the first uop is issued from the resteered path.",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xad",
	+ "EventName": "INT_MISC.CLEAR_RESTEER_CYCLES",
	+ "PublicDescription": "Cycles after recovery from a branch misprediction or machine clear till the first uop is issued from the resteered path.",
	+ "SampleAfterValue": "500009",
	+ "UMask": "0x80"
	+ },
	+ {
	+ "BriefDescription": "INT_MISC.MBA_STALLS",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xad",
	+ "EventName": "INT_MISC.MBA_STALLS",
	+ "SampleAfterValue": "1000003",
	+ "UMask": "0x20"
	+ },
	+ {
	+ "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for this thread",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xad",
	+ "EventName": "INT_MISC.RECOVERY_CYCLES",
	+ "PublicDescription": "Counts core cycles when the Resource allocator was stalled due to recovery from an earlier branch misprediction or machine clear event.",
	+ "SampleAfterValue": "500009",
	+ "UMask": "0x1"
	+ },
	+ {
	+ "BriefDescription": "Bubble cycles of BAClear (Unknown Branch).",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xad",
	+ "EventName": "INT_MISC.UNKNOWN_BRANCH_CYCLES",
	+ "MSRIndex": "0x3F7",
	+ "MSRValue": "0x7",
	+ "SampleAfterValue": "1000003",
	+ "UMask": "0x40"
	+ },
	+ {
	+ "BriefDescription": "TMA slots where uops got dropped",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xad",
	+ "EventName": "INT_MISC.UOP_DROPPING",
	+ "PublicDescription": "Estimated number of Top-down Microarchitecture Analysis slots that got dropped due to non front-end reasons",
	+ "SampleAfterValue": "1000003",
	+ "UMask": "0x10"
	+ },
	+ {
	+ "BriefDescription": "INT_VEC_RETIRED.128BIT",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xe7",
	+ "EventName": "INT_VEC_RETIRED.128BIT",
	+ "SampleAfterValue": "1000003",
	+ "UMask": "0x13"
	+ },
	+ {
	+ "BriefDescription": "INT_VEC_RETIRED.256BIT",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xe7",
	+ "EventName": "INT_VEC_RETIRED.256BIT",
	+ "SampleAfterValue": "1000003",
	+ "UMask": "0xac"
	+ },
	+ {
	+ "BriefDescription": "integer ADD, SUB, SAD 128-bit vector instructions.",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xe7",
	+ "EventName": "INT_VEC_RETIRED.ADD_128",
	+ "PublicDescription": "Number of retired integer ADD/SUB (regular or horizontal), SAD 128-bit vector instructions.",
	+ "SampleAfterValue": "1000003",
	+ "UMask": "0x3"
	+ },
	+ {
	+ "BriefDescription": "integer ADD, SUB, SAD 256-bit vector instructions.",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xe7",
	+ "EventName": "INT_VEC_RETIRED.ADD_256",
	+ "PublicDescription": "Number of retired integer ADD/SUB (regular or horizontal), SAD 256-bit vector instructions.",
	+ "SampleAfterValue": "1000003",
	+ "UMask": "0xc"
	+ },
	+ {
	+ "BriefDescription": "INT_VEC_RETIRED.MUL_256",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xe7",
	+ "EventName": "INT_VEC_RETIRED.MUL_256",
	+ "SampleAfterValue": "1000003",
	+ "UMask": "0x80"
	+ },
	+ {
	+ "BriefDescription": "INT_VEC_RETIRED.SHUFFLES",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xe7",
	+ "EventName": "INT_VEC_RETIRED.SHUFFLES",
	+ "SampleAfterValue": "1000003",
	+ "UMask": "0x40"
	+ },
	+ {
	+ "BriefDescription": "INT_VEC_RETIRED.VNNI_128",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xe7",
	+ "EventName": "INT_VEC_RETIRED.VNNI_128",
	+ "SampleAfterValue": "1000003",
	+ "UMask": "0x10"
	+ },
	+ {
	+ "BriefDescription": "INT_VEC_RETIRED.VNNI_256",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xe7",
	+ "EventName": "INT_VEC_RETIRED.VNNI_256",
	+ "SampleAfterValue": "1000003",
	+ "UMask": "0x20"
	+ },
	+ {
	+ "BriefDescription": "False dependencies in MOB due to partial compare on address.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x03",
	+ "EventName": "LD_BLOCKS.ADDRESS_ALIAS",
	+ "PublicDescription": "Counts the number of times a load got blocked due to false dependencies in MOB due to partial compare on address.",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x4"
	+ },
	+ {
	+ "BriefDescription": "The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x03",
	+ "EventName": "LD_BLOCKS.NO_SR",
	+ "PublicDescription": "Counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x88"
	+ },
	+ {
	+ "BriefDescription": "Loads blocked due to overlapping with a preceding store that cannot be forwarded.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x03",
	+ "EventName": "LD_BLOCKS.STORE_FORWARD",
	+ "PublicDescription": "Counts the number of times where store forwarding was prevented for a load operation. The most common case is a load blocked due to the address of memory access (partially) overlapping with a preceding uncompleted store. Note: See the table of not supported store forwards in the Optimization Guide.",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x82"
	+ },
	+ {
	+ "BriefDescription": "Counts the number of demand load dispatches that hit L1D fill buffer (FB) allocated for software prefetch.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x4c",
	+ "EventName": "LOAD_HIT_PREFETCH.SWPF",
	+ "PublicDescription": "Counts all software-prefetch load dispatches that hit the fill buffer (FB) allocated for the software prefetch. It can also be incremented by some lock instructions. So it should only be used with profiling so that the locks can be excluded by ASM (Assembly File) inspection of the nearby instructions.",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x1"
	+ },
	+ {
	+ "BriefDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder.",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "CounterMask": "1",
	+ "EventCode": "0xa8",
	+ "EventName": "LSD.CYCLES_ACTIVE",
	+ "PublicDescription": "Counts the cycles when at least one uop is delivered by the LSD (Loop-stream detector).",
	+ "SampleAfterValue": "2000003",
	+ "UMask": "0x1"
	+ },
	+ {
	+ "BriefDescription": "Cycles optimal number of Uops delivered by the LSD, but did not come from the decoder.",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "CounterMask": "6",
	+ "EventCode": "0xa8",
	+ "EventName": "LSD.CYCLES_OK",
	+ "PublicDescription": "Counts the cycles when optimal number of uops is delivered by the LSD (Loop-stream detector).",
	+ "SampleAfterValue": "2000003",
	+ "UMask": "0x1"
	+ },
	+ {
	+ "BriefDescription": "Number of Uops delivered by the LSD.",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xa8",
	+ "EventName": "LSD.UOPS",
	+ "PublicDescription": "Counts the number of uops delivered to the back-end by the LSD(Loop Stream Detector).",
	+ "SampleAfterValue": "2000003",
	+ "UMask": "0x1"
	+ },
	+ {
	+ "BriefDescription": "Number of machine clears (nukes) of any type.",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "CounterMask": "1",
	+ "EdgeDetect": "1",
	+ "EventCode": "0xc3",
	+ "EventName": "MACHINE_CLEARS.COUNT",
	+ "PublicDescription": "Counts the number of machine clears (nukes) of any type.",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x1"
	+ },
	+ {
	+ "BriefDescription": "Self-modifying code (SMC) detected.",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xc3",
	+ "EventName": "MACHINE_CLEARS.SMC",
	+ "PublicDescription": "Counts self-modifying code (SMC) detected, which causes a machine clear.",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x4"
	+ },
	+ {
	+ "BriefDescription": "LFENCE instructions retired",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xe0",
	+ "EventName": "MISC2_RETIRED.LFENCE",
	+ "PublicDescription": "number of LFENCE retired instructions",
	+ "SampleAfterValue": "400009",
	+ "UMask": "0x20"
	+ },
	+ {
	+ "BriefDescription": "Increments whenever there is an update to the LBR array.",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xcc",
	+ "EventName": "MISC_RETIRED.LBR_INSERTS",
	+ "PublicDescription": "Increments when an entry is added to the Last Branch Record (LBR) array (or removed from the array in case of RETURNs in call stack mode). The event requires LBR enable via IA32_DEBUGCTL MSR and branch type selection via MSR_LBR_SELECT.",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x20"
	+ },
	+ {
	+ "BriefDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xa2",
	+ "EventName": "RESOURCE_STALLS.SB",
	+ "PublicDescription": "Counts allocation stall cycles caused by the store buffer (SB) being full. This counts cycles that the pipeline back-end blocked uop delivery from the front-end.",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x8"
	+ },
	+ {
	+ "BriefDescription": "Counts cycles where the pipeline is stalled due to serializing operations.",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xa2",
	+ "EventName": "RESOURCE_STALLS.SCOREBOARD",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x2"
	+ },
	+ {
	+ "BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread.",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xa5",
	+ "EventName": "RS.EMPTY",
	+ "PublicDescription": "Counts cycles during which the reservation station (RS) is empty for this logical processor. This is usually caused when the front-end pipeline runs into starvation periods (e.g. branch mispredictions or i-cache misses)",
	+ "SampleAfterValue": "1000003",
	+ "UMask": "0x7"
	+ },
	+ {
	+ "BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty.",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "CounterMask": "1",
	+ "EdgeDetect": "1",
	+ "EventCode": "0xa5",
	+ "EventName": "RS.EMPTY_COUNT",
	+ "Invert": "1",
	+ "PublicDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to closely sample on front-end latency issues (see the FRONTEND_RETIRED event of designated precise events)",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x7"
	+ },
	+ {
	+ "BriefDescription": "Cycles when RS was empty and a resource allocation stall is asserted",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xa5",
	+ "EventName": "RS.EMPTY_RESOURCE",
	+ "SampleAfterValue": "1000003",
	+ "UMask": "0x1"
	+ },
	+ {
	+ "BriefDescription": "This event counts a subset of the Topdown Slots event that were not consumed by the back-end pipeline due to lack of back-end resources, as a result of memory subsystem delays, execution units limitations, or other conditions.",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xa4",
	+ "EventName": "TOPDOWN.BACKEND_BOUND_SLOTS",
	+ "PublicDescription": "This event counts a subset of the Topdown Slots event that were not consumed by the back-end pipeline due to lack of back-end resources, as a result of memory subsystem delays, execution units limitations, or other conditions. The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core, in processors that support Intel Hyper-Threading Technology. Software can use this event as the numerator for the Backend Bound metric (or top-level category) of the Top-down Microarchitecture Analysis method.",
	+ "SampleAfterValue": "10000003",
	+ "UMask": "0x2"
	+ },
	+ {
	+ "BriefDescription": "TMA slots wasted due to incorrect speculations.",
	+ "Counter": "0",
	+ "EventCode": "0xa4",
	+ "EventName": "TOPDOWN.BAD_SPEC_SLOTS",
	+ "PublicDescription": "Number of slots of TMA method that were wasted due to incorrect speculation. It covers all types of control-flow or data-related mis-speculations.",
	+ "SampleAfterValue": "10000003",
	+ "UMask": "0x4"
	+ },
	+ {
	+ "BriefDescription": "TMA slots wasted due to incorrect speculation by branch mispredictions",
	+ "Counter": "0",
	+ "EventCode": "0xa4",
	+ "EventName": "TOPDOWN.BR_MISPREDICT_SLOTS",
	+ "PublicDescription": "Number of TMA slots that were wasted due to incorrect speculation by (any type of) branch mispredictions. This event estimates number of speculative operations that were issued but not retired as well as the out-of-order engine recovery past a branch misprediction.",
	+ "SampleAfterValue": "10000003",
	+ "UMask": "0x8"
	+ },
	+ {
	+ "BriefDescription": "TOPDOWN.MEMORY_BOUND_SLOTS",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xa4",
	+ "EventName": "TOPDOWN.MEMORY_BOUND_SLOTS",
	+ "SampleAfterValue": "10000003",
	+ "UMask": "0x10"
	+ },
	+ {
	+ "BriefDescription": "TMA slots available for an unhalted logical processor. Fixed counter - architectural event",
	+ "Counter": "Fixed counter 3",
	+ "EventName": "TOPDOWN.SLOTS",
	+ "PublicDescription": "Number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method (TMA). The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core. Software can use this event as the denominator for the top-level metrics of the TMA method. This architectural event is counted on a designated fixed counter (Fixed Counter 3).",
	+ "SampleAfterValue": "10000003",
	+ "UMask": "0x4"
	+ },
	+ {
	+ "BriefDescription": "TMA slots available for an unhalted logical processor. General counter - architectural event",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xa4",
	+ "EventName": "TOPDOWN.SLOTS_P",
	+ "PublicDescription": "Counts the number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method. The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core.",
	+ "SampleAfterValue": "10000003",
	+ "UMask": "0x1"
	+ },
	+ {
	+ "BriefDescription": "Number of non dec-by-all uops decoded by decoder",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x76",
	+ "EventName": "UOPS_DECODED.DEC0_UOPS",
	+ "PublicDescription": "This event counts the number of not dec-by-all uops decoded by decoder 0.",
	+ "SampleAfterValue": "1000003",
	+ "UMask": "0x1"
	+ },
	+ {
	+ "BriefDescription": "Uops executed on port 0",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xb2",
	+ "EventName": "UOPS_DISPATCHED.PORT_0",
	+ "PublicDescription": "Number of uops dispatch to execution port 0.",
	+ "SampleAfterValue": "2000003",
	+ "UMask": "0x1"
	+ },
	+ {
	+ "BriefDescription": "Uops executed on port 1",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xb2",
	+ "EventName": "UOPS_DISPATCHED.PORT_1",
	+ "PublicDescription": "Number of uops dispatch to execution port 1.",
	+ "SampleAfterValue": "2000003",
	+ "UMask": "0x2"
	+ },
	+ {
	+ "BriefDescription": "Uops executed on ports 2, 3 and 10",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xb2",
	+ "EventName": "UOPS_DISPATCHED.PORT_2_3_10",
	+ "PublicDescription": "Number of uops dispatch to execution ports 2, 3 and 10",
	+ "SampleAfterValue": "2000003",
	+ "UMask": "0x4"
	+ },
	+ {
	+ "BriefDescription": "Uops executed on ports 4 and 9",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xb2",
	+ "EventName": "UOPS_DISPATCHED.PORT_4_9",
	+ "PublicDescription": "Number of uops dispatch to execution ports 4 and 9",
	+ "SampleAfterValue": "2000003",
	+ "UMask": "0x10"
	+ },
	+ {
	+ "BriefDescription": "Uops executed on ports 5 and 11",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xb2",
	+ "EventName": "UOPS_DISPATCHED.PORT_5_11",
	+ "PublicDescription": "Number of uops dispatch to execution ports 5 and 11",
	+ "SampleAfterValue": "2000003",
	+ "UMask": "0x20"
	+ },
	+ {
	+ "BriefDescription": "Uops executed on port 6",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xb2",
	+ "EventName": "UOPS_DISPATCHED.PORT_6",
	+ "PublicDescription": "Number of uops dispatch to execution port 6.",
	+ "SampleAfterValue": "2000003",
	+ "UMask": "0x40"
	+ },
	+ {
	+ "BriefDescription": "Uops executed on ports 7 and 8",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xb2",
	+ "EventName": "UOPS_DISPATCHED.PORT_7_8",
	+ "PublicDescription": "Number of uops dispatch to execution ports 7 and 8.",
	+ "SampleAfterValue": "2000003",
	+ "UMask": "0x80"
	+ },
	+ {
	+ "BriefDescription": "Number of uops executed on the core.",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xb1",
	+ "EventName": "UOPS_EXECUTED.CORE",
	+ "PublicDescription": "Counts the number of uops executed from any thread.",
	+ "SampleAfterValue": "2000003",
	+ "UMask": "0x2"
	+ },
	+ {
	+ "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "CounterMask": "1",
	+ "EventCode": "0xb1",
	+ "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1",
	+ "PublicDescription": "Counts cycles when at least 1 micro-op is executed from any thread on physical core.",
	+ "SampleAfterValue": "2000003",
	+ "UMask": "0x2"
	+ },
	+ {
	+ "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "CounterMask": "2",
	+ "EventCode": "0xb1",
	+ "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2",
	+ "PublicDescription": "Counts cycles when at least 2 micro-ops are executed from any thread on physical core.",
	+ "SampleAfterValue": "2000003",
	+ "UMask": "0x2"
	+ },
	+ {
	+ "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "CounterMask": "3",
	+ "EventCode": "0xb1",
	+ "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3",
	+ "PublicDescription": "Counts cycles when at least 3 micro-ops are executed from any thread on physical core.",
	+ "SampleAfterValue": "2000003",
	+ "UMask": "0x2"
	+ },
	+ {
	+ "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "CounterMask": "4",
	+ "EventCode": "0xb1",
	+ "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4",
	+ "PublicDescription": "Counts cycles when at least 4 micro-ops are executed from any thread on physical core.",
	+ "SampleAfterValue": "2000003",
	+ "UMask": "0x2"
	+ },
	+ {
	+ "BriefDescription": "Cycles where at least 1 uop was executed per-thread",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "CounterMask": "1",
	+ "EventCode": "0xb1",
	+ "EventName": "UOPS_EXECUTED.CYCLES_GE_1",
	+ "PublicDescription": "Cycles where at least 1 uop was executed per-thread.",
	+ "SampleAfterValue": "2000003",
	+ "UMask": "0x1"
	+ },
	+ {
	+ "BriefDescription": "Cycles where at least 2 uops were executed per-thread",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "CounterMask": "2",
	+ "EventCode": "0xb1",
	+ "EventName": "UOPS_EXECUTED.CYCLES_GE_2",
	+ "PublicDescription": "Cycles where at least 2 uops were executed per-thread.",
	+ "SampleAfterValue": "2000003",
	+ "UMask": "0x1"
	+ },
	+ {
	+ "BriefDescription": "Cycles where at least 3 uops were executed per-thread",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "CounterMask": "3",
	+ "EventCode": "0xb1",
	+ "EventName": "UOPS_EXECUTED.CYCLES_GE_3",
	+ "PublicDescription": "Cycles where at least 3 uops were executed per-thread.",
	+ "SampleAfterValue": "2000003",
	+ "UMask": "0x1"
	+ },
	+ {
	+ "BriefDescription": "Cycles where at least 4 uops were executed per-thread",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "CounterMask": "4",
	+ "EventCode": "0xb1",
	+ "EventName": "UOPS_EXECUTED.CYCLES_GE_4",
	+ "PublicDescription": "Cycles where at least 4 uops were executed per-thread.",
	+ "SampleAfterValue": "2000003",
	+ "UMask": "0x1"
	+ },
	+ {
	+ "BriefDescription": "Counts number of cycles no uops were dispatched to be executed on this thread.",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "CounterMask": "1",
	+ "EventCode": "0xb1",
	+ "EventName": "UOPS_EXECUTED.STALLS",
	+ "Invert": "1",
	+ "PublicDescription": "Counts cycles during which no uops were dispatched from the Reservation Station (RS) per thread.",
	+ "SampleAfterValue": "2000003",
	+ "UMask": "0x1"
	+ },
	+ {
	+ "BriefDescription": "Counts the number of uops to be executed per-thread each cycle.",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xb1",
	+ "EventName": "UOPS_EXECUTED.THREAD",
	+ "SampleAfterValue": "2000003",
	+ "UMask": "0x1"
	+ },
	+ {
	+ "BriefDescription": "Counts the number of x87 uops dispatched.",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xb1",
	+ "EventName": "UOPS_EXECUTED.X87",
	+ "PublicDescription": "Counts the number of x87 uops executed.",
	+ "SampleAfterValue": "2000003",
	+ "UMask": "0x10"
	+ },
	+ {
	+ "BriefDescription": "Uops that RAT issues to RS",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xae",
	+ "EventName": "UOPS_ISSUED.ANY",
	+ "PublicDescription": "Counts the number of uops that the Resource Allocation Table (RAT) issues to the Reservation Station (RS).",
	+ "SampleAfterValue": "2000003",
	+ "UMask": "0x1"
	+ },
	+ {
	+ "BriefDescription": "UOPS_ISSUED.CYCLES",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "CounterMask": "1",
	+ "EventCode": "0xae",
	+ "EventName": "UOPS_ISSUED.CYCLES",
	+ "SampleAfterValue": "2000003",
	+ "UMask": "0x1"
	+ },
	+ {
	+ "BriefDescription": "Cycles with retired uop(s).",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "CounterMask": "1",
	+ "EventCode": "0xc2",
	+ "EventName": "UOPS_RETIRED.CYCLES",
	+ "PublicDescription": "Counts cycles where at least one uop has retired.",
	+ "SampleAfterValue": "1000003",
	+ "UMask": "0x2"
	+ },
	+ {
	+ "BriefDescription": "Retired uops except the last uop of each instruction.",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xc2",
	+ "EventName": "UOPS_RETIRED.HEAVY",
	+ "PublicDescription": "Counts the number of retired micro-operations (uops) except the last uop of each instruction. An instruction that is decoded into less than two uops does not contribute to the count.",
	+ "SampleAfterValue": "2000003",
	+ "UMask": "0x1"
	+ },
	+ {
	+ "BriefDescription": "UOPS_RETIRED.MS",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xc2",
	+ "EventName": "UOPS_RETIRED.MS",
	+ "MSRIndex": "0x3F7",
	+ "MSRValue": "0x8",
	+ "SampleAfterValue": "2000003",
	+ "UMask": "0x4"
	+ },
	+ {
	+ "BriefDescription": "This event counts a subset of the Topdown Slots event that are utilized by operations that eventually get retired (committed) by the processor pipeline. Usually, this event positively correlates with higher performance for example, as measured by the instructions-per-cycle metric.",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "EventCode": "0xc2",
	+ "EventName": "UOPS_RETIRED.SLOTS",
	+ "PublicDescription": "This event counts a subset of the Topdown Slots event that are utilized by operations that eventually get retired (committed) by the processor pipeline. Usually, this event positively correlates with higher performance for example, as measured by the instructions-per-cycle metric. Software can use this event as the numerator for the Retiring metric (or top-level category) of the Top-down Microarchitecture Analysis method.",
	+ "SampleAfterValue": "2000003",
	+ "UMask": "0x2"
	+ },
	+ {
	+ "BriefDescription": "Cycles without actually retired uops.",
	+ "Counter": "0,1,2,3,4,5,6,7",
	+ "CounterMask": "1",
	+ "EventCode": "0xc2",
	+ "EventName": "UOPS_RETIRED.STALLS",
	+ "Invert": "1",
	+ "PublicDescription": "This event counts cycles without actually retired uops.",
	+ "SampleAfterValue": "1000003",
	+ "UMask": "0x2"
	+ }
	+]
	\ No newline at end of file
	diff --git a/lib/libpmc/pmu-events/arch/x86/graniterapids/uncore-cache.json b/lib/libpmc/pmu-events/arch/x86/graniterapids/uncore-cache.json
	new file mode 100644
	--- /dev/null
	+++ b/lib/libpmc/pmu-events/arch/x86/graniterapids/uncore-cache.json
	@@ -0,0 +1,3745 @@
	+[
	+ {
	+ "BriefDescription": "Clockticks for CMS units attached to CHA",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x01",
	+ "EventName": "UNC_CHACMS_CLOCKTICKS",
	+ "PerPkg": "1",
	+ "PortMask": "0x000",
	+ "PublicDescription": "UNC_CHACMS_CLOCKTICKS",
	+ "Unit": "CHACMS"
	+ },
	+ {
	+ "BriefDescription": "UNC_CHACMS_DISTRESS_ASSERTED",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHACMS_DISTRESS_ASSERTED",
	+ "PerPkg": "1",
	+ "PortMask": "0x000",
	+ "Unit": "CHACMS"
	+ },
	+ {
	+ "BriefDescription": "Counts the number of cycles FAST trigger is received from the global FAST distress wire.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x34",
	+ "EventName": "UNC_CHACMS_RING_SRC_THRTL",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PortMask": "0x000",
	+ "Unit": "CHACMS"
	+ },
	+ {
	+ "BriefDescription": "Number of CHA clock cycles while the event is enabled",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x01",
	+ "EventName": "UNC_CHA_CLOCKTICKS",
	+ "PerPkg": "1",
	+ "PublicDescription": "Clockticks of the uncore caching and home agent (CHA)",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "Counts transactions that looked into the multi-socket cacheline Directory state, and therefore did not send a snoop because the Directory indicated it was not needed.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x53",
	+ "EventName": "UNC_CHA_DIR_LOOKUP.NO_SNP",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x2",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "Counts transactions that looked into the multi-socket cacheline Directory state, and sent one or more snoops, because the Directory indicated it was needed.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x53",
	+ "EventName": "UNC_CHA_DIR_LOOKUP.SNP",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x1",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "Counts only multi-socket cacheline Directory state updates memory writes issued from the HA pipe. This does not include memory write requests which are for I (Invalid) or E (Exclusive) cachelines.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x54",
	+ "EventName": "UNC_CHA_DIR_UPDATE.HA",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x1",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "Counts only multi-socket cacheline Directory state updates due to memory writes issued from the TOR pipe which are the result of remote transaction hitting the SF/LLC and returning data Core2Core. This does not include memory write requests which are for I (Invalid) or E (Exclusive) cachelines.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x54",
	+ "EventName": "UNC_CHA_DIR_UPDATE.TOR",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x2",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "Distress signal assertion for dynamic prefetch throttle (DPT). Threshold for distress signal assertion reached in TOR or IRQ (immediate cause for triggering).",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x59",
	+ "EventName": "UNC_CHA_DISTRESS_ASSERTED.DPT_ANY",
	+ "PerPkg": "1",
	+ "PortMask": "0x000",
	+ "UMask": "0x3",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "Distress signal assertion for dynamic prefetch throttle (DPT). Threshold for distress signal assertion reached in IRQ (immediate cause for triggering).",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x59",
	+ "EventName": "UNC_CHA_DISTRESS_ASSERTED.DPT_IRQ",
	+ "PerPkg": "1",
	+ "UMask": "0x1",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "Distress signal assertion for dynamic prefetch throttle (DPT). Threshold for distress signal assertion reached in TOR (immediate cause for triggering).",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x59",
	+ "EventName": "UNC_CHA_DISTRESS_ASSERTED.DPT_TOR",
	+ "PerPkg": "1",
	+ "UMask": "0x2",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "Counts when a normal (Non-Isochronous) full line write is issued from the CHA to the any of the memory controller channels.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x5b",
	+ "EventName": "UNC_CHA_IMC_WRITES_COUNT.FULL",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x1",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "CHA to iMC Full Line Writes Issued : ISOCH Full Line : Counts the total number of full line writes issued from the HA into the memory controller.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x5b",
	+ "EventName": "UNC_CHA_IMC_WRITES_COUNT.FULL_PRIORITY",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x4",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "CHA to iMC Full Line Writes Issued : Partial Non-ISOCH : Counts the total number of full line writes issued from the HA into the memory controller.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x5b",
	+ "EventName": "UNC_CHA_IMC_WRITES_COUNT.PARTIAL",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x2",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "CHA to iMC Full Line Writes Issued : ISOCH Partial : Counts the total number of full line writes issued from the HA into the memory controller.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x5b",
	+ "EventName": "UNC_CHA_IMC_WRITES_COUNT.PARTIAL_PRIORITY",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x8",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "Cache Lookups: All Requests to Remotely Homed Memory",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x34",
	+ "EventName": "UNC_CHA_LLC_LOOKUP.ALL_REMOTE",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PublicDescription": "Cache Lookups : All transactions from Remote Agents",
	+ "UMask": "0x17e0ff",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "Cache Lookups: CRd Requests",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x34",
	+ "EventName": "UNC_CHA_LLC_LOOKUP.CODE",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PublicDescription": "Cache Lookups : CRd Requests",
	+ "UMask": "0x1bd0ff",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "Cache Lookups: Read Requests and Read Prefetches",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x34",
	+ "EventName": "UNC_CHA_LLC_LOOKUP.DATA_RD",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state. Read transactions",
	+ "UMask": "0x1bc1ff",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "Cache Lookups: Read Requests, Read Prefetches, and Snoops",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x34",
	+ "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ_ALL",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PublicDescription": "Cache Lookups : Data Reads",
	+ "UMask": "0x1fc1ff",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "Cache Lookups: Read Requests to Locally Homed Memory",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x34",
	+ "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ_LOCAL",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PublicDescription": "Cache Lookups : Demand Data Reads, Core and LLC prefetches",
	+ "UMask": "0x841ff",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "Cache Lookups: Read Requests, Read Prefetches, and Snoops which miss the Cache",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x34",
	+ "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ_MISS",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PublicDescription": "Cache Lookups : Data Read Misses",
	+ "UMask": "0x1fc101",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "Cache Lookups: All Requests to Locally Homed Memory",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x34",
	+ "EventName": "UNC_CHA_LLC_LOOKUP.LOCALLY_HOMED_ADDRESS",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PublicDescription": "Cache Lookups : Transactions homed locally",
	+ "UMask": "0xbdfff",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "Cache Lookups: Code Read Requests and Code Read Prefetches to Locally Homed Memory",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x34",
	+ "EventName": "UNC_CHA_LLC_LOOKUP.LOCAL_CODE",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PublicDescription": "Cache Lookups : CRd Requests",
	+ "UMask": "0x19d0ff",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "Cache Lookups: Read Requests and Read Prefetches to Locally Homed Memory",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x34",
	+ "EventName": "UNC_CHA_LLC_LOOKUP.LOCAL_DATA_RD",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state. Read transactions",
	+ "UMask": "0x19c1ff",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "Cache Lookups: Code Read Requests to Locally Homed Memory",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x34",
	+ "EventName": "UNC_CHA_LLC_LOOKUP.LOCAL_DMND_CODE",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PublicDescription": "Cache Lookups : CRd Requests",
	+ "UMask": "0x1850ff",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "Cache Lookups: Read Requests to Locally Homed Memory",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x34",
	+ "EventName": "UNC_CHA_LLC_LOOKUP.LOCAL_DMND_DATA_RD",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state. Read transactions",
	+ "UMask": "0x1841ff",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "Cache Lookups: RFO Requests to Locally Homed Memory",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x34",
	+ "EventName": "UNC_CHA_LLC_LOOKUP.LOCAL_DMND_RFO",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PublicDescription": "Cache Lookups : RFO Requests",
	+ "UMask": "0x1848ff",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "Cache Lookups: LLC Prefetch Requests to Locally Homed Memory",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x34",
	+ "EventName": "UNC_CHA_LLC_LOOKUP.LOCAL_LLC_PF",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state. Read transactions",
	+ "UMask": "0x189dff",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "Cache Lookups: All Prefetches to Locally Homed Memory",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x34",
	+ "EventName": "UNC_CHA_LLC_LOOKUP.LOCAL_PF",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state. Read transactions",
	+ "UMask": "0x199dff",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "Cache Lookups: Code Prefetches to Locally Homed Memory",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x34",
	+ "EventName": "UNC_CHA_LLC_LOOKUP.LOCAL_PF_CODE",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PublicDescription": "Cache Lookups : CRd Requests",
	+ "UMask": "0x1910ff",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "Cache Lookups: Read Prefetches to Locally Homed Memory",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x34",
	+ "EventName": "UNC_CHA_LLC_LOOKUP.LOCAL_PF_DATA_RD",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state. Read transactions",
	+ "UMask": "0x1981ff",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "Cache Lookups: RFO Prefetches to Locally Homed Memory",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x34",
	+ "EventName": "UNC_CHA_LLC_LOOKUP.LOCAL_PF_RFO",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PublicDescription": "Cache Lookups : RFO Requests",
	+ "UMask": "0x1908ff",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "Cache Lookups: RFO Requests and RFO Prefetches to Locally Homed Memory",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x34",
	+ "EventName": "UNC_CHA_LLC_LOOKUP.LOCAL_RFO",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PublicDescription": "Cache Lookups : RFO Requests",
	+ "UMask": "0x19c8ff",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "Cache Lookups: All Requests to Remotely Homed Memory",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x34",
	+ "EventName": "UNC_CHA_LLC_LOOKUP.REMOTELY_HOMED_ADDRESS",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PublicDescription": "Cache Lookups : Transactions homed remotely : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Transaction whose address resides in a remote MC",
	+ "UMask": "0x15dfff",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "Cache Lookups: Code Read/Prefetch Requests from a Remote Socket",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x34",
	+ "EventName": "UNC_CHA_LLC_LOOKUP.REMOTE_CODE",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PublicDescription": "Cache Lookups : CRd Requests",
	+ "UMask": "0x1a10ff",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "Cache Lookups: Data Read/Prefetch Requests from a Remote Socket",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x34",
	+ "EventName": "UNC_CHA_LLC_LOOKUP.REMOTE_DATA_RD",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state. Read transactions",
	+ "UMask": "0x1a01ff",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "Cache Lookups: RFO Requests/Prefetches from a Remote Socket",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x34",
	+ "EventName": "UNC_CHA_LLC_LOOKUP.REMOTE_RFO",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PublicDescription": "Cache Lookups : RFO Requests",
	+ "UMask": "0x1a08ff",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "Cache Lookups: Snoop Requests from a Remote Socket",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x34",
	+ "EventName": "UNC_CHA_LLC_LOOKUP.REMOTE_SNP",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PublicDescription": "Counts the number of times the LLC was accessed",
	+ "UMask": "0x1c19ff",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "Cache Lookups: All RFO and RFO Prefetches",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x34",
	+ "EventName": "UNC_CHA_LLC_LOOKUP.RFO",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PublicDescription": "Cache Lookups : All RFOs - Demand and Prefetches",
	+ "UMask": "0x1bc8ff",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "Cache Lookups: RFO Requests and RFO Prefetches to Locally Homed Memory",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x34",
	+ "EventName": "UNC_CHA_LLC_LOOKUP.RFO_LOCAL",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PublicDescription": "Cache Lookups : Locally HOMed RFOs - Demand and Prefetches",
	+ "UMask": "0x9c8ff",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "Cache Lookups: Writes to Locally Homed Memory (includes writebacks from L1/L2)",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x34",
	+ "EventName": "UNC_CHA_LLC_LOOKUP.WRITE_LOCAL",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PublicDescription": "Cache Lookups : Writes",
	+ "UMask": "0x842ff",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "Cache Lookups: Writes to Remotely Homed Memory (includes writebacks from L1/L2)",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x34",
	+ "EventName": "UNC_CHA_LLC_LOOKUP.WRITE_REMOTE",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PublicDescription": "Cache Lookups : Remote Writes",
	+ "UMask": "0x17c2ff",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x37",
	+ "EventName": "UNC_CHA_LLC_VICTIMS.ALL",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PublicDescription": "Lines Victimized : All Lines Victimized",
	+ "UMask": "0xf",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "Lines Victimized : IA traffic : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x37",
	+ "EventName": "UNC_CHA_LLC_VICTIMS.IA",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x20",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "Lines Victimized : IO traffic : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x37",
	+ "EventName": "UNC_CHA_LLC_VICTIMS.IO",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x10",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x37",
	+ "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_ALL",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PublicDescription": "Lines Victimized : Local - All Lines",
	+ "UMask": "0x200f",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "Lines Victimized : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x37",
	+ "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_E",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PublicDescription": "Lines Victimized : Local - Lines in E State",
	+ "UMask": "0x2002",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "Lines Victimized : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x37",
	+ "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_F",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PublicDescription": "Lines Victimized : Local - Lines in F State",
	+ "UMask": "0x2008",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "Lines Victimized : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x37",
	+ "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_M",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PublicDescription": "Lines Victimized : Local - Lines in M State",
	+ "UMask": "0x2001",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "Lines Victimized : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x37",
	+ "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_S",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PublicDescription": "Lines Victimized : Local - Lines in S State",
	+ "UMask": "0x2004",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x37",
	+ "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_ALL",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PublicDescription": "Lines Victimized : Remote - All Lines",
	+ "UMask": "0x800f",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "Lines Victimized : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x37",
	+ "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_E",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PublicDescription": "Lines Victimized : Remote - Lines in E State",
	+ "UMask": "0x8002",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "Lines Victimized : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x37",
	+ "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_M",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PublicDescription": "Lines Victimized : Remote - Lines in M State",
	+ "UMask": "0x8001",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "Lines Victimized : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x37",
	+ "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_S",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PublicDescription": "Lines Victimized : Remote - Lines in S State",
	+ "UMask": "0x8004",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x37",
	+ "EventName": "UNC_CHA_LLC_VICTIMS.TOTAL_E",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PublicDescription": "Lines Victimized : Lines in E state",
	+ "UMask": "0x2",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x37",
	+ "EventName": "UNC_CHA_LLC_VICTIMS.TOTAL_M",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PublicDescription": "Lines Victimized : Lines in M state",
	+ "UMask": "0x1",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x37",
	+ "EventName": "UNC_CHA_LLC_VICTIMS.TOTAL_S",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PublicDescription": "Lines Victimized : Lines in S State",
	+ "UMask": "0x4",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "Counts when a RFO (the Read for Ownership issued before a write) request hit a cacheline in the S (Shared) state.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x39",
	+ "EventName": "UNC_CHA_MISC.RFO_HIT_S",
	+ "PerPkg": "1",
	+ "PublicDescription": "Cbo Misc : RFO HitS",
	+ "UMask": "0x8",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "OSB Snoop Broadcast : Local InvItoE : Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x55",
	+ "EventName": "UNC_CHA_OSB.LOCAL_INVITOE",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x1",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "OSB Snoop Broadcast : Local Rd : Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x55",
	+ "EventName": "UNC_CHA_OSB.LOCAL_READ",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x2",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "OSB Snoop Broadcast : Off : Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x55",
	+ "EventName": "UNC_CHA_OSB.OFF_PWRHEURISTIC",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x20",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "OSB Snoop Broadcast : Remote Rd : Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x55",
	+ "EventName": "UNC_CHA_OSB.REMOTE_READ",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x4",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "OSB Snoop Broadcast : RFO HitS Snoop Broadcast : Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x55",
	+ "EventName": "UNC_CHA_OSB.RFO_HITS_SNP_BCAST",
	+ "PerPkg": "1",
	+ "UMask": "0x10",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "UNC_CHA_REMOTE_SF.ALLOC_EXCLUSIVE",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x69",
	+ "EventName": "UNC_CHA_REMOTE_SF.ALLOC_EXCLUSIVE",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x10",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "UNC_CHA_REMOTE_SF.ALLOC_SHARED",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x69",
	+ "EventName": "UNC_CHA_REMOTE_SF.ALLOC_SHARED",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x8",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "UNC_CHA_REMOTE_SF.DEALLOC_EVCTCLN",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x69",
	+ "EventName": "UNC_CHA_REMOTE_SF.DEALLOC_EVCTCLN",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x40",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "UNC_CHA_REMOTE_SF.DIRBACKED_ONLY",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x69",
	+ "EventName": "UNC_CHA_REMOTE_SF.DIRBACKED_ONLY",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "UNC_CHA_REMOTE_SF.HIT_EXCLUSIVE",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x69",
	+ "EventName": "UNC_CHA_REMOTE_SF.HIT_EXCLUSIVE",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x2",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "UNC_CHA_REMOTE_SF.HIT_SHARED",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x69",
	+ "EventName": "UNC_CHA_REMOTE_SF.HIT_SHARED",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x1",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "UNC_CHA_REMOTE_SF.INCLUSIVE_ONLY",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x69",
	+ "EventName": "UNC_CHA_REMOTE_SF.INCLUSIVE_ONLY",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "UNC_CHA_REMOTE_SF.MISS",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x69",
	+ "EventName": "UNC_CHA_REMOTE_SF.MISS",
	+ "PerPkg": "1",
	+ "UMask": "0x4",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "UNC_CHA_REMOTE_SF.UPDATE_EXCLUSIVE",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x69",
	+ "EventName": "UNC_CHA_REMOTE_SF.UPDATE_EXCLUSIVE",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "UNC_CHA_REMOTE_SF.UPDATE_SHARED",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x69",
	+ "EventName": "UNC_CHA_REMOTE_SF.UPDATE_SHARED",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x80",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "UNC_CHA_REMOTE_SF.VICTIM_EXCLUSIVE",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x69",
	+ "EventName": "UNC_CHA_REMOTE_SF.VICTIM_EXCLUSIVE",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "UNC_CHA_REMOTE_SF.VICTIM_SHARED",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x69",
	+ "EventName": "UNC_CHA_REMOTE_SF.VICTIM_SHARED",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "Counts the total number of requests coming from a unit on this socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHA.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x50",
	+ "EventName": "UNC_CHA_REQUESTS.INVITOE",
	+ "PerPkg": "1",
	+ "PublicDescription": "HA Read and Write Requests : InvalItoE",
	+ "UMask": "0x30",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "Counts the total number of requests coming from a unit on this socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHA.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x50",
	+ "EventName": "UNC_CHA_REQUESTS.INVITOE_LOCAL",
	+ "PerPkg": "1",
	+ "UMask": "0x10",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "Counts the total number of requests coming from a remote socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHA.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x50",
	+ "EventName": "UNC_CHA_REQUESTS.INVITOE_REMOTE",
	+ "PerPkg": "1",
	+ "UMask": "0x20",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "Counts read requests made into this CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a write) .",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x50",
	+ "EventName": "UNC_CHA_REQUESTS.READS",
	+ "PerPkg": "1",
	+ "PublicDescription": "HA Read and Write Requests : Reads",
	+ "UMask": "0x3",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "Counts read requests coming from a unit on this socket made into this CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a write).",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x50",
	+ "EventName": "UNC_CHA_REQUESTS.READS_LOCAL",
	+ "PerPkg": "1",
	+ "UMask": "0x1",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "Counts read requests coming from a remote socket made into the CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a write).",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x50",
	+ "EventName": "UNC_CHA_REQUESTS.READS_REMOTE",
	+ "PerPkg": "1",
	+ "UMask": "0x2",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "Counts write requests made into the CHA, including streaming, evictions, HitM (Reads from another core to a Modified cacheline), etc.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x50",
	+ "EventName": "UNC_CHA_REQUESTS.WRITES",
	+ "PerPkg": "1",
	+ "PublicDescription": "HA Read and Write Requests : Writes",
	+ "UMask": "0xc",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "Counts write requests coming from a unit on this socket made into this CHA, including streaming, evictions, HitM (Reads from another core to a Modified cacheline), etc.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x50",
	+ "EventName": "UNC_CHA_REQUESTS.WRITES_LOCAL",
	+ "PerPkg": "1",
	+ "UMask": "0x4",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO). Writes include all writes (streaming, evictions, HitM, etc).",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x50",
	+ "EventName": "UNC_CHA_REQUESTS.WRITES_REMOTE",
	+ "PerPkg": "1",
	+ "UMask": "0x8",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "Ingress (from CMS) Allocations : IRQ : Counts number of allocations per cycle into the specified Ingress queue.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x13",
	+ "EventName": "UNC_CHA_RxC_INSERTS.IRQ",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x1",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "Ingress (from CMS) Occupancy : IRQ : Counts number of entries in the specified Ingress queue in each cycle.",
	+ "Counter": "0",
	+ "EventCode": "0x11",
	+ "EventName": "UNC_CHA_RxC_OCCUPANCY.IRQ",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x1",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "Counts snoop filter capacity evictions for entries tracking exclusive lines in the core's cache. Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry. Does not count clean evictions such as when a core's cache replaces a tracked cacheline with a new cacheline.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x3d",
	+ "EventName": "UNC_CHA_SF_EVICTION.E_STATE",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PublicDescription": "Snoop Filter Capacity Evictions : E state",
	+ "UMask": "0x2",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "Counts snoop filter capacity evictions for entries tracking modified lines in the core's cache. Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry. Does not count clean evictions such as when a core's cache replaces a tracked cacheline with a new cacheline.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x3d",
	+ "EventName": "UNC_CHA_SF_EVICTION.M_STATE",
	+ "PerPkg": "1",
	+ "PublicDescription": "Snoop Filter Capacity Evictions : M state",
	+ "UMask": "0x1",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "Counts snoop filter capacity evictions for entries tracking shared lines in the core's cache. Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry. Does not count clean evictions such as when a core's cache replaces a tracked cacheline with a new cacheline.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x3d",
	+ "EventName": "UNC_CHA_SF_EVICTION.S_STATE",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PublicDescription": "Snoop Filter Capacity Evictions : S state",
	+ "UMask": "0x4",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "All TOR Inserts",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.ALL",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Inserts : All",
	+ "UMask": "0xc001ffff",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "CLFlush transactions from a CXL device which hit in the L3.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.CXL_HIT_CLFLUSH",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x78c8c7fd20",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "FsRdCur transactions from a CXL device which hit in the L3.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.CXL_HIT_FSRDCUR",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x78c8effd20",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "FsRdCurPtl transactions from a CXL device which hit in the L3.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.CXL_HIT_FSRDCURPTL",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x78c9effd20",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "ItoM transactions from a CXL device which hit in the L3.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.CXL_HIT_ITOM",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x78cc47fd20",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "ItoMWr transactions from a CXL device which hit in the L3.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.CXL_HIT_ITOMWR",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x78cc4ffd20",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "MemPushWr transactions from a CXL device which hit in the L3.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.CXL_HIT_MEMPUSHWR",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x78cc6ffd20",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "WCiL transactions from a CXL device which hit in the L3.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.CXL_HIT_WCIL",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x78c86ffd20",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "WcilF transactions from a CXL device which hit in the L3.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.CXL_HIT_WCILF",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x78c867fd20",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "WiL transactions from a CXL device which hit in the L3.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.CXL_HIT_WIL",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x78c87ffd20",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "CLFlush transactions from a CXL device which miss the L3.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.CXL_MISS_CLFLUSH",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x78c8c7fe20",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "FsRdCur transactions from a CXL device which miss the L3.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.CXL_MISS_FSRDCUR",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x78c8effe20",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "FsRdCurPtl transactions from a CXL device which miss the L3.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.CXL_MISS_FSRDCURPTL",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x78c9effe20",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "ItoM transactions from a CXL device which miss the L3.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.CXL_MISS_ITOM",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x78cc47fe20",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "ItoMWr transactions from a CXL device which miss the L3.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.CXL_MISS_ITOMWR",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x78cc4ffe20",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "MemPushWr transactions from a CXL device which miss the L3.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.CXL_MISS_MEMPUSHWR",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x78cc6ffe20",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "WCiL transactions from a CXL device which miss the L3.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.CXL_MISS_WCIL",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x78c86ffe20",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "WcilF transactions from a CXL device which miss the L3.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.CXL_MISS_WCILF",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x78c867fe20",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "WiL transactions from a CXL device which miss the L3.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.CXL_MISS_WIL",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x78c87ffe20",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "All locally initiated requests from IA Cores",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.IA",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Inserts : All requests from iA Cores",
	+ "UMask": "0xc001ff01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "CLFlush events that are initiated from the Core",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.IA_CLFLUSH",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Inserts : CLFlushes issued by iA Cores",
	+ "UMask": "0xc8c7ff01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "Code read from local IA",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.IA_CRD",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Inserts : CRDs issued by iA Cores",
	+ "UMask": "0xc80fff01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "Code read prefetch from local IA that miss the cache",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.IA_CRD_PREF",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Inserts; Code read prefetch from local IA that misses in the snoop filter",
	+ "UMask": "0xc88fff01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "Data read from local IA",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.IA_DRD",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Inserts : DRds issued by iA Cores",
	+ "UMask": "0xc817ff01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "DRd PTEs issued by iA Cores due to a page walk",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.IA_DRDPTE",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Inserts : DRdPte issued by iA Cores due to a page walk",
	+ "UMask": "0xc837ff01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "Data read prefetch from local IA",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.IA_DRD_PREF",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Inserts : DRd_Prefs issued by iA Cores",
	+ "UMask": "0xc897ff01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "All locally initiated requests from IA Cores which hit the cache",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Inserts : All requests from iA Cores that Hit the LLC",
	+ "UMask": "0xc001fd01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "Code read from local IA that hit the cache",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_CRD",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Inserts : CRds issued by iA Cores that Hit the LLC",
	+ "UMask": "0xc80ffd01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "Code read prefetch from local IA that hit the cache",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_CRD_PREF",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that hit the LLC",
	+ "UMask": "0xc88ffd01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "All requests issued from IA cores to CXL accelerator memory regions that hit the LLC.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_CXL_ACC",
	+ "PerPkg": "1",
	+ "UMask": "0x10c0018101",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "Data read from local IA that hit the cache",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Inserts : DRds issued by iA Cores that Hit the LLC",
	+ "UMask": "0xc817fd01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "DRd PTEs issued by iA Cores due to page walks that hit the LLC",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRDPTE",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Inserts : DRdPte issued by iA Cores due to a page walk that hit the LLC",
	+ "UMask": "0xc837fd01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "Data read prefetch from local IA that hit the cache",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD_PREF",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Inserts : DRd_Prefs issued by iA Cores that Hit the LLC",
	+ "UMask": "0xc897fd01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "ItoM requests from local IA cores that hit the cache",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_ITOM",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Inserts : ItoMs issued by iA Cores that Hit LLC",
	+ "UMask": "0xcc47fd01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "Last level cache prefetch code read from local IA that hit the cache",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFCODE",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Inserts : LLCPrefCode issued by iA Cores that hit the LLC",
	+ "UMask": "0xcccffd01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "Last level cache prefetch data read from local IA that hit the cache",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFDATA",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Inserts : LLCPrefData issued by iA Cores that hit the LLC",
	+ "UMask": "0xccd7fd01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "Last level cache prefetch read for ownership from local IA that hit the cache",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFRFO",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores that hit the LLC",
	+ "UMask": "0xccc7fd01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "Read for ownership from local IA that hit the cache",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_RFO",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Inserts : RFOs issued by iA Cores that Hit the LLC",
	+ "UMask": "0xc807fd01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "Read for ownership prefetch from local IA that hit the cache",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_RFO_PREF",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Inserts : RFO_Prefs issued by iA Cores that Hit the LLC",
	+ "UMask": "0xc887fd01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "ItoM events that are initiated from the Core",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.IA_ITOM",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Inserts : ItoMs issued by iA Cores",
	+ "UMask": "0xcc47ff01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "ItoMCacheNear requests from local IA cores",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.IA_ITOMCACHENEAR",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Inserts : ItoMCacheNears issued by iA Cores",
	+ "UMask": "0xcd47ff01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "Last level cache prefetch code read from local IA.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.IA_LLCPREFCODE",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Inserts : LLCPrefCode issued by iA Cores",
	+ "UMask": "0xcccfff01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "Last level cache prefetch data read from local IA.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.IA_LLCPREFDATA",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Inserts : LLCPrefData issued by iA Cores",
	+ "UMask": "0xccd7ff01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "Last level cache prefetch read for ownership from local IA",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.IA_LLCPREFRFO",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores",
	+ "UMask": "0xccc7ff01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "All locally initiated requests from IA Cores which miss the cache",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Inserts : All requests from iA Cores that Missed the LLC",
	+ "UMask": "0xc001fe01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "Code read from local IA that miss the cache",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Inserts : CRds issued by iA Cores that Missed the LLC",
	+ "UMask": "0xc80ffe01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "CRDs from local IA cores to locally homed memory",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_LOCAL",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Inserts : CRd issued by iA Cores that Missed the LLC - HOMed locally",
	+ "UMask": "0xc80efe01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "Code read prefetch from local IA that miss the cache",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC",
	+ "UMask": "0xc88ffe01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "CRD Prefetches from local IA cores to locally homed memory",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF_LOCAL",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed locally",
	+ "UMask": "0xc88efe01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "CRD Prefetches from local IA cores to remotely homed memory",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF_REMOTE",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed remotely",
	+ "UMask": "0xc88f7e01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "CRDs from local IA cores to remotely homed memory",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_REMOTE",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Inserts : CRd issued by iA Cores that Missed the LLC - HOMed remotely",
	+ "UMask": "0xc80f7e01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "All requests issued from IA cores to CXL accelerator memory regions that miss the LLC.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CXL_ACC",
	+ "PerPkg": "1",
	+ "UMask": "0x10c0018201",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "Data read from local IA that miss the cache",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Inserts : DRds issued by iA Cores that Missed the LLC",
	+ "UMask": "0xc817fe01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "DRd PTEs issued by iA Cores due to a page walk that missed the LLC",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRDPTE",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Inserts : DRdPte issued by iA Cores due to a page walk that missed the LLC",
	+ "UMask": "0xc837fe01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "DRds and equivalent opcodes issued from an IA core which miss the L3 and target memory in a CXL type 2 memory expander card.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_CXL_ACC",
	+ "PerPkg": "1",
	+ "PublicDescription": "DRds issued from an IA core which miss the L3 and target memory in a CXL type 2 memory expander card.",
	+ "UMask": "0x10c8178201",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "DRds issued by iA Cores targeting DDR Mem that Missed the LLC",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_DDR",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Inserts : DRds issued by iA Cores targeting DDR Mem that Missed the LLC",
	+ "UMask": "0xc8178601",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "Data read from local IA that miss the cache and targets local memory",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Inserts : DRds issued by iA Cores that Missed the LLC - HOMed locally",
	+ "UMask": "0xc816fe01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "DRds from local IA cores to locally homed DDR addresses that miss the cache",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL_DDR",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Inserts : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally",
	+ "UMask": "0xc8168601",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "DRds from local IA cores to locally homed PMM addresses that miss the cache",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL_PMM",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Inserts : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally",
	+ "UMask": "0xc8168a01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "DRds issued by iA Cores targeting PMM Mem that Missed the LLC",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PMM",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Inserts : DRds issued by iA Cores targeting PMM Mem that Missed the LLC",
	+ "UMask": "0xc8178a01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "Data read prefetch from local IA that miss the cache",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Inserts : DRd_Prefs issued by iA Cores that Missed the LLC",
	+ "UMask": "0xc897fe01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "L2 data prefetches issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_CXL_ACC",
	+ "PerPkg": "1",
	+ "UMask": "0x10c8978201",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "DRd Prefetches from local IA cores to DDR addresses that miss the cache",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_DDR",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC",
	+ "UMask": "0xc8978601",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "Data read prefetch from local IA that miss the cache and targets local memory",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL",
	+ "PerPkg": "1",
	+ "PublicDescription": "Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRD_PREF, and target local memory",
	+ "UMask": "0xc896fe01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "DRd Prefetches from local IA cores to locally homed DDR addresses that miss the cache",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL_DDR",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally",
	+ "UMask": "0xc8968601",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "DRd Prefetches from local IA cores to locally homed PMM addresses that miss the cache",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL_PMM",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally",
	+ "UMask": "0xc8968a01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "DRd Prefetches from local IA cores to PMM addresses that miss the cache",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_PMM",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC",
	+ "UMask": "0xc8978a01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "Data read prefetch from local IA that miss the cache and targets remote memory",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE",
	+ "PerPkg": "1",
	+ "PublicDescription": "Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRD_PREF, and target remote memory",
	+ "UMask": "0xc8977e01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "DRd Prefetches from local IA cores to remotely homed DDR addresses that miss the cache",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE_DDR",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely",
	+ "UMask": "0xc8970601",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "DRd Prefetches from local IA cores to remotely homed PMM addresses that miss the cache",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE_PMM",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely",
	+ "UMask": "0xc8970a01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "Data read from local IA that miss the cache and targets remote memory",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Inserts : DRds issued by iA Cores that Missed the LLC - HOMed remotely",
	+ "UMask": "0xc8177e01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "DRds from local IA cores to remotely homed DDR addresses that miss the cache",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE_DDR",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Inserts : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely",
	+ "UMask": "0xc8170601",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "DRds from local IA cores to remotely homed PMM addresses that miss the cache",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE_PMM",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Inserts : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely",
	+ "UMask": "0xc8170a01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "ItoM requests from local IA cores that miss the cache",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_ITOM",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Inserts : ItoMs issued by iA Cores that Missed LLC",
	+ "UMask": "0xcc47fe01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "Last level cache prefetch code read from local IA that miss the cache",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFCODE",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Inserts : LLCPrefCode issued by iA Cores that missed the LLC",
	+ "UMask": "0xcccffe01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "Last level cache prefetch data read from local IA that miss the cache",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Inserts : LLCPrefData issued by iA Cores that missed the LLC",
	+ "UMask": "0xccd7fe01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "LLC data prefetches issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA_CXL_ACC",
	+ "PerPkg": "1",
	+ "UMask": "0x10ccd78201",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "Last level cache prefetch read for ownership from local IA that miss the cache",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFRFO",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores that missed the LLC",
	+ "UMask": "0xccc7fe01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "L2 RFO prefetches issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFRFO_CXL_ACC",
	+ "PerPkg": "1",
	+ "UMask": "0x10c8878201",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "WCILF requests from local IA cores to locally homed DDR addresses that miss the cache",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCILF_DDR",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed locally",
	+ "UMask": "0xc8668601",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "WCILF requests from local IA cores to locally homed PMM addresses which miss the cache",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCILF_PMM",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed locally",
	+ "UMask": "0xc8668a01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "WCIL requests from local IA cores to locally homed DDR addresses that miss the cache",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCIL_DDR",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Inserts : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed locally",
	+ "UMask": "0xc86e8601",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "WCIL requests from local IA cores to locally homed PMM addresses which miss the cache",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCIL_PMM",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Inserts : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed locally",
	+ "UMask": "0xc86e8a01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "WCILF requests from local IA cores to remotely homed DDR addresses that miss the cache",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_REMOTE_WCILF_DDR",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely",
	+ "UMask": "0xc8670601",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "WCILF requests from local IA cores to remotely homed PMM addresses which miss the cache",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_REMOTE_WCILF_PMM",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely",
	+ "UMask": "0xc8670a01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "WCIL requests from local IA cores to remotely homed DDR addresses that miss the cache",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_REMOTE_WCIL_DDR",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Inserts : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely",
	+ "UMask": "0xc86f0601",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "WCIL requests from local IA cores to remotely homed PMM addresses which miss the cache",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_REMOTE_WCIL_PMM",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Inserts : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely",
	+ "UMask": "0xc86f0a01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "Read for ownership from local IA that miss the cache",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Inserts : RFOs issued by iA Cores that Missed the LLC",
	+ "UMask": "0xc807fe01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "RFOs issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_CXL_ACC",
	+ "PerPkg": "1",
	+ "UMask": "0x10c8078201",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "Read for ownership from local IA that miss the LLC targeting local memory",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_LOCAL",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Inserts : RFOs issued by iA Cores that Missed the LLC - HOMed locally",
	+ "UMask": "0xc806fe01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "Read for ownership prefetch from local IA that miss the cache",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC",
	+ "UMask": "0xc887fe01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "LLC RFO prefetches issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF_CXL_ACC",
	+ "PerPkg": "1",
	+ "UMask": "0x10ccc78201",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "Read for ownership prefetch from local IA that miss the LLC targeting local memory",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF_LOCAL",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed locally",
	+ "UMask": "0xc886fe01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "Read for ownership prefetch from local IA that miss the LLC targeting remote memory",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF_REMOTE",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed remotely",
	+ "UMask": "0xc8877e01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "Read for ownership from local IA that miss the LLC targeting remote memory",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_REMOTE",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Inserts : RFOs issued by iA Cores that Missed the LLC - HOMed remotely",
	+ "UMask": "0xc8077e01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "UCRDF requests from local IA cores that miss the cache",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_UCRDF",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Inserts : UCRdFs issued by iA Cores that Missed LLC",
	+ "UMask": "0xc877de01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "WCIL requests from a local IA core that miss the cache",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCIL",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Inserts : WCiLs issued by iA Cores that Missed the LLC",
	+ "UMask": "0xc86ffe01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "WCILF requests from local IA core that miss the cache",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCILF",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Inserts : WCiLF issued by iA Cores that Missed the LLC",
	+ "UMask": "0xc867fe01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "WCILF requests from local IA cores to DDR homed addresses which miss the cache",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCILF_DDR",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting DDR that missed the LLC",
	+ "UMask": "0xc8678601",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "WCILF requests from local IA cores to PMM homed addresses which miss the cache",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCILF_PMM",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting PMM that missed the LLC",
	+ "UMask": "0xc8678a01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "WCIL requests from local IA cores to DDR homed addresses which miss the cache",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCIL_DDR",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Inserts : WCiLs issued by iA Cores targeting DDR that missed the LLC",
	+ "UMask": "0xc86f8601",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "WCIL requests from a local IA core to PMM homed addresses that miss the cache",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCIL_PMM",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Inserts : WCiLs issued by iA Cores targeting PMM that missed the LLC",
	+ "UMask": "0xc86f8a01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "WIL requests from local IA cores that miss the cache",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WIL",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Inserts : WiLs issued by iA Cores that Missed LLC",
	+ "UMask": "0xc87fde01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "Read for ownership from local IA",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.IA_RFO",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Inserts : RFOs issued by iA Cores",
	+ "UMask": "0xc807ff01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "Read for ownership prefetch from local IA",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.IA_RFO_PREF",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Inserts : RFO_Prefs issued by iA Cores",
	+ "UMask": "0xc887ff01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "SpecItoM events that are initiated from the Core",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.IA_SPECITOM",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Inserts : SpecItoMs issued by iA Cores",
	+ "UMask": "0xcc57ff01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "WbEFtoEs issued by iA Cores. (Non Modified Write Backs)",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.IA_WBEFTOE",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Inserts : ItoMs issued by IO Devices that Hit the LLC",
	+ "UMask": "0xcc3fff01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "WbEFtoIs issued by iA Cores . (Non Modified Write Backs)",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.IA_WBEFTOI",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Inserts : ItoMs issued by IO Devices that Hit the LLC",
	+ "UMask": "0xcc37ff01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "WbMtoEs issued by iA Cores . (Modified Write Backs)",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.IA_WBMTOE",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Inserts : ItoMs issued by IO Devices that Hit the LLC",
	+ "UMask": "0xcc2fff01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "WbMtoI requests from local IA cores",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.IA_WBMTOI",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Inserts : WbMtoIs issued by iA Cores",
	+ "UMask": "0xcc27ff01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "WbStoIs issued by iA Cores . (Non Modified Write Backs)",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.IA_WBSTOI",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Inserts : ItoMs issued by IO Devices that Hit the LLC",
	+ "UMask": "0xcc67ff01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "WCIL requests from a local IA core",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.IA_WCIL",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Inserts : WCiLs issued by iA Cores",
	+ "UMask": "0xc86fff01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "WCILF requests from local IA core",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.IA_WCILF",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Inserts : WCiLF issued by iA Cores",
	+ "UMask": "0xc867ff01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "All TOR inserts from local IO devices",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.IO",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Inserts : All requests from IO Devices",
	+ "UMask": "0xc001ff04",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "CLFlush requests from IO devices",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.IO_CLFLUSH",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Inserts : CLFlushes issued by IO Devices",
	+ "UMask": "0xc8c3ff04",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "All TOR inserts from local IO devices which hit the cache",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Inserts : All requests from IO Devices that hit the LLC",
	+ "UMask": "0xc001fd04",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "ItoMs from local IO devices which hit the cache",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_ITOM",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Inserts : ItoMs issued by IO Devices that Hit the LLC",
	+ "UMask": "0xcc43fd04",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_ITOMCACHENEAR",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC",
	+ "UMask": "0xcd43fd04",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "PCIRDCURs issued by IO devices which hit the LLC",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_PCIRDCUR",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Inserts : PCIRdCurs issued by IO Devices that hit the LLC",
	+ "UMask": "0xc8f3fd04",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "RFOs from local IO devices which hit the cache",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_RFO",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Inserts : RFOs issued by IO Devices that hit the LLC",
	+ "UMask": "0xc803fd04",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "All TOR ItoM inserts from local IO devices",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOM",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Inserts : ItoMs issued by IO Devices",
	+ "UMask": "0xcc43ff04",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "ItoMCacheNears, indicating a partial write request, from IO Devices",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices",
	+ "UMask": "0xcd43ff04",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "ItoMCacheNear (partial write) transactions from an IO device that addresses memory on the local socket",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR_LOCAL",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that address memory on the local socket",
	+ "UMask": "0xcd42ff04",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "ItoMCacheNear (partial write) transactions from an IO device that addresses memory on a remote socket",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR_REMOTE",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that address memory on a remote socket",
	+ "UMask": "0xcd437f04",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "ItoM (write) transactions from an IO device that addresses memory on the local socket",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOM_LOCAL",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Inserts : ItoM, indicating a write request, from IO Devices that address memory on the local socket",
	+ "UMask": "0xcc42ff04",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "ItoM (write) transactions from an IO device that addresses memory on a remote socket",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOM_REMOTE",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Inserts : ItoM, indicating a write request, from IO Devices that address memory on a remote socket",
	+ "UMask": "0xcc437f04",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "All TOR inserts from local IO devices which miss the cache",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Inserts : All requests from IO Devices that missed the LLC",
	+ "UMask": "0xc001fe04",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "All TOR ItoM inserts from local IO devices which miss the cache",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOM",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Inserts : ItoMs issued by IO Devices that missed the LLC",
	+ "UMask": "0xcc43fe04",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOMCACHENEAR",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC",
	+ "UMask": "0xcd43fe04",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "PCIRDCURs issued by IO devices which miss the LLC",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_PCIRDCUR",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Inserts : PCIRdCurs issued by IO Devices that missed the LLC",
	+ "UMask": "0xc8f3fe04",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "All TOR RFO inserts from local IO devices which miss the cache",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_RFO",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Inserts : RFOs issued by IO Devices that missed the LLC",
	+ "UMask": "0xc803fe04",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "PCIRDCURs issued by IO devices",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Inserts : PCIRdCurs issued by IO Devices",
	+ "UMask": "0xc8f3ff04",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "PCIRDCUR (read) transactions from an IO device that addresses memory on the local socket",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR_LOCAL",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Inserts : PCIRdCurs issued by IO Devices that addresses memory on the local socket",
	+ "UMask": "0xc8f2ff04",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "PCIRDCUR (read) transactions from an IO device that addresses memory on a remote socket",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR_REMOTE",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Inserts : PCIRdCurs issued by IO Devices that addresses memory on a remote socket",
	+ "UMask": "0xc8f37f04",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "RFOs from local IO devices",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.IO_RFO",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Inserts : RFOs issued by IO Devices",
	+ "UMask": "0xc803ff04",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "WBMtoI requests from IO devices",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.IO_WBMTOI",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Inserts : WbMtoIs issued by IO Devices",
	+ "UMask": "0xcc23ff04",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Inserts for SF or LLC Evictions",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.LLC_OR_SF_EVICTIONS",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR allocation occurred as a result of SF/LLC evictions (came from the ISMQ)",
	+ "UMask": "0xc001ff02",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "All locally initiated requests",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.LOC_ALL",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Inserts : All from Local iA and IO",
	+ "UMask": "0xc000ff05",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "All from Local iA",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.LOC_IA",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Inserts : All from Local iA",
	+ "UMask": "0xc000ff01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "All from Local IO",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.LOC_IO",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Inserts : All from Local IO",
	+ "UMask": "0xc000ff04",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "All remote requests (e.g. snoops, writebacks) that came from remote sockets",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.REM_ALL",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Inserts : All Remote Requests",
	+ "UMask": "0xc001ffc8",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "All snoops to this LLC that came from remote sockets",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_CHA_TOR_INSERTS.REM_SNPS",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Inserts : All Snoops from Remote",
	+ "UMask": "0xc001ff08",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "Occupancy for all TOR entries",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.ALL",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Occupancy : All",
	+ "UMask": "0xc001ffff",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for CLFlush transactions from a CXL device which hit in the L3.",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.CXL_HIT_CLFLUSH",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x78c8c7fd20",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for FsRdCur transactions from a CXL device which hit in the L3.",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.CXL_HIT_FSRDCUR",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x78c8effd20",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for FsRdCurPtl transactions from a CXL device which hit in the L3.",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.CXL_HIT_FSRDCURPTL",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x78c9effd20",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for ItoM transactions from a CXL device which hit in the L3.",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.CXL_HIT_ITOM",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x78cc47fd20",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for ItoMWr transactions from a CXL device which hit in the L3.",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.CXL_HIT_ITOMWR",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x78cc4ffd20",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for MemPushWr transactions from a CXL device which hit in the L3.",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.CXL_HIT_MEMPUSHWR",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x78cc6ffd20",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for WCiL transactions from a CXL device which hit in the L3.",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.CXL_HIT_WCIL",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x78c86ffd20",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for WcilF transactions from a CXL device which hit in the L3.",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.CXL_HIT_WCILF",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x78c867fd20",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for WiL transactions from a CXL device which hit in the L3.",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.CXL_HIT_WIL",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x78c87ffd20",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for CLFlush transactions from a CXL device which miss the L3.",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.CXL_MISS_CLFLUSH",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x78c8c7fe20",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for FsRdCur transactions from a CXL device which miss the L3.",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.CXL_MISS_FSRDCUR",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x78c8effe20",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for FsRdCurPtl transactions from a CXL device which miss the L3.",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.CXL_MISS_FSRDCURPTL",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x78c9effe20",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for ItoM transactions from a CXL device which miss the L3.",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.CXL_MISS_ITOM",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x78cc47fe20",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for ItoMWr transactions from a CXL device which miss the L3.",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.CXL_MISS_ITOMWR",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x78cc4ffe20",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for MemPushWr transactions from a CXL device which miss the L3.",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.CXL_MISS_MEMPUSHWR",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x78cc6ffe20",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for WCiL transactions from a CXL device which miss the L3.",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.CXL_MISS_WCIL",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x78c86ffe20",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for WcilF transactions from a CXL device which miss the L3.",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.CXL_MISS_WCILF",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x78c867fe20",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for WiL transactions from a CXL device which miss the L3.",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.CXL_MISS_WIL",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x78c87ffe20",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for All locally initiated requests from IA Cores",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Occupancy : All requests from iA Cores",
	+ "UMask": "0xc001ff01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for CLFlush events that are initiated from the Core",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CLFLUSH",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Occupancy : CLFlushes issued by iA Cores",
	+ "UMask": "0xc8c7ff01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for Code read from local IA that miss the cache",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CRD",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Occupancy : CRDs issued by iA Cores",
	+ "UMask": "0xc80fff01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for Code read prefetch from local IA that miss the cache",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CRD_PREF",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Occupancy; Code read prefetch from local IA that misses in the snoop filter",
	+ "UMask": "0xc88fff01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for Data read from local IA that miss the cache",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRD",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Occupancy : DRds issued by iA Cores",
	+ "UMask": "0xc817ff01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for DRd PTEs issued by iA Cores due to a page walk",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRDPTE",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Occupancy : DRdPte issued by iA Cores due to a page walk",
	+ "UMask": "0xc837ff01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for Data read prefetch from local IA that miss the cache",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRD_PREF",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores",
	+ "UMask": "0xc897ff01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for All locally initiated requests from IA Cores which hit the cache",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Occupancy : All requests from iA Cores that Hit the LLC",
	+ "UMask": "0xc001fd01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for Code read from local IA that hit the cache",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CRD",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Occupancy : CRds issued by iA Cores that Hit the LLC",
	+ "UMask": "0xc80ffd01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for Code read prefetch from local IA that hit the cache",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CRD_PREF",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores that hit the LLC",
	+ "UMask": "0xc88ffd01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for All requests issued from IA cores to CXL accelerator memory regions that hit the LLC.",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CXL_ACC",
	+ "PerPkg": "1",
	+ "UMask": "0x10c0018101",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for Data read from local IA that hit the cache",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Occupancy : DRds issued by iA Cores that Hit the LLC",
	+ "UMask": "0xc817fd01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for DRd PTEs issued by iA Cores due to page walks that hit the LLC",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRDPTE",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Occupancy : DRdPte issued by iA Cores due to a page walk that hit the LLC",
	+ "UMask": "0xc837fd01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for Data read prefetch from local IA that hit the cache",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD_PREF",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores that Hit the LLC",
	+ "UMask": "0xc897fd01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for ItoM requests from local IA cores that hit the cache",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_ITOM",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Occupancy : ItoMs issued by iA Cores that Hit LLC",
	+ "UMask": "0xcc47fd01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for Last level cache prefetch code read from local IA that hit the cache",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LLCPREFCODE",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Occupancy : LLCPrefCode issued by iA Cores that hit the LLC",
	+ "UMask": "0xcccffd01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for Last level cache prefetch data read from local IA that hit the cache",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LLCPREFDATA",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Occupancy : LLCPrefData issued by iA Cores that hit the LLC",
	+ "UMask": "0xccd7fd01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for Last level cache prefetch read for ownership from local IA that hit the cache",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LLCPREFRFO",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Occupancy : LLCPrefRFO issued by iA Cores that hit the LLC",
	+ "UMask": "0xccc7fd01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for Read for ownership from local IA that hit the cache",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Occupancy : RFOs issued by iA Cores that Hit the LLC",
	+ "UMask": "0xc807fd01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for Read for ownership prefetch from local IA that hit the cache",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO_PREF",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores that Hit the LLC",
	+ "UMask": "0xc887fd01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for ItoM events that are initiated from the Core",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_ITOM",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Occupancy : ItoMs issued by iA Cores",
	+ "UMask": "0xcc47ff01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for ItoMCacheNear requests from local IA cores",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_ITOMCACHENEAR",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Occupancy : ItoMCacheNears issued by iA Cores",
	+ "UMask": "0xcd47ff01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for Last level cache prefetch code read from local IA.",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_LLCPREFCODE",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Occupancy : LLCPrefCode issued by iA Cores",
	+ "UMask": "0xcccfff01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for Last level cache prefetch data read from local IA.",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_LLCPREFDATA",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Occupancy : LLCPrefData issued by iA Cores",
	+ "UMask": "0xccd7ff01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for Last level cache prefetch read for ownership from local IA that miss the cache",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_LLCPREFRFO",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Occupancy : LLCPrefRFO issued by iA Cores",
	+ "UMask": "0xccc7ff01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for All locally initiated requests from IA Cores which miss the cache",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Occupancy : All requests from iA Cores that Missed the LLC",
	+ "UMask": "0xc001fe01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for Code read from local IA that miss the cache",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Occupancy : CRds issued by iA Cores that Missed the LLC",
	+ "UMask": "0xc80ffe01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for CRDs from local IA cores to locally homed memory",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_LOCAL",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Occupancy : CRd issued by iA Cores that Missed the LLC - HOMed locally",
	+ "UMask": "0xc80efe01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for Code read prefetch from local IA that miss the cache",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_PREF",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores that Missed the LLC",
	+ "UMask": "0xc88ffe01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for CRD Prefetches from local IA cores to locally homed memory",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_PREF_LOCAL",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed locally",
	+ "UMask": "0xc88efe01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for CRD Prefetches from local IA cores to remotely homed memory",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_PREF_REMOTE",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed remotely",
	+ "UMask": "0xc88f7e01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for CRDs from local IA cores to remotely homed memory",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_REMOTE",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Occupancy : CRd issued by iA Cores that Missed the LLC - HOMed remotely",
	+ "UMask": "0xc80f7e01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for All requests issued from IA cores to CXL accelerator memory regions that miss the LLC.",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CXL_ACC",
	+ "PerPkg": "1",
	+ "UMask": "0x10c0018201",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for Data read from local IA that miss the cache",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Occupancy : DRds issued by iA Cores that Missed the LLC",
	+ "UMask": "0xc817fe01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for DRd PTEs issued by iA Cores due to a page walk that missed the LLC",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRDPTE",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Occupancy : DRdPte issued by iA Cores due to a page walk that missed the LLC",
	+ "UMask": "0xc837fe01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for DRds and equivalent opcodes issued from an IA core which miss the L3 and target memory in a CXL type 2 memory expander card.",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_CXL_ACC",
	+ "PerPkg": "1",
	+ "UMask": "0x10c8178201",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for DRds issued by iA Cores targeting DDR Mem that Missed the LLC",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_DDR",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Occupancy : DRds issued by iA Cores targeting DDR Mem that Missed the LLC",
	+ "UMask": "0xc8178601",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for Data read from local IA that miss the cache",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Occupancy : DRds issued by iA Cores that Missed the LLC - HOMed locally",
	+ "UMask": "0xc816fe01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for DRds from local IA cores to locally homed DDR addresses that miss the cache",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL_DDR",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Occupancy : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally",
	+ "UMask": "0xc8168601",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for DRds from local IA cores to locally homed PMM addresses that miss the cache",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL_PMM",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Occupancy : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally",
	+ "UMask": "0xc8168a01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for DRds issued by iA Cores targeting PMM Mem that Missed the LLC",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PMM",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Occupancy : DRds issued by iA Cores targeting PMM Mem that Missed the LLC",
	+ "UMask": "0xc8178a01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for Data read prefetch from local IA that miss the cache",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores that Missed the LLC",
	+ "UMask": "0xc897fe01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for L2 data prefetches issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator.",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_CXL_ACC",
	+ "PerPkg": "1",
	+ "UMask": "0x10c8978201",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for DRd Prefetches from local IA cores to DDR addresses that miss the cache",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_DDR",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC",
	+ "UMask": "0xc8978601",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for Data read prefetch from local IA that miss the cache",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_LOCAL",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Occupancy; Data read prefetch from local IA that misses in the snoop filter",
	+ "UMask": "0xc896fe01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for DRd Prefetches from local IA cores to locally homed DDR addresses that miss the cache",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_LOCAL_DDR",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally",
	+ "UMask": "0xc8968601",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for DRd Prefetches from local IA cores to locally homed PMM addresses that miss the cache",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_LOCAL_PMM",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally",
	+ "UMask": "0xc8968a01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for DRd Prefetches from local IA cores to PMM addresses that miss the cache",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_PMM",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC",
	+ "UMask": "0xc8978a01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for Data read prefetch from local IA that miss the cache",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_REMOTE",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Occupancy; Data read prefetch from local IA that misses in the snoop filter",
	+ "UMask": "0xc8977e01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for DRd Prefetches from local IA cores to remotely homed DDR addresses that miss the cache",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_REMOTE_DDR",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely",
	+ "UMask": "0xc8970601",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for DRd Prefetches from local IA cores to remotely homed PMM addresses that miss the cache",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_REMOTE_PMM",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely",
	+ "UMask": "0xc8970a01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for Data read from local IA that miss the cache",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Occupancy : DRds issued by iA Cores that Missed the LLC - HOMed remotely",
	+ "UMask": "0xc8177e01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for DRds from local IA cores to remotely homed DDR addresses that miss the cache",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE_DDR",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Occupancy : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely",
	+ "UMask": "0xc8170601",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for DRds from local IA cores to remotely homed PMM addresses that miss the cache",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE_PMM",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Occupancy : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely",
	+ "UMask": "0xc8170a01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for ItoM requests from local IA cores that miss the cache",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_ITOM",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Occupancy : ItoMs issued by iA Cores that Missed LLC",
	+ "UMask": "0xcc47fe01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for Last level cache prefetch code read from local IA that miss the cache",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFCODE",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Occupancy : LLCPrefCode issued by iA Cores that missed the LLC",
	+ "UMask": "0xcccffe01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for Last level cache prefetch data read from local IA that miss the cache",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFDATA",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Occupancy : LLCPrefData issued by iA Cores that missed the LLC",
	+ "UMask": "0xccd7fe01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for LLC data prefetches issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator.",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFDATA_CXL_ACC",
	+ "PerPkg": "1",
	+ "UMask": "0x10ccd78201",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for Last level cache prefetch read for ownership from local IA that miss the cache",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFRFO",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Occupancy : LLCPrefRFO issued by iA Cores that missed the LLC",
	+ "UMask": "0xccc7fe01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for L2 RFO prefetches issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator.",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFRFO_CXL_ACC",
	+ "PerPkg": "1",
	+ "UMask": "0x10c8878201",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for WCILF requests from local IA cores to locally homed DDR addresses that miss the cache",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LOCAL_WCILF_DDR",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed locally",
	+ "UMask": "0xc8668601",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for WCILF requests from local IA cores to locally homed PMM addresses which miss the cache",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LOCAL_WCILF_PMM",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed locally",
	+ "UMask": "0xc8668a01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for WCIL requests from local IA cores to locally homed DDR addresses that miss the cache",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LOCAL_WCIL_DDR",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed locally",
	+ "UMask": "0xc86e8601",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for WCIL requests from local IA cores to locally homed PMM addresses which miss the cache",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LOCAL_WCIL_PMM",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed locally",
	+ "UMask": "0xc86e8a01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for WCILF requests from local IA cores to remotely homed DDR addresses that miss the cache",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_REMOTE_WCILF_DDR",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely",
	+ "UMask": "0xc8670601",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for WCILF requests from local IA cores to remotely homed PMM addresses which miss the cache",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_REMOTE_WCILF_PMM",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely",
	+ "UMask": "0xc8670a01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for WCIL requests from local IA cores to remotely homed DDR addresses that miss the cache",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_REMOTE_WCIL_DDR",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely",
	+ "UMask": "0xc86f0601",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for WCIL requests from local IA cores to remotely homed PMM addresses which miss the cache",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_REMOTE_WCIL_PMM",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely",
	+ "UMask": "0xc86f0a01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for Read for ownership from local IA that miss the cache",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Occupancy : RFOs issued by iA Cores that Missed the LLC",
	+ "UMask": "0xc807fe01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for RFOs issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator.",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_CXL_ACC",
	+ "PerPkg": "1",
	+ "UMask": "0x10c8078201",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for Read for ownership from local IA that miss the cache",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_LOCAL",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Occupancy : RFOs issued by iA Cores that Missed the LLC - HOMed locally",
	+ "UMask": "0xc806fe01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for Read for ownership prefetch from local IA that miss the cache",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores that Missed the LLC",
	+ "UMask": "0xc887fe01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for LLC RFO prefetches issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator.",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF_CXL_ACC",
	+ "PerPkg": "1",
	+ "UMask": "0x10ccc78201",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for Read for ownership prefetch from local IA that miss the cache",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF_LOCAL",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed locally",
	+ "UMask": "0xc886fe01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for Read for ownership prefetch from local IA that miss the cache",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF_REMOTE",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed remotely",
	+ "UMask": "0xc8877e01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for Read for ownership from local IA that miss the cache",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_REMOTE",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Occupancy : RFOs issued by iA Cores that Missed the LLC - HOMed remotely",
	+ "UMask": "0xc8077e01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for UCRDF requests from local IA cores that miss the cache",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_UCRDF",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Occupancy : UCRdFs issued by iA Cores that Missed LLC",
	+ "UMask": "0xc877de01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for WCIL requests from a local IA core that miss the cache",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCIL",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores that Missed the LLC",
	+ "UMask": "0xc86ffe01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for WCILF requests from local IA core that miss the cache",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCILF",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Occupancy : WCiLF issued by iA Cores that Missed the LLC",
	+ "UMask": "0xc867fe01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for WCILF requests from local IA cores to DDR homed addresses which miss the cache",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCILF_DDR",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC",
	+ "UMask": "0xc8678601",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for WCILF requests from local IA cores to PMM homed addresses which miss the cache",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCILF_PMM",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting PMM that missed the LLC",
	+ "UMask": "0xc8678a01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for WCIL requests from local IA cores to DDR homed addresses which miss the cache",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCIL_DDR",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC",
	+ "UMask": "0xc86f8601",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for WCIL requests from a local IA core to PMM homed addresses that miss the cache",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCIL_PMM",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting PMM that missed the LLC",
	+ "UMask": "0xc86f8a01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for WIL requests from local IA cores that miss the cache",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WIL",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Occupancy : WiLs issued by iA Cores that Missed LLC",
	+ "UMask": "0xc87fde01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for Read for ownership from local IA that miss the cache",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_RFO",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Occupancy : RFOs issued by iA Cores",
	+ "UMask": "0xc807ff01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for Read for ownership prefetch from local IA that miss the cache",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_RFO_PREF",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores",
	+ "UMask": "0xc887ff01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for SpecItoM events that are initiated from the Core",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_SPECITOM",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Occupancy : SpecItoMs issued by iA Cores",
	+ "UMask": "0xcc57ff01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for WbMtoI requests from local IA cores",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_WBMTOI",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Occupancy : WbMtoIs issued by iA Cores",
	+ "UMask": "0xcc27ff01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for WCIL requests from a local IA core",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_WCIL",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores",
	+ "UMask": "0xc86fff01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for WCILF requests from local IA core",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_WCILF",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Occupancy : WCiLF issued by iA Cores",
	+ "UMask": "0xc867ff01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for All TOR inserts from local IO devices",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IO",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Occupancy : All requests from IO Devices",
	+ "UMask": "0xc001ff04",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for CLFlush requests from IO devices",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_CLFLUSH",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Occupancy : CLFlushes issued by IO Devices",
	+ "UMask": "0xc8c3ff04",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for All TOR inserts from local IO devices which hit the cache",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Occupancy : All requests from IO Devices that hit the LLC",
	+ "UMask": "0xc001fd04",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for ItoMs from local IO devices which hit the cache",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_ITOM",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Occupancy : ItoMs issued by IO Devices that Hit the LLC",
	+ "UMask": "0xcc43fd04",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_ITOMCACHENEAR",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC",
	+ "UMask": "0xcd43fd04",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for PCIRDCURs issued by IO devices which hit the LLC",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_PCIRDCUR",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Occupancy : PCIRdCurs issued by IO Devices that hit the LLC",
	+ "UMask": "0xc8f3fd04",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for RFOs from local IO devices which hit the cache",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_RFO",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Occupancy : RFOs issued by IO Devices that hit the LLC",
	+ "UMask": "0xc803fd04",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for All TOR ItoM inserts from local IO devices",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_ITOM",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Occupancy : ItoMs issued by IO Devices",
	+ "UMask": "0xcc43ff04",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for ItoMCacheNears, indicating a partial write request, from IO Devices",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_ITOMCACHENEAR",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices",
	+ "UMask": "0xcd43ff04",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for All TOR inserts from local IO devices which miss the cache",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Occupancy : All requests from IO Devices that missed the LLC",
	+ "UMask": "0xc001fe04",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for All TOR ItoM inserts from local IO devices which miss the cache",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOM",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Occupancy : ItoMs issued by IO Devices that missed the LLC",
	+ "UMask": "0xcc43fe04",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOMCACHENEAR",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC",
	+ "UMask": "0xcd43fe04",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for ItoMCacheNear transactions from an IO device on the local socket that miss the cache",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOMCACHENEAR_LOCAL",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC",
	+ "UMask": "0xcd42fe04",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for ItoMCacheNear transactions from an IO device on a remote socket that miss the cache",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOMCACHENEAR_REMOTE",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC",
	+ "UMask": "0xcd437e04",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for ItoM transactions from an IO device on the local socket that miss the cache",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOM_LOCAL",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Occupancy : ItoMs issued by IO Devices that missed the LLC",
	+ "UMask": "0xcc42fe04",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for ItoM transactions from an IO device on a remote socket that miss the cache",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOM_REMOTE",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Occupancy : ItoMs issued by IO Devices that missed the LLC",
	+ "UMask": "0xcc437e04",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for PCIRDCURs issued by IO devices which miss the LLC",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_PCIRDCUR",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Occupancy : PCIRdCurs issued by IO Devices that missed the LLC",
	+ "UMask": "0xc8f3fe04",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for PCIRDCUR transactions from an IO device on the local socket that miss the cache",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_PCIRDCUR_LOCAL",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Occupancy : PCIRdCurs issued by IO Devices that missed the LLC",
	+ "UMask": "0xc8f2fe04",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for PCIRDCUR transactions from an IO device on a remote socket that miss the cache",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_PCIRDCUR_REMOTE",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Occupancy : PCIRdCurs issued by IO Devices that missed the LLC",
	+ "UMask": "0xc8f37e04",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for All TOR RFO inserts from local IO devices which miss the cache",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_RFO",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Occupancy : RFOs issued by IO Devices that missed the LLC",
	+ "UMask": "0xc803fe04",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for PCIRDCURs issued by IO devices",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_PCIRDCUR",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Occupancy : PCIRdCurs issued by IO Devices",
	+ "UMask": "0xc8f3ff04",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for RFOs from local IO devices",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_RFO",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Occupancy : RFOs issued by IO Devices",
	+ "UMask": "0xc803ff04",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for WBMtoI requests from IO devices",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_WBMTOI",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Occupancy : WbMtoIs issued by IO Devices",
	+ "UMask": "0xcc23ff04",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for All locally initiated requests",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.LOC_ALL",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Occupancy : All from Local iA and IO",
	+ "UMask": "0xc000ff05",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for All from Local iA",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.LOC_IA",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Occupancy : All from Local iA",
	+ "UMask": "0xc000ff01",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for All from Local IO",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.LOC_IO",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Occupancy : All from Local IO",
	+ "UMask": "0xc000ff04",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for All remote requests (e.g. snoops, writebacks) that came from remote sockets",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.REM_ALL",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Occupancy : All Remote Requests",
	+ "UMask": "0xc001ffc8",
	+ "Unit": "CHA"
	+ },
	+ {
	+ "BriefDescription": "TOR Occupancy for All snoops to this LLC that came from remote sockets",
	+ "Counter": "0",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_CHA_TOR_OCCUPANCY.REM_SNPS",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PublicDescription": "TOR Occupancy : All Snoops from Remote",
	+ "UMask": "0xc001ff08",
	+ "Unit": "CHA"
	+ }
	+]
	\ No newline at end of file
	diff --git a/lib/libpmc/pmu-events/arch/x86/graniterapids/uncore-cxl.json b/lib/libpmc/pmu-events/arch/x86/graniterapids/uncore-cxl.json
	new file mode 100644
	--- /dev/null
	+++ b/lib/libpmc/pmu-events/arch/x86/graniterapids/uncore-cxl.json
	@@ -0,0 +1,29 @@
	+[
	+ {
	+ "BriefDescription": "B2CXL Clockticks",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x01",
	+ "EventName": "UNC_B2CXL_CLOCKTICKS",
	+ "PerPkg": "1",
	+ "PortMask": "0x000",
	+ "Unit": "B2CXL"
	+ },
	+ {
	+ "BriefDescription": "Number of Allocation to Mem Data Packing buffer",
	+ "Counter": "4,5,6,7",
	+ "EventCode": "0x41",
	+ "EventName": "UNC_CXLCM_RxC_PACK_BUF_INSERTS.MEM_DATA",
	+ "PerPkg": "1",
	+ "UMask": "0x10",
	+ "Unit": "CXLCM"
	+ },
	+ {
	+ "BriefDescription": "Number of Allocation to M2S Data AGF",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x02",
	+ "EventName": "UNC_CXLDP_TxC_AGF_INSERTS.M2S_DATA",
	+ "PerPkg": "1",
	+ "UMask": "0x20",
	+ "Unit": "CXLDP"
	+ }
	+]
	\ No newline at end of file
	diff --git a/lib/libpmc/pmu-events/arch/x86/graniterapids/uncore-interconnect.json b/lib/libpmc/pmu-events/arch/x86/graniterapids/uncore-interconnect.json
	new file mode 100644
	--- /dev/null
	+++ b/lib/libpmc/pmu-events/arch/x86/graniterapids/uncore-interconnect.json
	@@ -0,0 +1,1979 @@
	+[
	+ {
	+ "BriefDescription": "Clockticks of the mesh to memory (B2CMI)",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x01",
	+ "EventName": "UNC_B2CMI_CLOCKTICKS",
	+ "PerPkg": "1",
	+ "Unit": "B2CMI"
	+ },
	+ {
	+ "BriefDescription": "Counts the number of time D2C was not honoured by egress due to directory state constraints",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x17",
	+ "EventName": "UNC_B2CMI_DIRECT2CORE_NOT_TAKEN_DIRSTATE",
	+ "PerPkg": "1",
	+ "UMask": "0x1",
	+ "Unit": "B2CMI"
	+ },
	+ {
	+ "BriefDescription": "Counts the number of times B2CMI egress did D2C (direct to core)",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x16",
	+ "EventName": "UNC_B2CMI_DIRECT2CORE_TAKEN",
	+ "PerPkg": "1",
	+ "UMask": "0x1",
	+ "Unit": "B2CMI"
	+ },
	+ {
	+ "BriefDescription": "Counts the number of times D2C wasn't honoured even though the incoming request had d2c set for non cisgress txn",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x18",
	+ "EventName": "UNC_B2CMI_DIRECT2CORE_TXN_OVERRIDE",
	+ "PerPkg": "1",
	+ "UMask": "0x1",
	+ "Unit": "B2CMI"
	+ },
	+ {
	+ "BriefDescription": "Counts the number of d2k wasn't done due to credit constraints",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x1B",
	+ "EventName": "UNC_B2CMI_DIRECT2UPI_NOT_TAKEN_CREDITS",
	+ "PerPkg": "1",
	+ "UMask": "0x1",
	+ "Unit": "B2CMI"
	+ },
	+ {
	+ "BriefDescription": "Direct to UPI Transactions - Ignored due to lack of credits : All : Counts the number of d2k wasn't done due to credit constraints",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x1B",
	+ "EventName": "UNC_B2CMI_DIRECT2UPI_NOT_TAKEN_CREDITS.EGRESS",
	+ "PerPkg": "1",
	+ "UMask": "0x1",
	+ "Unit": "B2CMI"
	+ },
	+ {
	+ "BriefDescription": "Counts the number of time D2K was not honoured by egress due to directory state constraints",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x1A",
	+ "EventName": "UNC_B2CMI_DIRECT2UPI_NOT_TAKEN_DIRSTATE",
	+ "PerPkg": "1",
	+ "UMask": "0x1",
	+ "Unit": "B2CMI"
	+ },
	+ {
	+ "BriefDescription": "Cycles when Direct2UPI was Disabled : Egress Ignored D2U : Counts the number of time D2K was not honoured by egress due to directory state constraints",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x1A",
	+ "EventName": "UNC_B2CMI_DIRECT2UPI_NOT_TAKEN_DIRSTATE.EGRESS",
	+ "PerPkg": "1",
	+ "UMask": "0x1",
	+ "Unit": "B2CMI"
	+ },
	+ {
	+ "BriefDescription": "Counts the number of times egress did D2K (Direct to KTI)",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x19",
	+ "EventName": "UNC_B2CMI_DIRECT2UPI_TAKEN",
	+ "PerPkg": "1",
	+ "UMask": "0x1",
	+ "Unit": "B2CMI"
	+ },
	+ {
	+ "BriefDescription": "Counts the number of times D2K wasn't honoured even though the incoming request had d2k set for non cisgress txn",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x1C",
	+ "EventName": "UNC_B2CMI_DIRECT2UPI_TXN_OVERRIDE",
	+ "PerPkg": "1",
	+ "UMask": "0x1",
	+ "Unit": "B2CMI"
	+ },
	+ {
	+ "BriefDescription": "Directory Hit Clean",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x1D",
	+ "EventName": "UNC_B2CMI_DIRECTORY_HIT.CLEAN",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x38",
	+ "Unit": "B2CMI"
	+ },
	+ {
	+ "BriefDescription": "Directory Hit : On NonDirty Line in A State",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x1D",
	+ "EventName": "UNC_B2CMI_DIRECTORY_HIT.CLEAN_A",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x20",
	+ "Unit": "B2CMI"
	+ },
	+ {
	+ "BriefDescription": "Directory Hit : On NonDirty Line in I State",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x1D",
	+ "EventName": "UNC_B2CMI_DIRECTORY_HIT.CLEAN_I",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x8",
	+ "Unit": "B2CMI"
	+ },
	+ {
	+ "BriefDescription": "Directory Hit : On NonDirty Line in S State",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x1D",
	+ "EventName": "UNC_B2CMI_DIRECTORY_HIT.CLEAN_S",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x10",
	+ "Unit": "B2CMI"
	+ },
	+ {
	+ "BriefDescription": "Directory Hit Dirty (modified)",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x1D",
	+ "EventName": "UNC_B2CMI_DIRECTORY_HIT.DIRTY",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x7",
	+ "Unit": "B2CMI"
	+ },
	+ {
	+ "BriefDescription": "Directory Hit : On Dirty Line in A State",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x1D",
	+ "EventName": "UNC_B2CMI_DIRECTORY_HIT.DIRTY_A",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x4",
	+ "Unit": "B2CMI"
	+ },
	+ {
	+ "BriefDescription": "Directory Hit : On Dirty Line in I State",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x1D",
	+ "EventName": "UNC_B2CMI_DIRECTORY_HIT.DIRTY_I",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x1",
	+ "Unit": "B2CMI"
	+ },
	+ {
	+ "BriefDescription": "Directory Hit : On Dirty Line in S State",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x1D",
	+ "EventName": "UNC_B2CMI_DIRECTORY_HIT.DIRTY_S",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x2",
	+ "Unit": "B2CMI"
	+ },
	+ {
	+ "BriefDescription": "Counts the number of 1lm or 2lm hit read data returns to egress with any directory to non persistent memory",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x20",
	+ "EventName": "UNC_B2CMI_DIRECTORY_LOOKUP.ANY",
	+ "PerPkg": "1",
	+ "UMask": "0x1",
	+ "Unit": "B2CMI"
	+ },
	+ {
	+ "BriefDescription": "Counts the number of 1lm or 2lm hit read data returns to egress with directory A to non persistent memory",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x20",
	+ "EventName": "UNC_B2CMI_DIRECTORY_LOOKUP.STATE_A",
	+ "PerPkg": "1",
	+ "UMask": "0x8",
	+ "Unit": "B2CMI"
	+ },
	+ {
	+ "BriefDescription": "Counts the number of 1lm or 2lm hit read data returns to egress with directory I to non persistent memory",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x20",
	+ "EventName": "UNC_B2CMI_DIRECTORY_LOOKUP.STATE_I",
	+ "PerPkg": "1",
	+ "UMask": "0x2",
	+ "Unit": "B2CMI"
	+ },
	+ {
	+ "BriefDescription": "Counts the number of 1lm or 2lm hit read data returns to egress with directory S to non persistent memory",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x20",
	+ "EventName": "UNC_B2CMI_DIRECTORY_LOOKUP.STATE_S",
	+ "PerPkg": "1",
	+ "PublicDescription": "Counts the number of 1lm or 2lm hit read data returns to egress with directory S to non persistent memory",
	+ "UMask": "0x4",
	+ "Unit": "B2CMI"
	+ },
	+ {
	+ "BriefDescription": "Directory Miss Clean",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x1E",
	+ "EventName": "UNC_B2CMI_DIRECTORY_MISS.CLEAN",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x38",
	+ "Unit": "B2CMI"
	+ },
	+ {
	+ "BriefDescription": "Directory Miss : On NonDirty Line in A State",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x1E",
	+ "EventName": "UNC_B2CMI_DIRECTORY_MISS.CLEAN_A",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x20",
	+ "Unit": "B2CMI"
	+ },
	+ {
	+ "BriefDescription": "Directory Miss : On NonDirty Line in I State",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x1E",
	+ "EventName": "UNC_B2CMI_DIRECTORY_MISS.CLEAN_I",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x8",
	+ "Unit": "B2CMI"
	+ },
	+ {
	+ "BriefDescription": "Directory Miss : On NonDirty Line in S State",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x1E",
	+ "EventName": "UNC_B2CMI_DIRECTORY_MISS.CLEAN_S",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x10",
	+ "Unit": "B2CMI"
	+ },
	+ {
	+ "BriefDescription": "Directory Miss Dirty (modified)",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x1E",
	+ "EventName": "UNC_B2CMI_DIRECTORY_MISS.DIRTY",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x7",
	+ "Unit": "B2CMI"
	+ },
	+ {
	+ "BriefDescription": "Directory Miss : On Dirty Line in A State",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x1E",
	+ "EventName": "UNC_B2CMI_DIRECTORY_MISS.DIRTY_A",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x4",
	+ "Unit": "B2CMI"
	+ },
	+ {
	+ "BriefDescription": "Directory Miss : On Dirty Line in I State",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x1E",
	+ "EventName": "UNC_B2CMI_DIRECTORY_MISS.DIRTY_I",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x1",
	+ "Unit": "B2CMI"
	+ },
	+ {
	+ "BriefDescription": "Directory Miss : On Dirty Line in S State",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x1E",
	+ "EventName": "UNC_B2CMI_DIRECTORY_MISS.DIRTY_S",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x2",
	+ "Unit": "B2CMI"
	+ },
	+ {
	+ "BriefDescription": "Any A2I Transition",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x21",
	+ "EventName": "UNC_B2CMI_DIRECTORY_UPDATE.A2I",
	+ "PerPkg": "1",
	+ "UMask": "0x320",
	+ "Unit": "B2CMI"
	+ },
	+ {
	+ "BriefDescription": "Any A2S Transition",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x21",
	+ "EventName": "UNC_B2CMI_DIRECTORY_UPDATE.A2S",
	+ "PerPkg": "1",
	+ "UMask": "0x340",
	+ "Unit": "B2CMI"
	+ },
	+ {
	+ "BriefDescription": "Counts cisgress directory updates",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x21",
	+ "EventName": "UNC_B2CMI_DIRECTORY_UPDATE.ANY",
	+ "PerPkg": "1",
	+ "UMask": "0x301",
	+ "Unit": "B2CMI"
	+ },
	+ {
	+ "BriefDescription": "Counts any 1lm or 2lm hit data return that would result in directory update to non persistent memory (DRAM)",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x21",
	+ "EventName": "UNC_B2CMI_DIRECTORY_UPDATE.HIT_ANY",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x101",
	+ "Unit": "B2CMI"
	+ },
	+ {
	+ "BriefDescription": "Directory update in near memory to the A state",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x21",
	+ "EventName": "UNC_B2CMI_DIRECTORY_UPDATE.HIT_X2A",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x114",
	+ "Unit": "B2CMI"
	+ },
	+ {
	+ "BriefDescription": "Directory update in near memory to the I state",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x21",
	+ "EventName": "UNC_B2CMI_DIRECTORY_UPDATE.HIT_X2I",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x128",
	+ "Unit": "B2CMI"
	+ },
	+ {
	+ "BriefDescription": "Directory update in near memory to the S state",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x21",
	+ "EventName": "UNC_B2CMI_DIRECTORY_UPDATE.HIT_X2S",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x142",
	+ "Unit": "B2CMI"
	+ },
	+ {
	+ "BriefDescription": "Any I2A Transition",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x21",
	+ "EventName": "UNC_B2CMI_DIRECTORY_UPDATE.I2A",
	+ "PerPkg": "1",
	+ "UMask": "0x304",
	+ "Unit": "B2CMI"
	+ },
	+ {
	+ "BriefDescription": "Any I2S Transition",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x21",
	+ "EventName": "UNC_B2CMI_DIRECTORY_UPDATE.I2S",
	+ "PerPkg": "1",
	+ "UMask": "0x302",
	+ "Unit": "B2CMI"
	+ },
	+ {
	+ "BriefDescription": "Directory update in far memory to the A state",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x21",
	+ "EventName": "UNC_B2CMI_DIRECTORY_UPDATE.MISS_X2A",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x214",
	+ "Unit": "B2CMI"
	+ },
	+ {
	+ "BriefDescription": "Directory update in far memory to the I state",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x21",
	+ "EventName": "UNC_B2CMI_DIRECTORY_UPDATE.MISS_X2I",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x228",
	+ "Unit": "B2CMI"
	+ },
	+ {
	+ "BriefDescription": "Directory update in far memory to the S state",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x21",
	+ "EventName": "UNC_B2CMI_DIRECTORY_UPDATE.MISS_X2S",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x242",
	+ "Unit": "B2CMI"
	+ },
	+ {
	+ "BriefDescription": "Any S2A Transition",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x21",
	+ "EventName": "UNC_B2CMI_DIRECTORY_UPDATE.S2A",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x310",
	+ "Unit": "B2CMI"
	+ },
	+ {
	+ "BriefDescription": "Any S2I Transition",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x21",
	+ "EventName": "UNC_B2CMI_DIRECTORY_UPDATE.S2I",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x308",
	+ "Unit": "B2CMI"
	+ },
	+ {
	+ "BriefDescription": "Directory update to the A state",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x21",
	+ "EventName": "UNC_B2CMI_DIRECTORY_UPDATE.X2A",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x314",
	+ "Unit": "B2CMI"
	+ },
	+ {
	+ "BriefDescription": "Directory update to the I state",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x21",
	+ "EventName": "UNC_B2CMI_DIRECTORY_UPDATE.X2I",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x328",
	+ "Unit": "B2CMI"
	+ },
	+ {
	+ "BriefDescription": "Directory update to the S state",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x21",
	+ "EventName": "UNC_B2CMI_DIRECTORY_UPDATE.X2S",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x342",
	+ "Unit": "B2CMI"
	+ },
	+ {
	+ "BriefDescription": "Counts any read",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x24",
	+ "EventName": "UNC_B2CMI_IMC_READS.ALL",
	+ "PerPkg": "1",
	+ "UMask": "0x104",
	+ "Unit": "B2CMI"
	+ },
	+ {
	+ "BriefDescription": "Counts normal reads issue to CMI",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x24",
	+ "EventName": "UNC_B2CMI_IMC_READS.NORMAL",
	+ "PerPkg": "1",
	+ "UMask": "0x101",
	+ "Unit": "B2CMI"
	+ },
	+ {
	+ "BriefDescription": "Count reads to NM region",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x24",
	+ "EventName": "UNC_B2CMI_IMC_READS.TO_DDR_AS_CACHE",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x110",
	+ "Unit": "B2CMI"
	+ },
	+ {
	+ "BriefDescription": "Counts reads to 1lm non persistent memory regions",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x24",
	+ "EventName": "UNC_B2CMI_IMC_READS.TO_DDR_AS_MEM",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x108",
	+ "Unit": "B2CMI"
	+ },
	+ {
	+ "BriefDescription": "All Writes - All Channels",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x25",
	+ "EventName": "UNC_B2CMI_IMC_WRITES.ALL",
	+ "PerPkg": "1",
	+ "UMask": "0x110",
	+ "Unit": "B2CMI"
	+ },
	+ {
	+ "BriefDescription": "Full Non-ISOCH - All Channels",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x25",
	+ "EventName": "UNC_B2CMI_IMC_WRITES.FULL",
	+ "PerPkg": "1",
	+ "UMask": "0x101",
	+ "Unit": "B2CMI"
	+ },
	+ {
	+ "BriefDescription": "Non-Inclusive - All Channels",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x25",
	+ "EventName": "UNC_B2CMI_IMC_WRITES.NI",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "Unit": "B2CMI"
	+ },
	+ {
	+ "BriefDescription": "Non-Inclusive Miss - All Channels",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x25",
	+ "EventName": "UNC_B2CMI_IMC_WRITES.NI_MISS",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "Unit": "B2CMI"
	+ },
	+ {
	+ "BriefDescription": "Partial Non-ISOCH - All Channels",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x25",
	+ "EventName": "UNC_B2CMI_IMC_WRITES.PARTIAL",
	+ "PerPkg": "1",
	+ "UMask": "0x102",
	+ "Unit": "B2CMI"
	+ },
	+ {
	+ "BriefDescription": "DDR, acting as Cache - All Channels",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x25",
	+ "EventName": "UNC_B2CMI_IMC_WRITES.TO_DDR_AS_CACHE",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x140",
	+ "Unit": "B2CMI"
	+ },
	+ {
	+ "BriefDescription": "DDR - All Channels",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x25",
	+ "EventName": "UNC_B2CMI_IMC_WRITES.TO_DDR_AS_MEM",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x120",
	+ "Unit": "B2CMI"
	+ },
	+ {
	+ "BriefDescription": "Prefetch CAM Inserts : UPI - Ch 0",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x56",
	+ "EventName": "UNC_B2CMI_PREFCAM_INSERTS.CH0_UPI",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x2",
	+ "Unit": "B2CMI"
	+ },
	+ {
	+ "BriefDescription": "Prefetch CAM Inserts : XPT - Ch 0",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x56",
	+ "EventName": "UNC_B2CMI_PREFCAM_INSERTS.CH0_XPT",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x1",
	+ "Unit": "B2CMI"
	+ },
	+ {
	+ "BriefDescription": "Prefetch CAM Inserts : UPI - All Channels",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x56",
	+ "EventName": "UNC_B2CMI_PREFCAM_INSERTS.UPI_ALLCH",
	+ "PerPkg": "1",
	+ "UMask": "0x2",
	+ "Unit": "B2CMI"
	+ },
	+ {
	+ "BriefDescription": "Prefetch CAM Inserts : XPT -All Channels",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x56",
	+ "EventName": "UNC_B2CMI_PREFCAM_INSERTS.XPT_ALLCH",
	+ "PerPkg": "1",
	+ "PublicDescription": "Prefetch CAM Inserts : XPT - All Channels",
	+ "UMask": "0x1",
	+ "Unit": "B2CMI"
	+ },
	+ {
	+ "BriefDescription": "Prefetch CAM Occupancy : Channel 0",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x54",
	+ "EventName": "UNC_B2CMI_PREFCAM_OCCUPANCY.CH0",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x1",
	+ "Unit": "B2CMI"
	+ },
	+ {
	+ "BriefDescription": "Counts the 2lm reads and WRNI which were a hit",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x1F",
	+ "EventName": "UNC_B2CMI_TAG_HIT.ALL",
	+ "PerPkg": "1",
	+ "UMask": "0xf",
	+ "Unit": "B2CMI"
	+ },
	+ {
	+ "BriefDescription": "Counts the 2lm reads which were a hit clean",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x1F",
	+ "EventName": "UNC_B2CMI_TAG_HIT.RD_CLEAN",
	+ "PerPkg": "1",
	+ "UMask": "0x1",
	+ "Unit": "B2CMI"
	+ },
	+ {
	+ "BriefDescription": "Counts the 2lm reads which were a hit dirty",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x1F",
	+ "EventName": "UNC_B2CMI_TAG_HIT.RD_DIRTY",
	+ "PerPkg": "1",
	+ "UMask": "0x2",
	+ "Unit": "B2CMI"
	+ },
	+ {
	+ "BriefDescription": "Counts the 2lm WRNI which were a hit clean",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x1F",
	+ "EventName": "UNC_B2CMI_TAG_HIT.WR_CLEAN",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x4",
	+ "Unit": "B2CMI"
	+ },
	+ {
	+ "BriefDescription": "Counts the 2lm WRNI which were a hit dirty",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x1F",
	+ "EventName": "UNC_B2CMI_TAG_HIT.WR_DIRTY",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x8",
	+ "Unit": "B2CMI"
	+ },
	+ {
	+ "BriefDescription": "Counts the 2lm second way read miss for a WrNI",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x4B",
	+ "EventName": "UNC_B2CMI_TAG_MISS.CLEAN",
	+ "PerPkg": "1",
	+ "UMask": "0x5",
	+ "Unit": "B2CMI"
	+ },
	+ {
	+ "BriefDescription": "Counts the 2lm second way read miss for a WrNI",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x4B",
	+ "EventName": "UNC_B2CMI_TAG_MISS.DIRTY",
	+ "PerPkg": "1",
	+ "UMask": "0xa",
	+ "Unit": "B2CMI"
	+ },
	+ {
	+ "BriefDescription": "Counts the 2lm second way read miss for a Rd",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x4B",
	+ "EventName": "UNC_B2CMI_TAG_MISS.RD_2WAY",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x10",
	+ "Unit": "B2CMI"
	+ },
	+ {
	+ "BriefDescription": "Counts the 2lm reads which were a miss and the cache line is unmodified",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x4B",
	+ "EventName": "UNC_B2CMI_TAG_MISS.RD_CLEAN",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x1",
	+ "Unit": "B2CMI"
	+ },
	+ {
	+ "BriefDescription": "Counts the 2lm reads which were a miss and the cache line is modified",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x4B",
	+ "EventName": "UNC_B2CMI_TAG_MISS.RD_DIRTY",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x2",
	+ "Unit": "B2CMI"
	+ },
	+ {
	+ "BriefDescription": "Counts the 2lm second way read miss for a WrNI",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x4B",
	+ "EventName": "UNC_B2CMI_TAG_MISS.WR_2WAY",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x20",
	+ "Unit": "B2CMI"
	+ },
	+ {
	+ "BriefDescription": "Counts the 2lm WRNI which were a miss and the cache line is unmodified",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x4B",
	+ "EventName": "UNC_B2CMI_TAG_MISS.WR_CLEAN",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x4",
	+ "Unit": "B2CMI"
	+ },
	+ {
	+ "BriefDescription": "Counts the 2lm WRNI which were a miss and the cache line is modified",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x4B",
	+ "EventName": "UNC_B2CMI_TAG_MISS.WR_DIRTY",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x8",
	+ "Unit": "B2CMI"
	+ },
	+ {
	+ "BriefDescription": "Tracker Inserts : Channel 0",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x32",
	+ "EventName": "UNC_B2CMI_TRACKER_INSERTS.CH0",
	+ "PerPkg": "1",
	+ "UMask": "0x104",
	+ "Unit": "B2CMI"
	+ },
	+ {
	+ "BriefDescription": "Tracker Occupancy : Channel 0",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x33",
	+ "EventName": "UNC_B2CMI_TRACKER_OCCUPANCY.CH0",
	+ "PerPkg": "1",
	+ "UMask": "0x1",
	+ "Unit": "B2CMI"
	+ },
	+ {
	+ "BriefDescription": "Write Tracker Inserts : Channel 0",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x40",
	+ "EventName": "UNC_B2CMI_WR_TRACKER_INSERTS.CH0",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x1",
	+ "Unit": "B2CMI"
	+ },
	+ {
	+ "BriefDescription": "UNC_B2HOT_CLOCKTICKS",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x01",
	+ "EventName": "UNC_B2HOT_CLOCKTICKS",
	+ "PerPkg": "1",
	+ "PublicDescription": "Clockticks for the B2HOT unit",
	+ "UMask": "0x1",
	+ "Unit": "B2HOT"
	+ },
	+ {
	+ "BriefDescription": "Number of uclks in domain",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x01",
	+ "EventName": "UNC_B2UPI_CLOCKTICKS",
	+ "PerPkg": "1",
	+ "Unit": "B2UPI"
	+ },
	+ {
	+ "BriefDescription": "Total Write Cache Occupancy : Mem",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x0F",
	+ "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.MEM",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x4",
	+ "Unit": "IRP"
	+ },
	+ {
	+ "BriefDescription": "IRP Clockticks",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x01",
	+ "EventName": "UNC_I_CLOCKTICKS",
	+ "PerPkg": "1",
	+ "Unit": "IRP"
	+ },
	+ {
	+ "BriefDescription": "Inbound read requests received by the IRP and inserted into the FAF queue",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x18",
	+ "EventName": "UNC_I_FAF_INSERTS",
	+ "PerPkg": "1",
	+ "Unit": "IRP"
	+ },
	+ {
	+ "BriefDescription": "FAF occupancy",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x19",
	+ "EventName": "UNC_I_FAF_OCCUPANCY",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "Unit": "IRP"
	+ },
	+ {
	+ "BriefDescription": "Counts Timeouts - Set 0 : Fastpath Rejects",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x1E",
	+ "EventName": "UNC_I_MISC0.FAST_REJ",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x2",
	+ "Unit": "IRP"
	+ },
	+ {
	+ "BriefDescription": "Counts Timeouts - Set 0 : Fastpath Requests",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x1E",
	+ "EventName": "UNC_I_MISC0.FAST_REQ",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x1",
	+ "Unit": "IRP"
	+ },
	+ {
	+ "BriefDescription": "Misc Events - Set 1 : Lost Forward : Snoop pulled away ownership before a write was committed",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x1F",
	+ "EventName": "UNC_I_MISC1.LOST_FWD",
	+ "PerPkg": "1",
	+ "UMask": "0x10",
	+ "Unit": "IRP"
	+ },
	+ {
	+ "BriefDescription": "Misc Events - Set 1 : Received Invalid : Secondary received a transfer that did not have sufficient MESI state",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x1F",
	+ "EventName": "UNC_I_MISC1.SEC_RCVD_INVLD",
	+ "PerPkg": "1",
	+ "UMask": "0x20",
	+ "Unit": "IRP"
	+ },
	+ {
	+ "BriefDescription": "Snoop Hit E/S responses",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x12",
	+ "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_ES",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x74",
	+ "Unit": "IRP"
	+ },
	+ {
	+ "BriefDescription": "Snoop Hit I responses",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x12",
	+ "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_I",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x72",
	+ "Unit": "IRP"
	+ },
	+ {
	+ "BriefDescription": "Snoop Hit M responses",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x12",
	+ "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_M",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x78",
	+ "Unit": "IRP"
	+ },
	+ {
	+ "BriefDescription": "Snoop miss responses",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x12",
	+ "EventName": "UNC_I_SNOOP_RESP.ALL_MISS",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x71",
	+ "Unit": "IRP"
	+ },
	+ {
	+ "BriefDescription": "Inbound write (fast path) requests to coherent memory, received by the IRP resulting in write ownership requests issued by IRP to the mesh.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x11",
	+ "EventName": "UNC_I_TRANSACTIONS.WR_PREF",
	+ "PerPkg": "1",
	+ "UMask": "0x8",
	+ "Unit": "IRP"
	+ },
	+ {
	+ "BriefDescription": "MDF Clockticks",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x01",
	+ "EventName": "UNC_MDF_CLOCKTICKS",
	+ "PerPkg": "1",
	+ "Unit": "MDF"
	+ },
	+ {
	+ "BriefDescription": "Number of packets bypassing the ingress queue",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x14",
	+ "EventName": "UNC_MDF_RxR_BYPASS.AD_BNC",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x1",
	+ "Unit": "MDF"
	+ },
	+ {
	+ "BriefDescription": "Number of packets bypassing the ingress queue",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x14",
	+ "EventName": "UNC_MDF_RxR_BYPASS.AD_CRD",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x10",
	+ "Unit": "MDF"
	+ },
	+ {
	+ "BriefDescription": "Number of packets bypassing the ingress queue",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x14",
	+ "EventName": "UNC_MDF_RxR_BYPASS.AK",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x2",
	+ "Unit": "MDF"
	+ },
	+ {
	+ "BriefDescription": "Number of packets bypassing the ingress queue",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x14",
	+ "EventName": "UNC_MDF_RxR_BYPASS.BL_BNC",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x4",
	+ "Unit": "MDF"
	+ },
	+ {
	+ "BriefDescription": "Number of packets bypassing the ingress queue",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x14",
	+ "EventName": "UNC_MDF_RxR_BYPASS.BL_CRD",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x20",
	+ "Unit": "MDF"
	+ },
	+ {
	+ "BriefDescription": "Number of packets bypassing the ingress queue",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x14",
	+ "EventName": "UNC_MDF_RxR_BYPASS.IV",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x8",
	+ "Unit": "MDF"
	+ },
	+ {
	+ "BriefDescription": "Number of allocations into the Ingress used to queue up requests from the mesh (AD_BNC)",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x12",
	+ "EventName": "UNC_MDF_RxR_INSERTS.AD_BNC",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x1",
	+ "Unit": "MDF"
	+ },
	+ {
	+ "BriefDescription": "Number of allocations into the Ingress used to queue up requests from the mesh (AD)",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x12",
	+ "EventName": "UNC_MDF_RxR_INSERTS.AD_CRD",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x10",
	+ "Unit": "MDF"
	+ },
	+ {
	+ "BriefDescription": "Number of allocations into the Ingress used to queue up requests from the mesh (AK)",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x12",
	+ "EventName": "UNC_MDF_RxR_INSERTS.AK",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x2",
	+ "Unit": "MDF"
	+ },
	+ {
	+ "BriefDescription": "Number of allocations into the Ingress used to queue up requests from the mesh (BL_BNC)",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x12",
	+ "EventName": "UNC_MDF_RxR_INSERTS.BL_BNC",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x4",
	+ "Unit": "MDF"
	+ },
	+ {
	+ "BriefDescription": "Number of allocations into the Ingress used to queue up requests from the mesh (BL_CRD)",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x12",
	+ "EventName": "UNC_MDF_RxR_INSERTS.BL_CRD",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x20",
	+ "Unit": "MDF"
	+ },
	+ {
	+ "BriefDescription": "Number of allocations into the Ingress used to queue up requests from the mesh (IV)",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x12",
	+ "EventName": "UNC_MDF_RxR_INSERTS.IV",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x8",
	+ "Unit": "MDF"
	+ },
	+ {
	+ "BriefDescription": "Occupancy counts for the Ingress buffer",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x13",
	+ "EventName": "UNC_MDF_RxR_OCCUPANCY.AD_BNC",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x1",
	+ "Unit": "MDF"
	+ },
	+ {
	+ "BriefDescription": "Occupancy counts for the Ingress buffer",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x13",
	+ "EventName": "UNC_MDF_RxR_OCCUPANCY.AD_CRD",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x10",
	+ "Unit": "MDF"
	+ },
	+ {
	+ "BriefDescription": "Occupancy counts for the Ingress buffer",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x13",
	+ "EventName": "UNC_MDF_RxR_OCCUPANCY.AK",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x2",
	+ "Unit": "MDF"
	+ },
	+ {
	+ "BriefDescription": "Occupancy counts for the Ingress buffer",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x13",
	+ "EventName": "UNC_MDF_RxR_OCCUPANCY.BL_BNC",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x4",
	+ "Unit": "MDF"
	+ },
	+ {
	+ "BriefDescription": "Occupancy counts for the Ingress buffer",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x13",
	+ "EventName": "UNC_MDF_RxR_OCCUPANCY.BL_CRD",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x20",
	+ "Unit": "MDF"
	+ },
	+ {
	+ "BriefDescription": "Occupancy counts for the Ingress buffer",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x13",
	+ "EventName": "UNC_MDF_RxR_OCCUPANCY.IV",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x8",
	+ "Unit": "MDF"
	+ },
	+ {
	+ "BriefDescription": "Egress bypasses for AD_BNC",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x1E",
	+ "EventName": "UNC_MDF_TxR_BYPASS.AD_BNC",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x1",
	+ "Unit": "MDF"
	+ },
	+ {
	+ "BriefDescription": "Egress bypasses for AD_CRD",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x1E",
	+ "EventName": "UNC_MDF_TxR_BYPASS.AD_CRD",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x10",
	+ "Unit": "MDF"
	+ },
	+ {
	+ "BriefDescription": "Egress bypasses for AK",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x1E",
	+ "EventName": "UNC_MDF_TxR_BYPASS.AK",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x2",
	+ "Unit": "MDF"
	+ },
	+ {
	+ "BriefDescription": "Egress bypasses for BL_BNC",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x1E",
	+ "EventName": "UNC_MDF_TxR_BYPASS.BL_BNC",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x4",
	+ "Unit": "MDF"
	+ },
	+ {
	+ "BriefDescription": "Egress bypasses for BL_CRD",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x1E",
	+ "EventName": "UNC_MDF_TxR_BYPASS.BL_CRD",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x20",
	+ "Unit": "MDF"
	+ },
	+ {
	+ "BriefDescription": "Egress bypasses for IV",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x1E",
	+ "EventName": "UNC_MDF_TxR_BYPASS.IV",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x8",
	+ "Unit": "MDF"
	+ },
	+ {
	+ "BriefDescription": "Number of egress inserts for AD_BNC",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x1C",
	+ "EventName": "UNC_MDF_TxR_INSERTS.AD_BNC",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x1",
	+ "Unit": "MDF"
	+ },
	+ {
	+ "BriefDescription": "Number of egress inserts for AD_CRD",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x1C",
	+ "EventName": "UNC_MDF_TxR_INSERTS.AD_CRD",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x10",
	+ "Unit": "MDF"
	+ },
	+ {
	+ "BriefDescription": "Number of egress inserts for AK",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x1C",
	+ "EventName": "UNC_MDF_TxR_INSERTS.AK",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x2",
	+ "Unit": "MDF"
	+ },
	+ {
	+ "BriefDescription": "Number of egress inserts for BL_BNC",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x1C",
	+ "EventName": "UNC_MDF_TxR_INSERTS.BL_BNC",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x4",
	+ "Unit": "MDF"
	+ },
	+ {
	+ "BriefDescription": "Number of egress inserts for BL_CRD",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x1C",
	+ "EventName": "UNC_MDF_TxR_INSERTS.BL_CRD",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x20",
	+ "Unit": "MDF"
	+ },
	+ {
	+ "BriefDescription": "Number of egress inserts for IV",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x1C",
	+ "EventName": "UNC_MDF_TxR_INSERTS.IV",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x8",
	+ "Unit": "MDF"
	+ },
	+ {
	+ "BriefDescription": "Egress occupancy for AD_BNC",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x1D",
	+ "EventName": "UNC_MDF_TxR_OCCUPANCY.AD_BNC",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x1",
	+ "Unit": "MDF"
	+ },
	+ {
	+ "BriefDescription": "Egress occupancy for AD_CRD",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x1D",
	+ "EventName": "UNC_MDF_TxR_OCCUPANCY.AD_CRD",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x10",
	+ "Unit": "MDF"
	+ },
	+ {
	+ "BriefDescription": "Egress occupancy for AK",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x1D",
	+ "EventName": "UNC_MDF_TxR_OCCUPANCY.AK",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x2",
	+ "Unit": "MDF"
	+ },
	+ {
	+ "BriefDescription": "Egress occupancy for BL_BNC",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x1D",
	+ "EventName": "UNC_MDF_TxR_OCCUPANCY.BL_BNC",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x4",
	+ "Unit": "MDF"
	+ },
	+ {
	+ "BriefDescription": "Egress occupancy for BL_CRD",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x1D",
	+ "EventName": "UNC_MDF_TxR_OCCUPANCY.BL_CRD",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x20",
	+ "Unit": "MDF"
	+ },
	+ {
	+ "BriefDescription": "Egress occupancy for IV",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x1D",
	+ "EventName": "UNC_MDF_TxR_OCCUPANCY.IV",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x8",
	+ "Unit": "MDF"
	+ },
	+ {
	+ "BriefDescription": "Number of UPI LL clock cycles while the event is enabled",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x01",
	+ "EventName": "UNC_UPI_CLOCKTICKS",
	+ "PerPkg": "1",
	+ "PublicDescription": "Number of kfclks",
	+ "Unit": "UPI"
	+ },
	+ {
	+ "BriefDescription": "Cycles in L1 : Number of UPI qfclk cycles spent in L1 power mode. L1 is a mode that totally shuts down a UPI link. Use edge detect to count the number of instances when the UPI link entered L1. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another. Because L1 totally shuts down the link, it takes a good amount of time to exit this mode.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x21",
	+ "EventName": "UNC_UPI_L1_POWER_CYCLES",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "Unit": "UPI"
	+ },
	+ {
	+ "BriefDescription": "Matches on Receive path of a UPI Port : Non-Coherent Bypass",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x05",
	+ "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCB",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0xe",
	+ "Unit": "UPI"
	+ },
	+ {
	+ "BriefDescription": "Matches on Receive path of a UPI Port : Non-Coherent Bypass, Match Opcode",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x05",
	+ "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCB_OPC",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x10e",
	+ "Unit": "UPI"
	+ },
	+ {
	+ "BriefDescription": "Matches on Receive path of a UPI Port : Non-Coherent Standard",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x05",
	+ "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCS",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0xf",
	+ "Unit": "UPI"
	+ },
	+ {
	+ "BriefDescription": "Matches on Receive path of a UPI Port : Non-Coherent Standard, Match Opcode",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x05",
	+ "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCS_OPC",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x10f",
	+ "Unit": "UPI"
	+ },
	+ {
	+ "BriefDescription": "Matches on Receive path of a UPI Port : Request",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x05",
	+ "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.REQ",
	+ "PerPkg": "1",
	+ "UMask": "0x8",
	+ "Unit": "UPI"
	+ },
	+ {
	+ "BriefDescription": "Matches on Receive path of a UPI Port : Request, Match Opcode",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x05",
	+ "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.REQ_OPC",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x108",
	+ "Unit": "UPI"
	+ },
	+ {
	+ "BriefDescription": "Matches on Receive path of a UPI Port : Response - Conflict",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x05",
	+ "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSPCNFLT",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x1aa",
	+ "Unit": "UPI"
	+ },
	+ {
	+ "BriefDescription": "Matches on Receive path of a UPI Port : Response - Invalid",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x05",
	+ "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSPI",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x12a",
	+ "Unit": "UPI"
	+ },
	+ {
	+ "BriefDescription": "Matches on Receive path of a UPI Port : Response - Data",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x05",
	+ "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_DATA",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0xc",
	+ "Unit": "UPI"
	+ },
	+ {
	+ "BriefDescription": "Matches on Receive path of a UPI Port : Response - Data, Match Opcode",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x05",
	+ "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_DATA_OPC",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x10c",
	+ "Unit": "UPI"
	+ },
	+ {
	+ "BriefDescription": "Matches on Receive path of a UPI Port : Response - No Data",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x05",
	+ "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_NODATA",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0xa",
	+ "Unit": "UPI"
	+ },
	+ {
	+ "BriefDescription": "Matches on Receive path of a UPI Port : Response - No Data, Match Opcode",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x05",
	+ "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_NODATA_OPC",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x10a",
	+ "Unit": "UPI"
	+ },
	+ {
	+ "BriefDescription": "Matches on Receive path of a UPI Port : Snoop",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x05",
	+ "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.SNP",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x9",
	+ "Unit": "UPI"
	+ },
	+ {
	+ "BriefDescription": "Matches on Receive path of a UPI Port : Snoop, Match Opcode",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x05",
	+ "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.SNP_OPC",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x109",
	+ "Unit": "UPI"
	+ },
	+ {
	+ "BriefDescription": "Matches on Receive path of a UPI Port : Writeback",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x05",
	+ "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.WB",
	+ "PerPkg": "1",
	+ "UMask": "0xd",
	+ "Unit": "UPI"
	+ },
	+ {
	+ "BriefDescription": "Matches on Receive path of a UPI Port : Writeback, Match Opcode",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x05",
	+ "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.WB_OPC",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x10d",
	+ "Unit": "UPI"
	+ },
	+ {
	+ "BriefDescription": "Valid Flits Received : All Data : Shows legal flit time (hides impact of L0p and L0c).",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x03",
	+ "EventName": "UNC_UPI_RxL_FLITS.ALL_DATA",
	+ "PerPkg": "1",
	+ "UMask": "0xf",
	+ "Unit": "UPI"
	+ },
	+ {
	+ "BriefDescription": "Null FLITs received from any slot",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x03",
	+ "EventName": "UNC_UPI_RxL_FLITS.ALL_NULL",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PublicDescription": "Valid Flits Received : Null FLITs received from any slot",
	+ "UMask": "0x27",
	+ "Unit": "UPI"
	+ },
	+ {
	+ "BriefDescription": "Valid Flits Received : Data : Shows legal flit time (hides impact of L0p and L0c). : Count Data Flits (which consume all slots), but how much to count is based on Slot0-2 mask, so count can be 0-3 depending on which slots are enabled for counting..",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x03",
	+ "EventName": "UNC_UPI_RxL_FLITS.DATA",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x8",
	+ "Unit": "UPI"
	+ },
	+ {
	+ "BriefDescription": "Valid Flits Received : Idle : Shows legal flit time (hides impact of L0p and L0c).",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x03",
	+ "EventName": "UNC_UPI_RxL_FLITS.IDLE",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x47",
	+ "Unit": "UPI"
	+ },
	+ {
	+ "BriefDescription": "Valid Flits Received : LLCRD Not Empty : Shows legal flit time (hides impact of L0p and L0c). : Enables counting of LLCRD (with non-zero payload). This only applies to slot 2 since LLCRD is only allowed in slot 2",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x03",
	+ "EventName": "UNC_UPI_RxL_FLITS.LLCRD",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x10",
	+ "Unit": "UPI"
	+ },
	+ {
	+ "BriefDescription": "Valid Flits Received : LLCTRL : Shows legal flit time (hides impact of L0p and L0c). : Equivalent to an idle packet. Enables counting of slot 0 LLCTRL messages.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x03",
	+ "EventName": "UNC_UPI_RxL_FLITS.LLCTRL",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x40",
	+ "Unit": "UPI"
	+ },
	+ {
	+ "BriefDescription": "Valid Flits Received : All Non Data : Shows legal flit time (hides impact of L0p and L0c).",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x03",
	+ "EventName": "UNC_UPI_RxL_FLITS.NON_DATA",
	+ "PerPkg": "1",
	+ "UMask": "0x97",
	+ "Unit": "UPI"
	+ },
	+ {
	+ "BriefDescription": "Valid Flits Received : Slot NULL or LLCRD Empty : Shows legal flit time (hides impact of L0p and L0c). : LLCRD with all zeros is treated as NULL. Slot 1 is not treated as NULL if slot 0 is a dual slot. This can apply to slot 0,1, or 2.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x03",
	+ "EventName": "UNC_UPI_RxL_FLITS.NULL",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x20",
	+ "Unit": "UPI"
	+ },
	+ {
	+ "BriefDescription": "Valid Flits Received : Protocol Header : Shows legal flit time (hides impact of L0p and L0c). : Enables count of protocol headers in slot 0,1,2 (depending on slot uMask bits)",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x03",
	+ "EventName": "UNC_UPI_RxL_FLITS.PROTHDR",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x80",
	+ "Unit": "UPI"
	+ },
	+ {
	+ "BriefDescription": "Valid Flits Received : Slot 0 : Shows legal flit time (hides impact of L0p and L0c). : Count Slot 0 - Other mask bits determine types of headers to count.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x03",
	+ "EventName": "UNC_UPI_RxL_FLITS.SLOT0",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x1",
	+ "Unit": "UPI"
	+ },
	+ {
	+ "BriefDescription": "Valid Flits Received : Slot 1 : Shows legal flit time (hides impact of L0p and L0c). : Count Slot 1 - Other mask bits determine types of headers to count.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x03",
	+ "EventName": "UNC_UPI_RxL_FLITS.SLOT1",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x2",
	+ "Unit": "UPI"
	+ },
	+ {
	+ "BriefDescription": "Valid Flits Received : Slot 2 : Shows legal flit time (hides impact of L0p and L0c). : Count Slot 2 - Other mask bits determine types of headers to count.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x03",
	+ "EventName": "UNC_UPI_RxL_FLITS.SLOT2",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x4",
	+ "Unit": "UPI"
	+ },
	+ {
	+ "BriefDescription": "RxQ Flit Buffer Allocations : Slot 0 : Number of allocations into the UPI Rx Flit Buffer. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x30",
	+ "EventName": "UNC_UPI_RxL_INSERTS.SLOT0",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x1",
	+ "Unit": "UPI"
	+ },
	+ {
	+ "BriefDescription": "RxQ Flit Buffer Allocations : Slot 1 : Number of allocations into the UPI Rx Flit Buffer. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x30",
	+ "EventName": "UNC_UPI_RxL_INSERTS.SLOT1",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x2",
	+ "Unit": "UPI"
	+ },
	+ {
	+ "BriefDescription": "RxQ Flit Buffer Allocations : Slot 2 : Number of allocations into the UPI Rx Flit Buffer. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x30",
	+ "EventName": "UNC_UPI_RxL_INSERTS.SLOT2",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x4",
	+ "Unit": "UPI"
	+ },
	+ {
	+ "BriefDescription": "RxQ Occupancy - All Packets : Slot 0",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x32",
	+ "EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT0",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x1",
	+ "Unit": "UPI"
	+ },
	+ {
	+ "BriefDescription": "RxQ Occupancy - All Packets : Slot 1",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x32",
	+ "EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT1",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x2",
	+ "Unit": "UPI"
	+ },
	+ {
	+ "BriefDescription": "RxQ Occupancy - All Packets : Slot 2",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x32",
	+ "EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT2",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x4",
	+ "Unit": "UPI"
	+ },
	+ {
	+ "BriefDescription": "Cycles in L0p",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x27",
	+ "EventName": "UNC_UPI_TxL0P_POWER_CYCLES",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "Unit": "UPI"
	+ },
	+ {
	+ "BriefDescription": "UNC_UPI_TxL0P_POWER_CYCLES_LL_ENTER",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x28",
	+ "EventName": "UNC_UPI_TxL0P_POWER_CYCLES_LL_ENTER",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "Unit": "UPI"
	+ },
	+ {
	+ "BriefDescription": "UNC_UPI_TxL0P_POWER_CYCLES_M3_EXIT",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x29",
	+ "EventName": "UNC_UPI_TxL0P_POWER_CYCLES_M3_EXIT",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "Unit": "UPI"
	+ },
	+ {
	+ "BriefDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Bypass",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x04",
	+ "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCB",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0xe",
	+ "Unit": "UPI"
	+ },
	+ {
	+ "BriefDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Bypass, Match Opcode",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x04",
	+ "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCB_OPC",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x10e",
	+ "Unit": "UPI"
	+ },
	+ {
	+ "BriefDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Standard",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x04",
	+ "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCS",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0xf",
	+ "Unit": "UPI"
	+ },
	+ {
	+ "BriefDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Standard, Match Opcode",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x04",
	+ "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCS_OPC",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x10f",
	+ "Unit": "UPI"
	+ },
	+ {
	+ "BriefDescription": "Matches on Transmit path of a UPI Port : Request",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x04",
	+ "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.REQ",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x8",
	+ "Unit": "UPI"
	+ },
	+ {
	+ "BriefDescription": "Matches on Transmit path of a UPI Port : Request, Match Opcode",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x04",
	+ "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.REQ_OPC",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x108",
	+ "Unit": "UPI"
	+ },
	+ {
	+ "BriefDescription": "Matches on Transmit path of a UPI Port : Response - Conflict",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x04",
	+ "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSPCNFLT",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x1aa",
	+ "Unit": "UPI"
	+ },
	+ {
	+ "BriefDescription": "Matches on Transmit path of a UPI Port : Response - Invalid",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x04",
	+ "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSPI",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x12a",
	+ "Unit": "UPI"
	+ },
	+ {
	+ "BriefDescription": "Matches on Transmit path of a UPI Port : Response - Data",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x04",
	+ "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_DATA",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0xc",
	+ "Unit": "UPI"
	+ },
	+ {
	+ "BriefDescription": "Matches on Transmit path of a UPI Port : Response - Data, Match Opcode",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x04",
	+ "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_DATA_OPC",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x10c",
	+ "Unit": "UPI"
	+ },
	+ {
	+ "BriefDescription": "Matches on Transmit path of a UPI Port : Response - No Data",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x04",
	+ "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_NODATA",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0xa",
	+ "Unit": "UPI"
	+ },
	+ {
	+ "BriefDescription": "Matches on Transmit path of a UPI Port : Response - No Data, Match Opcode",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x04",
	+ "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_NODATA_OPC",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x10a",
	+ "Unit": "UPI"
	+ },
	+ {
	+ "BriefDescription": "Matches on Transmit path of a UPI Port : Snoop",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x04",
	+ "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.SNP",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x9",
	+ "Unit": "UPI"
	+ },
	+ {
	+ "BriefDescription": "Matches on Transmit path of a UPI Port : Snoop, Match Opcode",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x04",
	+ "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.SNP_OPC",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x109",
	+ "Unit": "UPI"
	+ },
	+ {
	+ "BriefDescription": "Matches on Transmit path of a UPI Port : Writeback",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x04",
	+ "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.WB",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0xd",
	+ "Unit": "UPI"
	+ },
	+ {
	+ "BriefDescription": "Matches on Transmit path of a UPI Port : Writeback, Match Opcode",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x04",
	+ "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.WB_OPC",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x10d",
	+ "Unit": "UPI"
	+ },
	+ {
	+ "BriefDescription": "Valid Flits Sent : All Data : Counts number of data flits across this UPI link.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x02",
	+ "EventName": "UNC_UPI_TxL_FLITS.ALL_DATA",
	+ "PerPkg": "1",
	+ "UMask": "0xf",
	+ "Unit": "UPI"
	+ },
	+ {
	+ "BriefDescription": "All Null Flits",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x02",
	+ "EventName": "UNC_UPI_TxL_FLITS.ALL_NULL",
	+ "PerPkg": "1",
	+ "PublicDescription": "Valid Flits Sent : Idle",
	+ "UMask": "0x27",
	+ "Unit": "UPI"
	+ },
	+ {
	+ "BriefDescription": "Valid Flits Sent : Data : Shows legal flit time (hides impact of L0p and L0c). : Count Data Flits (which consume all slots), but how much to count is based on Slot0-2 mask, so count can be 0-3 depending on which slots are enabled for counting..",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x02",
	+ "EventName": "UNC_UPI_TxL_FLITS.DATA",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x8",
	+ "Unit": "UPI"
	+ },
	+ {
	+ "BriefDescription": "Valid Flits Sent : Idle : Shows legal flit time (hides impact of L0p and L0c).",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x02",
	+ "EventName": "UNC_UPI_TxL_FLITS.IDLE",
	+ "PerPkg": "1",
	+ "UMask": "0x47",
	+ "Unit": "UPI"
	+ },
	+ {
	+ "BriefDescription": "Valid Flits Sent : LLCRD Not Empty : Shows legal flit time (hides impact of L0p and L0c). : Enables counting of LLCRD (with non-zero payload). This only applies to slot 2 since LLCRD is only allowed in slot 2",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x02",
	+ "EventName": "UNC_UPI_TxL_FLITS.LLCRD",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x10",
	+ "Unit": "UPI"
	+ },
	+ {
	+ "BriefDescription": "Valid Flits Sent : LLCTRL : Shows legal flit time (hides impact of L0p and L0c). : Equivalent to an idle packet. Enables counting of slot 0 LLCTRL messages.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x02",
	+ "EventName": "UNC_UPI_TxL_FLITS.LLCTRL",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x40",
	+ "Unit": "UPI"
	+ },
	+ {
	+ "BriefDescription": "Valid Flits Sent : All Non Data : Shows legal flit time (hides impact of L0p and L0c).",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x02",
	+ "EventName": "UNC_UPI_TxL_FLITS.NON_DATA",
	+ "PerPkg": "1",
	+ "PublicDescription": "Valid Flits Sent : Null FLITs transmitted to any slot",
	+ "UMask": "0x97",
	+ "Unit": "UPI"
	+ },
	+ {
	+ "BriefDescription": "Valid Flits Sent : Slot NULL or LLCRD Empty : Shows legal flit time (hides impact of L0p and L0c). : LLCRD with all zeros is treated as NULL. Slot 1 is not treated as NULL if slot 0 is a dual slot. This can apply to slot 0,1, or 2.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x02",
	+ "EventName": "UNC_UPI_TxL_FLITS.NULL",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x20",
	+ "Unit": "UPI"
	+ },
	+ {
	+ "BriefDescription": "Valid Flits Sent : Protocol Header : Shows legal flit time (hides impact of L0p and L0c). : Enables count of protocol headers in slot 0,1,2 (depending on slot uMask bits)",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x02",
	+ "EventName": "UNC_UPI_TxL_FLITS.PROTHDR",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x80",
	+ "Unit": "UPI"
	+ },
	+ {
	+ "BriefDescription": "Valid Flits Sent : Slot 0 : Shows legal flit time (hides impact of L0p and L0c). : Count Slot 0 - Other mask bits determine types of headers to count.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x02",
	+ "EventName": "UNC_UPI_TxL_FLITS.SLOT0",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x1",
	+ "Unit": "UPI"
	+ },
	+ {
	+ "BriefDescription": "Valid Flits Sent : Slot 1 : Shows legal flit time (hides impact of L0p and L0c). : Count Slot 1 - Other mask bits determine types of headers to count.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x02",
	+ "EventName": "UNC_UPI_TxL_FLITS.SLOT1",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x2",
	+ "Unit": "UPI"
	+ },
	+ {
	+ "BriefDescription": "Valid Flits Sent : Slot 2 : Shows legal flit time (hides impact of L0p and L0c). : Count Slot 2 - Other mask bits determine types of headers to count.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x02",
	+ "EventName": "UNC_UPI_TxL_FLITS.SLOT2",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x4",
	+ "Unit": "UPI"
	+ },
	+ {
	+ "BriefDescription": "Message Received : Doorbell",
	+ "Counter": "0,1",
	+ "EventCode": "0x42",
	+ "EventName": "UNC_U_EVENT_MSG.DOORBELL_RCVD",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x8",
	+ "Unit": "UBOX"
	+ },
	+ {
	+ "BriefDescription": "Message Received : Interrupt",
	+ "Counter": "0,1",
	+ "EventCode": "0x42",
	+ "EventName": "UNC_U_EVENT_MSG.INT_PRIO",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PublicDescription": "Message Received : Interrupt : Interrupts",
	+ "UMask": "0x10",
	+ "Unit": "UBOX"
	+ },
	+ {
	+ "BriefDescription": "Message Received : IPI",
	+ "Counter": "0,1",
	+ "EventCode": "0x42",
	+ "EventName": "UNC_U_EVENT_MSG.IPI_RCVD",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PublicDescription": "Message Received : IPI : Inter Processor Interrupts",
	+ "UMask": "0x4",
	+ "Unit": "UBOX"
	+ },
	+ {
	+ "BriefDescription": "Message Received : MSI",
	+ "Counter": "0,1",
	+ "EventCode": "0x42",
	+ "EventName": "UNC_U_EVENT_MSG.MSI_RCVD",
	+ "PerPkg": "1",
	+ "PublicDescription": "Message Received : MSI : Message Signaled Interrupts - interrupts sent by devices (including PCIe via IOxAPIC) (Socket Mode only)",
	+ "UMask": "0x2",
	+ "Unit": "UBOX"
	+ },
	+ {
	+ "BriefDescription": "Message Received : VLW",
	+ "Counter": "0,1",
	+ "EventCode": "0x42",
	+ "EventName": "UNC_U_EVENT_MSG.VLW_RCVD",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PublicDescription": "Message Received : VLW : Virtual Logical Wire (legacy) message were received from Uncore.",
	+ "UMask": "0x1",
	+ "Unit": "UBOX"
	+ }
	+]
	\ No newline at end of file
	diff --git a/lib/libpmc/pmu-events/arch/x86/graniterapids/uncore-io.json b/lib/libpmc/pmu-events/arch/x86/graniterapids/uncore-io.json
	new file mode 100644
	--- /dev/null
	+++ b/lib/libpmc/pmu-events/arch/x86/graniterapids/uncore-io.json
	@@ -0,0 +1,1925 @@
	+[
	+ {
	+ "BriefDescription": "IIO Clockticks",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x01",
	+ "EventName": "UNC_IIO_CLOCKTICKS",
	+ "PerPkg": "1",
	+ "PortMask": "0x000",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "PCIE Completion Buffer Inserts. Counts once per 64 byte read issued from this PCIE device.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0xC2",
	+ "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.ALL_PARTS",
	+ "Experimental": "1",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x0FF",
	+ "UMask": "0x4",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "PCIE Completion Buffer Inserts. Counts once per 64 byte read issued from this PCIE device.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0xC2",
	+ "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART0",
	+ "Experimental": "1",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x001",
	+ "UMask": "0x4",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "PCIE Completion Buffer Inserts. Counts once per 64 byte read issued from this PCIE device.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0xC2",
	+ "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART1",
	+ "Experimental": "1",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x002",
	+ "UMask": "0x4",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "PCIE Completion Buffer Inserts. Counts once per 64 byte read issued from this PCIE device.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0xC2",
	+ "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART2",
	+ "Experimental": "1",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x004",
	+ "UMask": "0x4",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "PCIE Completion Buffer Inserts. Counts once per 64 byte read issued from this PCIE device.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0xC2",
	+ "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART3",
	+ "Experimental": "1",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x008",
	+ "UMask": "0x4",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "PCIE Completion Buffer Inserts. Counts once per 64 byte read issued from this PCIE device.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0xC2",
	+ "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART4",
	+ "Experimental": "1",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x010",
	+ "UMask": "0x4",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "PCIE Completion Buffer Inserts. Counts once per 64 byte read issued from this PCIE device.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0xC2",
	+ "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART5",
	+ "Experimental": "1",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x020",
	+ "UMask": "0x4",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "PCIE Completion Buffer Inserts. Counts once per 64 byte read issued from this PCIE device.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0xC2",
	+ "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART6",
	+ "Experimental": "1",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x040",
	+ "UMask": "0x4",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "PCIE Completion Buffer Inserts. Counts once per 64 byte read issued from this PCIE device.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0xC2",
	+ "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART7",
	+ "Experimental": "1",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x080",
	+ "UMask": "0x4",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Count of allocations in the completion buffer",
	+ "Counter": "2,3",
	+ "EventCode": "0xD5",
	+ "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.ALL_PARTS",
	+ "Experimental": "1",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x0FF",
	+ "UMask": "0xff",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Count of allocations in the completion buffer",
	+ "Counter": "2,3",
	+ "EventCode": "0xD5",
	+ "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART0",
	+ "Experimental": "1",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x001",
	+ "UMask": "0x1",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Count of allocations in the completion buffer",
	+ "Counter": "2,3",
	+ "EventCode": "0xD5",
	+ "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART1",
	+ "Experimental": "1",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x002",
	+ "UMask": "0x2",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Count of allocations in the completion buffer",
	+ "Counter": "2,3",
	+ "EventCode": "0xD5",
	+ "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART2",
	+ "Experimental": "1",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x004",
	+ "UMask": "0x4",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Count of allocations in the completion buffer",
	+ "Counter": "2,3",
	+ "EventCode": "0xD5",
	+ "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART3",
	+ "Experimental": "1",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x008",
	+ "UMask": "0x8",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Count of allocations in the completion buffer",
	+ "Counter": "2,3",
	+ "EventCode": "0xD5",
	+ "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART4",
	+ "Experimental": "1",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x010",
	+ "UMask": "0x10",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Count of allocations in the completion buffer",
	+ "Counter": "2,3",
	+ "EventCode": "0xD5",
	+ "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART5",
	+ "Experimental": "1",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x020",
	+ "UMask": "0x20",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Count of allocations in the completion buffer",
	+ "Counter": "2,3",
	+ "EventCode": "0xD5",
	+ "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART6",
	+ "Experimental": "1",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x040",
	+ "UMask": "0x40",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Count of allocations in the completion buffer",
	+ "Counter": "2,3",
	+ "EventCode": "0xD5",
	+ "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART7",
	+ "Experimental": "1",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x080",
	+ "UMask": "0x80",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",
	+ "Counter": "2,3",
	+ "EventCode": "0xC0",
	+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.ALL_PARTS",
	+ "Experimental": "1",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x0FF",
	+ "UMask": "0x4",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",
	+ "Counter": "2,3",
	+ "EventCode": "0xC0",
	+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART0",
	+ "Experimental": "1",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x001",
	+ "UMask": "0x4",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",
	+ "Counter": "2,3",
	+ "EventCode": "0xC0",
	+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART1",
	+ "Experimental": "1",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x002",
	+ "UMask": "0x4",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",
	+ "Counter": "2,3",
	+ "EventCode": "0xC0",
	+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART2",
	+ "Experimental": "1",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x004",
	+ "UMask": "0x4",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",
	+ "Counter": "2,3",
	+ "EventCode": "0xC0",
	+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART3",
	+ "Experimental": "1",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x008",
	+ "UMask": "0x4",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",
	+ "Counter": "2,3",
	+ "EventCode": "0xC0",
	+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART4",
	+ "Experimental": "1",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x010",
	+ "UMask": "0x4",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",
	+ "Counter": "2,3",
	+ "EventCode": "0xC0",
	+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART5",
	+ "Experimental": "1",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x020",
	+ "UMask": "0x4",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",
	+ "Counter": "2,3",
	+ "EventCode": "0xC0",
	+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART6",
	+ "Experimental": "1",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x040",
	+ "UMask": "0x4",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM",
	+ "Counter": "2,3",
	+ "EventCode": "0xC0",
	+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART7",
	+ "Experimental": "1",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x080",
	+ "UMask": "0x4",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Data requested by the CPU : Core writing to Cards MMIO space",
	+ "Counter": "2,3",
	+ "EventCode": "0xC0",
	+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.ALL_PARTS",
	+ "Experimental": "1",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x0FF",
	+ "UMask": "0x1",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Data requested by the CPU : Core writing to Cards MMIO space",
	+ "Counter": "2,3",
	+ "EventCode": "0xC0",
	+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART0",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x001",
	+ "UMask": "0x1",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Data requested by the CPU : Core writing to Cards MMIO space",
	+ "Counter": "2,3",
	+ "EventCode": "0xC0",
	+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART1",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x002",
	+ "UMask": "0x1",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Data requested by the CPU : Core writing to Cards MMIO space",
	+ "Counter": "2,3",
	+ "EventCode": "0xC0",
	+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART2",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x004",
	+ "UMask": "0x1",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Data requested by the CPU : Core writing to Cards MMIO space",
	+ "Counter": "2,3",
	+ "EventCode": "0xC0",
	+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART3",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x008",
	+ "UMask": "0x1",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Data requested by the CPU : Core writing to Cards MMIO space",
	+ "Counter": "2,3",
	+ "EventCode": "0xC0",
	+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART4",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x010",
	+ "UMask": "0x1",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Data requested by the CPU : Core writing to Cards MMIO space",
	+ "Counter": "2,3",
	+ "EventCode": "0xC0",
	+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART5",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x020",
	+ "UMask": "0x1",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Data requested by the CPU : Core writing to Cards MMIO space",
	+ "Counter": "2,3",
	+ "EventCode": "0xC0",
	+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART6",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x040",
	+ "UMask": "0x1",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Data requested by the CPU : Core writing to Cards MMIO space",
	+ "Counter": "2,3",
	+ "EventCode": "0xC0",
	+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART7",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x080",
	+ "UMask": "0x1",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card.",
	+ "Counter": "2,3",
	+ "EventCode": "0xC0",
	+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.ALL_PARTS",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x0FF",
	+ "UMask": "0x8",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card.",
	+ "Counter": "2,3",
	+ "EventCode": "0xC0",
	+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.ALL_PARTS",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x0FF",
	+ "UMask": "0x2",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Counts once for every 4 bytes read from this card to memory. This event does include reads to IO.",
	+ "Counter": "0,1",
	+ "EventCode": "0x83",
	+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.ALL_PARTS",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x0FF",
	+ "UMask": "0x4",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM",
	+ "Counter": "0,1",
	+ "EventCode": "0x83",
	+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x001",
	+ "UMask": "0x4",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM",
	+ "Counter": "0,1",
	+ "EventCode": "0x83",
	+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x02",
	+ "UMask": "0x4",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM",
	+ "Counter": "0,1",
	+ "EventCode": "0x83",
	+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x04",
	+ "UMask": "0x4",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM",
	+ "Counter": "0,1",
	+ "EventCode": "0x83",
	+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x08",
	+ "UMask": "0x4",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM",
	+ "Counter": "0,1",
	+ "EventCode": "0x83",
	+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART4",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x10",
	+ "UMask": "0x4",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM",
	+ "Counter": "0,1",
	+ "EventCode": "0x83",
	+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART5",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x20",
	+ "UMask": "0x4",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM",
	+ "Counter": "0,1",
	+ "EventCode": "0x83",
	+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART6",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x40",
	+ "UMask": "0x4",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM",
	+ "Counter": "0,1",
	+ "EventCode": "0x83",
	+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART7",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x80",
	+ "UMask": "0x4",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Counts once for every 4 bytes written from this card to memory. This event does include writes to IO.",
	+ "Counter": "0,1",
	+ "EventCode": "0x83",
	+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.ALL_PARTS",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x0FF",
	+ "UMask": "0x1",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM",
	+ "Counter": "0,1",
	+ "EventCode": "0x83",
	+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x001",
	+ "UMask": "0x1",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM",
	+ "Counter": "0,1",
	+ "EventCode": "0x83",
	+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x02",
	+ "UMask": "0x1",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM",
	+ "Counter": "0,1",
	+ "EventCode": "0x83",
	+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x04",
	+ "UMask": "0x1",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM",
	+ "Counter": "0,1",
	+ "EventCode": "0x83",
	+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x08",
	+ "UMask": "0x1",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM",
	+ "Counter": "0,1",
	+ "EventCode": "0x83",
	+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART4",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x10",
	+ "UMask": "0x1",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM",
	+ "Counter": "0,1",
	+ "EventCode": "0x83",
	+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART5",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x20",
	+ "UMask": "0x1",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM",
	+ "Counter": "0,1",
	+ "EventCode": "0x83",
	+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART6",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x40",
	+ "UMask": "0x1",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM",
	+ "Counter": "0,1",
	+ "EventCode": "0x83",
	+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART7",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x80",
	+ "UMask": "0x1",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)",
	+ "Counter": "0,1",
	+ "EventCode": "0x83",
	+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART0",
	+ "Experimental": "1",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x001",
	+ "UMask": "0x8",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)",
	+ "Counter": "0,1",
	+ "EventCode": "0x83",
	+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART1",
	+ "Experimental": "1",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x002",
	+ "UMask": "0x8",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)",
	+ "Counter": "0,1",
	+ "EventCode": "0x83",
	+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART2",
	+ "Experimental": "1",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x004",
	+ "UMask": "0x8",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)",
	+ "Counter": "0,1",
	+ "EventCode": "0x83",
	+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART3",
	+ "Experimental": "1",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x008",
	+ "UMask": "0x8",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)",
	+ "Counter": "0,1",
	+ "EventCode": "0x83",
	+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART4",
	+ "Experimental": "1",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x010",
	+ "UMask": "0x8",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)",
	+ "Counter": "0,1",
	+ "EventCode": "0x83",
	+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART5",
	+ "Experimental": "1",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x020",
	+ "UMask": "0x8",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)",
	+ "Counter": "0,1",
	+ "EventCode": "0x83",
	+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART6",
	+ "Experimental": "1",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x040",
	+ "UMask": "0x8",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)",
	+ "Counter": "0,1",
	+ "EventCode": "0x83",
	+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART7",
	+ "Experimental": "1",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x080",
	+ "UMask": "0x8",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Counts once for every 4 bytes written from this card to a peer device's IO space.",
	+ "Counter": "0,1",
	+ "EventCode": "0x83",
	+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.ALL_PARTS",
	+ "Experimental": "1",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x0FF",
	+ "UMask": "0x2",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
	+ "Counter": "0,1",
	+ "EventCode": "0x83",
	+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART0",
	+ "Experimental": "1",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x001",
	+ "UMask": "0x2",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
	+ "Counter": "0,1",
	+ "EventCode": "0x83",
	+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART1",
	+ "Experimental": "1",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x002",
	+ "UMask": "0x2",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
	+ "Counter": "0,1",
	+ "EventCode": "0x83",
	+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART2",
	+ "Experimental": "1",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x004",
	+ "UMask": "0x2",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
	+ "Counter": "0,1",
	+ "EventCode": "0x83",
	+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART3",
	+ "Experimental": "1",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x008",
	+ "UMask": "0x2",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
	+ "Counter": "0,1",
	+ "EventCode": "0x83",
	+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART4",
	+ "Experimental": "1",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x010",
	+ "UMask": "0x2",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
	+ "Counter": "0,1",
	+ "EventCode": "0x83",
	+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART5",
	+ "Experimental": "1",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x020",
	+ "UMask": "0x2",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
	+ "Counter": "0,1",
	+ "EventCode": "0x83",
	+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART6",
	+ "Experimental": "1",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x040",
	+ "UMask": "0x2",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)",
	+ "Counter": "0,1",
	+ "EventCode": "0x83",
	+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART7",
	+ "Experimental": "1",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x080",
	+ "UMask": "0x2",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "IOTLB Hits to a 1G Page",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x40",
	+ "EventName": "UNC_IIO_IOMMU0.1G_HITS",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PortMask": "0x000",
	+ "UMask": "0x10",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "IOTLB Hits to a 2M Page",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x40",
	+ "EventName": "UNC_IIO_IOMMU0.2M_HITS",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PortMask": "0x000",
	+ "UMask": "0x8",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "IOTLB Hits to a 4K Page",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x40",
	+ "EventName": "UNC_IIO_IOMMU0.4K_HITS",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PortMask": "0x000",
	+ "UMask": "0x4",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "IOTLB lookups all",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x40",
	+ "EventName": "UNC_IIO_IOMMU0.ALL_LOOKUPS",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PortMask": "0x000",
	+ "UMask": "0x2",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Context cache hits",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x40",
	+ "EventName": "UNC_IIO_IOMMU0.CTXT_CACHE_HITS",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PortMask": "0x000",
	+ "UMask": "0x80",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Context cache lookups",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x40",
	+ "EventName": "UNC_IIO_IOMMU0.CTXT_CACHE_LOOKUPS",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PortMask": "0x000",
	+ "UMask": "0x40",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "IOTLB lookups first",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x40",
	+ "EventName": "UNC_IIO_IOMMU0.FIRST_LOOKUPS",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PortMask": "0x000",
	+ "UMask": "0x1",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "IOTLB Fills (same as IOTLB miss)",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x40",
	+ "EventName": "UNC_IIO_IOMMU0.MISSES",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PortMask": "0x000",
	+ "UMask": "0x20",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "IOMMU memory access (both low and high priority)",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x41",
	+ "EventName": "UNC_IIO_IOMMU1.NUM_MEM_ACCESSES",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PortMask": "0x000",
	+ "UMask": "0xc0",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "IOMMU high priority memory access",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x41",
	+ "EventName": "UNC_IIO_IOMMU1.NUM_MEM_ACCESSES_HIGH",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PortMask": "0x000",
	+ "UMask": "0x80",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "IOMMU low priority memory access",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x41",
	+ "EventName": "UNC_IIO_IOMMU1.NUM_MEM_ACCESSES_LOW",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PortMask": "0x000",
	+ "UMask": "0x40",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Second Level Page Walk Cache Hit to a 1G page",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x41",
	+ "EventName": "UNC_IIO_IOMMU1.SLPWC_1G_HITS",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PortMask": "0x000",
	+ "UMask": "0x4",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Second Level Page Walk Cache Hit to a 256T page",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x41",
	+ "EventName": "UNC_IIO_IOMMU1.SLPWC_256T_HITS",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PortMask": "0x000",
	+ "UMask": "0x10",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Second Level Page Walk Cache Hit to a 2M page",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x41",
	+ "EventName": "UNC_IIO_IOMMU1.SLPWC_2M_HITS",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PortMask": "0x000",
	+ "UMask": "0x2",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Second Level Page Walk Cache Hit to a 512G page",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x41",
	+ "EventName": "UNC_IIO_IOMMU1.SLPWC_512G_HITS",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PortMask": "0x000",
	+ "UMask": "0x8",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Second Level Page Walk Cache fill",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x41",
	+ "EventName": "UNC_IIO_IOMMU1.SLPWC_CACHE_FILLS",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PortMask": "0x000",
	+ "UMask": "0x20",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Second Level Page Walk Cache lookup",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x41",
	+ "EventName": "UNC_IIO_IOMMU1.SLPWC_CACHE_LOOKUPS",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PortMask": "0x000",
	+ "UMask": "0x1",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Cycles PWT full",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x43",
	+ "EventName": "UNC_IIO_IOMMU3.CYC_PWT_FULL",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PortMask": "0x000",
	+ "UMask": "0x2",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Interrupt Entry cache hit",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x43",
	+ "EventName": "UNC_IIO_IOMMU3.INT_CACHE_HITS",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PortMask": "0x000",
	+ "UMask": "0x80",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Interrupt Entry cache lookup",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x43",
	+ "EventName": "UNC_IIO_IOMMU3.INT_CACHE_LOOKUPS",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PortMask": "0x000",
	+ "UMask": "0x40",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Context Cache invalidation events",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x43",
	+ "EventName": "UNC_IIO_IOMMU3.NUM_INVAL_CTXT_CACHE",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PortMask": "0x000",
	+ "UMask": "0x8",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Interrupt Entry Cache invalidation events",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x43",
	+ "EventName": "UNC_IIO_IOMMU3.NUM_INVAL_INT_CACHE",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PortMask": "0x000",
	+ "UMask": "0x20",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "IOTLB invalidation events",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x43",
	+ "EventName": "UNC_IIO_IOMMU3.NUM_INVAL_IOTLB",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PortMask": "0x000",
	+ "UMask": "0x4",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "PASID Cache invalidation events",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x43",
	+ "EventName": "UNC_IIO_IOMMU3.NUM_INVAL_PASID_CACHE",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PortMask": "0x000",
	+ "UMask": "0x10",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "This event is deprecated. [This event is alias to UNC_IIO_NUM_OUTSTANDING_REQ_FROM_CPU.TO_IO]",
	+ "Counter": "2,3",
	+ "Deprecated": "1",
	+ "EventCode": "0xc5",
	+ "EventName": "UNC_IIO_NUM_OUSTANDING_REQ_FROM_CPU.TO_IO",
	+ "Experimental": "1",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x0FF",
	+ "UMask": "0x8",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Occupancy of outbound request queue : To device : Counts number of outbound requests/completions IIO is currently processing [This event is alias to UNC_IIO_NUM_OUSTANDING_REQ_FROM_CPU.TO_IO]",
	+ "Counter": "2,3",
	+ "EventCode": "0xc5",
	+ "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_FROM_CPU.TO_IO",
	+ "Experimental": "1",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x0FF",
	+ "UMask": "0x8",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Passing data to be written",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x88",
	+ "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.DATA",
	+ "Experimental": "1",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x0FF",
	+ "UMask": "0x20",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Issuing final read or write of line",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x88",
	+ "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.FINAL_RD_WR",
	+ "Experimental": "1",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x0FF",
	+ "UMask": "0x8",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Processing response from IOMMU",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x88",
	+ "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.IOMMU_HIT",
	+ "Experimental": "1",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x0FF",
	+ "UMask": "0x2",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Issuing to IOMMU",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x88",
	+ "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.IOMMU_REQ",
	+ "Experimental": "1",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x0FF",
	+ "UMask": "0x1",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Request Ownership",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x88",
	+ "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.REQ_OWN",
	+ "Experimental": "1",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x0FF",
	+ "UMask": "0x4",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Writing line",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x88",
	+ "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.WR",
	+ "Experimental": "1",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x0FF",
	+ "UMask": "0x10",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "-",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x8e",
	+ "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.ABORT",
	+ "Experimental": "1",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x0FF",
	+ "UMask": "0x80",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "-",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x8e",
	+ "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.CONFINED_P2P",
	+ "Experimental": "1",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x0FF",
	+ "UMask": "0x40",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "-",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x8e",
	+ "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.LOC_P2P",
	+ "Experimental": "1",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x0FF",
	+ "UMask": "0x20",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "-",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x8e",
	+ "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.MCAST",
	+ "Experimental": "1",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x0FF",
	+ "UMask": "0x2",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "-",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x8e",
	+ "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.MEM",
	+ "Experimental": "1",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x0FF",
	+ "UMask": "0x8",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "-",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x8e",
	+ "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.MSGB",
	+ "Experimental": "1",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x0FF",
	+ "UMask": "0x1",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "-",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x8e",
	+ "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.REM_P2P",
	+ "Experimental": "1",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x0FF",
	+ "UMask": "0x10",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "-",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x8e",
	+ "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.UBOX",
	+ "Experimental": "1",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x0FF",
	+ "UMask": "0x4",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Posted requests sent by the integrated IO (IIO) controller to the Ubox, useful for counting message signaled interrupts (MSI).",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x8e",
	+ "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.UBOX_POSTED",
	+ "FCMask": "0x01",
	+ "PerPkg": "1",
	+ "PortMask": "0x0FF",
	+ "UMask": "0x4",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "All 9 bits of Page Walk Tracker Occupancy",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x42",
	+ "EventName": "UNC_IIO_PWT_OCCUPANCY",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PortMask": "0x000",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space",
	+ "Counter": "2,3",
	+ "EventCode": "0xC1",
	+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.ALL_PARTS",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x0FF",
	+ "UMask": "0x4",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space",
	+ "Counter": "2,3",
	+ "EventCode": "0xC1",
	+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART0",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x001",
	+ "UMask": "0x4",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space",
	+ "Counter": "2,3",
	+ "EventCode": "0xC1",
	+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART1",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x002",
	+ "UMask": "0x4",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space",
	+ "Counter": "2,3",
	+ "EventCode": "0xC1",
	+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART2",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x004",
	+ "UMask": "0x4",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space",
	+ "Counter": "2,3",
	+ "EventCode": "0xC1",
	+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART3",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x008",
	+ "UMask": "0x4",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space",
	+ "Counter": "2,3",
	+ "EventCode": "0xC1",
	+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART4",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x010",
	+ "UMask": "0x4",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space",
	+ "Counter": "2,3",
	+ "EventCode": "0xC1",
	+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART5",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x020",
	+ "UMask": "0x4",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space",
	+ "Counter": "2,3",
	+ "EventCode": "0xC1",
	+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART6",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x040",
	+ "UMask": "0x4",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space",
	+ "Counter": "2,3",
	+ "EventCode": "0xC1",
	+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART7",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x080",
	+ "UMask": "0x4",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space",
	+ "Counter": "2,3",
	+ "EventCode": "0xC1",
	+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.ALL_PARTS",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x0FF",
	+ "UMask": "0x1",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space",
	+ "Counter": "2,3",
	+ "EventCode": "0xC1",
	+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART0",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x001",
	+ "UMask": "0x1",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space",
	+ "Counter": "2,3",
	+ "EventCode": "0xC1",
	+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART1",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x002",
	+ "UMask": "0x1",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space",
	+ "Counter": "2,3",
	+ "EventCode": "0xC1",
	+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART2",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x004",
	+ "UMask": "0x1",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space",
	+ "Counter": "2,3",
	+ "EventCode": "0xC1",
	+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART3",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x008",
	+ "UMask": "0x1",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space",
	+ "Counter": "2,3",
	+ "EventCode": "0xC1",
	+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART4",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x010",
	+ "UMask": "0x1",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space",
	+ "Counter": "2,3",
	+ "EventCode": "0xC1",
	+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART5",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x020",
	+ "UMask": "0x1",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space",
	+ "Counter": "2,3",
	+ "EventCode": "0xC1",
	+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART6",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x040",
	+ "UMask": "0x1",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space",
	+ "Counter": "2,3",
	+ "EventCode": "0xC1",
	+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART7",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x080",
	+ "UMask": "0x1",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card.",
	+ "Counter": "2,3",
	+ "EventCode": "0xC1",
	+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.ALL_PARTS",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x0FF",
	+ "UMask": "0x8",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card.",
	+ "Counter": "2,3",
	+ "EventCode": "0xC1",
	+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.ALL_PARTS",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x0FF",
	+ "UMask": "0x2",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
	+ "Counter": "0,1",
	+ "EventCode": "0x84",
	+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART0",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x001",
	+ "UMask": "0x4",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
	+ "Counter": "0,1",
	+ "EventCode": "0x84",
	+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART1",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x002",
	+ "UMask": "0x4",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
	+ "Counter": "0,1",
	+ "EventCode": "0x84",
	+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART2",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x004",
	+ "UMask": "0x4",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
	+ "Counter": "0,1",
	+ "EventCode": "0x84",
	+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART3",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x008",
	+ "UMask": "0x4",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
	+ "Counter": "0,1",
	+ "EventCode": "0x84",
	+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART4",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x010",
	+ "UMask": "0x4",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
	+ "Counter": "0,1",
	+ "EventCode": "0x84",
	+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART5",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x020",
	+ "UMask": "0x4",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
	+ "Counter": "0,1",
	+ "EventCode": "0x84",
	+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART6",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x040",
	+ "UMask": "0x4",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM",
	+ "Counter": "0,1",
	+ "EventCode": "0x84",
	+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART7",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x080",
	+ "UMask": "0x4",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
	+ "Counter": "0,1",
	+ "EventCode": "0x84",
	+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART0",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x001",
	+ "UMask": "0x1",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
	+ "Counter": "0,1",
	+ "EventCode": "0x84",
	+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART1",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x002",
	+ "UMask": "0x1",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
	+ "Counter": "0,1",
	+ "EventCode": "0x84",
	+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART2",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x004",
	+ "UMask": "0x1",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
	+ "Counter": "0,1",
	+ "EventCode": "0x84",
	+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART3",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x008",
	+ "UMask": "0x1",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
	+ "Counter": "0,1",
	+ "EventCode": "0x84",
	+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART4",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x010",
	+ "UMask": "0x1",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
	+ "Counter": "0,1",
	+ "EventCode": "0x84",
	+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART5",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x020",
	+ "UMask": "0x1",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
	+ "Counter": "0,1",
	+ "EventCode": "0x84",
	+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART6",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x040",
	+ "UMask": "0x1",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM",
	+ "Counter": "0,1",
	+ "EventCode": "0x84",
	+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART7",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x080",
	+ "UMask": "0x1",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)",
	+ "Counter": "0,1",
	+ "EventCode": "0x84",
	+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART0",
	+ "Experimental": "1",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x001",
	+ "UMask": "0x8",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)",
	+ "Counter": "0,1",
	+ "EventCode": "0x84",
	+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART1",
	+ "Experimental": "1",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x002",
	+ "UMask": "0x8",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)",
	+ "Counter": "0,1",
	+ "EventCode": "0x84",
	+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART2",
	+ "Experimental": "1",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x004",
	+ "UMask": "0x8",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)",
	+ "Counter": "0,1",
	+ "EventCode": "0x84",
	+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART3",
	+ "Experimental": "1",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x008",
	+ "UMask": "0x8",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)",
	+ "Counter": "0,1",
	+ "EventCode": "0x84",
	+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART4",
	+ "Experimental": "1",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x010",
	+ "UMask": "0x8",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)",
	+ "Counter": "0,1",
	+ "EventCode": "0x84",
	+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART5",
	+ "Experimental": "1",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x020",
	+ "UMask": "0x8",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)",
	+ "Counter": "0,1",
	+ "EventCode": "0x84",
	+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART6",
	+ "Experimental": "1",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x040",
	+ "UMask": "0x8",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)",
	+ "Counter": "0,1",
	+ "EventCode": "0x84",
	+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART7",
	+ "Experimental": "1",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x080",
	+ "UMask": "0x8",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
	+ "Counter": "0,1",
	+ "EventCode": "0x84",
	+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART0",
	+ "Experimental": "1",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x001",
	+ "UMask": "0x2",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
	+ "Counter": "0,1",
	+ "EventCode": "0x84",
	+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART1",
	+ "Experimental": "1",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x002",
	+ "UMask": "0x2",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
	+ "Counter": "0,1",
	+ "EventCode": "0x84",
	+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART2",
	+ "Experimental": "1",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x004",
	+ "UMask": "0x2",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
	+ "Counter": "0,1",
	+ "EventCode": "0x84",
	+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART3",
	+ "Experimental": "1",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x008",
	+ "UMask": "0x2",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
	+ "Counter": "0,1",
	+ "EventCode": "0x84",
	+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART4",
	+ "Experimental": "1",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x010",
	+ "UMask": "0x2",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
	+ "Counter": "0,1",
	+ "EventCode": "0x84",
	+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART5",
	+ "Experimental": "1",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x020",
	+ "UMask": "0x2",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
	+ "Counter": "0,1",
	+ "EventCode": "0x84",
	+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART6",
	+ "Experimental": "1",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x040",
	+ "UMask": "0x2",
	+ "Unit": "IIO"
	+ },
	+ {
	+ "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)",
	+ "Counter": "0,1",
	+ "EventCode": "0x84",
	+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART7",
	+ "Experimental": "1",
	+ "FCMask": "0x07",
	+ "PerPkg": "1",
	+ "PortMask": "0x080",
	+ "UMask": "0x2",
	+ "Unit": "IIO"
	+ }
	+]
	\ No newline at end of file
	diff --git a/lib/libpmc/pmu-events/arch/x86/graniterapids/uncore-memory.json b/lib/libpmc/pmu-events/arch/x86/graniterapids/uncore-memory.json
	new file mode 100644
	--- /dev/null
	+++ b/lib/libpmc/pmu-events/arch/x86/graniterapids/uncore-memory.json
	@@ -0,0 +1,890 @@
	+[
	+ {
	+ "BriefDescription": "DRAM Activate Count : Counts the number of DRAM Activate commands sent on this channel. Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS. One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x02",
	+ "EventName": "UNC_M_ACT_COUNT.ALL",
	+ "PerPkg": "1",
	+ "UMask": "0xf7",
	+ "Unit": "IMC"
	+ },
	+ {
	+ "BriefDescription": "DRAM Activate Count : Read transaction on Page Empty or Page Miss : Counts the number of DRAM Activate commands sent on this channel. Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS. One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x02",
	+ "EventName": "UNC_M_ACT_COUNT.RD",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0xf1",
	+ "Unit": "IMC"
	+ },
	+ {
	+ "BriefDescription": "DRAM Activate Count : Underfill Read transaction on Page Empty or Page Miss : Counts the number of DRAM Activate commands sent on this channel. Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS. One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x02",
	+ "EventName": "UNC_M_ACT_COUNT.UFILL",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0xf4",
	+ "Unit": "IMC"
	+ },
	+ {
	+ "BriefDescription": "DRAM Activate Count : Write transaction on Page Empty or Page Miss : Counts the number of DRAM Activate commands sent on this channel. Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS. One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x02",
	+ "EventName": "UNC_M_ACT_COUNT.WR",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0xf2",
	+ "Unit": "IMC"
	+ },
	+ {
	+ "BriefDescription": "CAS count for SubChannel 0, all CAS operations",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x05",
	+ "EventName": "UNC_M_CAS_COUNT_SCH0.ALL",
	+ "PerPkg": "1",
	+ "UMask": "0xff",
	+ "Unit": "IMC"
	+ },
	+ {
	+ "BriefDescription": "CAS count for SubChannel 0, all reads",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x05",
	+ "EventName": "UNC_M_CAS_COUNT_SCH0.RD",
	+ "PerPkg": "1",
	+ "UMask": "0xcf",
	+ "Unit": "IMC"
	+ },
	+ {
	+ "BriefDescription": "CAS count for SubChannel 0 regular reads",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x05",
	+ "EventName": "UNC_M_CAS_COUNT_SCH0.RD_NON_UNDERFILL",
	+ "PerPkg": "1",
	+ "UMask": "0xc3",
	+ "Unit": "IMC"
	+ },
	+ {
	+ "BriefDescription": "CAS count for SubChannel 0 auto-precharge reads",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x05",
	+ "EventName": "UNC_M_CAS_COUNT_SCH0.RD_PRE_REG",
	+ "PerPkg": "1",
	+ "UMask": "0xc2",
	+ "Unit": "IMC"
	+ },
	+ {
	+ "BriefDescription": "CAS count for SubChannel 0 auto-precharge underfill reads",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x05",
	+ "EventName": "UNC_M_CAS_COUNT_SCH0.RD_PRE_UNDERFILL",
	+ "PerPkg": "1",
	+ "UMask": "0xc8",
	+ "Unit": "IMC"
	+ },
	+ {
	+ "BriefDescription": "CAS count for SubChannel 0 regular reads",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x05",
	+ "EventName": "UNC_M_CAS_COUNT_SCH0.RD_REG",
	+ "PerPkg": "1",
	+ "UMask": "0xc1",
	+ "Unit": "IMC"
	+ },
	+ {
	+ "BriefDescription": "CAS count for SubChannel 0 underfill reads",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x05",
	+ "EventName": "UNC_M_CAS_COUNT_SCH0.RD_UNDERFILL",
	+ "PerPkg": "1",
	+ "UMask": "0xc4",
	+ "Unit": "IMC"
	+ },
	+ {
	+ "BriefDescription": "CAS count for SubChannel 0 underfill reads",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x05",
	+ "EventName": "UNC_M_CAS_COUNT_SCH0.RD_UNDERFILL_ALL",
	+ "PerPkg": "1",
	+ "UMask": "0xcc",
	+ "Unit": "IMC"
	+ },
	+ {
	+ "BriefDescription": "CAS count for SubChannel 0, all writes",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x05",
	+ "EventName": "UNC_M_CAS_COUNT_SCH0.WR",
	+ "PerPkg": "1",
	+ "UMask": "0xf0",
	+ "Unit": "IMC"
	+ },
	+ {
	+ "BriefDescription": "CAS count for SubChannel 0 regular writes",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x05",
	+ "EventName": "UNC_M_CAS_COUNT_SCH0.WR_NONPRE",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0xd0",
	+ "Unit": "IMC"
	+ },
	+ {
	+ "BriefDescription": "CAS count for SubChannel 0 auto-precharge writes",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x05",
	+ "EventName": "UNC_M_CAS_COUNT_SCH0.WR_PRE",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0xe0",
	+ "Unit": "IMC"
	+ },
	+ {
	+ "BriefDescription": "CAS count for SubChannel 1, all CAS operations",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x06",
	+ "EventName": "UNC_M_CAS_COUNT_SCH1.ALL",
	+ "PerPkg": "1",
	+ "UMask": "0xff",
	+ "Unit": "IMC"
	+ },
	+ {
	+ "BriefDescription": "CAS count for SubChannel 1, all reads",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x06",
	+ "EventName": "UNC_M_CAS_COUNT_SCH1.RD",
	+ "PerPkg": "1",
	+ "UMask": "0xcf",
	+ "Unit": "IMC"
	+ },
	+ {
	+ "BriefDescription": "CAS count for SubChannel 1 regular reads",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x06",
	+ "EventName": "UNC_M_CAS_COUNT_SCH1.RD_NON_UNDERFILL",
	+ "PerPkg": "1",
	+ "UMask": "0xc3",
	+ "Unit": "IMC"
	+ },
	+ {
	+ "BriefDescription": "CAS count for SubChannel 1 auto-precharge reads",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x06",
	+ "EventName": "UNC_M_CAS_COUNT_SCH1.RD_PRE_REG",
	+ "PerPkg": "1",
	+ "UMask": "0xc2",
	+ "Unit": "IMC"
	+ },
	+ {
	+ "BriefDescription": "CAS count for SubChannel 1 auto-precharge underfill reads",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x06",
	+ "EventName": "UNC_M_CAS_COUNT_SCH1.RD_PRE_UNDERFILL",
	+ "PerPkg": "1",
	+ "UMask": "0xc8",
	+ "Unit": "IMC"
	+ },
	+ {
	+ "BriefDescription": "CAS count for SubChannel 1 regular reads",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x06",
	+ "EventName": "UNC_M_CAS_COUNT_SCH1.RD_REG",
	+ "PerPkg": "1",
	+ "UMask": "0xc1",
	+ "Unit": "IMC"
	+ },
	+ {
	+ "BriefDescription": "CAS count for SubChannel 1 underfill reads",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x06",
	+ "EventName": "UNC_M_CAS_COUNT_SCH1.RD_UNDERFILL",
	+ "PerPkg": "1",
	+ "UMask": "0xc4",
	+ "Unit": "IMC"
	+ },
	+ {
	+ "BriefDescription": "CAS count for SubChannel 1 underfill reads",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x06",
	+ "EventName": "UNC_M_CAS_COUNT_SCH1.RD_UNDERFILL_ALL",
	+ "PerPkg": "1",
	+ "UMask": "0xcc",
	+ "Unit": "IMC"
	+ },
	+ {
	+ "BriefDescription": "CAS count for SubChannel 1, all writes",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x06",
	+ "EventName": "UNC_M_CAS_COUNT_SCH1.WR",
	+ "PerPkg": "1",
	+ "UMask": "0xf0",
	+ "Unit": "IMC"
	+ },
	+ {
	+ "BriefDescription": "CAS count for SubChannel 1 regular writes",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x06",
	+ "EventName": "UNC_M_CAS_COUNT_SCH1.WR_NONPRE",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0xd0",
	+ "Unit": "IMC"
	+ },
	+ {
	+ "BriefDescription": "CAS count for SubChannel 1 auto-precharge writes",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x06",
	+ "EventName": "UNC_M_CAS_COUNT_SCH1.WR_PRE",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0xe0",
	+ "Unit": "IMC"
	+ },
	+ {
	+ "BriefDescription": "Number of DRAM DCLK clock cycles while the event is enabled. DCLK is 1/4 of DRAM data rate.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x01",
	+ "EventName": "UNC_M_CLOCKTICKS",
	+ "PerPkg": "1",
	+ "PublicDescription": "DRAM Clockticks",
	+ "UMask": "0x1",
	+ "Unit": "IMC"
	+ },
	+ {
	+ "BriefDescription": "Number of DRAM HCLK clock cycles while the event is enabled",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x01",
	+ "EventName": "UNC_M_HCLOCKTICKS",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PublicDescription": "DRAM Clockticks",
	+ "Unit": "IMC"
	+ },
	+ {
	+ "BriefDescription": "PMMNT is sending REF* commands while being in specified Refresh rate",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x72",
	+ "EventName": "UNC_M_MNTCMD_REFRATE.REFAB1X",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x1",
	+ "Unit": "IMC"
	+ },
	+ {
	+ "BriefDescription": "PMMNT is sending REF* commands while being in specified Refresh rate",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x72",
	+ "EventName": "UNC_M_MNTCMD_REFRATE.REFAB2X",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x4",
	+ "Unit": "IMC"
	+ },
	+ {
	+ "BriefDescription": "PMMNT is sending REF* commands while being in specified Refresh rate",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x72",
	+ "EventName": "UNC_M_MNTCMD_REFRATE.REFSB1X",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x2",
	+ "Unit": "IMC"
	+ },
	+ {
	+ "BriefDescription": "PMMNT is sending REF* commands while being in specified Refresh rate",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x72",
	+ "EventName": "UNC_M_MNTCMD_REFRATE.REFSB2X",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x8",
	+ "Unit": "IMC"
	+ },
	+ {
	+ "BriefDescription": "# of cycles MR4 temp readings forced 2x refresh",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0xA7",
	+ "EventName": "UNC_M_MR4_2XREF_CYCLES.SCH0_DIMM0",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x1",
	+ "Unit": "IMC"
	+ },
	+ {
	+ "BriefDescription": "# of cycles MR4 temp readings forced 2x refresh",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0xA7",
	+ "EventName": "UNC_M_MR4_2XREF_CYCLES.SCH0_DIMM1",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x2",
	+ "Unit": "IMC"
	+ },
	+ {
	+ "BriefDescription": "# of cycles MR4 temp readings forced 2x refresh",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0xA7",
	+ "EventName": "UNC_M_MR4_2XREF_CYCLES.SCH1_DIMM0",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x4",
	+ "Unit": "IMC"
	+ },
	+ {
	+ "BriefDescription": "# of cycles MR4 temp readings forced 2x refresh",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0xA7",
	+ "EventName": "UNC_M_MR4_2XREF_CYCLES.SCH1_DIMM1",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x8",
	+ "Unit": "IMC"
	+ },
	+ {
	+ "BriefDescription": "# of cycles MR4 MRRs was triggered/running",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0xA6",
	+ "EventName": "UNC_M_PDC_MR4ACTIVE_CYCLES.SCH0_DIMM0",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x1",
	+ "Unit": "IMC"
	+ },
	+ {
	+ "BriefDescription": "# of cycles MR4 MRRs was triggered/running",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0xA6",
	+ "EventName": "UNC_M_PDC_MR4ACTIVE_CYCLES.SCH0_DIMM1",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x2",
	+ "Unit": "IMC"
	+ },
	+ {
	+ "BriefDescription": "# of cycles MR4 MRRs was triggered/running",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0xA6",
	+ "EventName": "UNC_M_PDC_MR4ACTIVE_CYCLES.SCH1_DIMM0",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x4",
	+ "Unit": "IMC"
	+ },
	+ {
	+ "BriefDescription": "# of cycles MR4 MRRs was triggered/running",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0xA6",
	+ "EventName": "UNC_M_PDC_MR4ACTIVE_CYCLES.SCH1_DIMM1",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x8",
	+ "Unit": "IMC"
	+ },
	+ {
	+ "BriefDescription": "# of cycles a given rank is in Power Down Mode",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x47",
	+ "EventName": "UNC_M_POWERDOWN_CYCLES.SCH0_RANK0",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x1",
	+ "Unit": "IMC"
	+ },
	+ {
	+ "BriefDescription": "# of cycles a given rank is in Power Down Mode",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x47",
	+ "EventName": "UNC_M_POWERDOWN_CYCLES.SCH0_RANK1",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x2",
	+ "Unit": "IMC"
	+ },
	+ {
	+ "BriefDescription": "# of cycles a given rank is in Power Down Mode",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x47",
	+ "EventName": "UNC_M_POWERDOWN_CYCLES.SCH0_RANK2",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x4",
	+ "Unit": "IMC"
	+ },
	+ {
	+ "BriefDescription": "# of cycles a given rank is in Power Down Mode",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x47",
	+ "EventName": "UNC_M_POWERDOWN_CYCLES.SCH0_RANK3",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x8",
	+ "Unit": "IMC"
	+ },
	+ {
	+ "BriefDescription": "# of cycles a given rank is in Power Down Mode",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x47",
	+ "EventName": "UNC_M_POWERDOWN_CYCLES.SCH1_RANK0",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x10",
	+ "Unit": "IMC"
	+ },
	+ {
	+ "BriefDescription": "# of cycles a given rank is in Power Down Mode",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x47",
	+ "EventName": "UNC_M_POWERDOWN_CYCLES.SCH1_RANK1",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x20",
	+ "Unit": "IMC"
	+ },
	+ {
	+ "BriefDescription": "# of cycles a given rank is in Power Down Mode",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x47",
	+ "EventName": "UNC_M_POWERDOWN_CYCLES.SCH1_RANK2",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x40",
	+ "Unit": "IMC"
	+ },
	+ {
	+ "BriefDescription": "# of cycles a given rank is in Power Down Mode",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x47",
	+ "EventName": "UNC_M_POWERDOWN_CYCLES.SCH1_RANK3",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x80",
	+ "Unit": "IMC"
	+ },
	+ {
	+ "BriefDescription": "# of cycles a given rank is in Power Down Mode and all pages are closed",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x88",
	+ "EventName": "UNC_M_POWER_CHANNEL_PPD_CYCLES",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "Unit": "IMC"
	+ },
	+ {
	+ "BriefDescription": "# of cycles Throttling at Critical level on specified DIMM and throttle level is zero.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x89",
	+ "EventName": "UNC_M_POWER_CRITICAL_THROTTLE_CYCLES.SLOT0",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x1",
	+ "Unit": "IMC"
	+ },
	+ {
	+ "BriefDescription": "# of cycles Throttling at Critical level on specified DIMM and throttle level is zero.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x89",
	+ "EventName": "UNC_M_POWER_CRITICAL_THROTTLE_CYCLES.SLOT1",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x2",
	+ "Unit": "IMC"
	+ },
	+ {
	+ "BriefDescription": "UNC_M_POWER_THROTTLE_CYCLES.BW_SLOT0",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x46",
	+ "EventName": "UNC_M_POWER_THROTTLE_CYCLES.BW_SLOT0",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x1",
	+ "Unit": "IMC"
	+ },
	+ {
	+ "BriefDescription": "UNC_M_POWER_THROTTLE_CYCLES.BW_SLOT1",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x46",
	+ "EventName": "UNC_M_POWER_THROTTLE_CYCLES.BW_SLOT1",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x2",
	+ "Unit": "IMC"
	+ },
	+ {
	+ "BriefDescription": "MR4 temp reading is throttling",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x46",
	+ "EventName": "UNC_M_POWER_THROTTLE_CYCLES.MR4BLKEN",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x8",
	+ "Unit": "IMC"
	+ },
	+ {
	+ "BriefDescription": "RAPL is throttling",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x46",
	+ "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RAPLBLK",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x4",
	+ "Unit": "IMC"
	+ },
	+ {
	+ "BriefDescription": "DRAM Precharge commands. : Counts the number of DRAM Precharge commands sent on this channel.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x03",
	+ "EventName": "UNC_M_PRE_COUNT.ALL",
	+ "PerPkg": "1",
	+ "UMask": "0xff",
	+ "Unit": "IMC"
	+ },
	+ {
	+ "BriefDescription": "DRAM Precharge commands. : Precharge due to (?) : Counts the number of DRAM Precharge commands sent on this channel.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x03",
	+ "EventName": "UNC_M_PRE_COUNT.PGT",
	+ "PerPkg": "1",
	+ "UMask": "0xf8",
	+ "Unit": "IMC"
	+ },
	+ {
	+ "BriefDescription": "DRAM Precharge commands. : Counts the number of DRAM Precharge commands sent on this channel.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x03",
	+ "EventName": "UNC_M_PRE_COUNT.RD",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0xf1",
	+ "Unit": "IMC"
	+ },
	+ {
	+ "BriefDescription": "DRAM Precharge commands. : Counts the number of DRAM Precharge commands sent on this channel.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x03",
	+ "EventName": "UNC_M_PRE_COUNT.UFILL",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0xf4",
	+ "Unit": "IMC"
	+ },
	+ {
	+ "BriefDescription": "DRAM Precharge commands. : Counts the number of DRAM Precharge commands sent on this channel.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x03",
	+ "EventName": "UNC_M_PRE_COUNT.WR",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0xf2",
	+ "Unit": "IMC"
	+ },
	+ {
	+ "BriefDescription": "Read buffer inserts on subchannel 0",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x17",
	+ "EventName": "UNC_M_RDB_INSERTS.SCH0",
	+ "PerPkg": "1",
	+ "UMask": "0x40",
	+ "Unit": "IMC"
	+ },
	+ {
	+ "BriefDescription": "Read buffer inserts on subchannel 1",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x17",
	+ "EventName": "UNC_M_RDB_INSERTS.SCH1",
	+ "PerPkg": "1",
	+ "UMask": "0x80",
	+ "Unit": "IMC"
	+ },
	+ {
	+ "BriefDescription": "Read buffer occupancy on subchannel 0",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x1a",
	+ "EventName": "UNC_M_RDB_OCCUPANCY_SCH0",
	+ "PerPkg": "1",
	+ "Unit": "IMC"
	+ },
	+ {
	+ "BriefDescription": "Read buffer occupancy on subchannel 1",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x1b",
	+ "EventName": "UNC_M_RDB_OCCUPANCY_SCH1",
	+ "PerPkg": "1",
	+ "Unit": "IMC"
	+ },
	+ {
	+ "BriefDescription": "Read Pending Queue Allocations : Counts the number of allocations into the Read Pending Queue. This queue is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory. This includes both ISOCH and non-ISOCH requests.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x10",
	+ "EventName": "UNC_M_RPQ_INSERTS.PCH0",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x50",
	+ "Unit": "IMC"
	+ },
	+ {
	+ "BriefDescription": "Read Pending Queue Allocations : Counts the number of allocations into the Read Pending Queue. This queue is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory. This includes both ISOCH and non-ISOCH requests.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x10",
	+ "EventName": "UNC_M_RPQ_INSERTS.PCH1",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0xa0",
	+ "Unit": "IMC"
	+ },
	+ {
	+ "BriefDescription": "Read Pending Queue inserts for subchannel 0, pseudochannel 0",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x10",
	+ "EventName": "UNC_M_RPQ_INSERTS.SCH0_PCH0",
	+ "PerPkg": "1",
	+ "UMask": "0x10",
	+ "Unit": "IMC"
	+ },
	+ {
	+ "BriefDescription": "Read Pending Queue inserts for subchannel 0, pseudochannel 1",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x10",
	+ "EventName": "UNC_M_RPQ_INSERTS.SCH0_PCH1",
	+ "PerPkg": "1",
	+ "UMask": "0x20",
	+ "Unit": "IMC"
	+ },
	+ {
	+ "BriefDescription": "Read Pending Queue inserts for subchannel 1, pseudochannel 0",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x10",
	+ "EventName": "UNC_M_RPQ_INSERTS.SCH1_PCH0",
	+ "PerPkg": "1",
	+ "UMask": "0x40",
	+ "Unit": "IMC"
	+ },
	+ {
	+ "BriefDescription": "Read Pending Queue inserts for subchannel 1, pseudochannel 1",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x10",
	+ "EventName": "UNC_M_RPQ_INSERTS.SCH1_PCH1",
	+ "PerPkg": "1",
	+ "UMask": "0x80",
	+ "Unit": "IMC"
	+ },
	+ {
	+ "BriefDescription": "Read pending queue occupancy for subchannel 0, pseudochannel 0",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x80",
	+ "EventName": "UNC_M_RPQ_OCCUPANCY_SCH0_PCH0",
	+ "PerPkg": "1",
	+ "Unit": "IMC"
	+ },
	+ {
	+ "BriefDescription": "Read pending queue occupancy for subchannel 0, pseudochannel 1",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x81",
	+ "EventName": "UNC_M_RPQ_OCCUPANCY_SCH0_PCH1",
	+ "PerPkg": "1",
	+ "Unit": "IMC"
	+ },
	+ {
	+ "BriefDescription": "Read pending queue occupancy for subchannel 1, pseudochannel 0",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x82",
	+ "EventName": "UNC_M_RPQ_OCCUPANCY_SCH1_PCH0",
	+ "PerPkg": "1",
	+ "Unit": "IMC"
	+ },
	+ {
	+ "BriefDescription": "Read pending queue occupancy for subchannel 1, pseudochannel 1",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x83",
	+ "EventName": "UNC_M_RPQ_OCCUPANCY_SCH1_PCH1",
	+ "PerPkg": "1",
	+ "Unit": "IMC"
	+ },
	+ {
	+ "BriefDescription": "subevent0 - # of cycles all ranks were in SR subevent1 - # of times all ranks went into SR subevent2 -# of times ps_sr_active asserted (SRE) subevent3 - # of times ps_sr_active deasserted (SRX) subevent4 - # of times PS-&>Refresh ps_sr_req asserted (SRE) subevent5 - # of times PS-&>Refresh ps_sr_req deasserted (SRX) subevent6 - # of cycles PSCtrlr FSM was in FATAL",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x43",
	+ "EventName": "UNC_M_SELF_REFRESH.ENTER_SUCCESS",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x2",
	+ "Unit": "IMC"
	+ },
	+ {
	+ "BriefDescription": "# of cycles all ranks were in SR",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x43",
	+ "EventName": "UNC_M_SELF_REFRESH.ENTER_SUCCESS_CYCLES",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x1",
	+ "Unit": "IMC"
	+ },
	+ {
	+ "BriefDescription": "# of cycles Throttling at Critical level on specified DIMM",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x8e",
	+ "EventName": "UNC_M_THROTTLE_CRIT_CYCLES.SLOT0",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x1",
	+ "Unit": "IMC"
	+ },
	+ {
	+ "BriefDescription": "# of cycles Throttling at Critical level on specified DIMM",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x8e",
	+ "EventName": "UNC_M_THROTTLE_CRIT_CYCLES.SLOT1",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x2",
	+ "Unit": "IMC"
	+ },
	+ {
	+ "BriefDescription": "# of cycles Throttling at High level on specified DIMM",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x8d",
	+ "EventName": "UNC_M_THROTTLE_HIGH_CYCLES.SLOT0",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x1",
	+ "Unit": "IMC"
	+ },
	+ {
	+ "BriefDescription": "# of cycles Throttling at High level on specified DIMM",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x8d",
	+ "EventName": "UNC_M_THROTTLE_HIGH_CYCLES.SLOT1",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x2",
	+ "Unit": "IMC"
	+ },
	+ {
	+ "BriefDescription": "# of cycles Throttling at Normal level on specified DIMM",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x8b",
	+ "EventName": "UNC_M_THROTTLE_LOW_CYCLES.SLOT0",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x1",
	+ "Unit": "IMC"
	+ },
	+ {
	+ "BriefDescription": "# of cycles Throttling at Normal level on specified DIMM",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x8b",
	+ "EventName": "UNC_M_THROTTLE_LOW_CYCLES.SLOT1",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x2",
	+ "Unit": "IMC"
	+ },
	+ {
	+ "BriefDescription": "# of cycles Throttling at Mid level on specified DIMM",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x8c",
	+ "EventName": "UNC_M_THROTTLE_MID_CYCLES.SLOT0",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x1",
	+ "Unit": "IMC"
	+ },
	+ {
	+ "BriefDescription": "# of cycles Throttling at Mid level on specified DIMM",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x8c",
	+ "EventName": "UNC_M_THROTTLE_MID_CYCLES.SLOT1",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x2",
	+ "Unit": "IMC"
	+ },
	+ {
	+ "BriefDescription": "Write Pending Queue Allocations",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x22",
	+ "EventName": "UNC_M_WPQ_INSERTS.PCH0",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0x50",
	+ "Unit": "IMC"
	+ },
	+ {
	+ "BriefDescription": "Write Pending Queue Allocations",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x22",
	+ "EventName": "UNC_M_WPQ_INSERTS.PCH1",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "UMask": "0xa0",
	+ "Unit": "IMC"
	+ },
	+ {
	+ "BriefDescription": "Write Pending Queue inserts for subchannel 0, pseudochannel 0",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x22",
	+ "EventName": "UNC_M_WPQ_INSERTS.SCH0_PCH0",
	+ "PerPkg": "1",
	+ "UMask": "0x10",
	+ "Unit": "IMC"
	+ },
	+ {
	+ "BriefDescription": "Write Pending Queue inserts for subchannel 0, pseudochannel 1",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x22",
	+ "EventName": "UNC_M_WPQ_INSERTS.SCH0_PCH1",
	+ "PerPkg": "1",
	+ "UMask": "0x20",
	+ "Unit": "IMC"
	+ },
	+ {
	+ "BriefDescription": "Write Pending Queue inserts for subchannel 1, pseudochannel 0",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x22",
	+ "EventName": "UNC_M_WPQ_INSERTS.SCH1_PCH0",
	+ "PerPkg": "1",
	+ "UMask": "0x40",
	+ "Unit": "IMC"
	+ },
	+ {
	+ "BriefDescription": "Write Pending Queue inserts for subchannel 1, pseudochannel 1",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x22",
	+ "EventName": "UNC_M_WPQ_INSERTS.SCH1_PCH1",
	+ "PerPkg": "1",
	+ "UMask": "0x80",
	+ "Unit": "IMC"
	+ },
	+ {
	+ "BriefDescription": "Write pending queue occupancy for subchannel 0, pseudochannel 0",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x84",
	+ "EventName": "UNC_M_WPQ_OCCUPANCY_SCH0_PCH0",
	+ "PerPkg": "1",
	+ "Unit": "IMC"
	+ },
	+ {
	+ "BriefDescription": "Write pending queue occupancy for subchannel 0, pseudochannel 1",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x85",
	+ "EventName": "UNC_M_WPQ_OCCUPANCY_SCH0_PCH1",
	+ "PerPkg": "1",
	+ "Unit": "IMC"
	+ },
	+ {
	+ "BriefDescription": "Write pending queue occupancy for subchannel 1, pseudochannel 0",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x86",
	+ "EventName": "UNC_M_WPQ_OCCUPANCY_SCH1_PCH0",
	+ "PerPkg": "1",
	+ "Unit": "IMC"
	+ },
	+ {
	+ "BriefDescription": "Write pending queue occupancy for subchannel 1, pseudochannel 1",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x87",
	+ "EventName": "UNC_M_WPQ_OCCUPANCY_SCH1_PCH1",
	+ "PerPkg": "1",
	+ "Unit": "IMC"
	+ }
	+]
	\ No newline at end of file
	diff --git a/lib/libpmc/pmu-events/arch/x86/graniterapids/uncore-power.json b/lib/libpmc/pmu-events/arch/x86/graniterapids/uncore-power.json
	new file mode 100644
	--- /dev/null
	+++ b/lib/libpmc/pmu-events/arch/x86/graniterapids/uncore-power.json
	@@ -0,0 +1,109 @@
	+[
	+ {
	+ "BriefDescription": "PCU Clockticks",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x01",
	+ "EventName": "UNC_P_CLOCKTICKS",
	+ "PerPkg": "1",
	+ "PublicDescription": "PCU Clockticks: The PCU runs off a fixed 1 GHz clock. This event counts the number of pclk cycles measured while the counter was enabled. The pclk, like the Memory Controller's dclk, counts at a constant rate making it a good measure of actual wall time.",
	+ "Unit": "PCU"
	+ },
	+ {
	+ "BriefDescription": "Thermal Strongest Upper Limit Cycles",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x04",
	+ "EventName": "UNC_P_FREQ_MAX_LIMIT_THERMAL_CYCLES",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PublicDescription": "Thermal Strongest Upper Limit Cycles : Number of cycles any frequency is reduced due to a thermal limit. Count only if throttling is occurring.",
	+ "Unit": "PCU"
	+ },
	+ {
	+ "BriefDescription": "Power Strongest Upper Limit Cycles",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x05",
	+ "EventName": "UNC_P_FREQ_MAX_POWER_CYCLES",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PublicDescription": "Power Strongest Upper Limit Cycles : Counts the number of cycles when power is the upper limit on frequency.",
	+ "Unit": "PCU"
	+ },
	+ {
	+ "BriefDescription": "Cycles spent changing Frequency",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x74",
	+ "EventName": "UNC_P_FREQ_TRANS_CYCLES",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PublicDescription": "Cycles spent changing Frequency : Counts the number of cycles when the system is changing frequency. This can not be filtered by thread ID. One can also use it with the occupancy counter that monitors number of threads in C0 to estimate the performance impact that frequency transitions had on the system.",
	+ "Unit": "PCU"
	+ },
	+ {
	+ "BriefDescription": "Package C State Residency - C2E",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x2b",
	+ "EventName": "UNC_P_PKG_RESIDENCY_C2E_CYCLES",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PublicDescription": "Package C State Residency - C2E : Counts the number of cycles when the package was in C2E. This event can be used in conjunction with edge detect to count C2E entrances (or exits using invert). Residency events do not include transition times.",
	+ "Unit": "PCU"
	+ },
	+ {
	+ "BriefDescription": "Package C State Residency - C6",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x2d",
	+ "EventName": "UNC_P_PKG_RESIDENCY_C6_CYCLES",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PublicDescription": "Package C State Residency - C6 : Counts the number of cycles when the package was in C6. This event can be used in conjunction with edge detect to count C6 entrances (or exits using invert). Residency events do not include transition times.",
	+ "Unit": "PCU"
	+ },
	+ {
	+ "BriefDescription": "Number of cores in C0",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x35",
	+ "EventName": "UNC_P_POWER_STATE_OCCUPANCY_CORES_C0",
	+ "PerPkg": "1",
	+ "PublicDescription": "Number of cores in C0 : This is an occupancy event that tracks the number of cores that are in the chosen C-State. It can be used by itself to get the average number of cores in that C-state with thresholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.",
	+ "Unit": "PCU"
	+ },
	+ {
	+ "BriefDescription": "Number of cores in C3",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x36",
	+ "EventName": "UNC_P_POWER_STATE_OCCUPANCY_CORES_C3",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PublicDescription": "Number of cores in C3 : This is an occupancy event that tracks the number of cores that are in the chosen C-State. It can be used by itself to get the average number of cores in that C-state with thresholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.",
	+ "Unit": "PCU"
	+ },
	+ {
	+ "BriefDescription": "Number of cores in C6",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x37",
	+ "EventName": "UNC_P_POWER_STATE_OCCUPANCY_CORES_C6",
	+ "PerPkg": "1",
	+ "PublicDescription": "Number of cores in C6 : This is an occupancy event that tracks the number of cores that are in the chosen C-State. It can be used by itself to get the average number of cores in that C-state with thresholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.",
	+ "Unit": "PCU"
	+ },
	+ {
	+ "BriefDescription": "External Prochot",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x0a",
	+ "EventName": "UNC_P_PROCHOT_EXTERNAL_CYCLES",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PublicDescription": "External Prochot : Counts the number of cycles that we are in external PROCHOT mode. This mode is triggered when a sensor off the die determines that something off-die (like DRAM) is too hot and must throttle to avoid damaging the chip.",
	+ "Unit": "PCU"
	+ },
	+ {
	+ "BriefDescription": "Internal Prochot",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x09",
	+ "EventName": "UNC_P_PROCHOT_INTERNAL_CYCLES",
	+ "Experimental": "1",
	+ "PerPkg": "1",
	+ "PublicDescription": "Internal Prochot : Counts the number of cycles that we are in Internal PROCHOT mode. This mode is triggered when a sensor on the die determines that we are too hot and must throttle to avoid damaging the chip.",
	+ "Unit": "PCU"
	+ }
	+]
	\ No newline at end of file
	diff --git a/lib/libpmc/pmu-events/arch/x86/graniterapids/virtual-memory.json b/lib/libpmc/pmu-events/arch/x86/graniterapids/virtual-memory.json
	new file mode 100644
	--- /dev/null
	+++ b/lib/libpmc/pmu-events/arch/x86/graniterapids/virtual-memory.json
	@@ -0,0 +1,185 @@
	+[
	+ {
	+ "BriefDescription": "Loads that miss the DTLB and hit the STLB.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x12",
	+ "EventName": "DTLB_LOAD_MISSES.STLB_HIT",
	+ "PublicDescription": "Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB).",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x20"
	+ },
	+ {
	+ "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a demand load.",
	+ "Counter": "0,1,2,3",
	+ "CounterMask": "1",
	+ "EventCode": "0x12",
	+ "EventName": "DTLB_LOAD_MISSES.WALK_ACTIVE",
	+ "PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a demand load.",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x10"
	+ },
	+ {
	+ "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page sizes)",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x12",
	+ "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
	+ "PublicDescription": "Counts completed page walks (all page sizes) caused by demand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0xe"
	+ },
	+ {
	+ "BriefDescription": "Page walks completed due to a demand data load to a 1G page.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x12",
	+ "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G",
	+ "PublicDescription": "Counts completed page walks (1G sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x8"
	+ },
	+ {
	+ "BriefDescription": "Page walks completed due to a demand data load to a 2M/4M page.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x12",
	+ "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M",
	+ "PublicDescription": "Counts completed page walks (2M/4M sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x4"
	+ },
	+ {
	+ "BriefDescription": "Page walks completed due to a demand data load to a 4K page.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x12",
	+ "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K",
	+ "PublicDescription": "Counts completed page walks (4K sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x2"
	+ },
	+ {
	+ "BriefDescription": "Number of page walks outstanding for a demand load in the PMH each cycle.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x12",
	+ "EventName": "DTLB_LOAD_MISSES.WALK_PENDING",
	+ "PublicDescription": "Counts the number of page walks outstanding for a demand load in the PMH (Page Miss Handler) each cycle.",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x10"
	+ },
	+ {
	+ "BriefDescription": "Stores that miss the DTLB and hit the STLB.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x13",
	+ "EventName": "DTLB_STORE_MISSES.STLB_HIT",
	+ "PublicDescription": "Counts stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB).",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x20"
	+ },
	+ {
	+ "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a store.",
	+ "Counter": "0,1,2,3",
	+ "CounterMask": "1",
	+ "EventCode": "0x13",
	+ "EventName": "DTLB_STORE_MISSES.WALK_ACTIVE",
	+ "PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a store.",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x10"
	+ },
	+ {
	+ "BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page sizes)",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x13",
	+ "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
	+ "PublicDescription": "Counts completed page walks (all page sizes) caused by demand data stores. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0xe"
	+ },
	+ {
	+ "BriefDescription": "Page walks completed due to a demand data store to a 1G page.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x13",
	+ "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G",
	+ "PublicDescription": "Counts completed page walks (1G sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x8"
	+ },
	+ {
	+ "BriefDescription": "Page walks completed due to a demand data store to a 2M/4M page.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x13",
	+ "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M",
	+ "PublicDescription": "Counts completed page walks (2M/4M sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x4"
	+ },
	+ {
	+ "BriefDescription": "Page walks completed due to a demand data store to a 4K page.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x13",
	+ "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K",
	+ "PublicDescription": "Counts completed page walks (4K sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x2"
	+ },
	+ {
	+ "BriefDescription": "Number of page walks outstanding for a store in the PMH each cycle.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x13",
	+ "EventName": "DTLB_STORE_MISSES.WALK_PENDING",
	+ "PublicDescription": "Counts the number of page walks outstanding for a store in the PMH (Page Miss Handler) each cycle.",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x10"
	+ },
	+ {
	+ "BriefDescription": "Instruction fetch requests that miss the ITLB and hit the STLB.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x11",
	+ "EventName": "ITLB_MISSES.STLB_HIT",
	+ "PublicDescription": "Counts instruction fetch requests that miss the ITLB (Instruction TLB) and hit the STLB (Second-level TLB).",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x20"
	+ },
	+ {
	+ "BriefDescription": "Cycles when at least one PMH is busy with a page walk for code (instruction fetch) request.",
	+ "Counter": "0,1,2,3",
	+ "CounterMask": "1",
	+ "EventCode": "0x11",
	+ "EventName": "ITLB_MISSES.WALK_ACTIVE",
	+ "PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a code (instruction fetch) request.",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x10"
	+ },
	+ {
	+ "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (All page sizes)",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x11",
	+ "EventName": "ITLB_MISSES.WALK_COMPLETED",
	+ "PublicDescription": "Counts completed page walks (all page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0xe"
	+ },
	+ {
	+ "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x11",
	+ "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M",
	+ "PublicDescription": "Counts completed page walks (2M/4M page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x4"
	+ },
	+ {
	+ "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x11",
	+ "EventName": "ITLB_MISSES.WALK_COMPLETED_4K",
	+ "PublicDescription": "Counts completed page walks (4K page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x2"
	+ },
	+ {
	+ "BriefDescription": "Number of page walks outstanding for an outstanding code request in the PMH each cycle.",
	+ "Counter": "0,1,2,3",
	+ "EventCode": "0x11",
	+ "EventName": "ITLB_MISSES.WALK_PENDING",
	+ "PublicDescription": "Counts the number of page walks outstanding for an outstanding code (instruction fetch) request in the PMH (Page Miss Handler) each cycle.",
	+ "SampleAfterValue": "100003",
	+ "UMask": "0x10"
	+ }
	+]
	\ No newline at end of file
	diff --git a/lib/libpmc/pmu-events/arch/x86/mapfile.csv b/lib/libpmc/pmu-events/arch/x86/mapfile.csv
	--- a/lib/libpmc/pmu-events/arch/x86/mapfile.csv
	+++ b/lib/libpmc/pmu-events/arch/x86/mapfile.csv
	@@ -11,6 +11,7 @@
	GenuineIntel-6-5C,v8,goldmont,core
	GenuineIntel-6-5F,v8,goldmont,core
	GenuineIntel-6-7A,v1,goldmontplus,core
	+GenuineIntel-6-A[DE],v1,graniterapids,core
	GenuineIntel-6-CF,v1,emeraldrapids,core
	GenuineIntel-6-3C,v24,haswell,core
	GenuineIntel-6-45,v24,haswell,core
	diff --git a/sys/dev/hwpmc/hwpmc_intel.c b/sys/dev/hwpmc/hwpmc_intel.c
	--- a/sys/dev/hwpmc/hwpmc_intel.c
	+++ b/sys/dev/hwpmc/hwpmc_intel.c
	@@ -247,6 +247,11 @@
	cputype = PMC_CPU_INTEL_ATOM_TREMONT;
	nclasses = 3;
	break;
	+ case 0xAD:
	+ case 0xAE:
	+ cputype = PMC_CPU_INTEL_GRANITE_RAPIDS;
	+ nclasses = 3;
	+ break;
	case 0xBE:
	cputype = PMC_CPU_INTEL_ALDERLAKEN;
	nclasses = 3;
	diff --git a/sys/sys/pmc.h b/sys/sys/pmc.h
	--- a/sys/sys/pmc.h
	+++ b/sys/sys/pmc.h
	@@ -109,6 +109,7 @@
	__PMC_CPU(INTEL_ATOM_TREMONT, 0x9F, "Intel Atom Tremont") \
	__PMC_CPU(INTEL_EMERALD_RAPIDS, 0xA0, "Intel Emerald Rapids") \
	__PMC_CPU(INTEL_ALDERLAKEN, 0xA1, "Intel AlderlakeN") \
	+ __PMC_CPU(INTEL_GRANITE_RAPIDS, 0xA2, "Intel Granite Rapids") \
	__PMC_CPU(INTEL_XSCALE, 0x100, "Intel XScale") \
	__PMC_CPU(PPC_7450, 0x300, "PowerPC MPC7450") \
	__PMC_CPU(PPC_E500, 0x340, "PowerPC e500 Core") \

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