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diff --git a/sys/arm64/arm64/debug_monitor.c b/sys/arm64/arm64/debug_monitor.c
--- a/sys/arm64/arm64/debug_monitor.c
+++ b/sys/arm64/arm64/debug_monitor.c
@@ -634,8 +634,8 @@
/* Find out many breakpoints and watchpoints we can use */
aa64dfr0 = READ_SPECIALREG(id_aa64dfr0_el1);
- dbg_watchpoint_num = ID_AA64DFR0_WRPs_VAL(aa64dfr0);
- dbg_breakpoint_num = ID_AA64DFR0_BRPs_VAL(aa64dfr0);
+ dbg_watchpoint_num = ID_AA64DFR0_WRPs_NUM(aa64dfr0);
+ dbg_breakpoint_num = ID_AA64DFR0_BRPs_NUM(aa64dfr0);
if (bootverbose && PCPU_GET(cpuid) == 0) {
printf("%d watchpoints and %d breakpoints supported\n",
diff --git a/sys/arm64/arm64/exec_machdep.c b/sys/arm64/arm64/exec_machdep.c
--- a/sys/arm64/arm64/exec_machdep.c
+++ b/sys/arm64/arm64/exec_machdep.c
@@ -214,8 +214,8 @@
} else {
debug_ver = ID_AA64DFR0_DebugVer_VAL(dfr0) >>
ID_AA64DFR0_DebugVer_SHIFT;
- nbkpts = ID_AA64DFR0_BRPs_VAL(dfr0) >> ID_AA64DFR0_BRPs_SHIFT;
- nwtpts = ID_AA64DFR0_WRPs_VAL(dfr0) >> ID_AA64DFR0_WRPs_SHIFT;
+ nbkpts = ID_AA64DFR0_BRPs_NUM(dfr0);
+ nwtpts = ID_AA64DFR0_WRPs_NUM(dfr0);
}
/*
diff --git a/sys/arm64/include/armreg.h b/sys/arm64/include/armreg.h
--- a/sys/arm64/include/armreg.h
+++ b/sys/arm64/include/armreg.h
@@ -911,7 +911,7 @@
#define ID_AA64DFR0_BRPs_SHIFT 12
#define ID_AA64DFR0_BRPs_WIDTH 4
#define ID_AA64DFR0_BRPs_MASK (UL(0xf) << ID_AA64DFR0_BRPs_SHIFT)
-#define ID_AA64DFR0_BRPs_VAL(x) \
+#define ID_AA64DFR0_BRPs_NUM(x) \
((((x) >> ID_AA64DFR0_BRPs_SHIFT) & 0xf) + 1)
#define ID_AA64DFR0_PMSS_SHIFT 16
#define ID_AA64DFR0_PMSS_WIDTH 4
@@ -922,12 +922,12 @@
#define ID_AA64DFR0_WRPs_SHIFT 20
#define ID_AA64DFR0_WRPs_WIDTH 4
#define ID_AA64DFR0_WRPs_MASK (UL(0xf) << ID_AA64DFR0_WRPs_SHIFT)
-#define ID_AA64DFR0_WRPs_VAL(x) \
+#define ID_AA64DFR0_WRPs_NUM(x) \
((((x) >> ID_AA64DFR0_WRPs_SHIFT) & 0xf) + 1)
#define ID_AA64DFR0_CTX_CMPs_SHIFT 28
#define ID_AA64DFR0_CTX_CMPs_WIDTH 4
#define ID_AA64DFR0_CTX_CMPs_MASK (UL(0xf) << ID_AA64DFR0_CTX_CMPs_SHIFT)
-#define ID_AA64DFR0_CTX_CMPs_VAL(x) \
+#define ID_AA64DFR0_CTX_CMPs_NUM(x) \
((((x) >> ID_AA64DFR0_CTX_CMPs_SHIFT) & 0xf) + 1)
#define ID_AA64DFR0_PMSVer_SHIFT 32
#define ID_AA64DFR0_PMSVer_WIDTH 4
diff --git a/sys/arm64/vmm/vmm_hyp.c b/sys/arm64/vmm/vmm_hyp.c
--- a/sys/arm64/vmm/vmm_hyp.c
+++ b/sys/arm64/vmm/vmm_hyp.c
@@ -48,7 +48,7 @@
READ_SPECIALREG(dbgclaimset_el1));
dfr0 = READ_SPECIALREG(id_aa64dfr0_el1);
- switch (ID_AA64DFR0_BRPs_VAL(dfr0) - 1) {
+ switch (ID_AA64DFR0_BRPs_NUM(dfr0) - 1) {
#define STORE_DBG_BRP(x) \
case x: \
hypctx_write_sys_reg(hypctx, DBGBCR_EL1(x), \
@@ -75,7 +75,7 @@
#undef STORE_DBG_BRP
}
- switch (ID_AA64DFR0_WRPs_VAL(dfr0) - 1) {
+ switch (ID_AA64DFR0_WRPs_NUM(dfr0) - 1) {
#define STORE_DBG_WRP(x) \
case x: \
hypctx_write_sys_reg(hypctx, DBGWCR_EL1(x), \
@@ -529,7 +529,7 @@
hypctx_read_sys_reg(hypctx, DBGCLAIMSET_EL1));
dfr0 = READ_SPECIALREG(id_aa64dfr0_el1);
- switch (ID_AA64DFR0_BRPs_VAL(dfr0) - 1) {
+ switch (ID_AA64DFR0_BRPs_NUM(dfr0) - 1) {
#define LOAD_DBG_BRP(x) \
case x: \
WRITE_SPECIALREG(dbgbcr ## x ## _el1, \
@@ -556,7 +556,7 @@
#undef LOAD_DBG_BRP
}
- switch (ID_AA64DFR0_WRPs_VAL(dfr0) - 1) {
+ switch (ID_AA64DFR0_WRPs_NUM(dfr0) - 1) {
#define LOAD_DBG_WRP(x) \
case x: \
WRITE_SPECIALREG(dbgwcr ## x ## _el1, \

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