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D60219.diff
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diff --git a/usr.sbin/bhyve/pci_e82545.c b/usr.sbin/bhyve/pci_e82545.c
--- a/usr.sbin/bhyve/pci_e82545.c
+++ b/usr.sbin/bhyve/pci_e82545.c
@@ -122,6 +122,8 @@
#define E82545_NVM_EEPROM_SIZE 64 /* 64 * 16-bit values == 128K */
+#define E82545_NUNICAST 16 /* receive address registers */
+
#define E1000_ICR_SRPD 0x00010000
/* This is an arbitrary number. There is no hard limit on the chip. */
@@ -295,7 +297,7 @@
uint32_t esc_TADV; /* x382C intr absolute delay */
/* L2 frame acceptance */
- struct eth_uni esc_uni[16]; /* 16 x unicast MAC addresses */
+ struct eth_uni esc_uni[E82545_NUNICAST]; /* unicast MAC addresses */
uint32_t esc_fmcast[128]; /* Multicast filter bit-match */
uint32_t esc_fvlan[128]; /* VLAN 4096-bit filter */
@@ -1570,7 +1572,7 @@
int idx;
idx = reg >> 1;
- assert(idx < 15);
+ assert(idx < E82545_NUNICAST);
eu = &sc->esc_uni[idx];
@@ -1597,7 +1599,7 @@
int idx;
idx = reg >> 1;
- assert(idx < 15);
+ assert(idx < E82545_NUNICAST);
eu = &sc->esc_uni[idx];
@@ -2264,7 +2266,7 @@
ETHER_ADDR_LEN);
} else {
/* Clear RAH valid bits */
- for (i = 0; i < 16; i++)
+ for (i = 0; i < E82545_NUNICAST; i++)
sc->esc_uni[i].eu_valid = 0;
}
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D60219: bhyve: e82545: allow access to the last receive address register
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