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Index: head/sys/arm/arm/cpufunc_asm_sheeva.S
===================================================================
--- head/sys/arm/arm/cpufunc_asm_sheeva.S
+++ head/sys/arm/arm/cpufunc_asm_sheeva.S
@@ -29,6 +29,7 @@
* SUCH DAMAGE.
*/
+#include <machine/armreg.h>
#include <machine/asm.h>
__FBSDID("$FreeBSD$");
@@ -42,7 +43,7 @@
ENTRY(sheeva_setttb)
/* Disable irqs */
mrs r2, cpsr
- orr r3, r2, #I32_bit | F32_bit
+ orr r3, r2, #PSR_I | PSR_F
msr cpsr_c, r3
mov r1, #0
@@ -87,7 +88,7 @@
add r3, r0, ip
sub r2, r3, #1
/* Disable irqs */
- orr r3, lr, #I32_bit | F32_bit
+ orr r3, lr, #PSR_I | PSR_F
msr cpsr_c, r3
mcr p15, 5, r0, c15, c15, 0 /* Clean and inv zone start address */
mcr p15, 5, r2, c15, c15, 1 /* Clean and inv zone end address */
@@ -130,7 +131,7 @@
add r3, r0, ip
sub r2, r3, #1
/* Disable irqs */
- orr r3, lr, #I32_bit | F32_bit
+ orr r3, lr, #PSR_I | PSR_F
msr cpsr_c, r3
mcr p15, 5, r0, c15, c15, 0 /* Clean and inv zone start address */
mcr p15, 5, r2, c15, c15, 1 /* Clean and inv zone end address */
@@ -182,7 +183,7 @@
add r3, r0, ip
sub r2, r3, #1
/* Disable irqs */
- orr r3, lr, #I32_bit | F32_bit
+ orr r3, lr, #PSR_I | PSR_F
msr cpsr_c, r3
mcr p15, 5, r0, c15, c14, 0 /* Inv zone start address */
mcr p15, 5, r2, c15, c14, 1 /* Inv zone end address */
@@ -225,7 +226,7 @@
add r3, r0, ip
sub r2, r3, #1
/* Disable irqs */
- orr r3, lr, #I32_bit | F32_bit
+ orr r3, lr, #PSR_I | PSR_F
msr cpsr_c, r3
mcr p15, 5, r0, c15, c13, 0 /* Clean zone start address */
mcr p15, 5, r2, c15, c13, 1 /* Clean zone end address */
@@ -268,7 +269,7 @@
add r3, r0, ip
sub r2, r3, #1
/* Disable irqs */
- orr r3, lr, #I32_bit | F32_bit
+ orr r3, lr, #PSR_I | PSR_F
msr cpsr_c, r3
mcr p15, 1, r0, c15, c9, 4 /* Clean L2 zone start address */
mcr p15, 1, r2, c15, c9, 5 /* Clean L2 zone end address */
@@ -313,7 +314,7 @@
add r3, r0, ip
sub r2, r3, #1
/* Disable irqs */
- orr r3, lr, #I32_bit | F32_bit
+ orr r3, lr, #PSR_I | PSR_F
msr cpsr_c, r3
mcr p15, 1, r0, c15, c11, 4 /* Inv L2 zone start address */
mcr p15, 1, r2, c15, c11, 5 /* Inv L2 zone end address */
@@ -356,7 +357,7 @@
add r3, r0, ip
sub r2, r3, #1
/* Disable irqs */
- orr r3, lr, #I32_bit | F32_bit
+ orr r3, lr, #PSR_I | PSR_F
msr cpsr_c, r3
mcr p15, 1, r0, c15, c9, 4 /* Clean L2 zone start address */
mcr p15, 1, r2, c15, c9, 5 /* Clean L2 zone end address */
@@ -379,7 +380,7 @@
ENTRY(sheeva_l2cache_wbinv_all)
/* Disable irqs */
mrs r1, cpsr
- orr r2, r1, #I32_bit | F32_bit
+ orr r2, r1, #PSR_I | PSR_F
msr cpsr_c, r2
mov r0, #0
Index: head/sys/arm/arm/cpufunc_asm_xscale.S
===================================================================
--- head/sys/arm/arm/cpufunc_asm_xscale.S
+++ head/sys/arm/arm/cpufunc_asm_xscale.S
@@ -71,7 +71,7 @@
*
* XScale assembly functions for CPU / MMU / TLB specific operations
*/
-
+#include <machine/armreg.h>
#include <machine/asm.h>
__FBSDID("$FreeBSD$");
@@ -135,7 +135,7 @@
ENTRY(xscale_setttb)
#ifdef CACHE_CLEAN_BLOCK_INTR
mrs r3, cpsr
- orr r1, r3, #(I32_bit | F32_bit)
+ orr r1, r3, #(PSR_I | PSR_F)
msr cpsr_fsxc, r1
#else
ldr r3, .Lblock_userspace_access
@@ -267,7 +267,7 @@
#ifdef CACHE_CLEAN_BLOCK_INTR
#define XSCALE_CACHE_CLEAN_BLOCK \
mrs r3, cpsr ; \
- orr r0, r3, #(I32_bit | F32_bit) ; \
+ orr r0, r3, #(PSR_I | PSR_F) ; \
msr cpsr_fsxc, r0
#define XSCALE_CACHE_CLEAN_UNBLOCK \
Index: head/sys/arm/arm/cpufunc_asm_xscale_c3.S
===================================================================
--- head/sys/arm/arm/cpufunc_asm_xscale_c3.S
+++ head/sys/arm/arm/cpufunc_asm_xscale_c3.S
@@ -73,6 +73,7 @@
* XScale core 3 assembly functions for CPU / MMU / TLB specific operations
*/
+#include <machine/armreg.h>
#include <machine/asm.h>
__FBSDID("$FreeBSD$");
@@ -122,7 +123,7 @@
#define XSCALE_CACHE_CLEAN_BLOCK \
stmfd sp!, {r4} ; \
mrs r4, cpsr ; \
- orr r0, r4, #(I32_bit | F32_bit) ; \
+ orr r0, r4, #(PSR_I | PSR_F) ; \
msr cpsr_fsxc, r0
#define XSCALE_CACHE_CLEAN_UNBLOCK \
@@ -350,7 +351,7 @@
ENTRY(xscalec3_setttb)
#ifdef CACHE_CLEAN_BLOCK_INTR
mrs r3, cpsr
- orr r1, r3, #(I32_bit | F32_bit)
+ orr r1, r3, #(PSR_I | PSR_F)
msr cpsr_fsxc, r1
#else
ldr r3, .Lblock_userspace_access
Index: head/sys/arm/arm/exception.S
===================================================================
--- head/sys/arm/arm/exception.S
+++ head/sys/arm/arm/exception.S
@@ -244,12 +244,12 @@
#define DO_AST \
ldr r0, [sp] /* Get the SPSR from stack */ ;\
mrs r4, cpsr /* save CPSR */ ;\
- orr r1, r4, #(I32_bit|F32_bit) ;\
+ orr r1, r4, #(PSR_I|PSR_F) ;\
msr cpsr_c, r1 /* Disable interrupts */ ;\
and r0, r0, #(PSR_MODE) /* Returning to USR mode? */ ;\
teq r0, #(PSR_USR32_MODE) ;\
bne 2f /* Nope, get out now */ ;\
- bic r4, r4, #(I32_bit|F32_bit) ;\
+ bic r4, r4, #(PSR_I|PSR_F) ;\
1: GET_CURTHREAD_PTR(r5) ;\
ldr r1, [r5, #(TD_FLAGS)] ;\
and r1, r1, #(TDF_ASTPENDING|TDF_NEEDRESCHED) ;\
@@ -258,7 +258,7 @@
msr cpsr_c, r4 /* Restore interrupts */ ;\
mov r0, sp ;\
bl _C_LABEL(ast) /* ast(frame) */ ;\
- orr r0, r4, #(I32_bit|F32_bit) ;\
+ orr r0, r4, #(PSR_I|PSR_F) ;\
msr cpsr_c, r0 ;\
b 1b ;\
2:
@@ -382,7 +382,7 @@
*/
ASENTRY_NP(fiq_entry)
mrs r8, cpsr /* FIQ handling isn't supported, */
- bic r8, #(F32_bit) /* just disable FIQ and return. */
+ bic r8, #(PSR_F) /* just disable FIQ and return. */
msr cpsr_c, r8 /* The r8 we trash here is the */
subs pc, lr, #4 /* banked FIQ-mode r8. */
END(fiq_entry)
Index: head/sys/arm/arm/fiq.c
===================================================================
--- head/sys/arm/arm/fiq.c
+++ head/sys/arm/arm/fiq.c
@@ -41,6 +41,7 @@
#include <sys/param.h>
#include <sys/systm.h>
+#include <machine/armreg.h>
#include <machine/cpufunc.h>
#include <machine/fiq.h>
#include <vm/vm.h>
@@ -54,9 +55,6 @@
extern char *fiq_nullhandler_code;
extern uint32_t fiq_nullhandler_size;
-#define IRQ_BIT I32_bit
-#define FIQ_BIT F32_bit
-
/*
* fiq_installhandler:
*
@@ -102,7 +100,7 @@
if (fh->fh_size > 0x100)
return (EFBIG);
- oldirqstate = disable_interrupts(FIQ_BIT);
+ oldirqstate = disable_interrupts(PSR_F);
if ((ofh = TAILQ_FIRST(&fiqhandler_stack)) != NULL) {
if ((ofh->fh_flags & FH_CANPUSH) == 0) {
@@ -125,7 +123,7 @@
fiq_installhandler(fh->fh_func, fh->fh_size);
/* Make sure FIQs are enabled when we return. */
- oldirqstate &= ~FIQ_BIT;
+ oldirqstate &= ~PSR_F;
out:
restore_interrupts(oldirqstate);
@@ -143,7 +141,7 @@
u_int oldirqstate;
struct fiqhandler *ofh;
- oldirqstate = disable_interrupts(FIQ_BIT);
+ oldirqstate = disable_interrupts(PSR_F);
/*
* If we are the currently active FIQ handler, then we
@@ -167,7 +165,7 @@
fiq_installhandler(fiq_nullhandler_code, fiq_nullhandler_size);
/* Make sure FIQs are disabled when we return. */
- oldirqstate |= FIQ_BIT;
+ oldirqstate |= PSR_F;
}
restore_interrupts(oldirqstate);
Index: head/sys/arm/arm/locore.S
===================================================================
--- head/sys/arm/arm/locore.S
+++ head/sys/arm/arm/locore.S
@@ -88,7 +88,7 @@
/* Make sure interrupts are disabled. */
mrs r7, cpsr
- orr r7, r7, #(I32_bit|F32_bit)
+ orr r7, r7, #(PSR_I | PSR_F)
msr cpsr_c, r7
#if defined (FLASHADDR) && defined(LOADERRAMADDR)
@@ -386,7 +386,7 @@
/* Make sure interrupts are disabled. */
mrs r7, cpsr
- orr r7, r7, #(I32_bit|F32_bit)
+ orr r7, r7, #(PSR_I | PSR_F)
msr cpsr_c, r7
/* Disable MMU. It should be disabled already, but make sure. */
@@ -466,7 +466,7 @@
mrs r2, cpsr
bic r2, r2, #(PSR_MODE)
orr r2, r2, #(PSR_SVC32_MODE)
- orr r2, r2, #(I32_bit | F32_bit)
+ orr r2, r2, #(PSR_I | PSR_F)
msr cpsr_fsxc, r2
ldr r4, .Lcpu_reset_address
Index: head/sys/arm/arm/machdep.c
===================================================================
--- head/sys/arm/arm/machdep.c
+++ head/sys/arm/arm/machdep.c
@@ -620,7 +620,7 @@
td = curthread;
if (td->td_md.md_spinlock_count == 0) {
- cspr = disable_interrupts(I32_bit | F32_bit);
+ cspr = disable_interrupts(PSR_I | PSR_F);
td->td_md.md_spinlock_count = 1;
td->td_md.md_saved_cspr = cspr;
} else
@@ -747,7 +747,7 @@
*/
spsr = uc.uc_mcontext.__gregs[_REG_CPSR];
if ((spsr & PSR_MODE) != PSR_USR32_MODE ||
- (spsr & (I32_bit | F32_bit)) != 0)
+ (spsr & (PSR_I | PSR_F)) != 0)
return (EINVAL);
/* Restore register context. */
set_mcontext(td, &uc.uc_mcontext);
Index: head/sys/arm/arm/mp_machdep.c
===================================================================
--- head/sys/arm/arm/mp_machdep.c
+++ head/sys/arm/arm/mp_machdep.c
@@ -43,6 +43,7 @@
#include <vm/vm_kern.h>
#include <vm/pmap.h>
+#include <machine/armreg.h>
#include <machine/cpu.h>
#include <machine/cpufunc.h>
#include <machine/smp.h>
@@ -236,7 +237,7 @@
for (int i = start; i <= end; i++)
arm_unmask_irq(i);
- enable_interrupts(I32_bit);
+ enable_interrupts(PSR_I);
loop_counter = 0;
while (smp_started == 0) {
Index: head/sys/arm/arm/trap.c
===================================================================
--- head/sys/arm/arm/trap.c
+++ head/sys/arm/arm/trap.c
@@ -241,10 +241,10 @@
pcb = td->td_pcb;
/* Re-enable interrupts if they were enabled previously */
if (td->td_md.md_spinlock_count == 0) {
- if (__predict_true(tf->tf_spsr & I32_bit) == 0)
- enable_interrupts(I32_bit);
- if (__predict_true(tf->tf_spsr & F32_bit) == 0)
- enable_interrupts(F32_bit);
+ if (__predict_true(tf->tf_spsr & PSR_I) == 0)
+ enable_interrupts(PSR_I);
+ if (__predict_true(tf->tf_spsr & PSR_F) == 0)
+ enable_interrupts(PSR_F);
}
@@ -451,7 +451,7 @@
mode = TRAP_USERMODE(tf) ? "user" : "kernel";
- disable_interrupts(I32_bit|F32_bit);
+ disable_interrupts(PSR_I|PSR_F);
if (td != NULL) {
printf("Fatal %s mode data abort: '%s'\n", mode,
data_aborts[fsr & FAULT_TYPE_MASK].desc);
@@ -661,10 +661,10 @@
}
fault_pc = tf->tf_pc;
if (td->td_md.md_spinlock_count == 0) {
- if (__predict_true(tf->tf_spsr & I32_bit) == 0)
- enable_interrupts(I32_bit);
- if (__predict_true(tf->tf_spsr & F32_bit) == 0)
- enable_interrupts(F32_bit);
+ if (__predict_true(tf->tf_spsr & PSR_I) == 0)
+ enable_interrupts(PSR_I);
+ if (__predict_true(tf->tf_spsr & PSR_F) == 0)
+ enable_interrupts(PSR_F);
}
/* Prefetch aborts cannot happen in kernel mode */
@@ -869,10 +869,10 @@
* be safe to enable them, but check anyway.
*/
if (td->td_md.md_spinlock_count == 0) {
- if (__predict_true(frame->tf_spsr & I32_bit) == 0)
- enable_interrupts(I32_bit);
- if (__predict_true(frame->tf_spsr & F32_bit) == 0)
- enable_interrupts(F32_bit);
+ if (__predict_true(frame->tf_spsr & PSR_I) == 0)
+ enable_interrupts(PSR_I);
+ if (__predict_true(frame->tf_spsr & PSR_F) == 0)
+ enable_interrupts(PSR_F);
}
syscall(td, frame);
Index: head/sys/arm/arm/undefined.c
===================================================================
--- head/sys/arm/arm/undefined.c
+++ head/sys/arm/arm/undefined.c
@@ -69,6 +69,7 @@
#include <vm/vm.h>
#include <vm/vm_extern.h>
+#include <machine/armreg.h>
#include <machine/asm.h>
#include <machine/cpu.h>
#include <machine/frame.h>
@@ -180,8 +181,10 @@
ksiginfo_t ksi;
/* Enable interrupts if they were enabled before the exception. */
- if (!(frame->tf_spsr & I32_bit))
- enable_interrupts(I32_bit|F32_bit);
+ if (__predict_true(frame->tf_spsr & PSR_I) == 0)
+ enable_interrupts(PSR_I);
+ if (__predict_true(frame->tf_spsr & PSR_F) == 0)
+ enable_interrupts(PSR_F);
PCPU_INC(cnt.v_trap);
Index: head/sys/arm/arm/vm_machdep.c
===================================================================
--- head/sys/arm/arm/vm_machdep.c
+++ head/sys/arm/arm/vm_machdep.c
@@ -120,7 +120,7 @@
sf->sf_r4 = (u_int)fork_return;
sf->sf_r5 = (u_int)td2;
sf->sf_pc = (u_int)fork_trampoline;
- tf->tf_spsr &= ~PSR_C_bit;
+ tf->tf_spsr &= ~PSR_C;
tf->tf_r0 = 0;
tf->tf_r1 = 0;
pcb2->un_32.pcb32_sp = (u_int)sf;
@@ -190,7 +190,7 @@
frame->tf_r0 = td->td_retval[0];
frame->tf_r1 = td->td_retval[1];
}
- frame->tf_spsr &= ~PSR_C_bit; /* carry bit */
+ frame->tf_spsr &= ~PSR_C; /* carry bit */
break;
case ERESTART:
/*
@@ -203,7 +203,7 @@
break;
default:
frame->tf_r0 = error;
- frame->tf_spsr |= PSR_C_bit; /* carry bit */
+ frame->tf_spsr |= PSR_C; /* carry bit */
break;
}
}
@@ -228,7 +228,7 @@
sf->sf_r4 = (u_int)fork_return;
sf->sf_r5 = (u_int)td;
sf->sf_pc = (u_int)fork_trampoline;
- tf->tf_spsr &= ~PSR_C_bit;
+ tf->tf_spsr &= ~PSR_C;
tf->tf_r0 = 0;
td->td_pcb->un_32.pcb32_sp = (u_int)sf;
KASSERT((td->td_pcb->un_32.pcb32_sp & 7) == 0,
Index: head/sys/arm/at91/at91.c
===================================================================
--- head/sys/arm/at91/at91.c
+++ head/sys/arm/at91/at91.c
@@ -42,6 +42,7 @@
#include <vm/vm_page.h>
#include <vm/vm_extern.h>
+#include <machine/armreg.h>
#define _ARM32_BUS_DMA_PRIVATE
#include <machine/bus.h>
#include <machine/devmap.h>
@@ -303,7 +304,7 @@
bus_generic_probe(dev);
bus_generic_attach(dev);
- enable_interrupts(I32_bit | F32_bit);
+ enable_interrupts(PSR_I | PSR_F);
return (0);
}
Index: head/sys/arm/at91/at91_aic.c
===================================================================
--- head/sys/arm/at91/at91_aic.c
+++ head/sys/arm/at91/at91_aic.c
@@ -36,6 +36,7 @@
#include <sys/systm.h>
#include <sys/rman.h>
+#include <machine/armreg.h>
#include <machine/bus.h>
#include <machine/cpu.h>
#include <machine/cpufunc.h>
@@ -149,7 +150,7 @@
/* Disable and clear all interrupts. */
WR4(sc, IC_IDCR, 0xffffffff);
WR4(sc, IC_ICCR, 0xffffffff);
- enable_interrupts(I32_bit | F32_bit);
+ enable_interrupts(PSR_I | PSR_F);
return (err);
}
Index: head/sys/arm/cavium/cns11xx/econa.c
===================================================================
--- head/sys/arm/cavium/cns11xx/econa.c
+++ head/sys/arm/cavium/cns11xx/econa.c
@@ -42,6 +42,7 @@
#include <vm/vm_extern.h>
#define _ARM32_BUS_DMA_PRIVATE
+#include <machine/armreg.h>
#include <machine/bus.h>
#include <machine/intr.h>
#include <machine/resource.h>
@@ -508,7 +509,7 @@
bus_generic_probe(dev);
bus_generic_attach(dev);
- enable_interrupts(I32_bit | F32_bit);
+ enable_interrupts(PSR_I | PSR_F);
return (0);
}
Index: head/sys/arm/include/armreg.h
===================================================================
--- head/sys/arm/include/armreg.h
+++ head/sys/arm/include/armreg.h
@@ -68,8 +68,6 @@
#define PSR_N 0x80000000 /* Negative bit */
#define PSR_FLAGS 0xf0000000 /* Flags mask. */
-#define PSR_C_bit PSR_C
-
/* The high-order byte is always the implementor */
#define CPU_ID_IMPLEMENTOR_MASK 0xff000000
#define CPU_ID_ARM_LTD 0x41000000 /* 'A' */
Index: head/sys/arm/include/asm.h
===================================================================
--- head/sys/arm/include/asm.h
+++ head/sys/arm/include/asm.h
@@ -43,9 +43,6 @@
#define _C_LABEL(x) x
#define _ASM_LABEL(x) x
-#define I32_bit (1 << 7) /* IRQ disable */
-#define F32_bit (1 << 6) /* FIQ disable */
-
#ifndef _ALIGN_TEXT
# define _ALIGN_TEXT .align 0
#endif
Index: head/sys/arm/include/atomic.h
===================================================================
--- head/sys/arm/include/atomic.h
+++ head/sys/arm/include/atomic.h
@@ -40,6 +40,7 @@
#define _MACHINE_ATOMIC_H_
#include <sys/types.h>
+#include <machine/armreg.h>
#ifndef _KERNEL
#include <machine/sysarch.h>
@@ -67,12 +68,7 @@
#define wmb() dmb()
#define rmb() dmb()
-#ifndef I32_bit
-#define I32_bit (1 << 7) /* IRQ disable */
-#endif
-#ifndef F32_bit
-#define F32_bit (1 << 6) /* FIQ disable */
-#endif
+
/*
* It would be nice to use _HAVE_ARMv6_INSTRUCTIONS from machine/asm.h
@@ -702,7 +698,7 @@
"orr %1, %0, %2;" \
"msr cpsr_fsxc, %1;" \
: "=r" (cpsr_save), "=r" (tmp) \
- : "I" (I32_bit | F32_bit) \
+ : "I" (PSR_I | PSR_F) \
: "cc" ); \
(expr); \
__asm __volatile( \
Index: head/sys/arm/s3c2xx0/s3c24x0.c
===================================================================
--- head/sys/arm/s3c2xx0/s3c24x0.c
+++ head/sys/arm/s3c2xx0/s3c24x0.c
@@ -43,6 +43,7 @@
#include <vm/vm.h>
#include <vm/pmap.h>
+#include <machine/armreg.h>
#include <machine/cpu.h>
#include <machine/bus.h>
@@ -638,7 +639,7 @@
void
cpu_reset(void)
{
- (void) disable_interrupts(I32_bit|F32_bit);
+ (void) disable_interrupts(PSR_I|PSR_F);
bus_space_write_4(&s3c2xx0_bs_tag, s3c2xx0_softc->sc_wdt_ioh, WDT_WTCON,
WTCON_ENABLE | WTCON_CLKSEL_16 | WTCON_ENRST);
Index: head/sys/arm/xscale/i80321/i80321_intr.h
===================================================================
--- head/sys/arm/xscale/i80321/i80321_intr.h
+++ head/sys/arm/xscale/i80321/i80321_intr.h
@@ -106,7 +106,7 @@
hwpend = (i80321_ipending & ICU_INT_HWMASK) & ~new;
if (hwpend != 0) {
- oldirqstate = disable_interrupts(I32_bit);
+ oldirqstate = disable_interrupts(PSR_I);
intr_enabled |= hwpend;
i80321_set_intrmask();
restore_interrupts(oldirqstate);
Index: head/sys/arm/xscale/i80321/i80321_timer.c
===================================================================
--- head/sys/arm/xscale/i80321/i80321_timer.c
+++ head/sys/arm/xscale/i80321/i80321_timer.c
@@ -52,6 +52,7 @@
#include <sys/rman.h>
#include <sys/timetc.h>
+#include <machine/armreg.h>
#include <machine/bus.h>
#include <machine/cpu.h>
#include <machine/cpufunc.h>
@@ -381,7 +382,7 @@
/* Report the clock frequency. */
- oldirqstate = disable_interrupts(I32_bit);
+ oldirqstate = disable_interrupts(PSR_I);
irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid,
#ifdef CPU_XSCALE_81342
Index: head/sys/arm/xscale/i80321/iq80321.c
===================================================================
--- head/sys/arm/xscale/i80321/iq80321.c
+++ head/sys/arm/xscale/i80321/iq80321.c
@@ -52,6 +52,7 @@
#include <sys/module.h>
#include <sys/malloc.h>
#include <sys/rman.h>
+#include <machine/armreg.h>
#include <machine/bus.h>
#include <machine/intr.h>
@@ -325,7 +326,7 @@
void
cpu_reset()
{
- (void) disable_interrupts(I32_bit|F32_bit);
+ (void) disable_interrupts(PSR_I|PSR_F);
*(__volatile uint32_t *)(IQ80321_80321_VBASE + VERDE_ATU_BASE +
ATU_PCSR) = PCSR_RIB | PCSR_RPB;
printf("Reset failed!\n");
Index: head/sys/arm/xscale/i8134x/i81342.c
===================================================================
--- head/sys/arm/xscale/i8134x/i81342.c
+++ head/sys/arm/xscale/i8134x/i81342.c
@@ -34,6 +34,7 @@
#include <sys/module.h>
#define _ARM32_BUS_DMA_PRIVATE
+#include <machine/armreg.h>
#include <machine/bus.h>
#include <machine/intr.h>
@@ -248,7 +249,7 @@
cpu_reset(void)
{
- disable_interrupts(I32_bit);
+ disable_interrupts(PSR_I);
/* XXX: Use the watchdog to reset for now */
__asm __volatile("mcr p6, 0, %0, c8, c9, 0\n"
"mcr p6, 0, %1, c7, c9, 0\n"
Index: head/sys/arm/xscale/ixp425/ixp425.c
===================================================================
--- head/sys/arm/xscale/ixp425/ixp425.c
+++ head/sys/arm/xscale/ixp425/ixp425.c
@@ -46,6 +46,7 @@
#include <sys/module.h>
#include <sys/malloc.h>
#include <sys/rman.h>
+#include <machine/armreg.h>
#include <machine/bus.h>
#include <machine/intr.h>
@@ -202,7 +203,7 @@
{
int i;
- i = disable_interrupts(I32_bit);
+ i = disable_interrupts(PSR_I);
if (nb < 32) {
intr_enabled &= ~(1 << nb);
ixp425_set_intrmask();
@@ -220,7 +221,7 @@
{
int i;
- i = disable_interrupts(I32_bit);
+ i = disable_interrupts(PSR_I);
if (nb < 32) {
intr_enabled |= (1 << nb);
ixp425_set_intrmask();
Index: head/sys/arm/xscale/ixp425/ixp425_pci.c
===================================================================
--- head/sys/arm/xscale/ixp425/ixp425_pci.c
+++ head/sys/arm/xscale/ixp425/ixp425_pci.c
@@ -47,6 +47,7 @@
#include <dev/pci/pcivar.h>
+#include <machine/armreg.h>
#include <machine/bus.h>
#include <machine/cpu.h>
#include <machine/pcb.h>
@@ -70,7 +71,7 @@
#define PCI_CSR_READ_4(sc, reg) \
bus_read_4(sc->sc_csr, reg)
-#define PCI_CONF_LOCK(s) (s) = disable_interrupts(I32_bit)
+#define PCI_CONF_LOCK(s) (s) = disable_interrupts(PSR_I)
#define PCI_CONF_UNLOCK(s) restore_interrupts((s))
static device_probe_t ixppcib_probe;
Index: head/sys/arm/xscale/ixp425/ixp425_timer.c
===================================================================
--- head/sys/arm/xscale/ixp425/ixp425_timer.c
+++ head/sys/arm/xscale/ixp425/ixp425_timer.c
@@ -46,6 +46,7 @@
#include <sys/rman.h>
#include <sys/timetc.h>
+#include <machine/armreg.h>
#include <machine/bus.h>
#include <machine/cpu.h>
#include <machine/cpufunc.h>
@@ -175,7 +176,7 @@
/* Report the clock frequency. */
- oldirqstate = disable_interrupts(I32_bit);
+ oldirqstate = disable_interrupts(PSR_I);
irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, IXP425_INT_TMR0,
IXP425_INT_TMR0, 1, RF_ACTIVE);
Index: head/sys/arm/xscale/pxa/pxa_icu.c
===================================================================
--- head/sys/arm/xscale/pxa/pxa_icu.c
+++ head/sys/arm/xscale/pxa/pxa_icu.c
@@ -33,6 +33,7 @@
#include <sys/malloc.h>
#include <sys/rman.h>
#include <sys/timetc.h>
+#include <machine/armreg.h>
#include <machine/bus.h>
#include <machine/intr.h>
@@ -105,7 +106,7 @@
pxa_icu_set_iclr(0);
/* XXX: This should move to configure_final or something. */
- enable_interrupts(I32_bit|F32_bit);
+ enable_interrupts(PSR_I|PSR_F);
return (0);
}
Index: head/sys/arm/xscale/pxa/pxa_timer.c
===================================================================
--- head/sys/arm/xscale/pxa/pxa_timer.c
+++ head/sys/arm/xscale/pxa/pxa_timer.c
@@ -33,6 +33,7 @@
#include <sys/malloc.h>
#include <sys/rman.h>
#include <sys/timetc.h>
+#include <machine/armreg.h>
#include <machine/bus.h>
#include <machine/cpu.h>
#include <machine/frame.h>
@@ -190,7 +191,7 @@
{
uint32_t val;
- (void)disable_interrupts(I32_bit|F32_bit);
+ (void)disable_interrupts(PSR_I|PSR_F);
val = pxa_timer_get_oscr();
val += PXA_TIMER_FREQUENCY;
Index: head/usr.bin/truss/arm-fbsd.c
===================================================================
--- head/usr.bin/truss/arm-fbsd.c
+++ head/usr.bin/truss/arm-fbsd.c
@@ -316,7 +316,7 @@
}
retval = regs.r[0];
- errorp = !!(regs.r_cpsr & PSR_C_bit);
+ errorp = !!(regs.r_cpsr & PSR_C);
/*
* This code, while simpler than the initial versions I used, could

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