D60223.id.diff
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D60223.id.diff
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	diff --git a/usr.sbin/bhyve/amd64/task_switch.c b/usr.sbin/bhyve/amd64/task_switch.c
	--- a/usr.sbin/bhyve/amd64/task_switch.c
	+++ b/usr.sbin/bhyve/amd64/task_switch.c
	@@ -96,6 +96,9 @@
	#define SEL_LIMIT(sel) (((sel) \| 0x7))
	#define TSS_BUSY(type) (((type) & 0x2) != 0)

	+/* The bits of EFLAGS that are always zero: 3, 5, 15 and 22-31. */
	+#define PSL_RESERVED_ZERO 0xffc08028
	+
	static uint64_t
	GETREG(struct vcpu *vcpu, int reg)
	{
	@@ -491,7 +494,12 @@
	nested = true;
	}

	- eflags = tss->tss_eflags;
	+ /*
	+ * The reserved bits of EFLAGS are not loaded from the TSS: bit 1 is
	+ * always set and bits 3, 5, 15 and 22-31 are always clear. A VM
	+ * entry with any other value fails.
	+ */
	+ eflags = (tss->tss_eflags & ~PSL_RESERVED_ZERO) \| PSL_RESERVED_DEFAULT;
	if (nested)
	eflags \|= PSL_NT;