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diff --git a/lib/libpmc/libpmc_pmu_util.c b/lib/libpmc/libpmc_pmu_util.c
--- a/lib/libpmc/libpmc_pmu_util.c
+++ b/lib/libpmc/libpmc_pmu_util.c
@@ -535,7 +535,7 @@
if (ped->ped_umask > 0) {
pm->pm_caps |= PMC_CAP_QUALIFIER;
}
- pm->pm_class = PMC_CLASS_K8;
+ pm->pm_class = PMC_CLASS_AMD;
pe = pmu_event_get(NULL, event_name, &idx);
if (pe->pmu == NULL) {
diff --git a/lib/libpmc/pmc.3 b/lib/libpmc/pmc.3
--- a/lib/libpmc/pmc.3
+++ b/lib/libpmc/pmc.3
@@ -229,9 +229,9 @@
Instruction Based Sampling (IBS) counters present in
.Tn AMD
Family 10h and above.
-.It Li PMC_CLASS_K8
+.It Li PMC_CLASS_AMD
Programmable hardware counters present in
-.Tn "AMD Athlon64"
+.Tn "AMD"
CPUs.
.It Li PMC_CLASS_PERF
MPERF and APERF counters present in
@@ -509,7 +509,7 @@
.It Li PMC_CLASS_IAF Ta Xr pmc.iaf 3
.It Li PMC_CLASS_IAP Ta Xr pmc.atom 3 , Xr pmc.core 3 , Xr pmc.core2 3
.It Li PMC_CLASS_IBS Ta Xr pmc.ibs 3
-.It Li PMC_CLASS_K8 Ta Xr pmc.amd 3
+.It Li PMC_CLASS_AMD Ta Xr pmc.amd 3
.It Li PMC_CLASS_RAPL Ta Xr pmc.rapl 3
.It Li PMC_CLASS_PERF Ta Xr pmc.perf 3
.It Li PMC_CLASS_TSC Ta Xr pmc.tsc 3
diff --git a/sys/amd64/include/pmc_mdep.h b/sys/amd64/include/pmc_mdep.h
--- a/sys/amd64/include/pmc_mdep.h
+++ b/sys/amd64/include/pmc_mdep.h
@@ -53,7 +53,7 @@
* IAF, IAP, UCF and UCP.
*/
#define PMC_MDEP_CLASS_INDEX_TSC 1
-#define PMC_MDEP_CLASS_INDEX_K8 2
+#define PMC_MDEP_CLASS_INDEX_AMD 2
#define PMC_MDEP_CLASS_INDEX_IBS 3
#define PMC_MDEP_CLASS_INDEX_P4 2
#define PMC_MDEP_CLASS_INDEX_IAP 2
diff --git a/sys/dev/hwpmc/hwpmc_amd.c b/sys/dev/hwpmc/hwpmc_amd.c
--- a/sys/dev/hwpmc/hwpmc_amd.c
+++ b/sys/dev/hwpmc/hwpmc_amd.c
@@ -30,7 +30,11 @@
* SUCH DAMAGE.
*/
-/* Support for the AMD K8 and later processors */
+/*
+ * Support for 64-bit AMD processors:
+ * - Zen families of microarchitectures
+ * - (legacy) K8-K10, up to Bulldozer and Jaguar families
+ */
#include <sys/param.h>
#include <sys/lock.h>
@@ -55,7 +59,7 @@
DPCPU_DEFINE_STATIC(uint32_t, nmi_counter);
-/* AMD K8 PMCs */
+/* AMD PMC decriptors */
struct amd_descr {
struct pmc_descr pm_descr; /* "base class" */
uint32_t pm_evsel; /* address of EVSEL register */
@@ -849,7 +853,7 @@
* state and initialize pointers in the MI per-cpu descriptor.
*/
pc = pmc_pcpu[cpu];
- first_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_K8].pcd_ri;
+ first_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_AMD].pcd_ri;
KASSERT(pc != NULL, ("[amd,%d] NULL per-cpu pointer", __LINE__));
@@ -898,7 +902,7 @@
pc = pmc_pcpu[cpu];
KASSERT(pc != NULL, ("[amd,%d] NULL per-cpu state", __LINE__));
- first_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_K8].pcd_ri;
+ first_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_AMD].pcd_ri;
/*
* Reset pointers in the MI 'per-cpu' state.
@@ -1073,8 +1077,8 @@
for (i = 0; i < amd_core_npmcs; i++) {
d = &amd_pmcdesc[i];
snprintf(d->pm_descr.pd_name, PMC_NAME_MAX,
- "K8-%d", i);
- d->pm_descr.pd_class = PMC_CLASS_K8;
+ "AMD-%d", i);
+ d->pm_descr.pd_class = PMC_CLASS_AMD;
d->pm_descr.pd_caps = AMD_PMC_CAPS;
/*
* Zen 5 can precisely count retire events.
@@ -1101,8 +1105,8 @@
for (i = 0; i < amd_l3_npmcs; i++) {
d = &amd_pmcdesc[amd_npmcs + i];
snprintf(d->pm_descr.pd_name, PMC_NAME_MAX,
- "K8-L3-%d", i);
- d->pm_descr.pd_class = PMC_CLASS_K8;
+ "AMD-L3-%d", i);
+ d->pm_descr.pd_class = PMC_CLASS_AMD;
d->pm_descr.pd_caps = AMD_PMC_L3_CAPS;
d->pm_descr.pd_width = 48;
d->pm_evsel = AMD_PMC_L3_BASE + 2 * i;
@@ -1117,8 +1121,8 @@
for (i = 0; i < amd_df_npmcs; i++) {
d = &amd_pmcdesc[amd_npmcs + i];
snprintf(d->pm_descr.pd_name, PMC_NAME_MAX,
- "K8-DF-%d", i);
- d->pm_descr.pd_class = PMC_CLASS_K8;
+ "AMD-DF-%d", i);
+ d->pm_descr.pd_class = PMC_CLASS_AMD;
d->pm_descr.pd_caps = AMD_PMC_DF_CAPS;
d->pm_descr.pd_width = 48;
d->pm_evsel = AMD_PMC_DF_BASE + 2 * i;
@@ -1134,8 +1138,8 @@
for (i = 0; i < amd_umc_npmcs; i++) {
d = &amd_pmcdesc[amd_npmcs + i];
snprintf(d->pm_descr.pd_name, PMC_NAME_MAX,
- "K8-UMC%d-%d", i / pmcs_per_umc, i);
- d->pm_descr.pd_class = PMC_CLASS_K8;
+ "AMD-UMC%d-%d", i / pmcs_per_umc, i);
+ d->pm_descr.pd_class = PMC_CLASS_AMD;
d->pm_descr.pd_caps = AMD_PMC_UMC_CAPS;
d->pm_descr.pd_width = 48;
d->pm_evsel = AMD_PMC_UMC_BASE + 2 * i;
@@ -1196,11 +1200,11 @@
if (error != 0)
goto error;
- /* Initialize AMD K8 PMC handling. */
- pcd = &pmc_mdep->pmd_classdep[PMC_MDEP_CLASS_INDEX_K8];
+ /* Initialize AMD PMC handling. */
+ pcd = &pmc_mdep->pmd_classdep[PMC_MDEP_CLASS_INDEX_AMD];
pcd->pcd_caps = AMD_PMC_CAPS;
- pcd->pcd_class = PMC_CLASS_K8;
+ pcd->pcd_class = PMC_CLASS_AMD;
pcd->pcd_num = amd_npmcs;
pcd->pcd_ri = pmc_mdep->pmd_npmc;
pcd->pcd_width = 48;
diff --git a/sys/i386/include/pmc_mdep.h b/sys/i386/include/pmc_mdep.h
--- a/sys/i386/include/pmc_mdep.h
+++ b/sys/i386/include/pmc_mdep.h
@@ -62,7 +62,7 @@
* IAF, IAP, UCF and UCP.
*/
#define PMC_MDEP_CLASS_INDEX_TSC 1
-#define PMC_MDEP_CLASS_INDEX_K8 2
+#define PMC_MDEP_CLASS_INDEX_AMD 2
#define PMC_MDEP_CLASS_INDEX_IBS 3
#define PMC_MDEP_CLASS_INDEX_IAP 2
#define PMC_MDEP_CLASS_INDEX_IAF 3
diff --git a/sys/sys/pmc.h b/sys/sys/pmc.h
--- a/sys/sys/pmc.h
+++ b/sys/sys/pmc.h
@@ -141,7 +141,7 @@
*/
#define __PMC_CLASSES() \
__PMC_CLASS(TSC, 0x00, "CPU Timestamp counter") \
- __PMC_CLASS(K8, 0x02, "AMD K8 performance counters") \
+ __PMC_CLASS(AMD, 0x02, "AMD performance counters") \
__PMC_CLASS(IBS, 0x03, "AMD IBS performance counters") \
__PMC_CLASS(IAF, 0x06, "Intel Core2/Atom, fixed function") \
__PMC_CLASS(IAP, 0x07, "Intel Core...Atom, programmable") \
@@ -169,6 +169,9 @@
#define PMC_CLASS_FIRST PMC_CLASS_TSC
#define PMC_CLASS_LAST PMC_CLASS_RAPL
+/* Compat for the old name. */
+#define PMC_CLASS_K8 PMC_CLASS_AMD
+
/*
* A PMC can be in the following states:
*
diff --git a/tests/sys/pmc/pmc_exterr_test.c b/tests/sys/pmc/pmc_exterr_test.c
--- a/tests/sys/pmc/pmc_exterr_test.c
+++ b/tests/sys/pmc/pmc_exterr_test.c
@@ -254,11 +254,11 @@
ATF_REQUIRE_FEATURE("exterr_strings");
require_hwpmc();
- require_class(PMC_CLASS_K8, "AMD");
+ require_class(PMC_CLASS_AMD, "AMD");
clear_exterr();
memset(&pa, 0, sizeof(pa));
- pa.pm_class = PMC_CLASS_K8;
+ pa.pm_class = PMC_CLASS_AMD;
pa.pm_mode = PMC_MODE_TC;
pa.pm_cpu = PMC_CPU_ANY;
pa.pm_flags = PMC_F_EV_PMU;
@@ -276,13 +276,13 @@
ATF_REQUIRE_FEATURE("exterr_strings");
require_hwpmc();
- require_class(PMC_CLASS_K8, "AMD");
+ require_class(PMC_CLASS_AMD, "AMD");
if (!pmc_pmu_enabled())
atf_tc_skip("AMD PMU raw allocation path is unavailable");
clear_exterr();
memset(&pa, 0, sizeof(pa));
- pa.pm_class = PMC_CLASS_K8;
+ pa.pm_class = PMC_CLASS_AMD;
pa.pm_mode = PMC_MODE_TC;
pa.pm_cpu = PMC_CPU_ANY;
pa.pm_flags = PMC_F_EV_PMU;
@@ -315,13 +315,13 @@
ATF_REQUIRE_FEATURE("exterr_strings");
require_hwpmc();
- require_class(PMC_CLASS_K8, "AMD");
+ require_class(PMC_CLASS_AMD, "AMD");
if (!pmc_pmu_enabled())
atf_tc_skip("AMD PMU raw allocation path is unavailable");
clear_exterr();
memset(&pa, 0, sizeof(pa));
- pa.pm_class = PMC_CLASS_K8;
+ pa.pm_class = PMC_CLASS_AMD;
pa.pm_mode = PMC_MODE_SC;
pa.pm_cpu = 0;
pa.pm_flags = PMC_F_EV_PMU;

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