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diff --git a/sys/dev/hwpmc/hwpmc_amd.c b/sys/dev/hwpmc/hwpmc_amd.c
--- a/sys/dev/hwpmc/hwpmc_amd.c
+++ b/sys/dev/hwpmc/hwpmc_amd.c
@@ -397,57 +397,27 @@
}
/*
- * Check if a given PMC allocation is feasible.
+ * Allocation for older processors and event definitions (amd_event_codes[]).
*/
static int
-amd_allocate_pmc(int cpu __unused, int ri, struct pmc *pm,
+amd_allocate_legacy_pmc(int cpu __unused, int ri, struct pmc *pm,
const struct pmc_op_pmcallocate *a)
{
- const struct pmc_descr *pd;
uint64_t allowed_unitmask, config, unitmask;
- uint32_t caps;
enum pmc_event pe;
+ uint32_t caps;
int i;
KASSERT(ri >= 0 && ri < amd_npmcs,
("[amd,%d] illegal row index %d", __LINE__, ri));
- pd = &amd_pmcdesc[ri].pm_descr;
-
- /* check class match */
- if (pd->pd_class != a->pm_class)
+ if (a->pm_class != PMC_CLASS_AMD)
return (EINVAL);
caps = pm->pm_caps;
PMCDBG2(MDP, ALL, 1,"amd-allocate ri=%d caps=0x%x", ri, caps);
- /* Validate sub-class. */
- if (amd_pmcdesc[ri].pm_subclass != a->pm_md.pm_amd.pm_amd_sub_class)
- return (EINVAL);
-
- if (((caps & PMC_CAP_PRECISE) != 0) &&
- ((pd->pd_caps & PMC_CAP_PRECISE) == 0))
- return (EINVAL);
-
- /* PMC_F_EV_PMU: config comes from pmu-events tables. */
- if ((a->pm_flags & PMC_F_EV_PMU) != 0) {
- config = a->pm_md.pm_amd.pm_amd_config;
- if ((config & ~amd_config_mask(amd_pmcdesc[ri].pm_subclass,
- caps)) != 0)
- return (EXTERROR(EINVAL,
- "AMD PMU config has unsupported bits %#jx",
- (uintmax_t)(config & ~amd_config_mask(
- amd_pmcdesc[ri].pm_subclass, caps))));
- pm->pm_md.pm_amd.pm_amd_evsel = config;
- PMCDBG2(MDP, ALL, 2, "amd-allocate ri=%d -> config=0x%jx",
- ri, (uintmax_t)config);
- return (0);
- }
-
- /*
- * Everything below this is for supporting older processors.
- */
pe = a->pm_ev;
/* map ev to the correct event mask code */
@@ -500,6 +470,58 @@
return (0);
}
+/*
+ * Check if a given PMC allocation is feasible.
+ */
+static int
+amd_allocate_pmc(int cpu __unused, int ri, struct pmc *pm,
+ const struct pmc_op_pmcallocate *a)
+{
+ const struct pmc_descr *pd;
+ uint64_t config;
+ uint32_t caps;
+
+ /*
+ * PMC_F_EV_PMU: config comes from pmu-events tables; fall back to
+ * legacy events if absent.
+ */
+ if ((a->pm_flags & PMC_F_EV_PMU) == 0)
+ return (amd_allocate_legacy_pmc(cpu, ri, pm, a));
+
+ KASSERT(ri >= 0 && ri < amd_npmcs,
+ ("[amd,%d] illegal row index %d", __LINE__, ri));
+
+ pd = &amd_pmcdesc[ri].pm_descr;
+
+ /* check class match */
+ if (pd->pd_class != a->pm_class)
+ return (EINVAL);
+
+ caps = pm->pm_caps;
+
+ PMCDBG2(MDP, ALL, 1,"amd-allocate ri=%d caps=0x%x", ri, caps);
+
+ /* Validate sub-class. */
+ if (amd_pmcdesc[ri].pm_subclass != a->pm_md.pm_amd.pm_amd_sub_class)
+ return (EINVAL);
+
+ if (((caps & PMC_CAP_PRECISE) != 0) &&
+ ((pd->pd_caps & PMC_CAP_PRECISE) == 0))
+ return (EINVAL);
+
+ config = a->pm_md.pm_amd.pm_amd_config;
+ if ((config & ~amd_config_mask(amd_pmcdesc[ri].pm_subclass,
+ caps)) != 0)
+ return (EXTERROR(EINVAL,
+ "AMD PMU config has unsupported bits %#jx",
+ (uintmax_t)(config & ~amd_config_mask(
+ amd_pmcdesc[ri].pm_subclass, caps))));
+ pm->pm_md.pm_amd.pm_amd_evsel = config;
+ PMCDBG2(MDP, ALL, 2, "amd-allocate ri=%d -> config=0x%jx",
+ ri, (uintmax_t)config);
+ return (0);
+}
+
/*
* Release machine dependent state associated with a PMC. This is a
* no-op on this architecture.

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