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Index: sys/dev/nvme/nvme_ctrlr.c
===================================================================
--- sys/dev/nvme/nvme_ctrlr.c
+++ sys/dev/nvme/nvme_ctrlr.c
@@ -247,21 +247,25 @@
cc.raw = nvme_mmio_read_4(ctrlr, cc);
csts.raw = nvme_mmio_read_4(ctrlr, csts);
- if (cc.bits.en != desired_val) {
- nvme_printf(ctrlr, "%s called with desired_val = %d "
- "but cc.en = %d\n", __func__, desired_val, cc.bits.en);
- return (ENXIO);
+ ms_waited = 0;
+ while (cc.bits.en != desired_val) {
+ if (ms_waited++ > ctrlr->enable_timeout_in_ms) {
+ nvme_printf(ctrlr, "controller enable did not become %d "
+ "within %d ms\n", desired_val, ctrlr->enable_timeout_in_ms);
+ return (ENXIO);
+ }
+ DELAY(1000);
+ cc.raw = nvme_mmio_read_4(ctrlr, cc);
}
ms_waited = 0;
-
while (csts.bits.rdy != desired_val) {
- DELAY(1000);
if (ms_waited++ > ctrlr->ready_timeout_in_ms) {
nvme_printf(ctrlr, "controller ready did not become %d "
"within %d ms\n", desired_val, ctrlr->ready_timeout_in_ms);
return (ENXIO);
}
+ DELAY(1000);
csts.raw = nvme_mmio_read_4(ctrlr, csts);
}
@@ -282,7 +286,6 @@
cc.bits.en = 0;
nvme_mmio_write_4(ctrlr, cc, cc.raw);
- DELAY(5000);
nvme_ctrlr_wait_for_ready(ctrlr, 0);
}
@@ -326,7 +329,6 @@
cc.bits.mps = (PAGE_SIZE >> 13);
nvme_mmio_write_4(ctrlr, cc, cc.raw);
- DELAY(5000);
return (nvme_ctrlr_wait_for_ready(ctrlr, 1));
}
@@ -1123,6 +1125,7 @@
/* Get ready timeout value from controller, in units of 500ms. */
cap_lo.raw = nvme_mmio_read_4(ctrlr, cap_lo);
ctrlr->ready_timeout_in_ms = cap_lo.bits.to * 500;
+ ctrlr->enable_timeout_in_ms = 2500; /* Wait up to 2.5s for EN bit delta */
timeout_period = NVME_DEFAULT_TIMEOUT_PERIOD;
TUNABLE_INT_FETCH("hw.nvme.timeout_period", &timeout_period);
Index: sys/dev/nvme/nvme_private.h
===================================================================
--- sys/dev/nvme/nvme_private.h
+++ sys/dev/nvme/nvme_private.h
@@ -246,6 +246,7 @@
struct mtx lock;
uint32_t ready_timeout_in_ms;
+ uint32_t enable_timeout_in_ms;
bus_space_tag_t bus_tag;
bus_space_handle_t bus_handle;

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