D27116.id79710.diff
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	Index: head/sys/dev/ena/ena.c
	===================================================================
	--- head/sys/dev/ena/ena.c
	+++ head/sys/dev/ena/ena.c
	@@ -2797,6 +2797,8 @@
	(DRV_MODULE_VER_MINOR << ENA_ADMIN_HOST_INFO_MINOR_SHIFT) \|
	(DRV_MODULE_VER_SUBMINOR << ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT);
	host_info->num_cpus = mp_ncpus;
	+ host_info->driver_supported_features =
	+ ENA_ADMIN_HOST_INFO_RX_OFFSET_MASK;

	rc = ena_com_set_host_attributes(ena_dev);
	if (unlikely(rc != 0)) {
	Index: head/sys/dev/ena/ena_datapath.c
	===================================================================
	--- head/sys/dev/ena/ena_datapath.c
	+++ head/sys/dev/ena/ena_datapath.c
	@@ -431,6 +431,10 @@
	mbuf->m_flags \|= M_PKTHDR;
	mbuf->m_pkthdr.len = len;
	mbuf->m_len = len;
	+ // Only for the first segment the data starts at specific offset
	+ mbuf->m_data = mtodo(mbuf, ena_rx_ctx->pkt_offset);
	+ ena_trace(NULL, ENA_DBG \| ENA_RXPTH,
	+ "Mbuf data offset=%u\n", ena_rx_ctx->pkt_offset);
	mbuf->m_pkthdr.rcvif = rx_ring->que->adapter->ifp;

	/* Fill mbuf with hash key and it's interpretation for optimization */
	@@ -575,6 +579,8 @@
	ena_rx_ctx.ena_bufs = rx_ring->ena_bufs;
	ena_rx_ctx.max_bufs = adapter->max_rx_sgl_size;
	ena_rx_ctx.descs = 0;
	+ ena_rx_ctx.pkt_offset = 0;
	+
	bus_dmamap_sync(io_cq->cdesc_addr.mem_handle.tag,
	io_cq->cdesc_addr.mem_handle.map, BUS_DMASYNC_POSTREAD);
	rc = ena_com_rx_pkt(io_cq, io_sq, &ena_rx_ctx);