D2340.id5390.diff
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	Index: sys/arm/annapurna/alpine/alpine_machdep.c
	===================================================================
	--- /dev/null
	+++ sys/arm/annapurna/alpine/alpine_machdep.c
	@@ -0,0 +1,148 @@
	+/*-
	+ * Copyright (c) 2013 Ruslan Bukin <br@bsdpad.com>
	+ * Copyright (c) 2015 Semihalf
	+ * All rights reserved.
	+ *
	+ * Redistribution and use in source and binary forms, with or without
	+ * modification, are permitted provided that the following conditions
	+ * are met:
	+ * 1. Redistributions of source code must retain the above copyright
	+ * notice, this list of conditions and the following disclaimer.
	+ * 2. Redistributions in binary form must reproduce the above copyright
	+ * notice, this list of conditions and the following disclaimer in the
	+ * documentation and/or other materials provided with the distribution.
	+ *
	+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
	+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
	+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
	+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
	+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
	+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
	+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
	+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
	+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
	+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
	+ * SUCH DAMAGE.
	+ *
	+ */
	+
	+#include <sys/cdefs.h>
	+__FBSDID("$FreeBSD$");
	+
	+#define _ARM32_BUS_DMA_PRIVATE
	+#include <sys/param.h>
	+#include <sys/systm.h>
	+#include <sys/bus.h>
	+#include <sys/lock.h>
	+#include <sys/mutex.h>
	+
	+#include <vm/vm.h>
	+#include <vm/pmap.h>
	+
	+#include <machine/bus.h>
	+#include <machine/frame.h> /* For trapframe_t, used in <machine/machdep.h> */
	+#include <machine/machdep.h>
	+#include <machine/pmap.h>
	+#include <machine/devmap.h>
	+#include <machine/platform.h>
	+#include <machine/fdt.h>
	+
	+#include <dev/fdt/fdt_common.h>
	+
	+#include "opt_ddb.h"
	+#include "opt_platform.h"
	+
	+struct mtx al_dbg_lock;
	+
	+#define DEVMAP_MAX_VA_ADDRESS 0xF0000000
	+bus_addr_t al_devmap_pa;
	+bus_addr_t al_devmap_size;
	+
	+#define AL_NB_SERVICE_OFFSET 0x70000
	+#define AL_NB_CCU_OFFSET 0x90000
	+#define AL_CCU_SNOOP_CONTROL_IOFAB_0_OFFSET 0x4000
	+#define AL_CCU_SNOOP_CONTROL_IOFAB_1_OFFSET 0x5000
	+#define AL_CCU_SPECULATION_CONTROL_OFFSET 0x4
	+
	+#define AL_NB_ACF_MISC_OFFSET 0xD0
	+#define AL_NB_ACF_MISC_READ_BYPASS (1 << 30)
	+
	+int alpine_get_devmap_base(bus_addr_t pa, bus_addr_t size);
	+
	+vm_offset_t
	+platform_lastaddr(void)
	+{
	+
	+ return (DEVMAP_MAX_VA_ADDRESS);
	+}
	+
	+void
	+platform_probe_and_attach(void)
	+{
	+
	+}
	+
	+void
	+platform_gpio_init(void)
	+{
	+
	+}
	+
	+void
	+platform_late_init(void)
	+{
	+ bus_addr_t reg_baddr;
	+ uint32_t val;
	+
	+ if (!mtx_initialized(&al_dbg_lock))
	+ mtx_init(&al_dbg_lock, "ALDBG", "ALDBG", MTX_SPIN);
	+
	+ /* configure system fabric */
	+ if (bus_space_map(fdtbus_bs_tag, al_devmap_pa, al_devmap_size, 0,
	+ &reg_baddr))
	+ panic("Couldn't map Register Space area");
	+
	+ /* do not allow reads to bypass writes to different addresses */
	+ val = bus_space_read_4(fdtbus_bs_tag, reg_baddr,
	+ AL_NB_SERVICE_OFFSET + AL_NB_ACF_MISC_OFFSET);
	+ val &= ~AL_NB_ACF_MISC_READ_BYPASS;
	+ bus_space_write_4(fdtbus_bs_tag, reg_baddr,
	+ AL_NB_SERVICE_OFFSET + AL_NB_ACF_MISC_OFFSET, val);
	+
	+ /* enable cache snoop */
	+ bus_space_write_4(fdtbus_bs_tag, reg_baddr,
	+ AL_NB_CCU_OFFSET + AL_CCU_SNOOP_CONTROL_IOFAB_0_OFFSET, 1);
	+ bus_space_write_4(fdtbus_bs_tag, reg_baddr,
	+ AL_NB_CCU_OFFSET + AL_CCU_SNOOP_CONTROL_IOFAB_1_OFFSET, 1);
	+
	+ /* disable speculative fetches from masters */
	+ bus_space_write_4(fdtbus_bs_tag, reg_baddr,
	+ AL_NB_CCU_OFFSET + AL_CCU_SPECULATION_CONTROL_OFFSET, 7);
	+
	+ bus_space_unmap(fdtbus_bs_tag, reg_baddr, al_devmap_size);
	+}
	+
	+/*
	+ * Construct pmap_devmap[] with DT-derived config data.
	+ */
	+int
	+platform_devmap_init(void)
	+{
	+ alpine_get_devmap_base(&al_devmap_pa, &al_devmap_size);
	+ arm_devmap_add_entry(al_devmap_pa, al_devmap_size);
	+ return (0);
	+}
	+
	+struct arm32_dma_range *
	+bus_dma_get_range(void)
	+{
	+
	+ return (NULL);
	+}
	+
	+int
	+bus_dma_get_range_nb(void)
	+{
	+
	+ return (0);
	+}
	Index: sys/arm/annapurna/alpine/alpine_machdep_mp.c
	===================================================================
	--- /dev/null
	+++ sys/arm/annapurna/alpine/alpine_machdep_mp.c
	@@ -0,0 +1,335 @@
	+/*-
	+ * Copyright (c) 2013 Ruslan Bukin <br@bsdpad.com>
	+ * Copyright (c) 2015 Semihalf
	+ * All rights reserved.
	+ *
	+ * Redistribution and use in source and binary forms, with or without
	+ * modification, are permitted provided that the following conditions
	+ * are met:
	+ * 1. Redistributions of source code must retain the above copyright
	+ * notice, this list of conditions and the following disclaimer.
	+ * 2. Redistributions in binary form must reproduce the above copyright
	+ * notice, this list of conditions and the following disclaimer in the
	+ * documentation and/or other materials provided with the distribution.
	+ *
	+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
	+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
	+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
	+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
	+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
	+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
	+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
	+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
	+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
	+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
	+ * SUCH DAMAGE.
	+ *
	+ */
	+
	+#include <sys/cdefs.h>
	+__FBSDID("$FreeBSD$");
	+#include <sys/param.h>
	+#include <sys/systm.h>
	+#include <sys/bus.h>
	+#include <sys/lock.h>
	+#include <sys/mutex.h>
	+#include <sys/smp.h>
	+#include <sys/cpuset.h>
	+
	+#include <vm/vm.h>
	+#include <vm/pmap.h>
	+
	+#include <machine/smp.h>
	+#include <machine/fdt.h>
	+#include <machine/intr.h>
	+#include <machine/cpu-v6.h>
	+
	+#include <dev/fdt/fdt_common.h>
	+#include <dev/ofw/ofw_cpu.h>
	+#include <dev/ofw/ofw_bus_subr.h>
	+
	+#define AL_CPU_RESUME_WATERMARK_REG 0x00
	+#define AL_CPU_RESUME_FLAGS_REG 0x04
	+#define AL_CPU_RESUME_PCPU_RADDR_REG(cpu) (0x08 + 0x04 + 8*(cpu))
	+#define AL_CPU_RESUME_PCPU_FLAGS(cpu) (0x08 + 8*(cpu))
	+
	+/* Per-CPU flags */
	+#define AL_CPU_RESUME_FLG_PERCPU_DONT_RESUME (1 << 2)
	+
	+/* The expected magic number for validating the resume addresses */
	+#define AL_CPU_RESUME_MAGIC_NUM 0xf0e1d200
	+#define AL_CPU_RESUME_MAGIC_NUM_MASK 0xffffff00
	+
	+/* The expected minimal version number for validating the capabilities */
	+#define AL_CPU_RESUME_MIN_VER 0x000000c3
	+#define AL_CPU_RESUME_MIN_VER_MASK 0x000000ff
	+
	+/* Field controlling the boot-up of companion cores */
	+#define AL_NB_INIT_CONTROL (0x8)
	+#define AL_NB_CONFIG_STATUS_PWR_CTRL(cpu) (0x2020 + (cpu)*0x100)
	+
	+#define SERDES_NUM_GROUPS 4
	+#define SERDES_GROUP_SIZE 0x400
	+
	+extern bus_addr_t al_devmap_pa;
	+extern bus_addr_t al_devmap_size;
	+
	+extern void mpentry(void);
	+
	+int alpine_serdes_resource_get(uint32_t group, bus_space_tag_t *tag,
	+ bus_addr_t *baddr);
	+static int platform_mp_get_core_cnt(void);
	+static int alpine_get_cpu_resume_base(u_long pbase, u_long psize);
	+static int alpine_get_nb_base(u_long pbase, u_long psize);
	+static int alpine_get_serdes_base(u_long pbase, u_long psize);
	+int alpine_serdes_resource_get(uint32_t group, bus_space_tag_t *tag,
	+ bus_addr_t *baddr);
	+static boolean_t alpine_validate_cpu(u_int, phandle_t, u_int, pcell_t *);
	+
	+static boolean_t
	+alpine_validate_cpu(u_int id, phandle_t child, u_int addr_cell, pcell_t *reg)
	+{
	+ return fdt_is_compatible(child, "arm,cortex-a15");
	+}
	+
	+static int
	+platform_mp_get_core_cnt(void)
	+{
	+ static int ncores = 0;
	+ int nchilds;
	+ uint32_t reg;
	+
	+ /* Calculate ncores value only once */
	+ if (ncores)
	+ return (ncores);
	+
	+ reg = cp15_l2ctlr_get();
	+ ncores = CPUV7_L2CTLR_NPROC(reg);
	+
	+ nchilds = ofw_cpu_early_foreach(alpine_validate_cpu, false);
	+
	+ /* Limit CPUs if DTS has configured less than available */
	+ if ((nchilds > 0) && (nchilds < ncores)) {
	+ printf("SMP: limiting number of active CPUs to %d out of %d\n",
	+ nchilds, ncores);
	+ ncores = nchilds;
	+ }
	+
	+ return (ncores);
	+}
	+
	+void
	+platform_mp_init_secondary(void)
	+{
	+
	+ arm_init_secondary_ic();
	+}
	+
	+void
	+platform_mp_setmaxid(void)
	+{
	+ int core_cnt;
	+
	+ core_cnt = platform_mp_get_core_cnt();
	+ mp_maxid = core_cnt - 1;
	+}
	+
	+int
	+platform_mp_probe(void)
	+{
	+ mp_ncpus = platform_mp_get_core_cnt();
	+ return (1);
	+}
	+
	+static int
	+alpine_get_cpu_resume_base(u_long pbase, u_long psize)
	+{
	+ phandle_t node;
	+ u_long base = 0;
	+ u_long size = 0;
	+
	+ if (pbase == NULL \|\| psize == NULL)
	+ return (EINVAL);
	+
	+ if ((node = OF_finddevice("/")) == -1)
	+ return (EFAULT);
	+
	+ if ((node =
	+ ofw_bus_find_compatible(node, "annapurna-labs,al-cpu-resume")) == 0)
	+ return (EFAULT);
	+
	+ if (fdt_regsize(node, &base, &size))
	+ return (EFAULT);
	+
	+ *pbase = base;
	+ *psize = size;
	+
	+ return (0);
	+}
	+
	+static int
	+alpine_get_nb_base(u_long pbase, u_long psize)
	+{
	+ phandle_t node;
	+ u_long base = 0;
	+ u_long size = 0;
	+
	+ if (pbase == NULL \|\| psize == NULL)
	+ return (EINVAL);
	+
	+ if ((node = OF_finddevice("/")) == -1)
	+ return (EFAULT);
	+
	+ if ((node =
	+ ofw_bus_find_compatible(node, "annapurna-labs,al-nb-service")) == 0)
	+ return (EFAULT);
	+
	+ if (fdt_regsize(node, &base, &size))
	+ return (EFAULT);
	+
	+ *pbase = base;
	+ *psize = size;
	+
	+ return (0);
	+}
	+
	+void
	+platform_mp_start_ap(void)
	+{
	+ uint32_t physaddr;
	+ vm_offset_t vaddr;
	+ uint32_t val;
	+ uint32_t start_mask;
	+ u_long cpu_resume_base;
	+ u_long nb_base;
	+ u_long cpu_resume_size;
	+ u_long nb_size;
	+ bus_addr_t cpu_resume_baddr;
	+ bus_addr_t nb_baddr;
	+ int a;
	+
	+ if (alpine_get_cpu_resume_base(&cpu_resume_base, &cpu_resume_size))
	+ panic("Couldn't resolve cpu_resume_base address\n");
	+
	+ if (alpine_get_nb_base(&nb_base, &nb_size))
	+ panic("Couldn't resolve_nb_base address\n");
	+
	+ /* Proceed with start addresses for additional CPUs */
	+ if (bus_space_map(fdtbus_bs_tag, al_devmap_pa + cpu_resume_base,
	+ cpu_resume_size, 0, &cpu_resume_baddr))
	+ panic("Couldn't map CPU-resume area");
	+ if (bus_space_map(fdtbus_bs_tag, al_devmap_pa + nb_base,
	+ nb_size, 0, &nb_baddr))
	+ panic("Couldn't map NB-service area");
	+
	+ /* Proceed with start addresses for additional CPUs */
	+ val = bus_space_read_4(fdtbus_bs_tag, cpu_resume_baddr,
	+ AL_CPU_RESUME_WATERMARK_REG);
	+ if (((val & AL_CPU_RESUME_MAGIC_NUM_MASK) != AL_CPU_RESUME_MAGIC_NUM) \|\|
	+ ((val & AL_CPU_RESUME_MIN_VER_MASK) < AL_CPU_RESUME_MIN_VER)) {
	+ panic("CPU-resume device is not compatible");
	+ }
	+
	+ vaddr = (vm_offset_t)mpentry;
	+ physaddr = pmap_kextract(vaddr);
	+
	+ for (a = 1; a < platform_mp_get_core_cnt(); a++) {
	+ /* Power up the core */
	+ bus_space_write_4(fdtbus_bs_tag, nb_baddr,
	+ AL_NB_CONFIG_STATUS_PWR_CTRL(a), 0);
	+ mb();
	+
	+ /* Enable resume */
	+ val = bus_space_read_4(fdtbus_bs_tag, cpu_resume_baddr,
	+ AL_CPU_RESUME_PCPU_FLAGS(a));
	+ val &= ~AL_CPU_RESUME_FLG_PERCPU_DONT_RESUME;
	+ bus_space_write_4(fdtbus_bs_tag, cpu_resume_baddr,
	+ AL_CPU_RESUME_PCPU_FLAGS(a), val);
	+ mb();
	+
	+ /* Set resume physical address */
	+ bus_space_write_4(fdtbus_bs_tag, cpu_resume_baddr,
	+ AL_CPU_RESUME_PCPU_RADDR_REG(a), physaddr);
	+ mb();
	+ }
	+
	+ /* Release cores from reset */
	+ if (bus_space_map(fdtbus_bs_tag, al_devmap_pa + nb_base,
	+ nb_size, 0, &nb_baddr))
	+ panic("Couldn't map NB-service area");
	+
	+ start_mask = (1 << platform_mp_get_core_cnt()) - 1;
	+
	+ /* Release cores from reset */
	+ val = bus_space_read_4(fdtbus_bs_tag, nb_baddr, AL_NB_INIT_CONTROL);
	+ val \|= start_mask;
	+ bus_space_write_4(fdtbus_bs_tag, nb_baddr, AL_NB_INIT_CONTROL, val);
	+ dsb();
	+
	+ bus_space_unmap(fdtbus_bs_tag, nb_baddr, nb_size);
	+ bus_space_unmap(fdtbus_bs_tag, cpu_resume_baddr, cpu_resume_size);
	+}
	+
	+static int
	+alpine_get_serdes_base(u_long pbase, u_long psize)
	+{
	+ phandle_t node;
	+ u_long base = 0;
	+ u_long size = 0;
	+
	+ if (pbase == NULL \|\| psize == NULL)
	+ return (EINVAL);
	+
	+ if ((node = OF_finddevice("/")) == -1)
	+ return (EFAULT);
	+
	+ if ((node =
	+ ofw_bus_find_compatible(node, "annapurna-labs,al-serdes")) == 0)
	+ return (EFAULT);
	+
	+ if (fdt_regsize(node, &base, &size))
	+ return (EFAULT);
	+
	+ *pbase = base;
	+ *psize = size;
	+
	+ return (0);
	+}
	+
	+int
	+alpine_serdes_resource_get(uint32_t group, bus_space_tag_t tag, bus_addr_t baddr)
	+{
	+ u_long serdes_base, serdes_size;
	+ int ret;
	+ static bus_addr_t baddr_mapped[SERDES_NUM_GROUPS];
	+
	+ if (group >= SERDES_NUM_GROUPS)
	+ return (EINVAL);
	+
	+ if (baddr_mapped[group]) {
	+ *tag = fdtbus_bs_tag;
	+ *baddr = baddr_mapped[group];
	+ return (0);
	+ }
	+
	+ ret = alpine_get_serdes_base(&serdes_base, &serdes_size);
	+ if (ret)
	+ return (ret);
	+
	+ ret = bus_space_map(fdtbus_bs_tag,
	+ al_devmap_pa + serdes_base + group * SERDES_GROUP_SIZE,
	+ (SERDES_NUM_GROUPS - group) * SERDES_GROUP_SIZE, 0, baddr);
	+ if (ret)
	+ return (ret);
	+
	+ baddr_mapped[group] = *baddr;
	+
	+ return (0);
	+}
	+
	+void
	+platform_ipi_send(cpuset_t cpus, u_int ipi)
	+{
	+
	+ pic_ipi_send(cpus, ipi);
	+}
	Index: sys/arm/annapurna/alpine/common.c
	===================================================================
	--- /dev/null
	+++ sys/arm/annapurna/alpine/common.c
	@@ -0,0 +1,158 @@
	+/*-
	+ * Copyright (c) 2013 Ruslan Bukin <br@bsdpad.com>
	+ * Copyright (c) 2015 Semihalf.
	+ * All rights reserved.
	+ *
	+ * Redistribution and use in source and binary forms, with or without
	+ * modification, are permitted provided that the following conditions
	+ * are met:
	+ * 1. Redistributions of source code must retain the above copyright
	+ * notice, this list of conditions and the following disclaimer.
	+ * 2. Redistributions in binary form must reproduce the above copyright
	+ * notice, this list of conditions and the following disclaimer in the
	+ * documentation and/or other materials provided with the distribution.
	+ *
	+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
	+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
	+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
	+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
	+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
	+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
	+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
	+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
	+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
	+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
	+ * SUCH DAMAGE.
	+ *
	+ */
	+
	+#include <sys/cdefs.h>
	+__FBSDID("$FreeBSD$");
	+
	+#include <sys/param.h>
	+#include <sys/systm.h>
	+#include <sys/bus.h>
	+#include <sys/kernel.h>
	+
	+#include <dev/fdt/fdt_common.h>
	+#include <dev/ofw/openfirm.h>
	+
	+#include <machine/bus.h>
	+#include <machine/fdt.h>
	+#include <machine/intr.h>
	+
	+#define WDTLOAD 0x000
	+#define LOAD_MIN 0x00000001
	+#define LOAD_MAX 0xFFFFFFFF
	+#define WDTVALUE 0x004
	+#define WDTCONTROL 0x008
	+/* control register masks */
	+#define INT_ENABLE (1 << 0)
	+#define RESET_ENABLE (1 << 1)
	+#define WDTLOCK 0xC00
	+#define UNLOCK 0x1ACCE551
	+#define LOCK 0x00000001
	+
	+extern bus_addr_t al_devmap_pa;
	+struct fdt_fixup_entry fdt_fixup_table[] = {
	+ { NULL, NULL }
	+};
	+
	+static int alpine_get_wdt_base(uint32_t pbase, uint32_t psize);
	+static int alpine_pic_decode_fdt(uint32_t iparent, uint32_t *intr,
	+ int interrupt, int trig, int *pol);
	+
	+int alpine_get_devmap_base(bus_addr_t pa, bus_addr_t size);
	+
	+int alpine_get_devmap_base(bus_addr_t pa, bus_addr_t size)
	+{
	+ phandle_t node;
	+
	+ if ((node = OF_finddevice("/")) == 0)
	+ return (ENXIO);
	+
	+ if ((node = fdt_find_compatible(node, "simple-bus", 1)) == 0)
	+ return (ENXIO);
	+
	+ return fdt_get_range(node, 0, pa, size);
	+}
	+
	+static int
	+alpine_get_wdt_base(uint32_t pbase, uint32_t psize)
	+{
	+ phandle_t node;
	+ u_long base = 0;
	+ u_long size = 0;
	+
	+ if (pbase == NULL \|\| psize == NULL)
	+ return (EINVAL);
	+
	+ if ((node = OF_finddevice("/")) == -1)
	+ return (EFAULT);
	+
	+ if ((node = fdt_find_compatible(node, "simple-bus", 1)) == 0)
	+ return (EFAULT);
	+
	+ if ((node =
	+ fdt_find_compatible(node, "arm,sp805", 1)) == 0)
	+ return (EFAULT);
	+
	+ if (fdt_regsize(node, &base, &size))
	+ return (EFAULT);
	+
	+ *pbase = base;
	+ *psize = size;
	+
	+ return (0);
	+}
	+
	+void
	+cpu_reset(void)
	+{
	+ uint32_t wdbase, wdsize;
	+ bus_addr_t wdbaddr;
	+ int ret;
	+
	+ ret = alpine_get_wdt_base(&wdbase, &wdsize);
	+ if (ret) {
	+ printf("Unable to get WDT base, do power down manually...");
	+ goto infinite;
	+ }
	+
	+ ret = bus_space_map(fdtbus_bs_tag, al_devmap_pa + wdbase,
	+ wdsize, 0, &wdbaddr);
	+ if (ret) {
	+ printf("Unable to map WDT base, do power down manually...");
	+ goto infinite;
	+ }
	+
	+ bus_space_write_4(fdtbus_bs_tag, wdbaddr, WDTLOCK, UNLOCK);
	+ bus_space_write_4(fdtbus_bs_tag, wdbaddr, WDTLOAD, LOAD_MIN);
	+ bus_space_write_4(fdtbus_bs_tag, wdbaddr, WDTCONTROL, INT_ENABLE \| RESET_ENABLE);
	+
	+infinite:
	+ while (1) {}
	+}
	+
	+static int
	+alpine_pic_decode_fdt(uint32_t iparent, uint32_t intr, int interrupt,
	+ int trig, int pol)
	+{
	+ int rv = 0;
	+
	+ rv = gic_decode_fdt(iparent, intr, interrupt, trig, pol);
	+ if (rv == 0) {
	+ /* This was recognized as our PIC and decoded. */
	+ interrupt = FDT_MAP_IRQ(iparent, interrupt);
	+
	+ /* Configure the interrupt if callback provided */
	+ if (arm_config_irq)
	+ (arm_config_irq)(interrupt, trig, pol);
	+ }
	+ return (rv);
	+}
	+
	+fdt_pic_decode_t fdt_pic_table[] = {
	+ &alpine_pic_decode_fdt,
	+ NULL
	+};
	Index: sys/arm/annapurna/alpine/files.alpine
	===================================================================
	--- /dev/null
	+++ sys/arm/annapurna/alpine/files.alpine
	@@ -0,0 +1,16 @@
	+# $FreeBSD$
	+
	+kern/kern_clocksource.c standard
	+
	+arm/arm/bus_space_base.c standard
	+arm/arm/bus_space_generic.c standard
	+arm/arm/bus_space_asm_generic.S standard
	+
	+arm/versatile/sp804.c standard
	+arm/versatile/versatile_timer.c standard
	+dev/uart/uart_dev_ns8250.c optional uart
	+dev/ofw/ofw_cpu.c standard
	+
	+arm/annapurna/alpine/common.c standard
	+arm/annapurna/alpine/alpine_machdep.c standard
	+arm/annapurna/alpine/alpine_machdep_mp.c optional smp
	Index: sys/arm/annapurna/alpine/hal/al_hal_common.h
	===================================================================
	--- /dev/null
	+++ sys/arm/annapurna/alpine/hal/al_hal_common.h
	@@ -0,0 +1,70 @@
	+/*-
	+********************************************************************************
	+Copyright (C) 2015 Annapurna Labs Ltd.
	+
	+This file may be licensed under the terms of the Annapurna Labs Commercial
	+License Agreement.
	+
	+Alternatively, this file can be distributed under the terms of the GNU General
	+Public License V2 as published by the Free Software Foundation and can be
	+found at http://www.gnu.org/licenses/gpl-2.0.html
	+
	+Alternatively, redistribution and use in source and binary forms, with or
	+without modification, are permitted provided that the following conditions are
	+met:
	+
	+ * Redistributions of source code must retain the above copyright notice,
	+this list of conditions and the following disclaimer.
	+
	+ * Redistributions in binary form must reproduce the above copyright
	+notice, this list of conditions and the following disclaimer in
	+the documentation and/or other materials provided with the
	+distribution.
	+
	+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
	+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
	+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
	+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
	+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
	+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
	+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
	+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
	+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
	+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	+
	+*******************************************************************************/
	+
	+/**
	+ * @defgroup group_common HAL Common Layer
	+ * Includes all common header files used by HAL
	+ * @{
	+ * @file al_hal_common.h
	+ *
	+ */
	+
	+#ifndef __AL_HAL_COMMON_H__
	+#define __AL_HAL_COMMON_H__
	+
	+#include "al_hal_plat_types.h"
	+#include "al_hal_plat_services.h"
	+
	+#include "al_hal_types.h"
	+#include "al_hal_reg_utils.h"
	+
	+/* Get the maximal value out of two typed values */
	+#define al_max_t(type, x, y) ({ \
	+ type __max1 = (x); \
	+ type __max2 = (y); \
	+ __max1 > __max2 ? __max1 : __max2; })
	+
	+/* Get the minimal value out of two typed values */
	+#define al_min_t(type, x, y) ({ \
	+ type __min1 = (x); \
	+ type __min2 = (y); \
	+ __min1 < __min2 ? __min1 : __min2; })
	+
	+/* Get the number of elements in an array */
	+#define AL_ARR_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]))
	+
	+/** @} end of Common group */
	+#endif /* __AL_HAL_COMMON_H__ */
	Index: sys/arm/annapurna/alpine/hal/al_hal_iofic.h
	===================================================================
	--- /dev/null
	+++ sys/arm/annapurna/alpine/hal/al_hal_iofic.h
	@@ -0,0 +1,222 @@
	+/*-
	+********************************************************************************
	+Copyright (C) 2015 Annapurna Labs Ltd.
	+
	+This file may be licensed under the terms of the Annapurna Labs Commercial
	+License Agreement.
	+
	+Alternatively, this file can be distributed under the terms of the GNU General
	+Public License V2 as published by the Free Software Foundation and can be
	+found at http://www.gnu.org/licenses/gpl-2.0.html
	+
	+Alternatively, redistribution and use in source and binary forms, with or
	+without modification, are permitted provided that the following conditions are
	+met:
	+
	+ * Redistributions of source code must retain the above copyright notice,
	+this list of conditions and the following disclaimer.
	+
	+ * Redistributions in binary form must reproduce the above copyright
	+notice, this list of conditions and the following disclaimer in
	+the documentation and/or other materials provided with the
	+distribution.
	+
	+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
	+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
	+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
	+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
	+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
	+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
	+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
	+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
	+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
	+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	+
	+*******************************************************************************/
	+
	+/**
	+ * @defgroup group_interrupts Common I/O Fabric Interrupt Controller
	+ * This HAL provides the API for programming the Common I/O Fabric Interrupt
	+ * Controller (IOFIC) found in most of the units attached to the I/O Fabric of
	+ * Alpine platform
	+ * @{
	+ * @file al_hal_iofic.h
	+ *
	+ * @brief Header file for the interrupt controller that's embedded in various units
	+ *
	+ */
	+
	+#ifndef __AL_HAL_IOFIC_H__
	+#define __AL_HAL_IOFIC_H__
	+
	+#include <al_hal_common.h>
	+
	+/* INDENT-OFF */
	+#ifdef __cplusplus
	+extern "C" {
	+#endif
	+/* INDENT-ON */
	+
	+#define AL_IOFIC_MAX_GROUPS 4
	+
	+/*
	+ * Configurations
	+ */
	+
	+/**
	+ * Configure the interrupt controller registers, actual interrupts are still
	+ * masked at this stage.
	+ *
	+ * @param regs_base regs pointer to interrupt controller registers
	+ * @param group the interrupt group.
	+ * @param flags flags of Interrupt Control Register
	+ *
	+ * @return 0 on success. -EINVAL otherwise.
	+ */
	+int al_iofic_config(void __iomem *regs_base, int group,
	+ uint32_t flags);
	+
	+/**
	+ * configure the moderation timer resolution for a given group
	+ * Applies for both msix and legacy mode.
	+ *
	+ * @param regs_base pointer to unit registers
	+ * @param group the interrupt group
	+ * @param resolution resolution of the timer interval, the resolution determines the rate
	+ * of decrementing the interval timer, setting value N means that the interval
	+ * timer will be decremented each (N+1) * (0.68) micro seconds.
	+ *
	+ * @return 0 on success. -EINVAL otherwise.
	+ */
	+int al_iofic_moder_res_config(void __iomem *regs_base, int group,
	+ uint8_t resolution);
	+
	+/**
	+ * configure the moderation timer interval for a given legacy interrupt group
	+ *
	+ * @param regs_base regs pointer to unit registers
	+ * @param group the interrupt group
	+ * @param interval between interrupts in resolution units. 0 disable
	+ *
	+ * @return 0 on success. -EINVAL otherwise.
	+ */
	+int al_iofic_legacy_moder_interval_config(void __iomem *regs_base, int group,
	+ uint8_t interval);
	+
	+/**
	+ * configure the moderation timer interval for a given msix vector
	+ *
	+ * @param regs_base pointer to unit registers
	+ * @param group the interrupt group
	+ * @param vector vector index
	+ * @param interval interval between interrupts, 0 disable
	+ *
	+ * @return 0 on success. -EINVAL otherwise.
	+ */
	+int al_iofic_msix_moder_interval_config(void __iomem *regs_base, int group,
	+ uint8_t vector, uint8_t interval);
	+
	+/**
	+* configure the vmid attributes for a given msix vector.
	+*
	+* @param group the interrupt group
	+* @param vector index
	+* @param vmid the vmid value
	+* @param vmid_en take vmid from the intc
	+*
	+* @return 0 on success. -EINVAL otherwise.
	+*/
	+int al_iofic_msix_vmid_attributes_config(void __iomem *regs_base, int group,
	+ uint8_t vector, uint32_t vmid, uint8_t vmid_en);
	+
	+/**
	+ * return the offset of the unmask register for a given group.
	+ * this function can be used when the upper layer wants to directly
	+ * access the unmask regiter and bypass the al_iofic_unmask() API.
	+ *
	+ * @param regs_base regs pointer to unit registers
	+ * @param group the interrupt group
	+ * @return the offset of the unmask register.
	+ */
	+uint32_t __iomem * al_iofic_unmask_offset_get(void __iomem *regs_base, int group);
	+
	+/**
	+ * unmask specific interrupts for a given group
	+ * this functions guarantees atomic operations, it is performance optimized as
	+ * it will not require read-modify-write. The unmask done using the interrupt
	+ * mask clear register, so it's safe to call it while the mask is changed by
	+ * the HW (auto mask) or another core.
	+ *
	+ * @param regs_base pointer to unit registers
	+ * @param group the interrupt group
	+ * @param mask bitwise of interrupts to unmask, set bits will be unmasked.
	+ */
	+void al_iofic_unmask(void __iomem *regs_base, int group, uint32_t mask);
	+
	+/**
	+ * mask specific interrupts for a given group
	+ * this functions modifies interrupt mask register, the callee must make sure
	+ * the mask is not changed by another cpu.
	+ *
	+ * @param regs_base pointer to unit registers
	+ * @param group the interrupt group
	+ * @param mask bitwise of interrupts to mask, set bits will be masked.
	+ */
	+void al_iofic_mask(void __iomem *regs_base, int group, uint32_t mask);
	+
	+/**
	+ * read the mask register for a given group
	+ * this functions return the interrupt mask register
	+ *
	+ * @param regs_base pointer to unit registers
	+ * @param group the interrupt group
	+ */
	+uint32_t al_iofic_read_mask(void __iomem *regs_base, int group);
	+
	+/**
	+ * read interrupt cause register for a given group
	+ * this will clear the set bits if the Clear on Read mode enabled.
	+ * @param regs_base pointer to unit registers
	+ * @param group the interrupt group
	+ */
	+uint32_t al_iofic_read_cause(void __iomem *regs_base, int group);
	+
	+/**
	+ * clear bits in the interrupt cause register for a given group
	+ *
	+ * @param regs_base pointer to unit registers
	+ * @param group the interrupt group
	+ * @param mask bitwise of bits to be cleared, set bits will be cleared.
	+ */
	+void al_iofic_clear_cause(void __iomem *regs_base, int group, uint32_t mask);
	+
	+/**
	+ * set the cause register for a given group
	+ * this function set the cause register. It will generate an interrupt (if
	+ * the the interrupt isn't masked )
	+ *
	+ * @param regs_base pointer to unit registers
	+ * @param group the interrupt group
	+ * @param mask bitwise of bits to be set.
	+ */
	+void al_iofic_set_cause(void __iomem *regs_base, int group, uint32_t mask);
	+
	+/**
	+ * unmask specific interrupts from aborting the udma a given group
	+ *
	+ * @param regs_base pointer to unit registers
	+ * @param group the interrupt group
	+ * @param mask bitwise of interrupts to mask
	+ */
	+void al_iofic_abort_mask(void __iomem *regs_base, int group, uint32_t mask);
	+
	+/**
	+ * trigger all interrupts that are waiting for moderation timers to expire
	+ *
	+ * @param regs_base pointer to unit registers
	+ * @param group the interrupt group
	+ */
	+void al_iofic_interrupt_moderation_reset(void __iomem *regs_base, int group);
	+
	+#endif
	+/** @} end of interrupt controller group */
	Index: sys/arm/annapurna/alpine/hal/al_hal_iofic_regs.h
	===================================================================
	--- /dev/null
	+++ sys/arm/annapurna/alpine/hal/al_hal_iofic_regs.h
	@@ -0,0 +1,127 @@
	+/*_
	+********************************************************************************
	+Copyright (C) 2015 Annapurna Labs Ltd.
	+
	+This file may be licensed under the terms of the Annapurna Labs Commercial
	+License Agreement.
	+
	+Alternatively, this file can be distributed under the terms of the GNU General
	+Public License V2 as published by the Free Software Foundation and can be
	+found at http://www.gnu.org/licenses/gpl-2.0.html
	+
	+Alternatively, redistribution and use in source and binary forms, with or
	+without modification, are permitted provided that the following conditions are
	+met:
	+
	+ * Redistributions of source code must retain the above copyright notice,
	+this list of conditions and the following disclaimer.
	+
	+ * Redistributions in binary form must reproduce the above copyright
	+notice, this list of conditions and the following disclaimer in
	+the documentation and/or other materials provided with the
	+distribution.
	+
	+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
	+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
	+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
	+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
	+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
	+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
	+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
	+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
	+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
	+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	+
	+*******************************************************************************/
	+
	+
	+#ifndef __AL_HAL_IOFIC_REG_H
	+#define __AL_HAL_IOFIC_REG_H
	+
	+#ifdef __cplusplus
	+extern "C" {
	+#endif
	+/*
	+* Unit Registers
	+*/
	+
	+struct al_iofic_grp_ctrl {
	+ uint32_t int_cause_grp; /* Interrupt Cause RegisterSet by hardware */
	+ uint32_t rsrvd1;
	+ uint32_t int_cause_set_grp; /* Interrupt Cause Set RegisterWriting 1 to a bit in t ... */
	+ uint32_t rsrvd2;
	+ uint32_t int_mask_grp; /* Interrupt Mask RegisterIf Auto-mask control bit =TR ... */
	+ uint32_t rsrvd3;
	+ uint32_t int_mask_clear_grp; /* Interrupt Mask Clear RegisterUsed when auto-mask co ... */
	+ uint32_t rsrvd4;
	+ uint32_t int_status_grp; /* Interrupt status RegisterThis register latch the st ... */
	+ uint32_t rsrvd5;
	+ uint32_t int_control_grp; /* Interrupt Control Register */
	+ uint32_t rsrvd6;
	+ uint32_t int_abort_msk_grp; /* Interrupt Mask RegisterEach bit in this register ma ... */
	+ uint32_t rsrvd7;
	+ uint32_t int_log_msk_grp; /* Interrupt Log RegisterEach bit in this register mas ... */
	+ uint32_t rsrvd8;
	+};
	+
	+struct al_iofic_grp_mod {
	+ uint32_t grp_int_mod_reg; /* Interrupt moderation registerDedicated moderation in ... */
	+ uint32_t grp_int_vmid_reg;
	+};
	+
	+struct al_iofic_regs {
	+ struct al_iofic_grp_ctrl ctrl[0];
	+ uint32_t rsrvd1[0x400 >> 2];
	+ struct al_iofic_grp_mod grp_int_mod[0][32];
	+};
	+
	+
	+/*
	+* Registers Fields
	+*/
	+
	+
	+/** int_control_grp register **/
	+/* When Clear_on_Read =1, All bits of Cause register ... */
	+#define INT_CONTROL_GRP_CLEAR_ON_READ (1 << 0)
	+/* (must be set only when MSIX is enabled)When Auto-Ma ... */
	+#define INT_CONTROL_GRP_AUTO_MASK (1 << 1)
	+/* Auto_Clear (RW)When Auto-Clear =1, the bits in the ... */
	+#define INT_CONTROL_GRP_AUTO_CLEAR (1 << 2)
	+/* When Set_on_Posedge =1, the bits in the interrupt c ... */
	+#define INT_CONTROL_GRP_SET_ON_POSEDGE (1 << 3)
	+/* When Moderation_Reset =1, all Moderation timers ass ... */
	+#define INT_CONTROL_GRP_MOD_RST (1 << 4)
	+/* When mask_msi_x =1, No MSI-X from this group is sen ... */
	+#define INT_CONTROL_GRP_MASK_MSI_X (1 << 5)
	+/* MSI-X AWID value, same ID for all cause bits */
	+#define INT_CONTROL_GRP_AWID_MASK 0x00000F00
	+#define INT_CONTROL_GRP_AWID_SHIFT 8
	+/* This value determines the interval between interrup ... */
	+#define INT_CONTROL_GRP_MOD_INTV_MASK 0x00FF0000
	+#define INT_CONTROL_GRP_MOD_INTV_SHIFT 16
	+/* This value determines the Moderation_Timer_Clock sp ... */
	+#define INT_CONTROL_GRP_MOD_RES_MASK 0x0F000000
	+#define INT_CONTROL_GRP_MOD_RES_SHIFT 24
	+
	+/** grp_int_mod_reg register **/
	+/* Interrupt Moderation Interval registerDedicated reg ... */
	+#define INT_MOD_INTV_MASK 0x000000FF
	+#define INT_MOD_INTV_SHIFT 0
	+
	+/** grp_int_vmid_reg register **/
	+/* Interrupt vmid value registerDedicated reg ... */
	+#define INT_MSIX_VMID_MASK 0x0000FFFF
	+#define INT_MSIX_VMID_SHIFT 0
	+/* Interrupt vmid_en value registerDedicated reg ... */
	+#define INT_MSIX_VMID_EN_SHIFT 31
	+
	+#ifdef __cplusplus
	+}
	+#endif
	+
	+#endif /* __AL_HAL_IOFIC_REG_H */
	+
	+
	+
	+
	Index: sys/arm/annapurna/alpine/hal/al_hal_nb_regs.h
	===================================================================
	--- /dev/null
	+++ sys/arm/annapurna/alpine/hal/al_hal_nb_regs.h
	@@ -0,0 +1,1823 @@
	+/*-
	+********************************************************************************
	+Copyright (C) 2015 Annapurna Labs Ltd.
	+
	+This file may be licensed under the terms of the Annapurna Labs Commercial
	+License Agreement.
	+
	+Alternatively, this file can be distributed under the terms of the GNU General
	+Public License V2 as published by the Free Software Foundation and can be
	+found at http://www.gnu.org/licenses/gpl-2.0.html
	+
	+Alternatively, redistribution and use in source and binary forms, with or
	+without modification, are permitted provided that the following conditions are
	+met:
	+
	+ * Redistributions of source code must retain the above copyright notice,
	+this list of conditions and the following disclaimer.
	+
	+ * Redistributions in binary form must reproduce the above copyright
	+notice, this list of conditions and the following disclaimer in
	+the documentation and/or other materials provided with the
	+distribution.
	+
	+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
	+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
	+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
	+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
	+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
	+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
	+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
	+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
	+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
	+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	+
	+*******************************************************************************/
	+
	+/**
	+ * @{
	+ * @file al_hal_nb_regs.h
	+ *
	+ * @brief North Bridge service registers
	+ *
	+ */
	+
	+#ifndef __AL_HAL_NB_REGS_H__
	+#define __AL_HAL_NB_REGS_H__
	+
	+#include "al_hal_plat_types.h"
	+
	+#ifdef __cplusplus
	+extern "C" {
	+#endif
	+/*
	+* Unit Registers
	+*/
	+
	+
	+
	+struct al_nb_global {
	+ /* [0x0] */
	+ uint32_t cpus_config;
	+ /* [0x4] */
	+ uint32_t cpus_secure;
	+ /* [0x8] Force init reset. */
	+ uint32_t cpus_init_control;
	+ /* [0xc] Force init reset per DECEI mode. */
	+ uint32_t cpus_init_status;
	+ /* [0x10] */
	+ uint32_t nb_int_cause;
	+ /* [0x14] */
	+ uint32_t sev_int_cause;
	+ /* [0x18] */
	+ uint32_t pmus_int_cause;
	+ /* [0x1c] */
	+ uint32_t sev_mask;
	+ /* [0x20] */
	+ uint32_t cpus_hold_reset;
	+ /* [0x24] */
	+ uint32_t cpus_software_reset;
	+ /* [0x28] */
	+ uint32_t wd_timer0_reset;
	+ /* [0x2c] */
	+ uint32_t wd_timer1_reset;
	+ /* [0x30] */
	+ uint32_t wd_timer2_reset;
	+ /* [0x34] */
	+ uint32_t wd_timer3_reset;
	+ /* [0x38] */
	+ uint32_t ddrc_hold_reset;
	+ /* [0x3c] */
	+ uint32_t fabric_software_reset;
	+ /* [0x40] */
	+ uint32_t cpus_power_ctrl;
	+ uint32_t rsrvd_0[7];
	+ /* [0x60] */
	+ uint32_t acf_base_high;
	+ /* [0x64] */
	+ uint32_t acf_base_low;
	+ /* [0x68] */
	+ uint32_t acf_control_override;
	+ /* [0x6c] Read-only that reflects CPU Cluster Local GIC base high address */
	+ uint32_t lgic_base_high;
	+ /* [0x70] Read-only that reflects CPU Cluster Local GIC base low address */
	+ uint32_t lgic_base_low;
	+ /* [0x74] Read-only that reflects the device's IOGIC base high address. */
	+ uint32_t iogic_base_high;
	+ /* [0x78] Read-only that reflects IOGIC base low address */
	+ uint32_t iogic_base_low;
	+ /* [0x7c] */
	+ uint32_t io_wr_split_control;
	+ /* [0x80] */
	+ uint32_t io_rd_rob_control;
	+ /* [0x84] */
	+ uint32_t sb_pos_error_log_1;
	+ /* [0x88] */
	+ uint32_t sb_pos_error_log_0;
	+ /* [0x8c] */
	+ uint32_t c2swb_config;
	+ /* [0x90] */
	+ uint32_t msix_error_log;
	+ /* [0x94] */
	+ uint32_t error_cause;
	+ /* [0x98] */
	+ uint32_t error_mask;
	+ uint32_t rsrvd_1;
	+ /* [0xa0] */
	+ uint32_t qos_peak_control;
	+ /* [0xa4] */
	+ uint32_t qos_set_control;
	+ /* [0xa8] */
	+ uint32_t ddr_qos;
	+ uint32_t rsrvd_2[9];
	+ /* [0xd0] */
	+ uint32_t acf_misc;
	+ /* [0xd4] */
	+ uint32_t config_bus_control;
	+ uint32_t rsrvd_3[2];
	+ /* [0xe0] */
	+ uint32_t pos_id_match;
	+ uint32_t rsrvd_4[3];
	+ /* [0xf0] */
	+ uint32_t sb_sel_override_awuser;
	+ /* [0xf4] */
	+ uint32_t sb_override_awuser;
	+ /* [0xf8] */
	+ uint32_t sb_sel_override_aruser;
	+ /* [0xfc] */
	+ uint32_t sb_override_aruser;
	+ /* [0x100] */
	+ uint32_t cpu_max_pd_timer;
	+ /* [0x104] */
	+ uint32_t cpu_max_pu_timer;
	+ uint32_t rsrvd_5[2];
	+ /* [0x110] */
	+ uint32_t auto_ddr_self_refresh_counter;
	+ uint32_t rsrvd_6[3];
	+ /* [0x120] */
	+ uint32_t coresight_pd;
	+ /* [0x124] */
	+ uint32_t coresight_internal_0;
	+ /* [0x128] */
	+ uint32_t coresight_dbgromaddr;
	+ /* [0x12c] */
	+ uint32_t coresight_dbgselfaddr;
	+ /* [0x130] */
	+ uint32_t coresght_targetid;
	+ /* [0x134] */
	+ uint32_t coresght_targetid0;
	+ uint32_t rsrvd_7[10];
	+ /* [0x160] */
	+ uint32_t sb_force_same_id_cfg_0;
	+ /* [0x164] */
	+ uint32_t sb_mstr_force_same_id_sel_0;
	+ /* [0x168] */
	+ uint32_t sb_force_same_id_cfg_1;
	+ /* [0x16c] */
	+ uint32_t sb_mstr_force_same_id_sel_1;
	+ uint32_t rsrvd[932];
	+};
	+struct al_nb_system_counter {
	+ /* [0x0] */
	+ uint32_t cnt_control;
	+ /* [0x4] */
	+ uint32_t cnt_base_freq;
	+ /* [0x8] */
	+ uint32_t cnt_low;
	+ /* [0xc] */
	+ uint32_t cnt_high;
	+ /* [0x10] */
	+ uint32_t cnt_init_low;
	+ /* [0x14] */
	+ uint32_t cnt_init_high;
	+ uint32_t rsrvd[58];
	+};
	+struct al_nb_rams_control_misc {
	+ /* [0x0] */
	+ uint32_t ca15_rf_misc;
	+ uint32_t rsrvd_0;
	+ /* [0x8] */
	+ uint32_t nb_rf_misc;
	+ uint32_t rsrvd[61];
	+};
	+struct al_nb_ca15_rams_control {
	+ /* [0x0] */
	+ uint32_t rf_0;
	+ /* [0x4] */
	+ uint32_t rf_1;
	+ /* [0x8] */
	+ uint32_t rf_2;
	+ uint32_t rsrvd;
	+};
	+struct al_nb_semaphores {
	+ /* [0x0] This configuration is only sampled during reset of the processor */
	+ uint32_t lockn;
	+};
	+struct al_nb_debug {
	+ /* [0x0] */
	+ uint32_t ca15_outputs_1;
	+ /* [0x4] */
	+ uint32_t ca15_outputs_2;
	+ uint32_t rsrvd_0[2];
	+ /* [0x10] */
	+ uint32_t cpu_msg[4];
	+ /* [0x20] */
	+ uint32_t rsv0_config;
	+ /* [0x24] */
	+ uint32_t rsv1_config;
	+ uint32_t rsrvd_1[2];
	+ /* [0x30] */
	+ uint32_t rsv0_status;
	+ /* [0x34] */
	+ uint32_t rsv1_status;
	+ uint32_t rsrvd_2[2];
	+ /* [0x40] */
	+ uint32_t ddrc;
	+ /* [0x44] */
	+ uint32_t ddrc_phy_smode_control;
	+ /* [0x48] */
	+ uint32_t ddrc_phy_smode_status;
	+ uint32_t rsrvd_3[5];
	+ /* [0x60] */
	+ uint32_t pmc;
	+ uint32_t rsrvd_4[3];
	+ /* [0x70] */
	+ uint32_t cpus_general;
	+ /* [0x74] */
	+ uint32_t cpus_general_1;
	+ uint32_t rsrvd_5[2];
	+ /* [0x80] */
	+ uint32_t cpus_int_out;
	+ uint32_t rsrvd_6[3];
	+ /* [0x90] */
	+ uint32_t latch_pc_req;
	+ uint32_t rsrvd_7;
	+ /* [0x98] */
	+ uint32_t latch_pc_low;
	+ /* [0x9c] */
	+ uint32_t latch_pc_high;
	+ uint32_t rsrvd_8[24];
	+ /* [0x100] */
	+ uint32_t track_dump_ctrl;
	+ /* [0x104] */
	+ uint32_t track_dump_rdata_0;
	+ /* [0x108] */
	+ uint32_t track_dump_rdata_1;
	+ uint32_t rsrvd_9[5];
	+ /* [0x120] */
	+ uint32_t track_events;
	+ uint32_t rsrvd_10[3];
	+ /* [0x130] */
	+ uint32_t pos_track_dump_ctrl;
	+ /* [0x134] */
	+ uint32_t pos_track_dump_rdata_0;
	+ /* [0x138] */
	+ uint32_t pos_track_dump_rdata_1;
	+ uint32_t rsrvd_11;
	+ /* [0x140] */
	+ uint32_t c2swb_track_dump_ctrl;
	+ /* [0x144] */
	+ uint32_t c2swb_track_dump_rdata_0;
	+ /* [0x148] */
	+ uint32_t c2swb_track_dump_rdata_1;
	+ uint32_t rsrvd_12;
	+ /* [0x150] */
	+ uint32_t cpus_track_dump_ctrl;
	+ /* [0x154] */
	+ uint32_t cpus_track_dump_rdata_0;
	+ /* [0x158] */
	+ uint32_t cpus_track_dump_rdata_1;
	+ uint32_t rsrvd_13;
	+ /* [0x160] */
	+ uint32_t c2swb_bar_ovrd_high;
	+ /* [0x164] */
	+ uint32_t c2swb_bar_ovrd_low;
	+ uint32_t rsrvd[38];
	+};
	+struct al_nb_cpun_config_status {
	+ /* [0x0] This configuration is only sampled during reset of the processor. */
	+ uint32_t config;
	+ /* [0x4] This configuration is only sampled during reset of the processor. */
	+ uint32_t config_aarch64;
	+ /* [0x8] */
	+ uint32_t local_cause_mask;
	+ uint32_t rsrvd_0;
	+ /* [0x10] */
	+ uint32_t pmus_cause_mask;
	+ /* [0x14] */
	+ uint32_t sei_cause_mask;
	+ uint32_t rsrvd_1[2];
	+ /* [0x20] Specifies the state of the CPU with reference to power modes. */
	+ uint32_t power_ctrl;
	+ /* [0x24] */
	+ uint32_t power_status;
	+ /* [0x28] */
	+ uint32_t resume_addr_l;
	+ /* [0x2c] */
	+ uint32_t resume_addr_h;
	+ uint32_t rsrvd_2[4];
	+ /* [0x40] */
	+ uint32_t warm_rst_ctl;
	+ uint32_t rsrvd_3;
	+ /* [0x48] */
	+ uint32_t rvbar_low;
	+ /* [0x4c] */
	+ uint32_t rvbar_high;
	+ /* [0x50] */
	+ uint32_t pmu_snapshot;
	+ uint32_t rsrvd_4[3];
	+ /* [0x60] */
	+ uint32_t cpu_msg_in;
	+ uint32_t rsrvd[39];
	+};
	+struct al_nb_mc_pmu {
	+ /* [0x0] PMU Global Control Register */
	+ uint32_t pmu_control;
	+ /* [0x4] PMU Global Control Register */
	+ uint32_t overflow;
	+ uint32_t rsrvd[62];
	+};
	+struct al_nb_mc_pmu_counters {
	+ /* [0x0] Counter Configuration Register */
	+ uint32_t cfg;
	+ /* [0x4] Counter Control Register */
	+ uint32_t cntl;
	+ /* [0x8] Counter Control Register */
	+ uint32_t low;
	+ /* [0xc] Counter Control Register */
	+ uint32_t high;
	+ uint32_t rsrvd[4];
	+};
	+struct al_nb_nb_version {
	+ /* [0x0] Northbridge Revision */
	+ uint32_t version;
	+ uint32_t rsrvd;
	+};
	+struct al_nb_sriov {
	+ /* [0x0] */
	+ uint32_t cpu_vmid[4];
	+ uint32_t rsrvd[4];
	+};
	+struct al_nb_dram_channels {
	+ /* [0x0] */
	+ uint32_t dram_0_control;
	+ uint32_t rsrvd_0;
	+ /* [0x8] */
	+ uint32_t dram_0_status;
	+ uint32_t rsrvd_1;
	+ /* [0x10] */
	+ uint32_t ddr_int_cause;
	+ uint32_t rsrvd_2;
	+ /* [0x18] */
	+ uint32_t ddr_cause_mask;
	+ uint32_t rsrvd_3;
	+ /* [0x20] */
	+ uint32_t address_map;
	+ uint32_t rsrvd_4[3];
	+ /* [0x30] */
	+ uint32_t reorder_id_mask_0;
	+ /* [0x34] */
	+ uint32_t reorder_id_value_0;
	+ /* [0x38] */
	+ uint32_t reorder_id_mask_1;
	+ /* [0x3c] */
	+ uint32_t reorder_id_value_1;
	+ /* [0x40] */
	+ uint32_t reorder_id_mask_2;
	+ /* [0x44] */
	+ uint32_t reorder_id_value_2;
	+ /* [0x48] */
	+ uint32_t reorder_id_mask_3;
	+ /* [0x4c] */
	+ uint32_t reorder_id_value_3;
	+ /* [0x50] */
	+ uint32_t mrr_control_status;
	+ uint32_t rsrvd[43];
	+};
	+struct al_nb_ddr_0_mrr {
	+ /* [0x0] Counter Configuration Register */
	+ uint32_t val;
	+};
	+struct al_nb_push_packet {
	+ /* [0x0] */
	+ uint32_t pp_config;
	+ uint32_t rsrvd_0[3];
	+ /* [0x10] */
	+ uint32_t pp_ext_awuser;
	+ uint32_t rsrvd_1[3];
	+ /* [0x20] */
	+ uint32_t pp_base_low;
	+ /* [0x24] */
	+ uint32_t pp_base_high;
	+ uint32_t rsrvd_2[2];
	+ /* [0x30] */
	+ uint32_t pp_sel_awuser;
	+ uint32_t rsrvd[51];
	+};
	+
	+struct al_nb_regs {
	+ struct al_nb_global global; /* [0x0] */
	+ struct al_nb_system_counter system_counter; /* [0x1000] */
	+ struct al_nb_rams_control_misc rams_control_misc; /* [0x1100] */
	+ struct al_nb_ca15_rams_control ca15_rams_control[5]; /* [0x1200] */
	+ uint32_t rsrvd_0[108];
	+ struct al_nb_semaphores semaphores[64]; /* [0x1400] */
	+ uint32_t rsrvd_1[320];
	+ struct al_nb_debug debug; /* [0x1a00] */
	+ uint32_t rsrvd_2[256];
	+ struct al_nb_cpun_config_status cpun_config_status[4]; /* [0x2000] */
	+ uint32_t rsrvd_3[1792];
	+ struct al_nb_mc_pmu mc_pmu; /* [0x4000] */
	+ struct al_nb_mc_pmu_counters mc_pmu_counters[4]; /* [0x4100] */
	+ uint32_t rsrvd_4[160];
	+ struct al_nb_nb_version nb_version; /* [0x4400] */
	+ uint32_t rsrvd_5[126];
	+ struct al_nb_sriov sriov; /* [0x4600] */
	+ uint32_t rsrvd_6[120];
	+ struct al_nb_dram_channels dram_channels; /* [0x4800] */
	+ struct al_nb_ddr_0_mrr ddr_0_mrr[9]; /* [0x4900] */
	+ uint32_t rsrvd_7[439];
	+ uint32_t rsrvd_8[1024]; /* [0x5000] */
	+ struct al_nb_push_packet push_packet; /* [0x6000] */
	+};
	+
	+
	+/*
	+* Registers Fields
	+*/
	+
	+
	+/** CPUs_Config register **/
	+/* Disable broadcast of barrier onto system bus.
	+Connect to Processor Cluster SYSBARDISABLE. */
	+#define NB_GLOBAL_CPUS_CONFIG_SYSBARDISABLE (1 << 0)
	+/* Enable broadcast of inner shareable transactions from CPUs.
	+Connect to Processor Cluster BROADCASTINNER. */
	+#define NB_GLOBAL_CPUS_CONFIG_BROADCASTINNER (1 << 1)
	+/* Disable broadcast of cache maintenance system bus.
	+Connect to Processor Cluster BROADCASTCACHEMAIN */
	+#define NB_GLOBAL_CPUS_CONFIG_BROADCASTCACHEMAINT (1 << 2)
	+/* Enable broadcast of outer shareable transactions from CPUs.
	+Connect to Processor Cluster BROADCASTOUTER. */
	+#define NB_GLOBAL_CPUS_CONFIG_BROADCASTOUTER (1 << 3)
	+/* Defines the internal CPU GIC operating frequency ratio with the main CPU clock.
	+0x0: 1:1
	+0x1: 1:2
	+0x2: 1:3
	+0x3: 1:4
	+
	+Note: This is not in used with CA57 */
	+#define NB_GLOBAL_CPUS_CONFIG_PERIPHCLKEN_MASK 0x00000030
	+#define NB_GLOBAL_CPUS_CONFIG_PERIPHCLKEN_SHIFT 4
	+/* Disables the GIC CPU interface logic and routes the legacy nIRQ, nFIQ, nVIRQ, and nVFIQ
	+signals directly to the processor:
	+0 Enable the GIC CPU interface logic.
	+1 Disable the GIC CPU interface logic.
	+The processor only samples this signal as it exits reset. */
	+#define NB_GLOBAL_CPUS_CONFIG_GIC_DISABLE (1 << 6)
	+/* Disable L1 data cache and L2 snoop tag RAMs automatic invalidate on reset functionality */
	+#define NB_GLOBAL_CPUS_CONFIG_DBG_L1_RESET_DISABLE (1 << 7)
	+/* Value read in the Cluster ID Affinity Level-1 field, bits[15:8], of the Multiprocessor Affinity
	+Register (MPIDR).
	+This signal is only sampled during reset of the processor. */
	+#define NB_GLOBAL_CPUS_CONFIG_CLUSTERIDAFF1_MASK 0x00FF0000
	+#define NB_GLOBAL_CPUS_CONFIG_CLUSTERIDAFF1_SHIFT 16
	+/* Value read in the Cluster ID Affinity Level-2 field, bits[23:16], of the Multiprocessor Affinity
	+Register (MPIDR).
	+This signal is only sampled during reset of the processor.. */
	+#define NB_GLOBAL_CPUS_CONFIG_CLUSTERIDAFF2_MASK 0xFF000000
	+#define NB_GLOBAL_CPUS_CONFIG_CLUSTERIDAFF2_SHIFT 24
	+
	+/** CPUs_Secure register **/
	+/* DBGEN
	+ */
	+#define NB_GLOBAL_CPUS_SECURE_DBGEN (1 << 0)
	+/* NIDEN
	+ */
	+#define NB_GLOBAL_CPUS_SECURE_NIDEN (1 << 1)
	+/* SPIDEN
	+ */
	+#define NB_GLOBAL_CPUS_SECURE_SPIDEN (1 << 2)
	+/* SPNIDEN
	+ */
	+#define NB_GLOBAL_CPUS_SECURE_SPNIDEN (1 << 3)
	+/* Disable write access to some secure GIC registers */
	+#define NB_GLOBAL_CPUS_SECURE_CFGSDISABLE (1 << 4)
	+/* Disable write access to some secure IOGIC registers */
	+#define NB_GLOBAL_CPUS_SECURE_IOGIC_CFGSDISABLE (1 << 5)
	+
	+/** CPUs_Init_Control register **/
	+/* CPU Init Done
	+Specifies which CPUs' inits are done and can exit poreset.
	+By default, CPU0 only exits poreset when the CPUs cluster exits power-on-reset and then kicks other CPUs.
	+If this bit is cleared for a specific CPU, setting it by primary CPU as part of the initialization process will initiate power-on-reset to this specific CPU. */
	+#define NB_GLOBAL_CPUS_INIT_CONTROL_CPUS_INITDONE_MASK 0x0000000F
	+#define NB_GLOBAL_CPUS_INIT_CONTROL_CPUS_INITDONE_SHIFT 0
	+/* DBGPWRDNREQ Mask
	+When CPU does not exist, its DBGPWRDNREQ must be asserted.
	+If corresponding mask bit is set, the DBGPWDNREQ is deasserted. */
	+#define NB_GLOBAL_CPUS_INIT_CONTROL_DBGPWRDNREQ_MASK_MASK 0x000000F0
	+#define NB_GLOBAL_CPUS_INIT_CONTROL_DBGPWRDNREQ_MASK_SHIFT 4
	+/* Force CPU init power-on-reset exit.
	+For debug purposes only. */
	+#define NB_GLOBAL_CPUS_INIT_CONTROL_FORCE_CPUPOR_MASK 0x00000F00
	+#define NB_GLOBAL_CPUS_INIT_CONTROL_FORCE_CPUPOR_SHIFT 8
	+/* Force dbgpwrdup signal high
	+If dbgpwrdup is clear on the processor interface it indicates that the process debug resources are not available for APB access. */
	+#define NB_GLOBAL_CPUS_INIT_CONTROL_FORCE_DBGPWRDUP_MASK 0x0000F000
	+#define NB_GLOBAL_CPUS_INIT_CONTROL_FORCE_DBGPWRDUP_SHIFT 12
	+
	+/** CPUs_Init_Status register **/
	+/* Specifies which CPUs are enabled in the device configuration.
	+sample at rst_cpus_exist[3:0] reset strap. */
	+#define NB_GLOBAL_CPUS_INIT_STATUS_CPUS_EXIST_MASK 0x0000000F
	+#define NB_GLOBAL_CPUS_INIT_STATUS_CPUS_EXIST_SHIFT 0
	+
	+/** NB_Int_Cause register **/
	+/*
	+ * Each bit corresponds to an IRQ.
	+ * value is 1 for level irq, 0 for trigger irq
	+ * Level IRQ indices: 12-13, 23, 24, 26-29
	+ */
	+#define NB_GLOBAL_NB_INT_CAUSE_LEVEL_IRQ_MASK 0x3D803000
	+/* Cross trigger interrupt */
	+#define NB_GLOBAL_NB_INT_CAUSE_NCTIIRQ_MASK 0x0000000F
	+#define NB_GLOBAL_NB_INT_CAUSE_NCTIIRQ_SHIFT 0
	+/* Communications channel receive. Receive portion of Data Transfer Register full flag */
	+#define NB_GLOBAL_NB_INT_CAUSE_COMMRX_MASK 0x000000F0
	+#define NB_GLOBAL_NB_INT_CAUSE_COMMRX_SHIFT 4
	+/* Communication channel transmit. Transmit portion of Data Transfer Register empty flag. */
	+#define NB_GLOBAL_NB_INT_CAUSE_COMMTX_MASK 0x00000F00
	+#define NB_GLOBAL_NB_INT_CAUSE_COMMTX_SHIFT 8
	+/* Reserved, read undefined must write as zeros. */
	+#define NB_GLOBAL_NB_INT_CAUSE_RESERVED_15_15 (1 << 15)
	+/* Error indicator for AXI write transactions with a BRESP error condition. Writing 0 to bit[29] of the L2ECTLR clears the error indicator connected to CA15 nAXIERRIRQ. */
	+#define NB_GLOBAL_NB_INT_CAUSE_CPU_AXIERRIRQ (1 << 16)
	+/* Error indicator for: L2 RAM double-bit ECC error, illegal writes to the GIC memory-map region. */
	+#define NB_GLOBAL_NB_INT_CAUSE_CPU_INTERRIRQ (1 << 17)
	+/* Coherent fabric error summary interrupt */
	+#define NB_GLOBAL_NB_INT_CAUSE_ACF_ERRORIRQ (1 << 18)
	+/* DDR Controller ECC Correctable error summary interrupt */
	+#define NB_GLOBAL_NB_INT_CAUSE_MCTL_ECC_CORR_ERR (1 << 19)
	+/* DDR Controller ECC Uncorrectable error summary interrupt */
	+#define NB_GLOBAL_NB_INT_CAUSE_MCTL_ECC_UNCORR_ERR (1 << 20)
	+/* DRAM parity error interrupt */
	+#define NB_GLOBAL_NB_INT_CAUSE_MCTL_PARITY_ERR (1 << 21)
	+/* Reserved, not functional */
	+#define NB_GLOBAL_NB_INT_CAUSE_MCTL_WDATARAM_PAR (1 << 22)
	+/* Error cause summary interrupt */
	+#define NB_GLOBAL_NB_INT_CAUSE_ERR_CAUSE_SUM_A0 (1 << 23)
	+/* SB PoS error */
	+#define NB_GLOBAL_NB_INT_CAUSE_SB_POS_ERR (1 << 24)
	+/* Received msix is not mapped to local GIC or IO-GIC spin */
	+#define NB_GLOBAL_NB_INT_CAUSE_MSIX_ERR_INT_M0 (1 << 25)
	+/* Coresight timestamp overflow */
	+#define NB_GLOBAL_NB_INT_CAUSE_CORESIGHT_TS_OVERFLOW_M0 (1 << 26)
	+
	+/** SEV_Int_Cause register **/
	+/* SMMU 0/1 global non-secure fault interrupt */
	+#define NB_GLOBAL_SEV_INT_CAUSE_SMMU_GBL_FLT_IRPT_NS_MASK 0x00000003
	+#define NB_GLOBAL_SEV_INT_CAUSE_SMMU_GBL_FLT_IRPT_NS_SHIFT 0
	+/* SMMU 0/1 non-secure context interrupt */
	+#define NB_GLOBAL_SEV_INT_CAUSE_SMMU_CXT_IRPT_NS_MASK 0x0000000C
	+#define NB_GLOBAL_SEV_INT_CAUSE_SMMU_CXT_IRPT_NS_SHIFT 2
	+/* SMMU0/1 Non-secure configuration access fault interrupt */
	+#define NB_GLOBAL_SEV_INT_CAUSE_SMMU_CFG_FLT_IRPT_S_MASK 0x00000030
	+#define NB_GLOBAL_SEV_INT_CAUSE_SMMU_CFG_FLT_IRPT_S_SHIFT 4
	+/* Reserved. Read undefined; must write as zeros. */
	+#define NB_GLOBAL_SEV_INT_CAUSE_RESERVED_11_6_MASK 0x00000FC0
	+#define NB_GLOBAL_SEV_INT_CAUSE_RESERVED_11_6_SHIFT 6
	+/* Reserved. Read undefined; must write as zeros. */
	+#define NB_GLOBAL_SEV_INT_CAUSE_RESERVED_31_20_MASK 0xFFF00000
	+#define NB_GLOBAL_SEV_INT_CAUSE_RESERVED_31_20_SHIFT 20
	+
	+/** PMUs_Int_Cause register **/
	+/* CPUs PMU Overflow interrupt */
	+#define NB_GLOBAL_PMUS_INT_CAUSE_CPUS_OVFL_MASK 0x0000000F
	+#define NB_GLOBAL_PMUS_INT_CAUSE_CPUS_OVFL_SHIFT 0
	+/* Northbridge PMU overflow */
	+#define NB_GLOBAL_PMUS_INT_CAUSE_NB_OVFL (1 << 4)
	+/* Memory Controller PMU overflow */
	+#define NB_GLOBAL_PMUS_INT_CAUSE_MCTL_OVFL (1 << 5)
	+/* Coherency Interconnect PMU overflow */
	+#define NB_GLOBAL_PMUS_INT_CAUSE_CCI_OVFL_MASK 0x000007C0
	+#define NB_GLOBAL_PMUS_INT_CAUSE_CCI_OVFL_SHIFT 6
	+/* Coherency Interconnect PMU overflow */
	+#define NB_GLOBAL_PMUS_INT_CAUSE_SMMU_OVFL_MASK 0x00001800
	+#define NB_GLOBAL_PMUS_INT_CAUSE_SMMU_OVFL_SHIFT 11
	+/* Reserved. Read undefined; must write as zeros. */
	+#define NB_GLOBAL_PMUS_INT_CAUSE_RESERVED_23_13_MASK 0x00FFE000
	+#define NB_GLOBAL_PMUS_INT_CAUSE_RESERVED_23_13_SHIFT 13
	+/* Southbridge PMUs overflow */
	+#define NB_GLOBAL_PMUS_INT_CAUSE_SB_PMUS_OVFL_MASK 0xFF000000
	+#define NB_GLOBAL_PMUS_INT_CAUSE_SB_PMUS_OVFL_SHIFT 24
	+
	+/** CPUs_Hold_Reset register **/
	+/* Shared L2 memory system, interrupt controller and timer logic reset.
	+Reset is applied only when all processors are in STNDBYWFI state. */
	+#define NB_GLOBAL_CPUS_HOLD_RESET_L2RESET (1 << 0)
	+/* Shared debug domain reset */
	+#define NB_GLOBAL_CPUS_HOLD_RESET_PRESETDBG (1 << 1)
	+/* Individual CPU debug, PTM, watchpoint and breakpoint logic reset */
	+#define NB_GLOBAL_CPUS_HOLD_RESET_CPU_DBGRESET_MASK 0x000000F0
	+#define NB_GLOBAL_CPUS_HOLD_RESET_CPU_DBGRESET_SHIFT 4
	+/* Individual CPU core and VFP/NEON logic reset.
	+Reset is applied only when specific CPU is in STNDBYWFI state. */
	+#define NB_GLOBAL_CPUS_HOLD_RESET_CPU_CORERESET_MASK 0x00000F00
	+#define NB_GLOBAL_CPUS_HOLD_RESET_CPU_CORERESET_SHIFT 8
	+/* Individual CPU por-on-reset.
	+Reset is applied only when specific CPU is in STNDBYWFI state. */
	+#define NB_GLOBAL_CPUS_HOLD_RESET_CPU_PORESET_MASK 0x0000F000
	+#define NB_GLOBAL_CPUS_HOLD_RESET_CPU_PORESET_SHIFT 12
	+/* Wait for interrupt mask.
	+If set, reset is applied without waiting for the specified CPU's STNDBYWFI state. */
	+#define NB_GLOBAL_CPUS_HOLD_RESET_WFI_MASK_MASK 0x000F0000
	+#define NB_GLOBAL_CPUS_HOLD_RESET_WFI_MASK_SHIFT 16
	+
	+/** CPUs_Software_Reset register **/
	+/* Write 1. Apply the software reset. */
	+#define NB_GLOBAL_CPUS_SOFTWARE_RESET_SWRESET_REQ (1 << 0)
	+/* Defines the level of software reset.
	+0x0 - cpu_core: Individual CPU core reset.
	+0x1 - cpu_poreset: Individual CPU power-on-reset.
	+0x2 - cpu_dbg: Individual CPU debug reset.
	+0x3 - cluster_no_dbg: A Cluster reset puts each core into core reset (no dbg) and also resets the interrupt controller and L2 logic.
	+0x4 - cluster: A Cluster reset puts each core into power-on-reset and also resets the interrupt controller and L2 logic. Debug is active.
	+0x5 - cluster_poreset: A Cluster power-on-reset puts each core into power-on-reset and also resets the interrupt controller and L2 logic. This include the cluster debug logic. */
	+#define NB_GLOBAL_CPUS_SOFTWARE_RESET_LEVEL_MASK 0x0000000E
	+#define NB_GLOBAL_CPUS_SOFTWARE_RESET_LEVEL_SHIFT 1
	+/* Individual CPU core reset. */
	+#define NB_GLOBAL_CPUS_SOFTWARE_RESET_LEVEL_CPU_CORE \
	+ (0x0 << NB_GLOBAL_CPUS_SOFTWARE_RESET_LEVEL_SHIFT)
	+/* Individual CPU power-on-reset. */
	+#define NB_GLOBAL_CPUS_SOFTWARE_RESET_LEVEL_CPU_PORESET \
	+ (0x1 << NB_GLOBAL_CPUS_SOFTWARE_RESET_LEVEL_SHIFT)
	+/* Individual CPU debug reset. */
	+#define NB_GLOBAL_CPUS_SOFTWARE_RESET_LEVEL_CPU_DBG \
	+ (0x2 << NB_GLOBAL_CPUS_SOFTWARE_RESET_LEVEL_SHIFT)
	+/* A Cluster reset puts each core into core reset (no dbg) and a ... */
	+#define NB_GLOBAL_CPUS_SOFTWARE_RESET_LEVEL_CLUSTER_NO_DBG \
	+ (0x3 << NB_GLOBAL_CPUS_SOFTWARE_RESET_LEVEL_SHIFT)
	+/* A Cluster reset puts each core into power-on-reset and also r ... */
	+#define NB_GLOBAL_CPUS_SOFTWARE_RESET_LEVEL_CLUSTER \
	+ (0x4 << NB_GLOBAL_CPUS_SOFTWARE_RESET_LEVEL_SHIFT)
	+/* A Cluster power-on-reset puts each core into power-on-reset a ... */
	+#define NB_GLOBAL_CPUS_SOFTWARE_RESET_LEVEL_CLUSTER_PORESET \
	+ (0x5 << NB_GLOBAL_CPUS_SOFTWARE_RESET_LEVEL_SHIFT)
	+/* Defines which cores to reset when no cluster_poreset is requested. */
	+#define NB_GLOBAL_CPUS_SOFTWARE_RESET_CORES_MASK 0x000000F0
	+#define NB_GLOBAL_CPUS_SOFTWARE_RESET_CORES_SHIFT 4
	+/* CPUn wait for interrupt enable.
	+Defines which CPU WFI indication to wait for before applying the software reset. */
	+#define NB_GLOBAL_CPUS_SOFTWARE_RESET_WFI_MASK_MASK 0x000F0000
	+#define NB_GLOBAL_CPUS_SOFTWARE_RESET_WFI_MASK_SHIFT 16
	+
	+/** WD_Timer0_Reset register **/
	+/* Shared L2 memory system, interrupt controller and timer logic reset */
	+#define NB_GLOBAL_WD_TIMER0_RESET_L2RESET (1 << 0)
	+/* Shared debug domain reset */
	+#define NB_GLOBAL_WD_TIMER0_RESET_PRESETDBG (1 << 1)
	+/* Individual CPU debug PTM, watchpoint and breakpoint logic reset */
	+#define NB_GLOBAL_WD_TIMER0_RESET_CPU_DBGRESET_MASK 0x000000F0
	+#define NB_GLOBAL_WD_TIMER0_RESET_CPU_DBGRESET_SHIFT 4
	+/* Individual CPU core and VFP/NEON logic reset */
	+#define NB_GLOBAL_WD_TIMER0_RESET_CPU_CORERESET_MASK 0x00000F00
	+#define NB_GLOBAL_WD_TIMER0_RESET_CPU_CORERESET_SHIFT 8
	+/* Individual CPU por-on-reset */
	+#define NB_GLOBAL_WD_TIMER0_RESET_CPU_PORESET_MASK 0x0000F000
	+#define NB_GLOBAL_WD_TIMER0_RESET_CPU_PORESET_SHIFT 12
	+
	+/** WD_Timer1_Reset register **/
	+/* Shared L2 memory system, interrupt controller and timer logic reset */
	+#define NB_GLOBAL_WD_TIMER1_RESET_L2RESET (1 << 0)
	+/* Shared debug domain reset */
	+#define NB_GLOBAL_WD_TIMER1_RESET_PRESETDBG (1 << 1)
	+/* Individual CPU debug PTM, watchpoint and breakpoint logic reset */
	+#define NB_GLOBAL_WD_TIMER1_RESET_CPU_DBGRESET_MASK 0x000000F0
	+#define NB_GLOBAL_WD_TIMER1_RESET_CPU_DBGRESET_SHIFT 4
	+/* Individual CPU core and VFP/NEON logic reset */
	+#define NB_GLOBAL_WD_TIMER1_RESET_CPU_CORERESET_MASK 0x00000F00
	+#define NB_GLOBAL_WD_TIMER1_RESET_CPU_CORERESET_SHIFT 8
	+/* Individual CPU por-on-reset */
	+#define NB_GLOBAL_WD_TIMER1_RESET_CPU_PORESET_MASK 0x0000F000
	+#define NB_GLOBAL_WD_TIMER1_RESET_CPU_PORESET_SHIFT 12
	+
	+/** WD_Timer2_Reset register **/
	+/* Shared L2 memory system, interrupt controller and timer logic reset */
	+#define NB_GLOBAL_WD_TIMER2_RESET_L2RESET (1 << 0)
	+/* Shared debug domain reset */
	+#define NB_GLOBAL_WD_TIMER2_RESET_PRESETDBG (1 << 1)
	+/* Individual CPU debug, PTM, watchpoint and breakpoint logic reset */
	+#define NB_GLOBAL_WD_TIMER2_RESET_CPU_DBGRESET_MASK 0x000000F0
	+#define NB_GLOBAL_WD_TIMER2_RESET_CPU_DBGRESET_SHIFT 4
	+/* Individual CPU core and VFP/NEON logic reset */
	+#define NB_GLOBAL_WD_TIMER2_RESET_CPU_CORERESET_MASK 0x00000F00
	+#define NB_GLOBAL_WD_TIMER2_RESET_CPU_CORERESET_SHIFT 8
	+/* Individual CPU por-on-reset */
	+#define NB_GLOBAL_WD_TIMER2_RESET_CPU_PORESET_MASK 0x0000F000
	+#define NB_GLOBAL_WD_TIMER2_RESET_CPU_PORESET_SHIFT 12
	+
	+/** WD_Timer3_Reset register **/
	+/* Shared L2 memory system, interrupt controller and timer logic reset */
	+#define NB_GLOBAL_WD_TIMER3_RESET_L2RESET (1 << 0)
	+/* Shared debug domain reset */
	+#define NB_GLOBAL_WD_TIMER3_RESET_PRESETDBG (1 << 1)
	+/* Individual CPU debug, PTM, watchpoint and breakpoint logic reset */
	+#define NB_GLOBAL_WD_TIMER3_RESET_CPU_DBGRESET_MASK 0x000000F0
	+#define NB_GLOBAL_WD_TIMER3_RESET_CPU_DBGRESET_SHIFT 4
	+/* Individual CPU core and VFP/NEON logic reset */
	+#define NB_GLOBAL_WD_TIMER3_RESET_CPU_CORERESET_MASK 0x00000F00
	+#define NB_GLOBAL_WD_TIMER3_RESET_CPU_CORERESET_SHIFT 8
	+/* Individual CPU por-on-reset */
	+#define NB_GLOBAL_WD_TIMER3_RESET_CPU_PORESET_MASK 0x0000F000
	+#define NB_GLOBAL_WD_TIMER3_RESET_CPU_PORESET_SHIFT 12
	+
	+/** DDRC_Hold_Reset register **/
	+/* DDR Control and PHY memory mapped registers reset control
	+0 - Reset is deasserted.
	+1 - Reset is asserted (active). */
	+#define NB_GLOBAL_DDRC_HOLD_RESET_APB_SYNC_RESET (1 << 0)
	+/* DDR Control Core reset control
	+0 - Reset is deasserted.
	+1 - Reset is asserted.
	+This field must be set to 0 to start the initialization process after configuring the DDR Controller registers. */
	+#define NB_GLOBAL_DDRC_HOLD_RESET_CORE_SYNC_RESET (1 << 1)
	+/* DDR Control AXI Interface reset control
	+0 - Reset is deasserted.
	+1 - Reset is asserted.
	+This field must not be set to 0 while core_sync_reset is set to 1. */
	+#define NB_GLOBAL_DDRC_HOLD_RESET_AXI_SYNC_RESET (1 << 2)
	+/* DDR PUB Controller reset control
	+0 - Reset is deasserted.
	+1 - Reset is asserted.
	+This field must be set to 0 to start the initialization process after configuring the PUB Controller registers. */
	+#define NB_GLOBAL_DDRC_HOLD_RESET_PUB_CTL_SYNC_RESET (1 << 3)
	+/* DDR PUB SDR Controller reset control
	+0 - Reset is deasserted.
	+1 - Reset is asserted.
	+This field must be set to 0 to start the initialization process after configuring the PUB Controller registers. */
	+#define NB_GLOBAL_DDRC_HOLD_RESET_PUB_SDR_SYNC_RESET (1 << 4)
	+/* DDR PHY reset control
	+0 - Reset is deasserted.
	+1 - Reset is asserted. */
	+#define NB_GLOBAL_DDRC_HOLD_RESET_PHY_SYNC_RESET (1 << 5)
	+/* Memory initialization input to DDR SRAM for parity check support */
	+#define NB_GLOBAL_DDRC_HOLD_RESET_DDR_UNIT_MEM_INIT (1 << 6)
	+
	+/** Fabric_Software_Reset register **/
	+/* Write 1 apply the software reset. */
	+#define NB_GLOBAL_FABRIC_SOFTWARE_RESET_SWRESET_REQ (1 << 0)
	+/* Defines the level of software reset:
	+0x0 - fabric: Fabric reset
	+0x1 - gic: GIC reset
	+0x2 - smmu: SMMU reset */
	+#define NB_GLOBAL_FABRIC_SOFTWARE_RESET_LEVEL_MASK 0x0000000E
	+#define NB_GLOBAL_FABRIC_SOFTWARE_RESET_LEVEL_SHIFT 1
	+/* Fabric reset */
	+#define NB_GLOBAL_FABRIC_SOFTWARE_RESET_LEVEL_FABRIC \
	+ (0x0 << NB_GLOBAL_FABRIC_SOFTWARE_RESET_LEVEL_SHIFT)
	+/* GIC reset */
	+#define NB_GLOBAL_FABRIC_SOFTWARE_RESET_LEVEL_GIC \
	+ (0x1 << NB_GLOBAL_FABRIC_SOFTWARE_RESET_LEVEL_SHIFT)
	+/* SMMU reset */
	+#define NB_GLOBAL_FABRIC_SOFTWARE_RESET_LEVEL_SMMU \
	+ (0x2 << NB_GLOBAL_FABRIC_SOFTWARE_RESET_LEVEL_SHIFT)
	+/* CPUn waiting for interrupt enable.
	+Defines which CPU WFI indication to wait before applying the software reset. */
	+#define NB_GLOBAL_FABRIC_SOFTWARE_RESET_WFI_MASK_MASK 0x000F0000
	+#define NB_GLOBAL_FABRIC_SOFTWARE_RESET_WFI_MASK_SHIFT 16
	+
	+/** CPUs_Power_Ctrl register **/
	+/* L2 WFI enable
	+When all the processors are in WFI mode or powered-down, the shared L2 memory system Power Management controller resumes clock on any interrupt.
	+Power management controller resumes clock on snoop request.
	+NOT IMPLEMENTED */
	+#define NB_GLOBAL_CPUS_POWER_CTRL_L2WFI_EN (1 << 0)
	+/* L2 WFI status */
	+#define NB_GLOBAL_CPUS_POWER_CTRL_L2WFI_STATUS (1 << 1)
	+/* L2 RAMs Power Down
	+Power down the L2 RAMs. L2 caches must be flushed prior to entering this state. */
	+#define NB_GLOBAL_CPUS_POWER_CTRL_L2RAMS_PWRDN_EN (1 << 2)
	+/* L2 RAMs power down status */
	+#define NB_GLOBAL_CPUS_POWER_CTRL_L2RAMS_PWRDN_STATUS (1 << 3)
	+/* CPU state condition to enable L2 RAM power down
	+0 - Power down
	+1 - WFI
	+NOT IMPLEMENTED */
	+#define NB_GLOBAL_CPUS_POWER_CTRL_L2RAMS_PWRDN_CPUS_STATE_MASK 0x000000F0
	+#define NB_GLOBAL_CPUS_POWER_CTRL_L2RAMS_PWRDN_CPUS_STATE_SHIFT 4
	+/* Enable external debugger over power-down.
	+Provides support for external debug over power down. If any or all of the processors are powered down, the SoC can still use the debug facilities if the debug PCLKDBG domain is powered up. */
	+#define NB_GLOBAL_CPUS_POWER_CTRL_EXT_DEBUGGER_OVER_PD_EN (1 << 8)
	+/* L2 hardware flush request. This signal indicates:
	+0 L2 hardware flush request is not asserted. flush is performed by SW
	+1 L2 hardware flush request is asserted by power management block as part of cluster rams power down flow. HW starts L2 flush flow when all CPUs are in WFI */
	+#define NB_GLOBAL_CPUS_POWER_CTRL_L2FLUSH_EN (1 << 9)
	+/* Force wakeup the CPU in L2RAM power down
	+INTERNAL DEBUG PURPOSE ONLY */
	+#define NB_GLOBAL_CPUS_POWER_CTRL_FORCE_CPUS_OK_PWRUP (1 << 27)
	+/* L2 RAMs power down SM status */
	+#define NB_GLOBAL_CPUS_POWER_CTRL_L2RAMS_PWRDN_SM_STATUS_MASK 0xF0000000
	+#define NB_GLOBAL_CPUS_POWER_CTRL_L2RAMS_PWRDN_SM_STATUS_SHIFT 28
	+
	+/** ACF_Base_High register **/
	+/* Coherency Fabric registers base [39:32]. */
	+#define NB_GLOBAL_ACF_BASE_HIGH_BASE_39_32_MASK 0x000000FF
	+#define NB_GLOBAL_ACF_BASE_HIGH_BASE_39_32_SHIFT 0
	+/* Coherency Fabric registers base [31:15] */
	+#define NB_GLOBAL_ACF_BASE_LOW_BASED_31_15_MASK 0xFFFF8000
	+#define NB_GLOBAL_ACF_BASE_LOW_BASED_31_15_SHIFT 15
	+
	+/** ACF_Control_Override register **/
	+/* Override the AWCACHE[0] and ARCACHE[0] outputs to be
	+non-bufferable. One bit exists for each master interface.
	+Connected to BUFFERABLEOVERRIDE[2:0] */
	+#define NB_GLOBAL_ACF_CONTROL_OVERRIDE_BUFFOVRD_MASK 0x00000007
	+#define NB_GLOBAL_ACF_CONTROL_OVERRIDE_BUFFOVRD_SHIFT 0
	+/* Overrides the ARQOS and AWQOS input signals. One bit exists for each slave
	+interface.
	+Connected to QOSOVERRIDE[4:0] */
	+#define NB_GLOBAL_ACF_CONTROL_OVERRIDE_QOSOVRD_MASK 0x000000F8
	+#define NB_GLOBAL_ACF_CONTROL_OVERRIDE_QOSOVRD_SHIFT 3
	+/* If LOW, then AC requests are never issued on the corresponding slave
	+interface. One bit exists for each slave interface.
	+Connected to ACCHANNELEN[4:0]. */
	+#define NB_GLOBAL_ACF_CONTROL_OVERRIDE_ACE_CH_EN_MASK 0x00001F00
	+#define NB_GLOBAL_ACF_CONTROL_OVERRIDE_ACE_CH_EN_SHIFT 8
	+/* Internal register:
	+Enables 4k hazard of post-barrier vs pre-barrier transactions. Otherwise, 64B hazard granularity is applied. */
	+#define NB_GLOBAL_ACF_CONTROL_OVERRIDE_DMB_4K_HAZARD_EN (1 << 13)
	+
	+/** LGIC_Base_High register **/
	+/* GIC registers base [39:32].
	+This value is sampled into the CP15 Configuration Base Address Register (CBAR) at reset. */
	+#define NB_GLOBAL_LGIC_BASE_HIGH_BASE_39_32_MASK 0x000000FF
	+#define NB_GLOBAL_LGIC_BASE_HIGH_BASE_39_32_SHIFT 0
	+#define NB_GLOBAL_LGIC_BASE_HIGH_BASE_43_32_MASK_PKR 0x00000FFF
	+#define NB_GLOBAL_LGIC_BASE_HIGH_BASE_43_32_SHIFT_PKR 0
	+/* GIC registers base [31:15].
	+This value is sampled into the CP15 Configuration Base Address Register (CBAR) at reset */
	+#define NB_GLOBAL_LGIC_BASE_LOW_BASED_31_15_MASK 0xFFFF8000
	+#define NB_GLOBAL_LGIC_BASE_LOW_BASED_31_15_SHIFT 15
	+
	+/** IOGIC_Base_High register **/
	+/* IOGIC registers base [39:32] */
	+#define NB_GLOBAL_IOGIC_BASE_HIGH_BASE_39_32_MASK 0x000000FF
	+#define NB_GLOBAL_IOGIC_BASE_HIGH_BASE_39_32_SHIFT 0
	+/* IOGIC registers base [31:15] */
	+#define NB_GLOBAL_IOGIC_BASE_LOW_BASED_31_15_MASK 0xFFFF8000
	+#define NB_GLOBAL_IOGIC_BASE_LOW_BASED_31_15_SHIFT 15
	+
	+/** IO_Wr_Split_Control register **/
	+/* Write splitters bypass.
	+[0] Splitter 0 bypass enable
	+[1] Splitter 1 bypass enable */
	+#define NB_GLOBAL_IO_WR_SPLIT_CONTROL_WR_SPLT_BYPASS_MASK 0x00000003
	+#define NB_GLOBAL_IO_WR_SPLIT_CONTROL_WR_SPLT_BYPASS_SHIFT 0
	+/* Write splitters store and forward.
	+If store and forward is disabled, splitter does not check non-active BE in the middle of a transaction. */
	+#define NB_GLOBAL_IO_WR_SPLIT_CONTROL_WR_SPLT_ST_FW_MASK 0x0000000C
	+#define NB_GLOBAL_IO_WR_SPLIT_CONTROL_WR_SPLT_ST_FW_SHIFT 2
	+/* Write splitters unmodify snoop type.
	+Disables modifying snoop type from Clean & Invalidate to Invalidate when conditions enable it. Only split operation to 64B is applied. */
	+#define NB_GLOBAL_IO_WR_SPLIT_CONTROL_WR_SPLT_UNMODIFY_SNP_MASK 0x00000030
	+#define NB_GLOBAL_IO_WR_SPLIT_CONTROL_WR_SPLT_UNMODIFY_SNP_SHIFT 4
	+/* Write splitters unsplit non-coherent access.
	+Disables splitting of non-coherent access to cache-line chunks. */
	+#define NB_GLOBAL_IO_WR_SPLIT_CONTROL_WR_SPLT_UNSPLIT_NOSNP_MASK 0x000000C0
	+#define NB_GLOBAL_IO_WR_SPLIT_CONTROL_WR_SPLT_UNSPLIT_NOSNP_SHIFT 6
	+/* Write splitter rate limit. */
	+#define NB_GLOBAL_IO_WR_SPLIT_CONTROL_WR0_SPLT_RATE_LIMIT_MASK 0x00001F00
	+#define NB_GLOBAL_IO_WR_SPLIT_CONTROL_WR0_SPLT_RATE_LIMIT_SHIFT 8
	+/* Write splitter rate limit */
	+#define NB_GLOBAL_IO_WR_SPLIT_CONTROL_WR1_SPLT_RATE_LIMIT_MASK 0x0003E000
	+#define NB_GLOBAL_IO_WR_SPLIT_CONTROL_WR1_SPLT_RATE_LIMIT_SHIFT 13
	+/* Write splitters 64bit remap enable
	+Enables remapping of 64bit transactions */
	+#define NB_GLOBAL_IO_WR_SPLIT_CONTROL_WR_SPLT_REMAP_64BIT_EN_MASK 0x000C0000
	+#define NB_GLOBAL_IO_WR_SPLIT_CONTROL_WR_SPLT_REMAP_64BIT_EN_SHIFT 18
	+/* Clear is not supported. This bit was changed to wr_pack_disable.
	+In default mode, AWADDR waits for WDATA. */
	+#define NB_GLOBAL_IO_WR_SPLIT_CONTROL_WR_SPLT_CLEAR_MASK 0xC0000000
	+#define NB_GLOBAL_IO_WR_SPLIT_CONTROL_WR_SPLT_CLEAR_SHIFT 30
	+
	+/** IO_Rd_ROB_Control register **/
	+/* Read ROB Bypass
	+[0] Rd ROB 0 bypass enable.
	+[1] Rd ROB 1 bypass enable. */
	+#define NB_GLOBAL_IO_RD_ROB_CONTROL_RD_ROB_BYPASS_MASK 0x00000003
	+#define NB_GLOBAL_IO_RD_ROB_CONTROL_RD_ROB_BYPASS_SHIFT 0
	+/* Read ROB in order.
	+Return data in the order of request acceptance. */
	+#define NB_GLOBAL_IO_RD_ROB_CONTROL_RD_ROB_INORDER_MASK 0x0000000C
	+#define NB_GLOBAL_IO_RD_ROB_CONTROL_RD_ROB_INORDER_SHIFT 2
	+/* Read ROB response rate
	+When enabled drops one cycle from back to back read responses */
	+#define NB_GLOBAL_IO_RD_ROB_CONTROL_RD_ROB_RSP_RATE_MASK 0x00000030
	+#define NB_GLOBAL_IO_RD_ROB_CONTROL_RD_ROB_RSP_RATE_SHIFT 4
	+/* Read splitter rate limit */
	+#define NB_GLOBAL_IO_RD_ROB_CONTROL_RD0_ROB_RATE_LIMIT_MASK 0x00001F00
	+#define NB_GLOBAL_IO_RD_ROB_CONTROL_RD0_ROB_RATE_LIMIT_SHIFT 8
	+/* Read splitter rate limit */
	+#define NB_GLOBAL_IO_RD_ROB_CONTROL_RD1_ROB_RATE_LIMIT_MASK 0x0003E000
	+#define NB_GLOBAL_IO_RD_ROB_CONTROL_RD1_ROB_RATE_LIMIT_SHIFT 13
	+
	+/** SB_PoS_Error_Log_1 register **/
	+/* Error Log 1
	+[7:0] address_high
	+[16:8] request id
	+[18:17] bresp */
	+#define NB_GLOBAL_SB_POS_ERROR_LOG_1_ERR_LOG_MASK 0x7FFFFFFF
	+#define NB_GLOBAL_SB_POS_ERROR_LOG_1_ERR_LOG_SHIFT 0
	+/* Valid logged error
	+Set on SB PoS error occurrence on capturing the error information. Subsequent errors will not be captured until the valid bit is cleared.
	+The SB PoS reports on write errors.
	+When valid, an interrupt is set in the NB Cause Register. */
	+#define NB_GLOBAL_SB_POS_ERROR_LOG_1_VALID (1 << 31)
	+
	+/** MSIx_Error_Log register **/
	+/* Error Log
	+Corresponds to MSIx address message [30:0]. */
	+#define NB_GLOBAL_MSIX_ERROR_LOG_ERR_LOG_MASK 0x7FFFFFFF
	+#define NB_GLOBAL_MSIX_ERROR_LOG_ERR_LOG_SHIFT 0
	+/* Valid logged error */
	+#define NB_GLOBAL_MSIX_ERROR_LOG_VALID (1 << 31)
	+
	+/** Error_Cause register **/
	+/* Received msix is not mapped to local GIC or IO-GIC spin */
	+#define NB_GLOBAL_ERROR_CAUSE_MSIX_ERR_INT (1 << 2)
	+/* Coresight timestamp overflow */
	+#define NB_GLOBAL_ERROR_CAUSE_CORESIGHT_TS_OVERFLOW (1 << 3)
	+/* Write data parity error from SB channel 0. */
	+#define NB_GLOBAL_ERROR_CAUSE_SB0_WRDATA_PERR (1 << 4)
	+/* Write data parity error from SB channel 1. */
	+#define NB_GLOBAL_ERROR_CAUSE_SB1_WRDATA_PERR (1 << 5)
	+/* Read data parity error from SB slaves. */
	+#define NB_GLOBAL_ERROR_CAUSE_SB_SLV_RDATA_PERR (1 << 6)
	+/* Local GIC uncorrectable ECC error */
	+#define NB_GLOBAL_ERROR_CAUSE_LOCAL_GIC_ECC_FATAL (1 << 7)
	+/* SB PoS error */
	+#define NB_GLOBAL_ERROR_CAUSE_SB_POS_ERR (1 << 8)
	+/* Coherent fabric error summary interrupt */
	+#define NB_GLOBAL_ERROR_CAUSE_ACF_ERRORIRQ (1 << 9)
	+/* Error indicator for AXI write transactions with a BRESP error condition. Writing 0 to bit[29] of the L2ECTLR clears the error indicator connected to CA15 nAXIERRIRQ. */
	+#define NB_GLOBAL_ERROR_CAUSE_CPU_AXIERRIRQ (1 << 10)
	+/* Error indicator for: L2 RAM double-bit ECC error, illegal writes to the GIC memory-map region. */
	+#define NB_GLOBAL_ERROR_CAUSE_CPU_INTERRIRQ (1 << 12)
	+/* DDR cause summery interrupt */
	+#define NB_GLOBAL_ERROR_CAUSE_DDR_CAUSE_SUM (1 << 14)
	+
	+/** QoS_Peak_Control register **/
	+/* Peak Read Low Threshold
	+When the number of outstanding read transactions from SB masters is below this value, the CPU is assigned high-priority QoS. */
	+#define NB_GLOBAL_QOS_PEAK_CONTROL_PEAK_RD_L_THRESHOLD_MASK 0x0000007F
	+#define NB_GLOBAL_QOS_PEAK_CONTROL_PEAK_RD_L_THRESHOLD_SHIFT 0
	+/* Peak Read High Threshold
	+When the number of outstanding read transactions from SB masters exceeds this value, the CPU is assigned high-priority QoS. */
	+#define NB_GLOBAL_QOS_PEAK_CONTROL_PEAK_RD_H_THRESHOLD_MASK 0x00007F00
	+#define NB_GLOBAL_QOS_PEAK_CONTROL_PEAK_RD_H_THRESHOLD_SHIFT 8
	+/* Peak Write Low Threshold
	+When the number of outstanding write transactions from SB masters is below this value, the CPU is assigned high-priority QoS */
	+#define NB_GLOBAL_QOS_PEAK_CONTROL_PEAK_WR_L_THRESHOLD_MASK 0x007F0000
	+#define NB_GLOBAL_QOS_PEAK_CONTROL_PEAK_WR_L_THRESHOLD_SHIFT 16
	+/* Peak Write High Threshold
	+When the number of outstanding write transactions from SB masters exceeds this value, the CPU is assigned high-priority QoS. */
	+#define NB_GLOBAL_QOS_PEAK_CONTROL_PEAK_WR_H_THRESHOLD_MASK 0x7F000000
	+#define NB_GLOBAL_QOS_PEAK_CONTROL_PEAK_WR_H_THRESHOLD_SHIFT 24
	+
	+/** QoS_Set_Control register **/
	+/* CPU Low priority Read QoS */
	+#define NB_GLOBAL_QOS_SET_CONTROL_CPU_LP_ARQOS_MASK 0x0000000F
	+#define NB_GLOBAL_QOS_SET_CONTROL_CPU_LP_ARQOS_SHIFT 0
	+/* CPU High priority Read QoS */
	+#define NB_GLOBAL_QOS_SET_CONTROL_CPU_HP_ARQOS_MASK 0x000000F0
	+#define NB_GLOBAL_QOS_SET_CONTROL_CPU_HP_ARQOS_SHIFT 4
	+/* CPU Low priority Write QoS */
	+#define NB_GLOBAL_QOS_SET_CONTROL_CPU_LP_AWQOS_MASK 0x00000F00
	+#define NB_GLOBAL_QOS_SET_CONTROL_CPU_LP_AWQOS_SHIFT 8
	+/* CPU High priority Write QoS */
	+#define NB_GLOBAL_QOS_SET_CONTROL_CPU_HP_AWQOS_MASK 0x0000F000
	+#define NB_GLOBAL_QOS_SET_CONTROL_CPU_HP_AWQOS_SHIFT 12
	+/* SB Low priority Read QoS */
	+#define NB_GLOBAL_QOS_SET_CONTROL_SB_LP_ARQOS_MASK 0x000F0000
	+#define NB_GLOBAL_QOS_SET_CONTROL_SB_LP_ARQOS_SHIFT 16
	+/* SB Low-priority Write QoS */
	+#define NB_GLOBAL_QOS_SET_CONTROL_SB_LP_AWQOS_MASK 0x00F00000
	+#define NB_GLOBAL_QOS_SET_CONTROL_SB_LP_AWQOS_SHIFT 20
	+
	+/** DDR_QoS register **/
	+/* High Priority Read Threshold
	+Limits the number of outstanding high priority reads in the system through the memory controller.
	+This parameter is programmed in conjunction with number of outstanding high priority reads supported by the DDR controller. */
	+#define NB_GLOBAL_DDR_QOS_HIGH_PRIO_THRESHOLD_MASK 0x0000007F
	+#define NB_GLOBAL_DDR_QOS_HIGH_PRIO_THRESHOLD_SHIFT 0
	+/* DDR Low Priority QoS
	+Fabric priority below this value is mapped to DDR low priority queue. */
	+#define NB_GLOBAL_DDR_QOS_LP_QOS_MASK 0x00000F00
	+#define NB_GLOBAL_DDR_QOS_LP_QOS_SHIFT 8
	+
	+/** ACF_Misc register **/
	+/* Disable DDR Write Chop
	+Performance optimization feature to chop non-active data beats to the DDR. */
	+#define NB_GLOBAL_ACF_MISC_DDR_WR_CHOP_DIS (1 << 0)
	+/* Disable SB-2-SB path through NB fabric. */
	+#define NB_GLOBAL_ACF_MISC_SB2SB_PATH_DIS (1 << 1)
	+/* Disable ETR tracing to non-DDR. */
	+#define NB_GLOBAL_ACF_MISC_ETR2SB_PATH_DIS (1 << 2)
	+/* Disable ETR tracing to non-DDR. */
	+#define NB_GLOBAL_ACF_MISC_CPU2MSIX_DIS (1 << 3)
	+/* Disable CPU generation of MSIx
	+By default, the CPU can set any MSIx message results by setting any SPIn bit in the local and IO-GIC. */
	+#define NB_GLOBAL_ACF_MISC_MSIX_TERMINATE_DIS (1 << 4)
	+/* Disable snoop override for MSIx
	+By default, an MSIx transaction is downgraded to non-coherent. */
	+#define NB_GLOBAL_ACF_MISC_MSIX_SNOOPOVRD_DIS (1 << 5)
	+/* POS bypass */
	+#define NB_GLOBAL_ACF_MISC_POS_BYPASS (1 << 6)
	+/* PoS ReadStronglyOrdered enable
	+SO read forces flushing of all prior writes */
	+#define NB_GLOBAL_ACF_MISC_POS_RSO_EN (1 << 7)
	+/* WRAP to INC transfer enable */
	+#define NB_GLOBAL_ACF_MISC_POS_WRAP2INC (1 << 8)
	+/* PoS DSB flush Disable
	+On DSB from CPU, PoS blocks the progress of post-barrier reads and writes until all pre-barrier writes have been completed. */
	+#define NB_GLOBAL_ACF_MISC_POS_DSB_FLUSH_DIS (1 << 9)
	+/* PoS DMB Flush Disable
	+On DMB from CPU, the PoS blocks the progress of post-barrier non-buffereable reads or writes when there are outstanding non-bufferable writes that have not yet been completed.
	+Other access types are hazard check against the pre-barrier requests. */
	+#define NB_GLOBAL_ACF_MISC_POS_DMB_FLUSH_DIS (1 << 10)
	+/* change DMB functionality to DSB (block and drain) */
	+#define NB_GLOBAL_ACF_MISC_POS_DMB_TO_DSB_EN (1 << 11)
	+/* Disable write after read stall when accessing IO fabric slaves. */
	+#define NB_GLOBAL_ACF_MISC_M0_WAR_STALL_DIS (1 << 12)
	+/* Disable write after read stall when accessing DDR */
	+#define NB_GLOBAL_ACF_MISC_M1_WAR_STALL_DIS (1 << 13)
	+/* Disable counter (wait 1000 NB cycles) before applying PoS enable/disable configuration */
	+#define NB_GLOBAL_ACF_MISC_POS_CONFIG_CNT_DIS (1 << 14)
	+/* Disable wr spliter A0 bug fixes */
	+#define NB_GLOBAL_ACF_MISC_WRSPLT_ALPINE_M0_MODE (1 << 16)
	+/* Disable wr spliter PKR bug fixes */
	+#define NB_GLOBAL_ACF_MISC_WRSPLT_ALPINE_A0_MODE (1 << 17)
	+/* Override the address parity calucation for write transactions going to IO-fabric */
	+#define NB_GLOBAL_ACF_MISC_NB_NIC_AWADDR_PAR_OVRD (1 << 18)
	+/* Override the data parity calucation for write transactions going to IO-fabric */
	+#define NB_GLOBAL_ACF_MISC_NB_NIC_WDATA_PAR_OVRD (1 << 19)
	+/* Override the address parity calucation for read transactions going to IO-fabric */
	+#define NB_GLOBAL_ACF_MISC_NB_NIC_ARADDR_PAR_OVRD (1 << 20)
	+/* Halts CPU AXI interface (Ar/Aw channels), not allowing the CPU to send additional transactions */
	+#define NB_GLOBAL_ACF_MISC_CPU_AXI_HALT (1 << 23)
	+/* Disable early arbar termination when fabric write buffer is enabled. */
	+#define NB_GLOBAL_ACF_MISC_CCIWB_EARLY_ARBAR_TERM_DIS (1 << 24)
	+/* Enable wire interrupts connectivity to IO-GIC IRQs */
	+#define NB_GLOBAL_ACF_MISC_IOGIC_CHIP_SPI_EN (1 << 25)
	+/* Enable DMB flush request to NB to SB PoS when barrier is terminted inside the processor cluster */
	+#define NB_GLOBAL_ACF_MISC_CPU_DSB_FLUSH_DIS (1 << 26)
	+/* Enable DMB flush request to NB to SB PoS when barrier is terminted inside the processor cluster */
	+#define NB_GLOBAL_ACF_MISC_CPU_DMB_FLUSH_DIS (1 << 27)
	+/* Peakrock only: remap CPU address above 40 bits to Slave Error
	+INTERNAL */
	+#define NB_GLOBAL_ACF_MISC_ADDR43_40_REMAP_DIS (1 << 28)
	+/* Enable CPU WriteUnique to WriteNoSnoop trasform */
	+#define NB_GLOBAL_ACF_MISC_CPU_WU2WNS_EN (1 << 29)
	+/* Disable device after device check */
	+#define NB_GLOBAL_ACF_MISC_WR_POS_DEV_AFTER_DEV_DIS (1 << 30)
	+/* Disable wrap to inc on write */
	+#define NB_GLOBAL_ACF_MISC_WR_INC2WRAP_EN (1 << 31)
	+
	+/** Config_Bus_Control register **/
	+/* Write slave error enable */
	+#define NB_GLOBAL_CONFIG_BUS_CONTROL_WR_SLV_ERR_EN (1 << 0)
	+/* Write decode error enable */
	+#define NB_GLOBAL_CONFIG_BUS_CONTROL_WR_DEC_ERR_EN (1 << 1)
	+/* Read slave error enable */
	+#define NB_GLOBAL_CONFIG_BUS_CONTROL_RD_SLV_ERR_EN (1 << 2)
	+/* Read decode error enable */
	+#define NB_GLOBAL_CONFIG_BUS_CONTROL_RD_DEC_ERR_EN (1 << 3)
	+/* Ignore Write ID */
	+#define NB_GLOBAL_CONFIG_BUS_CONTROL_IGNORE_WR_ID (1 << 4)
	+/* Timeout limit before terminating configuration bus access with slave error */
	+#define NB_GLOBAL_CONFIG_BUS_CONTROL_TIMEOUT_LIMIT_MASK 0xFFFFFF00
	+#define NB_GLOBAL_CONFIG_BUS_CONTROL_TIMEOUT_LIMIT_SHIFT 8
	+
	+/** Pos_ID_Match register **/
	+/* Enable Device (GRE and nGRE) after Device ID hazard */
	+#define NB_GLOBAL_POS_ID_MATCH_ENABLE (1 << 0)
	+/* ID Field Mask
	+If set, corresonpding ID bits are not used for ID match */
	+#define NB_GLOBAL_POS_ID_MATCH_MASK_MASK 0xFFFF0000
	+#define NB_GLOBAL_POS_ID_MATCH_MASK_SHIFT 16
	+
	+/** sb_sel_override_awuser register **/
	+/* Select whether to use transaction awuser or sb_override_awuser value for awuser field on outgoing write transactions to SB.
	+Each bit if set to 1 selects the corresponding sb_override_awuser bit. Otherwise, selects the corersponding transaction awuser bit. */
	+#define NB_GLOBAL_SB_SEL_OVERRIDE_AWUSER_SEL_MASK 0x03FFFFFF
	+#define NB_GLOBAL_SB_SEL_OVERRIDE_AWUSER_SEL_SHIFT 0
	+
	+/** sb_override_awuser register **/
	+/* Awuser to use on overriden transactions
	+Only applicable if sel_override_awuser.sel is set to 1'b1 for the coressponding bit */
	+#define NB_GLOBAL_SB_OVERRIDE_AWUSER_AWUSER_MASK 0x03FFFFFF
	+#define NB_GLOBAL_SB_OVERRIDE_AWUSER_AWUSER_SHIFT 0
	+
	+/** sb_sel_override_aruser register **/
	+/* Select whether to use transaction aruser or sb_override_aruser value for aruser field on outgoing read transactions to SB.
	+Each bit if set to 1 selects the corresponding sb_override_aruser bit. Otherwise, selects the corersponding transaction aruser bit. */
	+#define NB_GLOBAL_SB_SEL_OVERRIDE_ARUSER_SEL_MASK 0x03FFFFFF
	+#define NB_GLOBAL_SB_SEL_OVERRIDE_ARUSER_SEL_SHIFT 0
	+
	+/** sb_override_aruser register **/
	+/* Aruser to use on overriden transactions
	+Only applicable if sb_sel_override_aruser.sel is set to 1'b1 for the coressponding bit */
	+#define NB_GLOBAL_SB_OVERRIDE_ARUSER_ARUSER_MASK 0x03FFFFFF
	+#define NB_GLOBAL_SB_OVERRIDE_ARUSER_ARUSER_SHIFT 0
	+
	+/** Coresight_PD register **/
	+/* ETF0 RAM force power down */
	+#define NB_GLOBAL_CORESIGHT_PD_ETF0_RAM_FORCE_PD (1 << 0)
	+/* ETF1 RAM force power down */
	+#define NB_GLOBAL_CORESIGHT_PD_ETF1_RAM_FORCE_PD (1 << 1)
	+/* ETF0 RAM force clock gate */
	+#define NB_GLOBAL_CORESIGHT_PD_ETF0_RAM_FORCE_CG (1 << 2)
	+/* ETF1 RAM force clock gate */
	+#define NB_GLOBAL_CORESIGHT_PD_ETF1_RAM_FORCE_CG (1 << 3)
	+/* APBIC clock enable */
	+#define NB_GLOBAL_CORESIGHT_PD_APBICLKEN (1 << 4)
	+/* DAP system clock enable */
	+#define NB_GLOBAL_CORESIGHT_PD_DAP_SYS_CLKEN (1 << 5)
	+
	+/** Coresight_INTERNAL_0 register **/
	+
	+#define NB_GLOBAL_CORESIGHT_INTERNAL_0_CTIAPBSBYPASS (1 << 0)
	+/* CA15 CTM and Coresight CTI operate at same clock, bypass modes can be enabled but it's being set to bypass disable to break timing path. */
	+#define NB_GLOBAL_CORESIGHT_INTERNAL_0_CISBYPASS (1 << 1)
	+/* CA15 CTM and Coresight CTI operate according to the same clock.
	+Bypass modes can be enabled, but it is set to bypass disable, to break the timing path. */
	+#define NB_GLOBAL_CORESIGHT_INTERNAL_0_CIHSBYPASS_MASK 0x0000003C
	+#define NB_GLOBAL_CORESIGHT_INTERNAL_0_CIHSBYPASS_SHIFT 2
	+
	+/** Coresight_DBGROMADDR register **/
	+/* Valid signal for DBGROMADDR.
	+Connected to DBGROMADDRV */
	+#define NB_GLOBAL_CORESIGHT_DBGROMADDR_VALID (1 << 0)
	+/* Specifies bits [39:12] of the ROM table physical address. */
	+#define NB_GLOBAL_CORESIGHT_DBGROMADDR_ADDR_39_12_MASK 0x3FFFFFFC
	+#define NB_GLOBAL_CORESIGHT_DBGROMADDR_ADDR_39_12_SHIFT 2
	+
	+/** Coresight_DBGSELFADDR register **/
	+/* Valid signal for DBGROMADDR.
	+Connected to DBGROMADDRV */
	+#define NB_GLOBAL_CORESIGHT_DBGSELFADDR_VALID (1 << 0)
	+/* Specifies bits [18:17] of the two's complement signed offset from the ROM table physical address to the physical address where the debug registers are memory-mapped.
	+Note: The CA15 debug unit starts at offset 0x1 within the Coresight cluster. */
	+#define NB_GLOBAL_CORESIGHT_DBGSELFADDR_ADDR_18_17_MASK 0x00000180
	+#define NB_GLOBAL_CORESIGHT_DBGSELFADDR_ADDR_18_17_SHIFT 7
	+/* Specifies bits [39:19] of the two's complement signed offset from the ROM table physical address to the physical address where the debug registers are memory-mapped.
	+Note: The CA15 debug unit starts at offset 0x1 within the Coresight cluster, so this offset if fixed to zero. */
	+#define NB_GLOBAL_CORESIGHT_DBGSELFADDR_ADDR_39_19_MASK 0x3FFFFE00
	+#define NB_GLOBAL_CORESIGHT_DBGSELFADDR_ADDR_39_19_SHIFT 9
	+
	+/** SB_force_same_id_cfg_0 register **/
	+/* Enables force same id mechanism for SB port 0 */
	+#define NB_GLOBAL_SB_FORCE_SAME_ID_CFG_0_FORCE_SAME_ID_EN (1 << 0)
	+/* Enables MSIx stall when write transactions from same ID mechanism are in progress for SB port 0 */
	+#define NB_GLOBAL_SB_FORCE_SAME_ID_CFG_0_FORCE_SAME_ID_MSIX_STALL_EN (1 << 1)
	+/* Mask for choosing which ID bits to match for indicating the originating master */
	+#define NB_GLOBAL_SB_FORCE_SAME_ID_CFG_0_SB_MSTR_ID_MASK_MASK 0x000000F8
	+#define NB_GLOBAL_SB_FORCE_SAME_ID_CFG_0_SB_MSTR_ID_MASK_SHIFT 3
	+
	+/** SB_force_same_id_cfg_1 register **/
	+/* Enables force same id mechanism for SB port 1 */
	+#define NB_GLOBAL_SB_FORCE_SAME_ID_CFG_1_FORCE_SAME_ID_EN (1 << 0)
	+/* Enables MSIx stall when write transactions from same ID mechanism are in progress for SB port 1 */
	+#define NB_GLOBAL_SB_FORCE_SAME_ID_CFG_1_FORCE_SAME_ID_MSIX_STALL_EN (1 << 1)
	+/* Mask for choosing which ID bits to match for indicating the originating master */
	+#define NB_GLOBAL_SB_FORCE_SAME_ID_CFG_1_SB_MSTR_ID_MASK_MASK 0x000000F8
	+#define NB_GLOBAL_SB_FORCE_SAME_ID_CFG_1_SB_MSTR_ID_MASK_SHIFT 3
	+
	+/** Cnt_Control register **/
	+/* System counter enable
	+Counter is enabled after reset. */
	+#define NB_SYSTEM_COUNTER_CNT_CONTROL_EN (1 << 0)
	+/* System counter restart
	+Initial value is reloaded from Counter_Init_L and Counter_Init_H registers.
	+Transition from 0 to 1 reloads the register. */
	+#define NB_SYSTEM_COUNTER_CNT_CONTROL_RESTART (1 << 1)
	+/* Disable CTI trigger out that halt the counter progress */
	+#define NB_SYSTEM_COUNTER_CNT_CONTROL_CTI_TRIGOUT_HALT_DIS (1 << 2)
	+/* System counter tick
	+Specifies the counter tick rate relative to the Northbridge clock, e.g., the counter is incremented every 16 NB cycles if programmed to 0x0f. */
	+#define NB_SYSTEM_COUNTER_CNT_CONTROL_SCALE_MASK 0x0000FF00
	+#define NB_SYSTEM_COUNTER_CNT_CONTROL_SCALE_SHIFT 8
	+
	+/** CA15_RF_Misc register **/
	+
	+#define NB_RAMS_CONTROL_MISC_CA15_RF_MISC_NONECPU_RF_MISC_MASK 0x0000000F
	+#define NB_RAMS_CONTROL_MISC_CA15_RF_MISC_NONECPU_RF_MISC_SHIFT 0
	+
	+#define NB_RAMS_CONTROL_MISC_CA15_RF_MISC_CPU_RF_MISC_MASK 0x00FFFF00
	+#define NB_RAMS_CONTROL_MISC_CA15_RF_MISC_CPU_RF_MISC_SHIFT 8
	+/* Pause for CPUs from the time all power is up to the time the SRAMs start opening. */
	+#define NB_RAMS_CONTROL_MISC_CA15_RF_MISC_PWR_UP_PAUSE_MASK 0xF8000000
	+#define NB_RAMS_CONTROL_MISC_CA15_RF_MISC_PWR_UP_PAUSE_SHIFT 27
	+
	+/** NB_RF_Misc register **/
	+/* SMMU TLB RAMs force power down */
	+#define NB_RAMS_CONTROL_MISC_NB_RF_MISC_SMMU_RAM_FORCE_PD (1 << 0)
	+
	+/** Lockn register **/
	+/* Semaphore Lock
	+CPU reads it:
	+If current value ==0, return 0 to CPU but set bit to 1. (CPU knows it captured the semaphore.)
	+If current value ==1, return 1 to CPU. (CPU knows it is already used and waits.)
	+CPU writes 0 to it to release the semaphore. */
	+#define NB_SEMAPHORES_LOCKN_LOCK (1 << 0)
	+
	+/** CA15_outputs_1 register **/
	+/*
	+ */
	+#define NB_DEBUG_CA15_OUTPUTS_1_STANDBYWFI_MASK 0x0000000F
	+#define NB_DEBUG_CA15_OUTPUTS_1_STANDBYWFI_SHIFT 0
	+/*
	+ */
	+#define NB_DEBUG_CA15_OUTPUTS_1_CPU_PWR_DN_ACK_MASK 0x000000F0
	+#define NB_DEBUG_CA15_OUTPUTS_1_CPU_PWR_DN_ACK_SHIFT 4
	+/*
	+ */
	+#define NB_DEBUG_CA15_OUTPUTS_1_IRQOUT_N_MASK 0x00000F00
	+#define NB_DEBUG_CA15_OUTPUTS_1_IRQOUT_N_SHIFT 8
	+/*
	+ */
	+#define NB_DEBUG_CA15_OUTPUTS_1_FIQOUT_N_MASK 0x0000F000
	+#define NB_DEBUG_CA15_OUTPUTS_1_FIQOUT_N_SHIFT 12
	+/*
	+ */
	+#define NB_DEBUG_CA15_OUTPUTS_1_CNTHPIRQ_N_MASK 0x000F0000
	+#define NB_DEBUG_CA15_OUTPUTS_1_CNTHPIRQ_N_SHIFT 16
	+/*
	+ */
	+#define NB_DEBUG_CA15_OUTPUTS_1_NCNTPNSIRQ_N_MASK 0x00F00000
	+#define NB_DEBUG_CA15_OUTPUTS_1_NCNTPNSIRQ_N_SHIFT 20
	+/*
	+ */
	+#define NB_DEBUG_CA15_OUTPUTS_1_NCNTPSIRQ_N_MASK 0x0F000000
	+#define NB_DEBUG_CA15_OUTPUTS_1_NCNTPSIRQ_N_SHIFT 24
	+/*
	+ */
	+#define NB_DEBUG_CA15_OUTPUTS_1_NCNTVIRQ_N_MASK 0xF0000000
	+#define NB_DEBUG_CA15_OUTPUTS_1_NCNTVIRQ_N_SHIFT 28
	+
	+/** CA15_outputs_2 register **/
	+/*
	+ */
	+#define NB_DEBUG_CA15_OUTPUTS_2_STANDBYWFIL2 (1 << 0)
	+/*
	+ */
	+#define NB_DEBUG_CA15_OUTPUTS_2_L2RAM_PWR_DN_ACK (1 << 1)
	+/* Indicates for each CPU if coherency is enabled
	+ */
	+#define NB_DEBUG_CA15_OUTPUTS_2_SMPEN_MASK 0x0000003C
	+#define NB_DEBUG_CA15_OUTPUTS_2_SMPEN_SHIFT 2
	+
	+/** cpu_msg register **/
	+/* Status/ASCII code */
	+#define NB_DEBUG_CPU_MSG_STATUS_MASK 0x000000FF
	+#define NB_DEBUG_CPU_MSG_STATUS_SHIFT 0
	+/* Toggle with each ASCII write */
	+#define NB_DEBUG_CPU_MSG_ASCII_TOGGLE (1 << 8)
	+/* Signals ASCII */
	+#define NB_DEBUG_CPU_MSG_ASCII (1 << 9)
	+
	+#define NB_DEBUG_CPU_MSG_RESERVED_11_10_MASK 0x00000C00
	+#define NB_DEBUG_CPU_MSG_RESERVED_11_10_SHIFT 10
	+/* Signals new section started in S/W */
	+#define NB_DEBUG_CPU_MSG_SECTION_START (1 << 12)
	+
	+#define NB_DEBUG_CPU_MSG_RESERVED_13 (1 << 13)
	+/* Signals a single CPU is done. */
	+#define NB_DEBUG_CPU_MSG_CPU_DONE (1 << 14)
	+/* Signals test is done */
	+#define NB_DEBUG_CPU_MSG_TEST_DONE (1 << 15)
	+
	+/** ddrc register **/
	+/* External DLL calibration request. Also compensates for VT variations, such as an external request for the controller (can be performed automatically by the controller at the normal settings). */
	+#define NB_DEBUG_DDRC_DLL_CALIB_EXT_REQ (1 << 0)
	+/* External request to perform short (long is performed during initialization) and/or ODT calibration. */
	+#define NB_DEBUG_DDRC_ZQ_SHORT_CALIB_EXT_REQ (1 << 1)
	+/* External request to perform a refresh command to a specific bank. Usually performed automatically by the controller, however, the controller supports disabling of the automatic mechanism, and use of an external pulse instead. */
	+#define NB_DEBUG_DDRC_RANK_REFRESH_EXT_REQ_MASK 0x0000003C
	+#define NB_DEBUG_DDRC_RANK_REFRESH_EXT_REQ_SHIFT 2
	+
	+/** ddrc_phy_smode_control register **/
	+/* DDR PHY special mode */
	+#define NB_DEBUG_DDRC_PHY_SMODE_CONTROL_CTL_MASK 0x0000FFFF
	+#define NB_DEBUG_DDRC_PHY_SMODE_CONTROL_CTL_SHIFT 0
	+
	+/** ddrc_phy_smode_status register **/
	+/* DDR PHY special mode */
	+#define NB_DEBUG_DDRC_PHY_SMODE_STATUS_STT_MASK 0x0000FFFF
	+#define NB_DEBUG_DDRC_PHY_SMODE_STATUS_STT_SHIFT 0
	+
	+/** pmc register **/
	+/* Enable system control on NB DRO */
	+#define NB_DEBUG_PMC_SYS_EN (1 << 0)
	+/* NB PMC HVT35 counter value */
	+#define NB_DEBUG_PMC_HVT35_VAL_14_0_MASK 0x0000FFFE
	+#define NB_DEBUG_PMC_HVT35_VAL_14_0_SHIFT 1
	+/* NB PMC SVT31 counter value */
	+#define NB_DEBUG_PMC_SVT31_VAL_14_0_MASK 0x7FFF0000
	+#define NB_DEBUG_PMC_SVT31_VAL_14_0_SHIFT 16
	+
	+/** cpus_general register **/
	+/* Swaps sysaddr[16:14] with sysaddr[19:17] for DDR access*/
	+#define NB_DEBUG_CPUS_GENERAL_ADDR_MAP_ECO (1 << 23)
	+
	+/** cpus_int_out register **/
	+/* Defines which CPUs' FIQ will be triggered out through the cpus_int_out[1] pinout. */
	+#define NB_DEBUG_CPUS_INT_OUT_FIQ_EN_MASK 0x0000000F
	+#define NB_DEBUG_CPUS_INT_OUT_FIQ_EN_SHIFT 0
	+/* Defines which CPUs' IRQ will be triggered out through the cpus_int_out[0] pinout. */
	+#define NB_DEBUG_CPUS_INT_OUT_IRQ_EN_MASK 0x000000F0
	+#define NB_DEBUG_CPUS_INT_OUT_IRQ_EN_SHIFT 4
	+/* Defines which CPUs' SEI will be triggered out through the cpus_int_out[0] pinout. */
	+#define NB_DEBUG_CPUS_INT_OUT_IRQ_SEI_EN_MASK 0x00000F00
	+#define NB_DEBUG_CPUS_INT_OUT_IRQ_SEI_EN_SHIFT 8
	+
	+/** latch_pc_req register **/
	+/* If set, request to latch execution PC from processor cluster */
	+#define NB_DEBUG_LATCH_PC_REQ_EN (1 << 0)
	+/* target CPU id to latch its execution PC */
	+#define NB_DEBUG_LATCH_PC_REQ_CPU_ID_MASK 0x000000F0
	+#define NB_DEBUG_LATCH_PC_REQ_CPU_ID_SHIFT 4
	+
	+/** latch_pc_low register **/
	+/* Set by hardware when the processor cluster ack the PC latch request.
	+Clear on read latch_pc_high */
	+#define NB_DEBUG_LATCH_PC_LOW_VALID (1 << 0)
	+/* Latched PC value [31:1] */
	+#define NB_DEBUG_LATCH_PC_LOW_VAL_MASK 0xFFFFFFFE
	+#define NB_DEBUG_LATCH_PC_LOW_VAL_SHIFT 1
	+
	+/** track_dump_ctrl register **/
	+/* [24:16]: Queue entry pointer
	+[2] Target queue: 1'b0: HazardTrack or 1'b1: AmiRMI queues
	+[1:0]: CCI target master: 2'b00: M0, 2'b01: M1, 2'b10: M2 */
	+#define NB_DEBUG_TRACK_DUMP_CTRL_PTR_MASK 0x7FFFFFFF
	+#define NB_DEBUG_TRACK_DUMP_CTRL_PTR_SHIFT 0
	+/* Track Dump Request
	+If set, queue entry info is latched on track_dump_rdata register.
	+Program the pointer and target queue.
	+This is a full handshake register.
	+Read <valid> bit from track_dump_rdata register. If set, clear the request field before triggering a new request. */
	+#define NB_DEBUG_TRACK_DUMP_CTRL_REQ (1 << 31)
	+
	+/** track_dump_rdata_0 register **/
	+/* Valid */
	+#define NB_DEBUG_TRACK_DUMP_RDATA_0_VALID (1 << 0)
	+/* Low data */
	+#define NB_DEBUG_TRACK_DUMP_RDATA_0_DATA_MASK 0xFFFFFFFE
	+#define NB_DEBUG_TRACK_DUMP_RDATA_0_DATA_SHIFT 1
	+
	+/** pos_track_dump_ctrl register **/
	+/* [24:16]: queue entry pointer */
	+#define NB_DEBUG_POS_TRACK_DUMP_CTRL_PTR_MASK 0x7FFFFFFF
	+#define NB_DEBUG_POS_TRACK_DUMP_CTRL_PTR_SHIFT 0
	+/* Track Dump Request
	+If set, queue entry info is latched on track_dump_rdata register.
	+Program the pointer and target queue.
	+This is a full handshake register
	+Read <valid> bit from track_dump_rdata register. If set, clear the request field before triggering a new request. */
	+#define NB_DEBUG_POS_TRACK_DUMP_CTRL_REQ (1 << 31)
	+
	+/** pos_track_dump_rdata_0 register **/
	+/* Valid */
	+#define NB_DEBUG_POS_TRACK_DUMP_RDATA_0_VALID (1 << 0)
	+/* Low data */
	+#define NB_DEBUG_POS_TRACK_DUMP_RDATA_0_DATA_MASK 0xFFFFFFFE
	+#define NB_DEBUG_POS_TRACK_DUMP_RDATA_0_DATA_SHIFT 1
	+
	+/** c2swb_track_dump_ctrl register **/
	+/* [24:16]: Queue entry pointer */
	+#define NB_DEBUG_C2SWB_TRACK_DUMP_CTRL_PTR_MASK 0x7FFFFFFF
	+#define NB_DEBUG_C2SWB_TRACK_DUMP_CTRL_PTR_SHIFT 0
	+/* Track Dump Request
	+If set, queue entry info is latched on track_dump_rdata register.
	+Program the pointer and target queue.
	+This is a full handshake register
	+Read <valid> bit from track_dump_rdata register. If set, clear the request field before triggering a new request. */
	+#define NB_DEBUG_C2SWB_TRACK_DUMP_CTRL_REQ (1 << 31)
	+
	+/** c2swb_track_dump_rdata_0 register **/
	+/* Valid */
	+#define NB_DEBUG_C2SWB_TRACK_DUMP_RDATA_0_VALID (1 << 0)
	+/* Low data */
	+#define NB_DEBUG_C2SWB_TRACK_DUMP_RDATA_0_DATA_MASK 0xFFFFFFFE
	+#define NB_DEBUG_C2SWB_TRACK_DUMP_RDATA_0_DATA_SHIFT 1
	+
	+/** cpus_track_dump_ctrl register **/
	+/* [24:16]: Queue entry pointer
	+[3:2] Target queue - 0:ASI, 1: AMI
	+[1:0]: Target Processor Cluster - 0: Cluster0, 1: Cluster1 */
	+#define NB_DEBUG_CPUS_TRACK_DUMP_CTRL_PTR_MASK 0x7FFFFFFF
	+#define NB_DEBUG_CPUS_TRACK_DUMP_CTRL_PTR_SHIFT 0
	+/* Track Dump Request
	+If set, queue entry info is latched on track_dump_rdata register.
	+Program the pointer and target queue.
	+This is a full handshake register
	+Read <valid> bit from track_dump_rdata register. If set, clear the request field before triggering a new request. */
	+#define NB_DEBUG_CPUS_TRACK_DUMP_CTRL_REQ (1 << 31)
	+
	+/** cpus_track_dump_rdata_0 register **/
	+/* Valid */
	+#define NB_DEBUG_CPUS_TRACK_DUMP_RDATA_0_VALID (1 << 0)
	+/* Low data */
	+#define NB_DEBUG_CPUS_TRACK_DUMP_RDATA_0_DATA_MASK 0xFFFFFFFE
	+#define NB_DEBUG_CPUS_TRACK_DUMP_RDATA_0_DATA_SHIFT 1
	+
	+/** c2swb_bar_ovrd_high register **/
	+/* Read barrier is progressed downstream when not terminated in the CCI.
	+By specification, barrier address is 0x0.
	+This register enables barrier address OVRD to a programmable value. */
	+#define NB_DEBUG_C2SWB_BAR_OVRD_HIGH_RD_ADDR_OVRD_EN (1 << 0)
	+/* Address bits 39:32 */
	+#define NB_DEBUG_C2SWB_BAR_OVRD_HIGH_ADDR_39_32_MASK 0x00FF0000
	+#define NB_DEBUG_C2SWB_BAR_OVRD_HIGH_ADDR_39_32_SHIFT 16
	+
	+/** Config register **/
	+/* Individual processor control of the endianness configuration at reset. It sets the initial value of the EE bit in the CP15 System Control Register (SCTLR) related to CFGEND<n> input:
	+little - 0x0: Little endian
	+bit - 0x1: Bit endian */
	+#define NB_CPUN_CONFIG_STATUS_CONFIG_ENDIAN (1 << 0)
	+/* Individual processor control of the default exception handling state. It sets the initial value of the TE bit in the CP15 System Control Register (SCTLR) related to CFGTE<n> input:
	+arm: 0x0: Exception operates ARM code.
	+Thumb: 0x1: Exception operates Thumb code. */
	+#define NB_CPUN_CONFIG_STATUS_CONFIG_TE (1 << 1)
	+/* Individual processor control of the location of the exception vectors at reset. It sets the initial value of the V bit in the CP15 System Control Register (SCTLR).
	+Connected to VINITHIGH<n> input.
	+low - 0x0: Exception vectors start at address 0x00000000.
	+high - 0x1: Exception vectors start at address 0xFFFF0000. */
	+#define NB_CPUN_CONFIG_STATUS_CONFIG_VINITHI (1 << 2)
	+/* Individual processor control to disable write access to some secure CP15 registers
	+connected to CP15SDISABLE<n> input. */
	+#define NB_CPUN_CONFIG_STATUS_CONFIG_CP15DISABLE (1 << 3)
	+/* Force Write init implementation to ConfigAARch64 register */
	+#define NB_CPUN_CONFIG_STATUS_CONFIG_AARCH64_REG_FORCE_WINIT (1 << 4)
	+/* Force Write Once implementation to ConfigAARch64 register. */
	+#define NB_CPUN_CONFIG_STATUS_CONFIG_AARCH64_REG_FORCE_WONCE (1 << 5)
	+
	+/** Config_AARch64 register **/
	+/* Individual processor register width state. The register width states are:
	+0 AArch32.
	+1 AArch64.
	+This signal is only sampled during reset of the processor.
	+This is Write Init register */
	+#define NB_CPUN_CONFIG_STATUS_CONFIG_AARCH64_AA64_NAA32 (1 << 0)
	+/* Individual processor Cryptography engine disable:
	+0 Enable the Cryptography engine.
	+1 Disable the Cryptography engine.
	+This signal is only sampled during reset of the processor */
	+#define NB_CPUN_CONFIG_STATUS_CONFIG_AARCH64_CRYPTO_DIS (1 << 1)
	+
	+/** Power_Ctrl register **/
	+/* Individual CPU power mode transition request
	+If requested to enter power mode other than normal mode, low power state is resumed whenever CPU reenters STNDBYWFI state:
	+normal: 0x0: normal power state
	+deep_idle: 0x2: Dormant power mode state
	+poweredoff: 0x3: Powered-off power mode */
	+#define NB_CPUN_CONFIG_STATUS_POWER_CTRL_PM_REQ_MASK 0x00000003
	+#define NB_CPUN_CONFIG_STATUS_POWER_CTRL_PM_REQ_SHIFT 0
	+/* Normal power mode state */
	+#define NB_CPUN_CONFIG_STATUS_POWER_CTRL_PM_REQ_NORMAL \
	+ (0x0 << NB_CPUN_CONFIG_STATUS_POWER_CTRL_PM_REQ_SHIFT)
	+/* Dormant power mode state */
	+#define NB_CPUN_CONFIG_STATUS_POWER_CTRL_PM_REQ_DEEP_IDLE \
	+ (0x2 << NB_CPUN_CONFIG_STATUS_POWER_CTRL_PM_REQ_SHIFT)
	+/* Powered-off power mode */
	+#define NB_CPUN_CONFIG_STATUS_POWER_CTRL_PM_REQ_POWEREDOFF \
	+ (0x3 << NB_CPUN_CONFIG_STATUS_POWER_CTRL_PM_REQ_SHIFT)
	+/* Power down regret disable
	+When power down regret is enabled, the powerdown enter flow can be halted whenever a valid wakeup event occurs. */
	+#define NB_CPUN_CONFIG_STATUS_POWER_CTRL_PWRDN_RGRT_DIS (1 << 16)
	+/* Power down emulation enable
	+If set, the entire power down sequence is applied, but the CPU is placed in soft reset instead of hardware power down. */
	+#define NB_CPUN_CONFIG_STATUS_POWER_CTRL_PWRDN_EMULATE (1 << 17)
	+/* Disable wakeup from Local--GIC FIQ. */
	+#define NB_CPUN_CONFIG_STATUS_POWER_CTRL_WU_LGIC_FIQ_DIS (1 << 18)
	+/* Disable wakeup from Local-GIC IRQ. */
	+#define NB_CPUN_CONFIG_STATUS_POWER_CTRL_WU_LGIC_IRQ_DIS (1 << 19)
	+/* Disable wakeup from IO-GIC FIQ. */
	+#define NB_CPUN_CONFIG_STATUS_POWER_CTRL_WU_IOGIC_FIQ_DIS (1 << 20)
	+/* Disable wakeup from IO-GIC IRQ. */
	+#define NB_CPUN_CONFIG_STATUS_POWER_CTRL_WU_IOGIC_IRQ_DIS (1 << 21)
	+/* Disable scheduling of interrrupts in GIC(500) to non-active CPU */
	+#define NB_CPUN_CONFIG_STATUS_POWER_CTRL_IOGIC_DIS_CPU (1 << 22)
	+
	+/** Power_Status register **/
	+/* Read-only bits that reflect the individual CPU power mode status.
	+Default value for non-exist CPU is 2b11:
	+normal - 0x0: Normal mode
	+por - 0x1: por on reset mode
	+deep_idle - 0x2: Dormant power mode state
	+poweredoff - 0x3: Powered-off power mode */
	+#define NB_CPUN_CONFIG_STATUS_POWER_STATUS_CPU_PM_MASK 0x00000003
	+#define NB_CPUN_CONFIG_STATUS_POWER_STATUS_CPU_PM_SHIFT 0
	+/* Normal power mode state */
	+#define NB_CPUN_CONFIG_STATUS_POWER_STATUS_CPU_PM_NORMAL \
	+ (0x0 << NB_CPUN_CONFIG_STATUS_POWER_STATUS_CPU_PM_SHIFT)
	+/* Idle power mode state (WFI) */
	+#define NB_CPUN_CONFIG_STATUS_POWER_STATUS_CPU_PM_IDLE \
	+ (0x1 << NB_CPUN_CONFIG_STATUS_POWER_STATUS_CPU_PM_SHIFT)
	+/* Dormant power mode state */
	+#define NB_CPUN_CONFIG_STATUS_POWER_STATUS_CPU_PM_DEEP_IDLE \
	+ (0x2 << NB_CPUN_CONFIG_STATUS_POWER_STATUS_CPU_PM_SHIFT)
	+/* Powered-off power mode */
	+#define NB_CPUN_CONFIG_STATUS_POWER_STATUS_CPU_PM_POWEREDOFF \
	+ (0x3 << NB_CPUN_CONFIG_STATUS_POWER_STATUS_CPU_PM_SHIFT)
	+/* WFI status */
	+#define NB_CPUN_CONFIG_STATUS_POWER_STATUS_WFI (1 << 2)
	+/* WFE status */
	+#define NB_CPUN_CONFIG_STATUS_POWER_STATUS_WFE (1 << 3)
	+
	+/** Warm_Rst_Ctl register **/
	+/* Disable CPU Warm Reset when warmrstreq is asserted
	+
	+When the Reset Request bit in the RMR or RMR_EL3 register is set to 1 in the CPU Core , the processor asserts the WARMRSTREQ signal and the SoC reset controller use this request to trigger a Warm reset of the processor and change the register width state. */
	+#define NB_CPUN_CONFIG_STATUS_WARM_RST_CTL_REQ_DIS (1 << 0)
	+/* Disable waiting WFI on Warm Reset */
	+#define NB_CPUN_CONFIG_STATUS_WARM_RST_CTL_WFI_DIS (1 << 1)
	+/* CPU Core AARach64 reset vector bar
	+This is Write Once register (controlled by aarch64_reg_force_* fields) */
	+#define NB_CPUN_CONFIG_STATUS_RVBAR_LOW_ADDR_31_2_MASK 0xFFFFFFFC
	+#define NB_CPUN_CONFIG_STATUS_RVBAR_LOW_ADDR_31_2_SHIFT 2
	+
	+/** Rvbar_High register **/
	+/* CPU Core AARach64 reset vector bar high bits
	+This is Write Once register (controlled by aarch64_reg_force_* fields) */
	+#define NB_CPUN_CONFIG_STATUS_RVBAR_HIGH_ADDR_43_32_MASK 0x00000FFF
	+#define NB_CPUN_CONFIG_STATUS_RVBAR_HIGH_ADDR_43_32_SHIFT 0
	+
	+/** pmu_snapshot register **/
	+/* PMU Snapshot Request */
	+#define NB_CPUN_CONFIG_STATUS_PMU_SNAPSHOT_REQ (1 << 0)
	+/* 0: HW deassert requests when received ack
	+1: SW deasserts request when received done */
	+#define NB_CPUN_CONFIG_STATUS_PMU_SNAPSHOT_MODE (1 << 1)
	+/* Snapshot process completed */
	+#define NB_CPUN_CONFIG_STATUS_PMU_SNAPSHOT_DONE (1 << 31)
	+
	+/** cpu_msg_in register **/
	+/* CPU read this register to receive input (char) from simulation. */
	+#define NB_CPUN_CONFIG_STATUS_CPU_MSG_IN_DATA_MASK 0x000000FF
	+#define NB_CPUN_CONFIG_STATUS_CPU_MSG_IN_DATA_SHIFT 0
	+/* Indicates the data is valid.
	+Cleared on read */
	+#define NB_CPUN_CONFIG_STATUS_CPU_MSG_IN_VALID (1 << 8)
	+
	+/** PMU_Control register **/
	+/* Disable all counters
	+When this bit is clear, counter state is determined through the specific counter control register */
	+#define NB_MC_PMU_PMU_CONTROL_DISABLE_ALL (1 << 0)
	+/* Pause all counters.
	+When this bit is clear, counter state is determined through the specific counter control register. */
	+#define NB_MC_PMU_PMU_CONTROL_PAUSE_ALL (1 << 1)
	+/* Overflow interrupt enable:
	+disable - 0x0: Disable interrupt on overflow.
	+enable - 0x1: Enable interrupt on overflow. */
	+#define NB_MC_PMU_PMU_CONTROL_OVRF_INTR_EN (1 << 2)
	+/* Number of monitored events supported by the PMU. */
	+#define NB_MC_PMU_PMU_CONTROL_NUM_OF_EVENTS_MASK 0x00FC0000
	+#define NB_MC_PMU_PMU_CONTROL_NUM_OF_EVENTS_SHIFT 18
	+#define NB_MC_PMU_PMU_CONTROL_NUM_OF_EVENTS_SHIFT_ALPINE 19
	+/* Number of counters implemented by PMU. */
	+#define NB_MC_PMU_PMU_CONTROL_NUM_OF_CNTS_MASK 0x0F000000
	+#define NB_MC_PMU_PMU_CONTROL_NUM_OF_CNTS_SHIFT 24
	+
	+/** Cfg register **/
	+/* Event select */
	+#define NB_MC_PMU_COUNTERS_CFG_EVENT_SEL_MASK 0x0000003F
	+#define NB_MC_PMU_COUNTERS_CFG_EVENT_SEL_SHIFT 0
	+/* Enable setting of counter low overflow status bit:
	+disable - 0x0: Disable setting.
	+enable - 0x1: Enable setting. */
	+#define NB_MC_PMU_COUNTERS_CFG_OVRF_LOW_STT_EN (1 << 6)
	+/* Enable setting of counter high overflow status bit:
	+disable - 0x0: Disable setting.
	+enable - 0x1: Enable setting. */
	+#define NB_MC_PMU_COUNTERS_CFG_OVRF_HIGH_STT_EN (1 << 7)
	+/* Enable pause on trigger in assertion:
	+disable - 0x0: Disable pause.
	+enable - 0x1: Enable pause. */
	+#define NB_MC_PMU_COUNTERS_CFG_TRIGIN_PAUSE_EN (1 << 8)
	+/* Enable increment trigger out for trace.
	+Trigger is generated whenever counter reaches <granule> value:
	+disable - 0x0: Disable trigger out.
	+enable - 0x1: Enable trigger out. */
	+#define NB_MC_PMU_COUNTERS_CFG_TRIGOUT_EN (1 << 9)
	+/* Trigger out granule value
	+Specifies the number of events counted between two consecutive trigger out events
	+0x0: 1 - Trigger out on every event occurrence.
	+0x1: 2 - Trigger out on every two events.
	+...
	+0xn: 2^(n-1) - Trigger out on event 2^(n-1) events.
	+...
	+0x1F: 2^31 */
	+#define NB_MC_PMU_COUNTERS_CFG_TRIGOUT_GRANULA_MASK 0x00007C00
	+#define NB_MC_PMU_COUNTERS_CFG_TRIGOUT_GRANULA_SHIFT 10
	+/* Pause on overflow bitmask
	+If set for counter <i>, current counter pauses counting when counter<i> is overflowed, including self-pause.
	+Bit [16]: counter 0
	+Bit [17]: counter 1
	+Note: This field must be changed for larger counters. */
	+#define NB_MC_PMU_COUNTERS_CFG_PAUSE_ON_OVRF_BITMASK_MASK 0x000F0000
	+#define NB_MC_PMU_COUNTERS_CFG_PAUSE_ON_OVRF_BITMASK_SHIFT 16
	+
	+/** Cntl register **/
	+/* Set the counter state to disable, enable, or pause:
	+0x0 - disable: Disable counter.
	+0x1 - enable: Enable counter.
	+0x3 - pause: Pause counter. */
	+#define NB_MC_PMU_COUNTERS_CNTL_CNT_STATE_MASK 0x00000003
	+#define NB_MC_PMU_COUNTERS_CNTL_CNT_STATE_SHIFT 0
	+/* Disable counter. */
	+#define NB_MC_PMU_COUNTERS_CNTL_CNT_STATE_DISABLE \
	+ (0x0 << NB_MC_PMU_COUNTERS_CNTL_CNT_STATE_SHIFT)
	+/* Enable counter. */
	+#define NB_MC_PMU_COUNTERS_CNTL_CNT_STATE_ENABLE \
	+ (0x1 << NB_MC_PMU_COUNTERS_CNTL_CNT_STATE_SHIFT)
	+/* Pause counter. */
	+#define NB_MC_PMU_COUNTERS_CNTL_CNT_STATE_PAUSE \
	+ (0x3 << NB_MC_PMU_COUNTERS_CNTL_CNT_STATE_SHIFT)
	+
	+/** High register **/
	+/* Counter high value */
	+#define NB_MC_PMU_COUNTERS_HIGH_COUNTER_MASK 0x0000FFFF
	+#define NB_MC_PMU_COUNTERS_HIGH_COUNTER_SHIFT 0
	+
	+/** version register **/
	+/* Revision number (Minor) */
	+#define NB_NB_VERSION_VERSION_RELEASE_NUM_MINOR_MASK 0x000000FF
	+#define NB_NB_VERSION_VERSION_RELEASE_NUM_MINOR_SHIFT 0
	+/* Revision number (Major) */
	+#define NB_NB_VERSION_VERSION_RELEASE_NUM_MAJOR_MASK 0x0000FF00
	+#define NB_NB_VERSION_VERSION_RELEASE_NUM_MAJOR_SHIFT 8
	+/* Date of release */
	+#define NB_NB_VERSION_VERSION_DATE_DAY_MASK 0x001F0000
	+#define NB_NB_VERSION_VERSION_DATE_DAY_SHIFT 16
	+/* Month of release */
	+#define NB_NB_VERSION_VERSION_DATA_MONTH_MASK 0x01E00000
	+#define NB_NB_VERSION_VERSION_DATA_MONTH_SHIFT 21
	+/* Year of release (starting from 2000) */
	+#define NB_NB_VERSION_VERSION_DATE_YEAR_MASK 0x3E000000
	+#define NB_NB_VERSION_VERSION_DATE_YEAR_SHIFT 25
	+/* Reserved */
	+#define NB_NB_VERSION_VERSION_RESERVED_MASK 0xC0000000
	+#define NB_NB_VERSION_VERSION_RESERVED_SHIFT 30
	+
	+/** cpu_vmid register **/
	+/* Target VMID */
	+#define NB_SRIOV_CPU_VMID_VAL_MASK 0x000000FF
	+#define NB_SRIOV_CPU_VMID_VAL_SHIFT 0
	+
	+/** DRAM_0_Control register **/
	+/* Controller Idle
	+Indicates to the DDR PHY, if set, that the memory controller is idle */
	+#define NB_DRAM_CHANNELS_DRAM_0_CONTROL_DDR_PHY_CTL_IDLE (1 << 0)
	+/* Disable clear exclusive monitor request from DDR controller to CPU
	+Clear request is triggered whenever an exlusive monitor inside the DDR controller is being invalidated. */
	+#define NB_DRAM_CHANNELS_DRAM_0_CONTROL_DDR_EXMON_REQ_DIS (1 << 1)
	+
	+/** DRAM_0_Status register **/
	+/* Bypass Mode: Indicates if set that the PHY is in PLL bypass mod */
	+#define NB_DRAM_CHANNELS_DRAM_0_STATUS_DDR_PHY_BYP_MODE (1 << 0)
	+/* Number of available AXI transactions (used positions) in the DDR controller read address FIFO. */
	+#define NB_DRAM_CHANNELS_DRAM_0_STATUS_RAQ_WCOUNT_MASK 0x00000030
	+#define NB_DRAM_CHANNELS_DRAM_0_STATUS_RAQ_WCOUNT_SHIFT 4
	+/* Number of available AXI transactions (used positions) in the DDR controller write address FIFO */
	+#define NB_DRAM_CHANNELS_DRAM_0_STATUS_WAQ_WCOUNT_0_MASK 0x000000C0
	+#define NB_DRAM_CHANNELS_DRAM_0_STATUS_WAQ_WCOUNT_0_SHIFT 6
	+/* Number of available Low priority read CAM slots (free positions) in the DDR controller.
	+Each slots holds a DRAM burst */
	+#define NB_DRAM_CHANNELS_DRAM_0_STATUS_LPR_CREDIT_CNT_MASK 0x00007F00
	+#define NB_DRAM_CHANNELS_DRAM_0_STATUS_LPR_CREDIT_CNT_SHIFT 8
	+/* Number of available High priority read CAM slots (free positions) in the DDR controller.
	+Each slots holds a DRAM burst */
	+#define NB_DRAM_CHANNELS_DRAM_0_STATUS_HPR_CREDIT_CNT_MASK 0x003F8000
	+#define NB_DRAM_CHANNELS_DRAM_0_STATUS_HPR_CREDIT_CNT_SHIFT 15
	+/* Number of available write CAM slots (free positions) in the DDR controller.
	+Each slots holds a DRAM burst */
	+#define NB_DRAM_CHANNELS_DRAM_0_STATUS_WR_CREDIT_CNT_MASK 0x1FC00000
	+#define NB_DRAM_CHANNELS_DRAM_0_STATUS_WR_CREDIT_CNT_SHIFT 22
	+
	+/** DDR_Int_Cause register **/
	+/* This interrupt is asserted when a correctable ECC error is detected */
	+#define NB_DRAM_CHANNELS_DDR_INT_CAUSE_ECC_CORRECTED_ERR (1 << 0)
	+/* This interrupt is asserted when a uncorrectable ECC error is detected */
	+#define NB_DRAM_CHANNELS_DDR_INT_CAUSE_ECC_UNCORRECTED_ERR (1 << 1)
	+/* This interrupt is asserted when a parity or CRC error is detected on the DFI interface */
	+#define NB_DRAM_CHANNELS_DDR_INT_CAUSE_DFI_ALERT_ERR (1 << 2)
	+/* On-Chip Write data parity error interrupt on output */
	+#define NB_DRAM_CHANNELS_DDR_INT_CAUSE_PAR_WDATA_OUT_ERR (1 << 3)
	+/* This interrupt is asserted when a parity error due to MRS is detected on the DFI interface */
	+#define NB_DRAM_CHANNELS_DDR_INT_CAUSE_DFI_ALERT_ERR_FATL (1 << 4)
	+/* This interrupt is asserted when the CRC/parity retry counter reaches it maximum value */
	+#define NB_DRAM_CHANNELS_DDR_INT_CAUSE_DFI_ALERT_ERR_MAX_REACHED (1 << 5)
	+/* AXI Read address parity error interrupt.
	+This interrupt is asserted when an on-chip parity error occurred on the DDR controller AXI read address. */
	+#define NB_DRAM_CHANNELS_DDR_INT_CAUSE_PAR_RADDR_ERR (1 << 6)
	+/* AXI Read data parity error interrupt.
	+This interrupt is asserted when an on-chip parity error occurred on the DDR controller AXI read data */
	+#define NB_DRAM_CHANNELS_DDR_INT_CAUSE_PAR_RDATA_ERR (1 << 7)
	+/* AXI Write address parity error interrupt.
	+This interrupt is asserted when an on-chip parity error occurred on the DDR controller AXI write address. */
	+#define NB_DRAM_CHANNELS_DDR_INT_CAUSE_PAR_WADDR_ERR (1 << 8)
	+/* AXI Write data parity error interrupt on input.
	+This interrupt is asserted when an on-chip parity error occurred on the DDR controller AXI write data */
	+#define NB_DRAM_CHANNELS_DDR_INT_CAUSE_PAR_WDATA_IN_ERR (1 << 9)
	+
	+/** Address_Map register **/
	+/* Controls which system address bit will be mapped to DDR row bit 2.
	+This field is only used when addrmap_part_en == 1 */
	+#define NB_DRAM_CHANNELS_ADDRESS_MAP_ADDRMAP_ROW_B2_MASK 0x0000000F
	+#define NB_DRAM_CHANNELS_ADDRESS_MAP_ADDRMAP_ROW_B2_SHIFT 0
	+/* Controls which system address bit will be mapped to DDR row bit 3.
	+This field is only used when addrmap_part_en == 1 */
	+#define NB_DRAM_CHANNELS_ADDRESS_MAP_ADDRMAP_ROW_B3_MASK 0x000003C0
	+#define NB_DRAM_CHANNELS_ADDRESS_MAP_ADDRMAP_ROW_B3_SHIFT 6
	+/* Controls which system address bit will be mapped to DDR row bit 4.
	+This field is only used when addrmap_part_en == 1 */
	+#define NB_DRAM_CHANNELS_ADDRESS_MAP_ADDRMAP_ROW_B4_MASK 0x0000F000
	+#define NB_DRAM_CHANNELS_ADDRESS_MAP_ADDRMAP_ROW_B4_SHIFT 12
	+/* Controls which system address bit will be mapped to DDR row bit 5.
	+This field is only used when addrmap_part_en == 1 */
	+#define NB_DRAM_CHANNELS_ADDRESS_MAP_ADDRMAP_ROW_B5_MASK 0x003C0000
	+#define NB_DRAM_CHANNELS_ADDRESS_MAP_ADDRMAP_ROW_B5_SHIFT 18
	+/* Enables partitioning of the address mapping control.
	+When set, addrmap_row_b2-5 are used inside DDR controler instead of the built in address mapping registers */
	+#define NB_DRAM_CHANNELS_ADDRESS_MAP_ADDRMAP_PART_EN (1 << 31)
	+
	+/** Reorder_ID_Mask register **/
	+/* DDR Read Reorder buffer ID mask.
	+If incoming read transaction ID ANDed with mask is equal Reorder_ID_Value, then the transaction is mapped to the DDR controller bypass channel.
	+Setting this register to 0 will disable the check */
	+#define NB_DRAM_CHANNELS_REORDER_ID_MASK_MASK_MASK 0x003FFFFF
	+#define NB_DRAM_CHANNELS_REORDER_ID_MASK_MASK_SHIFT 0
	+
	+/** Reorder_ID_Value register **/
	+/* DDR Read Reorder buffer ID value
	+If incoming read transaction ID ANDed with Reorder_ID_Mask is equal to this register, then the transaction is mapped to the DDR controller bypass channel */
	+#define NB_DRAM_CHANNELS_REORDER_ID_VALUE_VALUE_MASK 0x003FFFFF
	+#define NB_DRAM_CHANNELS_REORDER_ID_VALUE_VALUE_SHIFT 0
	+
	+/** MRR_Control_Status register **/
	+/* DDR4 Mode Register Read Data Valid */
	+#define NB_DRAM_CHANNELS_MRR_CONTROL_STATUS_MRR_VLD (1 << 0)
	+/* MRR Ack, when asserted it clears the mrr_val indication and ready to load new MRR data. Write 1 to clear and then 0 */
	+#define NB_DRAM_CHANNELS_MRR_CONTROL_STATUS_MRR_ACK (1 << 16)
	+
	+/** pp_config register **/
	+/* Bypass PP module (formality equivalent) */
	+#define NB_PUSH_PACKET_PP_CONFIG_FM_BYPASS (1 << 0)
	+/* Bypass PP module */
	+#define NB_PUSH_PACKET_PP_CONFIG_BYPASS (1 << 1)
	+/* Force Cleanup of entries */
	+#define NB_PUSH_PACKET_PP_CONFIG_CLEAR (1 << 2)
	+/* Enable forwarding DECERR response */
	+#define NB_PUSH_PACKET_PP_CONFIG_DECERR_EN (1 << 3)
	+/* Enable forwarding SLVERR response */
	+#define NB_PUSH_PACKET_PP_CONFIG_SLVERR_EN (1 << 4)
	+/* Enable forwarding of data parity generation */
	+#define NB_PUSH_PACKET_PP_CONFIG_PAR_GEN_EN (1 << 5)
	+/* Select channel on 8K boundaries ([15:13]) instead of 64k boundaries ([18:16]). */
	+#define NB_PUSH_PACKET_PP_CONFIG_SEL_8K (1 << 6)
	+/* Forces awuser to be as configured in ext_awuser register.
	+Not functional */
	+#define NB_PUSH_PACKET_PP_CONFIG_SEL_EXT_AWUSER (1 << 7)
	+/* Enables PP channel.
	+1 bit per channel */
	+#define NB_PUSH_PACKET_PP_CONFIG_CHANNEL_ENABLE_MASK 0x00030000
	+#define NB_PUSH_PACKET_PP_CONFIG_CHANNEL_ENABLE_SHIFT 16
	+
	+#define NB_PUSH_PACKET_PP_CONFIG_CHANNEL_ENABLE(i) \
	+ (1 << (NB_PUSH_PACKET_PP_CONFIG_CHANNEL_ENABLE_SHIFT + i))
	+
	+/** pp_ext_awuser register **/
	+/* Awuser to use on PP transactions
	+Only applicable if config.sel_ext_awuser is set to 1'b1
	+Parity bits are still generated per transaction */
	+#define NB_PUSH_PACKET_PP_EXT_AWUSER_AWUSER_MASK 0x03FFFFFF
	+#define NB_PUSH_PACKET_PP_EXT_AWUSER_AWUSER_SHIFT 0
	+
	+/** pp_sel_awuser register **/
	+/* Select whether to use addr[63:48] or PP awmisc as vmid.
	+Each bit if set to 1 selects the corresponding address bit. Otherwise, selects the corersponding awmis bit. */
	+#define NB_PUSH_PACKET_PP_SEL_AWUSER_SEL_MASK 0x0000FFFF
	+#define NB_PUSH_PACKET_PP_SEL_AWUSER_SEL_SHIFT 0
	+
	+#ifdef __cplusplus
	+}
	+#endif
	+
	+#endif /* __AL_HAL_NB_REGS_H__ */
	+
	+/** @} end of ... group */
	+
	+
	Index: sys/arm/annapurna/alpine/hal/al_hal_pbs_regs.h
	===================================================================
	--- /dev/null
	+++ sys/arm/annapurna/alpine/hal/al_hal_pbs_regs.h
	@@ -0,0 +1,2751 @@
	+/*-
	+********************************************************************************
	+Copyright (C) 2015 Annapurna Labs Ltd.
	+
	+This file may be licensed under the terms of the Annapurna Labs Commercial
	+License Agreement.
	+
	+Alternatively, this file can be distributed under the terms of the GNU General
	+Public License V2 as published by the Free Software Foundation and can be
	+found at http://www.gnu.org/licenses/gpl-2.0.html
	+
	+Alternatively, redistribution and use in source and binary forms, with or
	+without modification, are permitted provided that the following conditions are
	+met:
	+
	+ * Redistributions of source code must retain the above copyright notice,
	+this list of conditions and the following disclaimer.
	+
	+ * Redistributions in binary form must reproduce the above copyright
	+notice, this list of conditions and the following disclaimer in
	+the documentation and/or other materials provided with the
	+distribution.
	+
	+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
	+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
	+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
	+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
	+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
	+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
	+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
	+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
	+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
	+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	+
	+*******************************************************************************/
	+
	+/**
	+ * @{
	+ * @file al_hal_pbs_regs.h
	+ *
	+ * @brief ... registers
	+ *
	+ */
	+
	+#ifndef __AL_HAL_PBS_REGS_H__
	+#define __AL_HAL_PBS_REGS_H__
	+
	+#include "al_hal_plat_types.h"
	+
	+#ifdef __cplusplus
	+extern "C" {
	+#endif
	+/*
	+* Unit Registers
	+*/
	+
	+
	+
	+struct al_pbs_unit {
	+ /* [0x0] Conf_bus, Configuration of the SB */
	+ uint32_t conf_bus;
	+ /* [0x4] PASW high */
	+ uint32_t dram_0_nb_bar_high;
	+ /* [0x8] PASW low */
	+ uint32_t dram_0_nb_bar_low;
	+ /* [0xc] PASW high */
	+ uint32_t dram_1_nb_bar_high;
	+ /* [0x10] PASW low */
	+ uint32_t dram_1_nb_bar_low;
	+ /* [0x14] PASW high */
	+ uint32_t dram_2_nb_bar_high;
	+ /* [0x18] PASW low */
	+ uint32_t dram_2_nb_bar_low;
	+ /* [0x1c] PASW high */
	+ uint32_t dram_3_nb_bar_high;
	+ /* [0x20] PASW low */
	+ uint32_t dram_3_nb_bar_low;
	+ /* [0x24] PASW high */
	+ uint32_t msix_nb_bar_high;
	+ /* [0x28] PASW low */
	+ uint32_t msix_nb_bar_low;
	+ /* [0x2c] PASW high */
	+ uint32_t dram_0_sb_bar_high;
	+ /* [0x30] PASW low */
	+ uint32_t dram_0_sb_bar_low;
	+ /* [0x34] PASW high */
	+ uint32_t dram_1_sb_bar_high;
	+ /* [0x38] PASW low */
	+ uint32_t dram_1_sb_bar_low;
	+ /* [0x3c] PASW high */
	+ uint32_t dram_2_sb_bar_high;
	+ /* [0x40] PASW low */
	+ uint32_t dram_2_sb_bar_low;
	+ /* [0x44] PASW high */
	+ uint32_t dram_3_sb_bar_high;
	+ /* [0x48] PASW low */
	+ uint32_t dram_3_sb_bar_low;
	+ /* [0x4c] PASW high */
	+ uint32_t msix_sb_bar_high;
	+ /* [0x50] PASW low */
	+ uint32_t msix_sb_bar_low;
	+ /* [0x54] PASW high */
	+ uint32_t pcie_mem0_bar_high;
	+ /* [0x58] PASW low */
	+ uint32_t pcie_mem0_bar_low;
	+ /* [0x5c] PASW high */
	+ uint32_t pcie_mem1_bar_high;
	+ /* [0x60] PASW low */
	+ uint32_t pcie_mem1_bar_low;
	+ /* [0x64] PASW high */
	+ uint32_t pcie_mem2_bar_high;
	+ /* [0x68] PASW low */
	+ uint32_t pcie_mem2_bar_low;
	+ /* [0x6c] PASW high */
	+ uint32_t pcie_ext_ecam0_bar_high;
	+ /* [0x70] PASW low */
	+ uint32_t pcie_ext_ecam0_bar_low;
	+ /* [0x74] PASW high */
	+ uint32_t pcie_ext_ecam1_bar_high;
	+ /* [0x78] PASW low */
	+ uint32_t pcie_ext_ecam1_bar_low;
	+ /* [0x7c] PASW high */
	+ uint32_t pcie_ext_ecam2_bar_high;
	+ /* [0x80] PASW low */
	+ uint32_t pcie_ext_ecam2_bar_low;
	+ /* [0x84] PASW high */
	+ uint32_t pbs_nor_bar_high;
	+ /* [0x88] PASW low */
	+ uint32_t pbs_nor_bar_low;
	+ /* [0x8c] PASW high */
	+ uint32_t pbs_spi_bar_high;
	+ /* [0x90] PASW low */
	+ uint32_t pbs_spi_bar_low;
	+ uint32_t rsrvd_0[3];
	+ /* [0xa0] PASW high */
	+ uint32_t pbs_nand_bar_high;
	+ /* [0xa4] PASW low */
	+ uint32_t pbs_nand_bar_low;
	+ /* [0xa8] PASW high */
	+ uint32_t pbs_int_mem_bar_high;
	+ /* [0xac] PASW low */
	+ uint32_t pbs_int_mem_bar_low;
	+ /* [0xb0] PASW high */
	+ uint32_t pbs_boot_bar_high;
	+ /* [0xb4] PASW low */
	+ uint32_t pbs_boot_bar_low;
	+ /* [0xb8] PASW high */
	+ uint32_t nb_int_bar_high;
	+ /* [0xbc] PASW low */
	+ uint32_t nb_int_bar_low;
	+ /* [0xc0] PASW high */
	+ uint32_t nb_stm_bar_high;
	+ /* [0xc4] PASW low */
	+ uint32_t nb_stm_bar_low;
	+ /* [0xc8] PASW high */
	+ uint32_t pcie_ecam_int_bar_high;
	+ /* [0xcc] PASW low */
	+ uint32_t pcie_ecam_int_bar_low;
	+ /* [0xd0] PASW high */
	+ uint32_t pcie_mem_int_bar_high;
	+ /* [0xd4] PASW low */
	+ uint32_t pcie_mem_int_bar_low;
	+ /* [0xd8] Control */
	+ uint32_t winit_cntl;
	+ /* [0xdc] Control */
	+ uint32_t latch_bars;
	+ /* [0xe0] Control */
	+ uint32_t pcie_conf_0;
	+ /* [0xe4] Control */
	+ uint32_t pcie_conf_1;
	+ /* [0xe8] Control */
	+ uint32_t serdes_mux_pipe;
	+ /* [0xec] Control */
	+ uint32_t dma_io_master_map;
	+ /* [0xf0] Status */
	+ uint32_t i2c_pld_status_high;
	+ /* [0xf4] Status */
	+ uint32_t i2c_pld_status_low;
	+ /* [0xf8] Status */
	+ uint32_t spi_dbg_status_high;
	+ /* [0xfc] Status */
	+ uint32_t spi_dbg_status_low;
	+ /* [0x100] Status */
	+ uint32_t spi_mst_status_high;
	+ /* [0x104] Status */
	+ uint32_t spi_mst_status_low;
	+ /* [0x108] Log */
	+ uint32_t mem_pbs_parity_err_high;
	+ /* [0x10c] Log */
	+ uint32_t mem_pbs_parity_err_low;
	+ /* [0x110] Log */
	+ uint32_t boot_strap;
	+ /* [0x114] Conf */
	+ uint32_t cfg_axi_conf_0;
	+ /* [0x118] Conf */
	+ uint32_t cfg_axi_conf_1;
	+ /* [0x11c] Conf */
	+ uint32_t cfg_axi_conf_2;
	+ /* [0x120] Conf */
	+ uint32_t cfg_axi_conf_3;
	+ /* [0x124] Conf */
	+ uint32_t spi_mst_conf_0;
	+ /* [0x128] Conf */
	+ uint32_t spi_mst_conf_1;
	+ /* [0x12c] Conf */
	+ uint32_t spi_slv_conf_0;
	+ /* [0x130] Conf */
	+ uint32_t apb_mem_conf_int;
	+ /* [0x134] PASW remap register */
	+ uint32_t sb2nb_cfg_dram_remap;
	+ /* [0x138] Control */
	+ uint32_t pbs_mux_sel_0;
	+ /* [0x13c] Control */
	+ uint32_t pbs_mux_sel_1;
	+ /* [0x140] Control */
	+ uint32_t pbs_mux_sel_2;
	+ /* [0x144] Control */
	+ uint32_t pbs_mux_sel_3;
	+ /* [0x148] PASW high */
	+ uint32_t sb_int_bar_high;
	+ /* [0x14c] PASW low */
	+ uint32_t sb_int_bar_low;
	+ /* [0x150] log */
	+ uint32_t ufc_pbs_parity_err_high;
	+ /* [0x154] log */
	+ uint32_t ufc_pbs_parity_err_low;
	+ /* [0x158] Cntl - internal */
	+ uint32_t gen_conf;
	+ /* [0x15c] Device ID and Rev ID */
	+ uint32_t chip_id;
	+ /* [0x160] Status - internal */
	+ uint32_t uart0_debug;
	+ /* [0x164] Status - internal */
	+ uint32_t uart1_debug;
	+ /* [0x168] Status - internal */
	+ uint32_t uart2_debug;
	+ /* [0x16c] Status - internal */
	+ uint32_t uart3_debug;
	+ /* [0x170] Control - internal */
	+ uint32_t uart0_conf_status;
	+ /* [0x174] Control - internal */
	+ uint32_t uart1_conf_status;
	+ /* [0x178] Control - internal */
	+ uint32_t uart2_conf_status;
	+ /* [0x17c] Control - internal */
	+ uint32_t uart3_conf_status;
	+ /* [0x180] Control - internal */
	+ uint32_t gpio0_conf_status;
	+ /* [0x184] Control - internal */
	+ uint32_t gpio1_conf_status;
	+ /* [0x188] Control - internal */
	+ uint32_t gpio2_conf_status;
	+ /* [0x18c] Control - internal */
	+ uint32_t gpio3_conf_status;
	+ /* [0x190] Control - internal */
	+ uint32_t gpio4_conf_status;
	+ /* [0x194] Control - internal */
	+ uint32_t i2c_gen_conf_status;
	+ /* [0x198] Control - internal */
	+ uint32_t i2c_gen_debug;
	+ /* [0x19c] Cntl */
	+ uint32_t watch_dog_reset_out;
	+ /* [0x1a0] Cntl */
	+ uint32_t otp_magic_num;
	+ /*
	+ * [0x1a4] Control - internal
	+ */
	+ uint32_t otp_cntl;
	+ /* [0x1a8] Cfg - internal */
	+ uint32_t otp_cfg_0;
	+ /* [0x1ac] Cfg - internal */
	+ uint32_t otp_cfg_1;
	+ /* [0x1b0] Cfg - internal */
	+ uint32_t otp_cfg_3;
	+ /* [0x1b4] Cfg */
	+ uint32_t cfg_nand_0;
	+ /* [0x1b8] Cfg */
	+ uint32_t cfg_nand_1;
	+ /* [0x1bc] Cfg-- timing parameters internal. */
	+ uint32_t cfg_nand_2;
	+ /* [0x1c0] Cfg - internal */
	+ uint32_t cfg_nand_3;
	+ /* [0x1c4] PASW high */
	+ uint32_t nb_nic_regs_bar_high;
	+ /* [0x1c8] PASW low */
	+ uint32_t nb_nic_regs_bar_low;
	+ /* [0x1cc] PASW high */
	+ uint32_t sb_nic_regs_bar_high;
	+ /* [0x1d0] PASW low */
	+ uint32_t sb_nic_regs_bar_low;
	+ /* [0x1d4] Control */
	+ uint32_t serdes_mux_multi_0;
	+ /* [0x1d8] Control */
	+ uint32_t serdes_mux_multi_1;
	+ /* [0x1dc] Control - not in use any more - internal */
	+ uint32_t pbs_ulpi_mux_conf;
	+ /* [0x1e0] Cntl */
	+ uint32_t wr_once_dbg_dis_ovrd_reg;
	+ /* [0x1e4] Cntl - internal */
	+ uint32_t gpio5_conf_status;
	+ /* [0x1e8] PASW high */
	+ uint32_t pcie_mem3_bar_high;
	+ /* [0x1ec] PASW low */
	+ uint32_t pcie_mem3_bar_low;
	+ /* [0x1f0] PASW high */
	+ uint32_t pcie_mem4_bar_high;
	+ /* [0x1f4] PASW low */
	+ uint32_t pcie_mem4_bar_low;
	+ /* [0x1f8] PASW high */
	+ uint32_t pcie_mem5_bar_high;
	+ /* [0x1fc] PASW low */
	+ uint32_t pcie_mem5_bar_low;
	+ /* [0x200] PASW high */
	+ uint32_t pcie_ext_ecam3_bar_high;
	+ /* [0x204] PASW low */
	+ uint32_t pcie_ext_ecam3_bar_low;
	+ /* [0x208] PASW high */
	+ uint32_t pcie_ext_ecam4_bar_high;
	+ /* [0x20c] PASW low */
	+ uint32_t pcie_ext_ecam4_bar_low;
	+ /* [0x210] PASW high */
	+ uint32_t pcie_ext_ecam5_bar_high;
	+ /* [0x214] PASW low */
	+ uint32_t pcie_ext_ecam5_bar_low;
	+ /* [0x218] PASW high */
	+ uint32_t low_latency_sram_bar_high;
	+ /* [0x21c] PASW low */
	+ uint32_t low_latency_sram_bar_low;
	+ /* [0x220] Control */
	+ uint32_t pbs_mux_sel_4;
	+ /* [0x224] Control */
	+ uint32_t pbs_mux_sel_5;
	+ /* [0x228] Control */
	+ uint32_t serdes_mux_eth;
	+ /* [0x22c] Control */
	+ uint32_t serdes_mux_pcie;
	+ /* [0x230] Control */
	+ uint32_t serdes_mux_sata;
	+ uint32_t rsrvd[7];
	+};
	+struct al_pbs_low_latency_sram_remap {
	+ /* [0x0] PBS MEM Remap */
	+ uint32_t bar1_orig;
	+ /* [0x4] PBS MEM Remap */
	+ uint32_t bar1_remap;
	+ /* [0x8] ETH0 MEM Remap */
	+ uint32_t bar2_orig;
	+ /* [0xc] ETH0 MEM Remap */
	+ uint32_t bar2_remap;
	+ /* [0x10] ETH1 MEM Remap */
	+ uint32_t bar3_orig;
	+ /* [0x14] ETH1 MEM Remap */
	+ uint32_t bar3_remap;
	+ /* [0x18] ETH2 MEM Remap */
	+ uint32_t bar4_orig;
	+ /* [0x1c] ETH2 MEM Remap */
	+ uint32_t bar4_remap;
	+ /* [0x20] ETH3 MEM Remap */
	+ uint32_t bar5_orig;
	+ /* [0x24] ETH3 MEM Remap */
	+ uint32_t bar5_remap;
	+ /* [0x28] CRYPTO0 MEM Remap */
	+ uint32_t bar6_orig;
	+ /* [0x2c] CRYPTO0 MEM Remap */
	+ uint32_t bar6_remap;
	+ /* [0x30] RAID0 MEM Remap */
	+ uint32_t bar7_orig;
	+ /* [0x34] RAID0 MEM Remap */
	+ uint32_t bar7_remap;
	+ /* [0x38] CRYPTO1 MEM Remap */
	+ uint32_t bar8_orig;
	+ /* [0x3c] CRYPTO1 MEM Remap */
	+ uint32_t bar8_remap;
	+ /* [0x40] RAID1 MEM Remap */
	+ uint32_t bar9_orig;
	+ /* [0x44] RAID2 MEM Remap */
	+ uint32_t bar9_remap;
	+ /* [0x48] RESERVED MEM Remap */
	+ uint32_t bar10_orig;
	+ /* [0x4c] RESERVED MEM Remap */
	+ uint32_t bar10_remap;
	+};
	+struct al_pbs_target_id_enforcement {
	+ /* [0x0] target enforcement */
	+ uint32_t cpu;
	+ /* [0x4] target enforcement mask (bits which are 0 are not compared) */
	+ uint32_t cpu_mask;
	+ /* [0x8] target enforcement */
	+ uint32_t debug_nb;
	+ /* [0xc] target enforcement mask (bits which are 0 are not compared) */
	+ uint32_t debug_nb_mask;
	+ /* [0x10] target enforcement */
	+ uint32_t debug_sb;
	+ /* [0x14] target enforcement mask (bits which are 0 are not compared) */
	+ uint32_t debug_sb_mask;
	+ /* [0x18] target enforcement */
	+ uint32_t eth_0;
	+ /* [0x1c] target enforcement mask (bits which are 0 are not compared) */
	+ uint32_t eth_0_mask;
	+ /* [0x20] target enforcement */
	+ uint32_t eth_1;
	+ /* [0x24] target enforcement mask (bits which are 0 are not compared) */
	+ uint32_t eth_1_mask;
	+ /* [0x28] target enforcement */
	+ uint32_t eth_2;
	+ /* [0x2c] target enforcement mask (bits which are 0 are not compared) */
	+ uint32_t eth_2_mask;
	+ /* [0x30] target enforcement */
	+ uint32_t eth_3;
	+ /* [0x34] target enforcement mask (bits which are 0 are not compared) */
	+ uint32_t eth_3_mask;
	+ /* [0x38] target enforcement */
	+ uint32_t sata_0;
	+ /* [0x3c] target enforcement mask (bits which are 0 are not compared) */
	+ uint32_t sata_0_mask;
	+ /* [0x40] target enforcement */
	+ uint32_t sata_1;
	+ /* [0x44] target enforcement mask (bits which are 0 are not compared) */
	+ uint32_t sata_1_mask;
	+ /* [0x48] target enforcement */
	+ uint32_t crypto_0;
	+ /* [0x4c] target enforcement mask (bits which are 0 are not compared) */
	+ uint32_t crypto_0_mask;
	+ /* [0x50] target enforcement */
	+ uint32_t crypto_1;
	+ /* [0x54] target enforcement mask (bits which are 0 are not compared) */
	+ uint32_t crypto_1_mask;
	+ /* [0x58] target enforcement */
	+ uint32_t pcie_0;
	+ /* [0x5c] target enforcement mask (bits which are 0 are not compared) */
	+ uint32_t pcie_0_mask;
	+ /* [0x60] target enforcement */
	+ uint32_t pcie_1;
	+ /* [0x64] target enforcement mask (bits which are 0 are not compared) */
	+ uint32_t pcie_1_mask;
	+ /* [0x68] target enforcement */
	+ uint32_t pcie_2;
	+ /* [0x6c] target enforcement mask (bits which are 0 are not compared) */
	+ uint32_t pcie_2_mask;
	+ /* [0x70] target enforcement */
	+ uint32_t pcie_3;
	+ /* [0x74] target enforcement mask (bits which are 0 are not compared) */
	+ uint32_t pcie_3_mask;
	+ /* [0x78] Control */
	+ uint32_t latch;
	+ uint32_t rsrvd[9];
	+};
	+
	+struct al_pbs_regs {
	+ struct al_pbs_unit unit; /* [0x0] */
	+struct al_pbs_low_latency_sram_remap low_latency_sram_remap;
	+/* [0x250] */
	+ uint32_t rsrvd_0[88];
	+ struct al_pbs_target_id_enforcement target_id_enforcement; /* [0x400] */
	+};
	+
	+
	+/*
	+* Registers Fields
	+*/
	+
	+
	+/** conf_bus register **/
	+/* Read slave error enable */
	+#define PBS_UNIT_CONF_BUS_RD_SLVERR_EN (1 << 0)
	+/* Write slave error enable */
	+#define PBS_UNIT_CONF_BUS_WR_SLVERR_EN (1 << 1)
	+/* Read decode error enable */
	+#define PBS_UNIT_CONF_BUS_RD_DECERR_EN (1 << 2)
	+/* Write decode error enable */
	+#define PBS_UNIT_CONF_BUS_WR_DECERR_EN (1 << 3)
	+/* For debug clear the APB SM */
	+#define PBS_UNIT_CONF_BUS_CLR_APB_FSM (1 << 4)
	+/* For debug clear the WFIFO */
	+#define PBS_UNIT_CONF_BUS_CLR_WFIFO_CLEAR (1 << 5)
	+/* Arbiter between read and write channel */
	+#define PBS_UNIT_CONF_BUS_WRR_CNT_MASK 0x000001C0
	+#define PBS_UNIT_CONF_BUS_WRR_CNT_SHIFT 6
	+
	+
	+/* general PASWS */
	+/* window size = 2 ^ (15 + win_size), zero value disable the win ... */
	+#define PBS_PASW_WIN_SIZE_MASK 0x0000003F
	+#define PBS_PASW_WIN_SIZE_SHIFT 0
	+/* reserved fields */
	+#define PBS_PASW_BAR_LOW_RSRVD_MASK 0x0000FFC0
	+#define PBS_PASW_BAR_LOW_RSRVD_SHIFT 6
	+/* bar low address 16 MSB bits */
	+#define PBS_PASW_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000
	+#define PBS_PASW_BAR_LOW_ADDR_HIGH_SHIFT 16
	+
	+/** dram_0_nb_bar_low register **/
	+/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */
	+#define PBS_UNIT_DRAM_0_NB_BAR_LOW_WIN_SIZE_MASK 0x0000003F
	+#define PBS_UNIT_DRAM_0_NB_BAR_LOW_WIN_SIZE_SHIFT 0
	+/* Reserved fields */
	+#define PBS_UNIT_DRAM_0_NB_BAR_LOW_RSRVD_MASK 0x0000FFC0
	+#define PBS_UNIT_DRAM_0_NB_BAR_LOW_RSRVD_SHIFT 6
	+/* bar low address 16 MSB bits */
	+#define PBS_UNIT_DRAM_0_NB_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000
	+#define PBS_UNIT_DRAM_0_NB_BAR_LOW_ADDR_HIGH_SHIFT 16
	+
	+/** dram_1_nb_bar_low register **/
	+/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */
	+#define PBS_UNIT_DRAM_1_NB_BAR_LOW_WIN_SIZE_MASK 0x0000003F
	+#define PBS_UNIT_DRAM_1_NB_BAR_LOW_WIN_SIZE_SHIFT 0
	+/* Reserved fields */
	+#define PBS_UNIT_DRAM_1_NB_BAR_LOW_RSRVD_MASK 0x0000FFC0
	+#define PBS_UNIT_DRAM_1_NB_BAR_LOW_RSRVD_SHIFT 6
	+/* bar low address 16 MSB bits */
	+#define PBS_UNIT_DRAM_1_NB_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000
	+#define PBS_UNIT_DRAM_1_NB_BAR_LOW_ADDR_HIGH_SHIFT 16
	+
	+/** dram_2_nb_bar_low register **/
	+/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */
	+#define PBS_UNIT_DRAM_2_NB_BAR_LOW_WIN_SIZE_MASK 0x0000003F
	+#define PBS_UNIT_DRAM_2_NB_BAR_LOW_WIN_SIZE_SHIFT 0
	+/* Reserved fields */
	+#define PBS_UNIT_DRAM_2_NB_BAR_LOW_RSRVD_MASK 0x0000FFC0
	+#define PBS_UNIT_DRAM_2_NB_BAR_LOW_RSRVD_SHIFT 6
	+/* bar low address 16 MSB bits */
	+#define PBS_UNIT_DRAM_2_NB_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000
	+#define PBS_UNIT_DRAM_2_NB_BAR_LOW_ADDR_HIGH_SHIFT 16
	+
	+/** dram_3_nb_bar_low register **/
	+/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */
	+#define PBS_UNIT_DRAM_3_NB_BAR_LOW_WIN_SIZE_MASK 0x0000003F
	+#define PBS_UNIT_DRAM_3_NB_BAR_LOW_WIN_SIZE_SHIFT 0
	+/* Reserved fields */
	+#define PBS_UNIT_DRAM_3_NB_BAR_LOW_RSRVD_MASK 0x0000FFC0
	+#define PBS_UNIT_DRAM_3_NB_BAR_LOW_RSRVD_SHIFT 6
	+/* bar low address 16 MSB bits */
	+#define PBS_UNIT_DRAM_3_NB_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000
	+#define PBS_UNIT_DRAM_3_NB_BAR_LOW_ADDR_HIGH_SHIFT 16
	+
	+/** msix_nb_bar_low register **/
	+/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */
	+#define PBS_UNIT_MSIX_NB_BAR_LOW_WIN_SIZE_MASK 0x0000003F
	+#define PBS_UNIT_MSIX_NB_BAR_LOW_WIN_SIZE_SHIFT 0
	+/* Reserved fields */
	+#define PBS_UNIT_MSIX_NB_BAR_LOW_RSRVD_MASK 0x0000FFC0
	+#define PBS_UNIT_MSIX_NB_BAR_LOW_RSRVD_SHIFT 6
	+/* bar low address 16 MSB bits */
	+#define PBS_UNIT_MSIX_NB_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000
	+#define PBS_UNIT_MSIX_NB_BAR_LOW_ADDR_HIGH_SHIFT 16
	+
	+/** dram_0_sb_bar_low register **/
	+/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */
	+#define PBS_UNIT_DRAM_0_SB_BAR_LOW_WIN_SIZE_MASK 0x0000003F
	+#define PBS_UNIT_DRAM_0_SB_BAR_LOW_WIN_SIZE_SHIFT 0
	+/* Reserved fields */
	+#define PBS_UNIT_DRAM_0_SB_BAR_LOW_RSRVD_MASK 0x0000FFC0
	+#define PBS_UNIT_DRAM_0_SB_BAR_LOW_RSRVD_SHIFT 6
	+/* bar low address 16 MSB bits */
	+#define PBS_UNIT_DRAM_0_SB_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000
	+#define PBS_UNIT_DRAM_0_SB_BAR_LOW_ADDR_HIGH_SHIFT 16
	+
	+/** dram_1_sb_bar_low register **/
	+/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */
	+#define PBS_UNIT_DRAM_1_SB_BAR_LOW_WIN_SIZE_MASK 0x0000003F
	+#define PBS_UNIT_DRAM_1_SB_BAR_LOW_WIN_SIZE_SHIFT 0
	+/* Reserved fields */
	+#define PBS_UNIT_DRAM_1_SB_BAR_LOW_RSRVD_MASK 0x0000FFC0
	+#define PBS_UNIT_DRAM_1_SB_BAR_LOW_RSRVD_SHIFT 6
	+/* bar low address 16 MSB bits */
	+#define PBS_UNIT_DRAM_1_SB_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000
	+#define PBS_UNIT_DRAM_1_SB_BAR_LOW_ADDR_HIGH_SHIFT 16
	+
	+/** dram_2_sb_bar_low register **/
	+/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */
	+#define PBS_UNIT_DRAM_2_SB_BAR_LOW_WIN_SIZE_MASK 0x0000003F
	+#define PBS_UNIT_DRAM_2_SB_BAR_LOW_WIN_SIZE_SHIFT 0
	+/* Reserved fields */
	+#define PBS_UNIT_DRAM_2_SB_BAR_LOW_RSRVD_MASK 0x0000FFC0
	+#define PBS_UNIT_DRAM_2_SB_BAR_LOW_RSRVD_SHIFT 6
	+/* bar low address 16 MSB bits */
	+#define PBS_UNIT_DRAM_2_SB_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000
	+#define PBS_UNIT_DRAM_2_SB_BAR_LOW_ADDR_HIGH_SHIFT 16
	+
	+/** dram_3_sb_bar_low register **/
	+/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */
	+#define PBS_UNIT_DRAM_3_SB_BAR_LOW_WIN_SIZE_MASK 0x0000003F
	+#define PBS_UNIT_DRAM_3_SB_BAR_LOW_WIN_SIZE_SHIFT 0
	+/* Reserved fields */
	+#define PBS_UNIT_DRAM_3_SB_BAR_LOW_RSRVD_MASK 0x0000FFC0
	+#define PBS_UNIT_DRAM_3_SB_BAR_LOW_RSRVD_SHIFT 6
	+/* bar low address 16 MSB bits */
	+#define PBS_UNIT_DRAM_3_SB_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000
	+#define PBS_UNIT_DRAM_3_SB_BAR_LOW_ADDR_HIGH_SHIFT 16
	+
	+/** msix_sb_bar_low register **/
	+/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */
	+#define PBS_UNIT_MSIX_SB_BAR_LOW_WIN_SIZE_MASK 0x0000003F
	+#define PBS_UNIT_MSIX_SB_BAR_LOW_WIN_SIZE_SHIFT 0
	+/* Reserved fields */
	+#define PBS_UNIT_MSIX_SB_BAR_LOW_RSRVD_MASK 0x0000FFC0
	+#define PBS_UNIT_MSIX_SB_BAR_LOW_RSRVD_SHIFT 6
	+/* bar low address 16 MSB bits */
	+#define PBS_UNIT_MSIX_SB_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000
	+#define PBS_UNIT_MSIX_SB_BAR_LOW_ADDR_HIGH_SHIFT 16
	+
	+/** pcie_mem0_bar_low register **/
	+/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */
	+#define PBS_UNIT_PCIE_MEM0_BAR_LOW_WIN_SIZE_MASK 0x0000003F
	+#define PBS_UNIT_PCIE_MEM0_BAR_LOW_WIN_SIZE_SHIFT 0
	+/* Reserved fields */
	+#define PBS_UNIT_PCIE_MEM0_BAR_LOW_RSRVD_MASK 0x0000FFC0
	+#define PBS_UNIT_PCIE_MEM0_BAR_LOW_RSRVD_SHIFT 6
	+/* bar low address 16 MSB bits */
	+#define PBS_UNIT_PCIE_MEM0_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000
	+#define PBS_UNIT_PCIE_MEM0_BAR_LOW_ADDR_HIGH_SHIFT 16
	+
	+/** pcie_mem1_bar_low register **/
	+/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */
	+#define PBS_UNIT_PCIE_MEM1_BAR_LOW_WIN_SIZE_MASK 0x0000003F
	+#define PBS_UNIT_PCIE_MEM1_BAR_LOW_WIN_SIZE_SHIFT 0
	+/* Reserved fields */
	+#define PBS_UNIT_PCIE_MEM1_BAR_LOW_RSRVD_MASK 0x0000FFC0
	+#define PBS_UNIT_PCIE_MEM1_BAR_LOW_RSRVD_SHIFT 6
	+/* bar low address 16 MSB bits */
	+#define PBS_UNIT_PCIE_MEM1_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000
	+#define PBS_UNIT_PCIE_MEM1_BAR_LOW_ADDR_HIGH_SHIFT 16
	+
	+/** pcie_mem2_bar_low register **/
	+/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */
	+#define PBS_UNIT_PCIE_MEM2_BAR_LOW_WIN_SIZE_MASK 0x0000003F
	+#define PBS_UNIT_PCIE_MEM2_BAR_LOW_WIN_SIZE_SHIFT 0
	+/* Reserved fields */
	+#define PBS_UNIT_PCIE_MEM2_BAR_LOW_RSRVD_MASK 0x0000FFC0
	+#define PBS_UNIT_PCIE_MEM2_BAR_LOW_RSRVD_SHIFT 6
	+/* bar low address 16 MSB bits */
	+#define PBS_UNIT_PCIE_MEM2_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000
	+#define PBS_UNIT_PCIE_MEM2_BAR_LOW_ADDR_HIGH_SHIFT 16
	+
	+/** pcie_ext_ecam0_bar_low register **/
	+/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */
	+#define PBS_UNIT_PCIE_EXT_ECAM0_BAR_LOW_WIN_SIZE_MASK 0x0000003F
	+#define PBS_UNIT_PCIE_EXT_ECAM0_BAR_LOW_WIN_SIZE_SHIFT 0
	+/* Reserved fields */
	+#define PBS_UNIT_PCIE_EXT_ECAM0_BAR_LOW_RSRVD_MASK 0x0000FFC0
	+#define PBS_UNIT_PCIE_EXT_ECAM0_BAR_LOW_RSRVD_SHIFT 6
	+/* bar low address 16 MSB bits */
	+#define PBS_UNIT_PCIE_EXT_ECAM0_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000
	+#define PBS_UNIT_PCIE_EXT_ECAM0_BAR_LOW_ADDR_HIGH_SHIFT 16
	+
	+/** pcie_ext_ecam1_bar_low register **/
	+/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */
	+#define PBS_UNIT_PCIE_EXT_ECAM1_BAR_LOW_WIN_SIZE_MASK 0x0000003F
	+#define PBS_UNIT_PCIE_EXT_ECAM1_BAR_LOW_WIN_SIZE_SHIFT 0
	+/* Reserved fields */
	+#define PBS_UNIT_PCIE_EXT_ECAM1_BAR_LOW_RSRVD_MASK 0x0000FFC0
	+#define PBS_UNIT_PCIE_EXT_ECAM1_BAR_LOW_RSRVD_SHIFT 6
	+/* bar low address 16 MSB bits */
	+#define PBS_UNIT_PCIE_EXT_ECAM1_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000
	+#define PBS_UNIT_PCIE_EXT_ECAM1_BAR_LOW_ADDR_HIGH_SHIFT 16
	+
	+/** pcie_ext_ecam2_bar_low register **/
	+/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */
	+#define PBS_UNIT_PCIE_EXT_ECAM2_BAR_LOW_WIN_SIZE_MASK 0x0000003F
	+#define PBS_UNIT_PCIE_EXT_ECAM2_BAR_LOW_WIN_SIZE_SHIFT 0
	+/* Reserved fields */
	+#define PBS_UNIT_PCIE_EXT_ECAM2_BAR_LOW_RSRVD_MASK 0x0000FFC0
	+#define PBS_UNIT_PCIE_EXT_ECAM2_BAR_LOW_RSRVD_SHIFT 6
	+/* bar low address 16 MSB bits */
	+#define PBS_UNIT_PCIE_EXT_ECAM2_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000
	+#define PBS_UNIT_PCIE_EXT_ECAM2_BAR_LOW_ADDR_HIGH_SHIFT 16
	+
	+/** pbs_nor_bar_low register **/
	+/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */
	+#define PBS_UNIT_PBS_NOR_BAR_LOW_WIN_SIZE_MASK 0x0000003F
	+#define PBS_UNIT_PBS_NOR_BAR_LOW_WIN_SIZE_SHIFT 0
	+/* Reserved fields */
	+#define PBS_UNIT_PBS_NOR_BAR_LOW_RSRVD_MASK 0x0000FFC0
	+#define PBS_UNIT_PBS_NOR_BAR_LOW_RSRVD_SHIFT 6
	+/* bar low address 16 MSB bits */
	+#define PBS_UNIT_PBS_NOR_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000
	+#define PBS_UNIT_PBS_NOR_BAR_LOW_ADDR_HIGH_SHIFT 16
	+
	+/** pbs_spi_bar_low register **/
	+/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */
	+#define PBS_UNIT_PBS_SPI_BAR_LOW_WIN_SIZE_MASK 0x0000003F
	+#define PBS_UNIT_PBS_SPI_BAR_LOW_WIN_SIZE_SHIFT 0
	+/* Reserved fields */
	+#define PBS_UNIT_PBS_SPI_BAR_LOW_RSRVD_MASK 0x0000FFC0
	+#define PBS_UNIT_PBS_SPI_BAR_LOW_RSRVD_SHIFT 6
	+/* bar low address 16 MSB bits */
	+#define PBS_UNIT_PBS_SPI_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000
	+#define PBS_UNIT_PBS_SPI_BAR_LOW_ADDR_HIGH_SHIFT 16
	+
	+/** pbs_nand_bar_low register **/
	+/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */
	+#define PBS_UNIT_PBS_NAND_BAR_LOW_WIN_SIZE_MASK 0x0000003F
	+#define PBS_UNIT_PBS_NAND_BAR_LOW_WIN_SIZE_SHIFT 0
	+/* Reserved fields */
	+#define PBS_UNIT_PBS_NAND_BAR_LOW_RSRVD_MASK 0x0000FFC0
	+#define PBS_UNIT_PBS_NAND_BAR_LOW_RSRVD_SHIFT 6
	+/* bar low address 16 MSB bits */
	+#define PBS_UNIT_PBS_NAND_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000
	+#define PBS_UNIT_PBS_NAND_BAR_LOW_ADDR_HIGH_SHIFT 16
	+
	+/** pbs_int_mem_bar_low register **/
	+/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */
	+#define PBS_UNIT_PBS_INT_MEM_BAR_LOW_WIN_SIZE_MASK 0x0000003F
	+#define PBS_UNIT_PBS_INT_MEM_BAR_LOW_WIN_SIZE_SHIFT 0
	+/* Reserved fields */
	+#define PBS_UNIT_PBS_INT_MEM_BAR_LOW_RSRVD_MASK 0x0000FFC0
	+#define PBS_UNIT_PBS_INT_MEM_BAR_LOW_RSRVD_SHIFT 6
	+/* bar low address 16 MSB bits */
	+#define PBS_UNIT_PBS_INT_MEM_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000
	+#define PBS_UNIT_PBS_INT_MEM_BAR_LOW_ADDR_HIGH_SHIFT 16
	+
	+/** pbs_boot_bar_low register **/
	+/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */
	+#define PBS_UNIT_PBS_BOOT_BAR_LOW_WIN_SIZE_MASK 0x0000003F
	+#define PBS_UNIT_PBS_BOOT_BAR_LOW_WIN_SIZE_SHIFT 0
	+/* Reserved fields */
	+#define PBS_UNIT_PBS_BOOT_BAR_LOW_RSRVD_MASK 0x0000FFC0
	+#define PBS_UNIT_PBS_BOOT_BAR_LOW_RSRVD_SHIFT 6
	+/* bar low address 16 MSB bits */
	+#define PBS_UNIT_PBS_BOOT_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000
	+#define PBS_UNIT_PBS_BOOT_BAR_LOW_ADDR_HIGH_SHIFT 16
	+
	+/** nb_int_bar_low register **/
	+/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */
	+#define PBS_UNIT_NB_INT_BAR_LOW_WIN_SIZE_MASK 0x0000003F
	+#define PBS_UNIT_NB_INT_BAR_LOW_WIN_SIZE_SHIFT 0
	+/* Reserved fields */
	+#define PBS_UNIT_NB_INT_BAR_LOW_RSRVD_MASK 0x0000FFC0
	+#define PBS_UNIT_NB_INT_BAR_LOW_RSRVD_SHIFT 6
	+/* bar low address 16 MSB bits */
	+#define PBS_UNIT_NB_INT_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000
	+#define PBS_UNIT_NB_INT_BAR_LOW_ADDR_HIGH_SHIFT 16
	+
	+/** nb_stm_bar_low register **/
	+/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */
	+#define PBS_UNIT_NB_STM_BAR_LOW_WIN_SIZE_MASK 0x0000003F
	+#define PBS_UNIT_NB_STM_BAR_LOW_WIN_SIZE_SHIFT 0
	+/* Reserved fields */
	+#define PBS_UNIT_NB_STM_BAR_LOW_RSRVD_MASK 0x0000FFC0
	+#define PBS_UNIT_NB_STM_BAR_LOW_RSRVD_SHIFT 6
	+/* bar low address 16 MSB bits */
	+#define PBS_UNIT_NB_STM_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000
	+#define PBS_UNIT_NB_STM_BAR_LOW_ADDR_HIGH_SHIFT 16
	+
	+/** pcie_ecam_int_bar_low register **/
	+/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */
	+#define PBS_UNIT_PCIE_ECAM_INT_BAR_LOW_WIN_SIZE_MASK 0x0000003F
	+#define PBS_UNIT_PCIE_ECAM_INT_BAR_LOW_WIN_SIZE_SHIFT 0
	+/* Reserved fields */
	+#define PBS_UNIT_PCIE_ECAM_INT_BAR_LOW_RSRVD_MASK 0x0000FFC0
	+#define PBS_UNIT_PCIE_ECAM_INT_BAR_LOW_RSRVD_SHIFT 6
	+/* bar low address 16 MSB bits */
	+#define PBS_UNIT_PCIE_ECAM_INT_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000
	+#define PBS_UNIT_PCIE_ECAM_INT_BAR_LOW_ADDR_HIGH_SHIFT 16
	+
	+/** pcie_mem_int_bar_low register **/
	+/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */
	+#define PBS_UNIT_PCIE_MEM_INT_BAR_LOW_WIN_SIZE_MASK 0x0000003F
	+#define PBS_UNIT_PCIE_MEM_INT_BAR_LOW_WIN_SIZE_SHIFT 0
	+/* Reserved fields */
	+#define PBS_UNIT_PCIE_MEM_INT_BAR_LOW_RSRVD_MASK 0x0000FFC0
	+#define PBS_UNIT_PCIE_MEM_INT_BAR_LOW_RSRVD_SHIFT 6
	+/* bar low address 16 MSB bits */
	+#define PBS_UNIT_PCIE_MEM_INT_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000
	+#define PBS_UNIT_PCIE_MEM_INT_BAR_LOW_ADDR_HIGH_SHIFT 16
	+
	+/** winit_cntl register **/
	+/* When set, enables access to winit regs, in normal mode. */
	+#define PBS_UNIT_WINIT_CNTL_ENABLE_WINIT_REGS_ACCESS (1 << 0)
	+/* Reserved */
	+#define PBS_UNIT_WINIT_CNTL_RSRVD_MASK 0xFFFFFFFE
	+#define PBS_UNIT_WINIT_CNTL_RSRVD_SHIFT 1
	+
	+/** latch_bars register **/
	+/*
	+ * Software clears this bit before any bar update, and set it after all bars
	+ * updated.
	+ */
	+#define PBS_UNIT_LATCH_BARS_ENABLE (1 << 0)
	+/* Reserved */
	+#define PBS_UNIT_LATCH_BARS_RSRVD_MASK 0xFFFFFFFE
	+#define PBS_UNIT_LATCH_BARS_RSRVD_SHIFT 1
	+
	+/** pcie_conf_0 register **/
	+/* NOT_use, config internal inside each PCIe core */
	+#define PBS_UNIT_PCIE_CONF_0_DEVS_TYPE_MASK 0x00000FFF
	+#define PBS_UNIT_PCIE_CONF_0_DEVS_TYPE_SHIFT 0
	+/* sys_aux_det value */
	+#define PBS_UNIT_PCIE_CONF_0_SYS_AUX_PWR_DET_VEC_MASK 0x00007000
	+#define PBS_UNIT_PCIE_CONF_0_SYS_AUX_PWR_DET_VEC_SHIFT 12
	+/* Reserved */
	+#define PBS_UNIT_PCIE_CONF_0_RSRVD_MASK 0xFFFF8000
	+#define PBS_UNIT_PCIE_CONF_0_RSRVD_SHIFT 15
	+
	+/** pcie_conf_1 register **/
	+/*
	+ * Which PCIe exists? The PCIe device is under reset until the corresponding bit
	+ * is set.
	+ */
	+#define PBS_UNIT_PCIE_CONF_1_PCIE_EXIST_MASK 0x0000003F
	+#define PBS_UNIT_PCIE_CONF_1_PCIE_EXIST_SHIFT 0
	+/* Reserved */
	+#define PBS_UNIT_PCIE_CONF_1_RSRVD_MASK 0xFFFFFFC0
	+#define PBS_UNIT_PCIE_CONF_1_RSRVD_SHIFT 6
	+
	+/** serdes_mux_pipe register **/
	+/* SerDes one hot mux control. For details see datasheet. */
	+#define PBS_UNIT_SERDES_MUX_PIPE_SELECT_OH_SERDES_2_MASK 0x00000007
	+#define PBS_UNIT_SERDES_MUX_PIPE_SELECT_OH_SERDES_2_SHIFT 0
	+/* Reserved */
	+#define PBS_UNIT_SERDES_MUX_PIPE_RSRVD_3 (1 << 3)
	+/* SerDes one hot mux control. For details see datasheet. */
	+#define PBS_UNIT_SERDES_MUX_PIPE_SELECT_OH_SERDES_3_MASK 0x00000070
	+#define PBS_UNIT_SERDES_MUX_PIPE_SELECT_OH_SERDES_3_SHIFT 4
	+/* Reserved */
	+#define PBS_UNIT_SERDES_MUX_PIPE_RSRVD_7 (1 << 7)
	+/* SerDes one hot mux control. For details see datasheet. */
	+#define PBS_UNIT_SERDES_MUX_PIPE_SELECT_OH_PCI_B_0_MASK 0x00000300
	+#define PBS_UNIT_SERDES_MUX_PIPE_SELECT_OH_PCI_B_0_SHIFT 8
	+/* SerDes one hot mux control. For details see datasheet. */
	+#define PBS_UNIT_SERDES_MUX_PIPE_SELECT_OH_PCI_B_1_MASK 0x00000C00
	+#define PBS_UNIT_SERDES_MUX_PIPE_SELECT_OH_PCI_B_1_SHIFT 10
	+/* SerDes one hot mux control. For details see datasheet. */
	+#define PBS_UNIT_SERDES_MUX_PIPE_SELECT_OH_PCI_C_0_MASK 0x00003000
	+#define PBS_UNIT_SERDES_MUX_PIPE_SELECT_OH_PCI_C_0_SHIFT 12
	+/* SerDes one hot mux control. For details see datasheet. */
	+#define PBS_UNIT_SERDES_MUX_PIPE_SELECT_OH_PCI_C_1_MASK 0x0000C000
	+#define PBS_UNIT_SERDES_MUX_PIPE_SELECT_OH_PCI_C_1_SHIFT 14
	+/* SerDes one hot mux control. For details see datasheet. */
	+#define PBS_UNIT_SERDES_MUX_PIPE_SELECT_OH_USB_A_0_MASK 0x00030000
	+#define PBS_UNIT_SERDES_MUX_PIPE_SELECT_OH_USB_A_0_SHIFT 16
	+/* SerDes one hot mux control. For details see datasheet. */
	+#define PBS_UNIT_SERDES_MUX_PIPE_SELECT_OH_USB_B_0_MASK 0x000C0000
	+#define PBS_UNIT_SERDES_MUX_PIPE_SELECT_OH_USB_B_0_SHIFT 18
	+/* SerDes one hot mux control. For details see datasheet. */
	+#define PBS_UNIT_SERDES_MUX_PIPE_SELECT_OH_CLKI_SER_2_MASK 0x00300000
	+#define PBS_UNIT_SERDES_MUX_PIPE_SELECT_OH_CLKI_SER_2_SHIFT 20
	+/* Reserved */
	+#define PBS_UNIT_SERDES_MUX_PIPE_RSRVD_23_22_MASK 0x00C00000
	+#define PBS_UNIT_SERDES_MUX_PIPE_RSRVD_23_22_SHIFT 22
	+/* SerDes one hot mux control. For details see datasheet. */
	+#define PBS_UNIT_SERDES_MUX_PIPE_SELECT_OH_CLKI_SER_3_MASK 0x07000000
	+#define PBS_UNIT_SERDES_MUX_PIPE_SELECT_OH_CLKI_SER_3_SHIFT 24
	+/* Reserved */
	+#define PBS_UNIT_SERDES_MUX_PIPE_RSRVD_MASK 0xF8000000
	+#define PBS_UNIT_SERDES_MUX_PIPE_RSRVD_SHIFT 27
	+
	+/*
	+ * 2'b01 - select pcie_b[0]
	+ * 2'b10 - select pcie_a[2]
	+ */
	+#define PBS_UNIT_SERDES_MUX_PIPE_PKR_SELECT_OH_SERDES_2_MASK 0x00000003
	+#define PBS_UNIT_SERDES_MUX_PIPE_PKR_SELECT_OH_SERDES_2_SHIFT 0
	+/*
	+ * 2'b01 - select pcie_b[1]
	+ * 2'b10 - select pcie_a[3]
	+ */
	+#define PBS_UNIT_SERDES_MUX_PIPE_PKR_SELECT_OH_SERDES_3_MASK 0x00000030
	+#define PBS_UNIT_SERDES_MUX_PIPE_PKR_SELECT_OH_SERDES_3_SHIFT 4
	+/*
	+ * 2'b01 - select pcie_b[0]
	+ * 2'b10 - select pcie_a[4]
	+ */
	+#define PBS_UNIT_SERDES_MUX_PIPE_PKR_SELECT_OH_SERDES_4_MASK 0x00000300
	+#define PBS_UNIT_SERDES_MUX_PIPE_PKR_SELECT_OH_SERDES_4_SHIFT 8
	+/*
	+ * 2'b01 - select pcie_b[1]
	+ * 2'b10 - select pcie_a[5]
	+ */
	+#define PBS_UNIT_SERDES_MUX_PIPE_PKR_SELECT_OH_SERDES_5_MASK 0x00003000
	+#define PBS_UNIT_SERDES_MUX_PIPE_PKR_SELECT_OH_SERDES_5_SHIFT 12
	+/*
	+ * 2'b01 - select pcie_b[2]
	+ * 2'b10 - select pcie_a[6]
	+ */
	+#define PBS_UNIT_SERDES_MUX_PIPE_PKR_SELECT_OH_SERDES_6_MASK 0x00030000
	+#define PBS_UNIT_SERDES_MUX_PIPE_PKR_SELECT_OH_SERDES_6_SHIFT 16
	+/*
	+ * 2'b01 - select pcie_b[3]
	+ * 2'b10 - select pcie_a[7]
	+ */
	+#define PBS_UNIT_SERDES_MUX_PIPE_PKR_SELECT_OH_SERDES_7_MASK 0x00300000
	+#define PBS_UNIT_SERDES_MUX_PIPE_PKR_SELECT_OH_SERDES_7_SHIFT 20
	+/*
	+ * 2'b01 - select pcie_d[0]
	+ * 2'b10 - select pcie_c[2]
	+ */
	+#define PBS_UNIT_SERDES_MUX_PIPE_PKR_SELECT_OH_SERDES_10_MASK 0x03000000
	+#define PBS_UNIT_SERDES_MUX_PIPE_PKR_SELECT_OH_SERDES_10_SHIFT 24
	+/*
	+ * 2'b01 - select pcie_d[1]
	+ * 2'b10 - select pcie_c[3]
	+ */
	+#define PBS_UNIT_SERDES_MUX_PIPE_PKR_SELECT_OH_SERDES_11_MASK 0x30000000
	+#define PBS_UNIT_SERDES_MUX_PIPE_PKR_SELECT_OH_SERDES_11_SHIFT 28
	+
	+/** dma_io_master_map register **/
	+/*
	+ * [0]: When set, maps all the io_dma transactions to the NB/DRAM, regardless of
	+ * the window hit.
	+ * [1]: When set, maps all the eth_0 transactions to the NB/DRAM, regardless of
	+ * the window hit.
	+ * [2]: When set, maps all the eth_2 transaction to the NB/DRAM, regardless of
	+ * the window hit.
	+ * [3]: When set, maps all the sata_0 transactions to the NB/DRAM, regardless of
	+ * the window hit.
	+ * [4]: When set, maps all the sata_1 transactions to the NB/DRAM, regardless of
	+ * the window hit.
	+ * [5]: When set, maps all the pcie_0 master transactions to the NB/DRAM,
	+ * regardless of the window hit.
	+ * [6]: When set, maps all the SPI debug port transactions to the NB/DRAM,
	+ * regardless of the window hit.
	+ * [7]: When set, maps all the CPU debug port transactions to the NB/DRAM,
	+ * regardless of the window hit.
	+ * [8] When set, maps all the Crypto transactions to the NB/DRAM, regardless of
	+ * the window hit.
	+ * [15:9] - Reserved
	+ */
	+#define PBS_UNIT_DMA_IO_MASTER_MAP_CNTL_MASK 0x0000FFFF
	+#define PBS_UNIT_DMA_IO_MASTER_MAP_CNTL_SHIFT 0
	+/* Reserved fields */
	+#define PBS_UNIT_DMA_IO_MASTER_MAP_RSRVD_MASK 0xFFFF0000
	+#define PBS_UNIT_DMA_IO_MASTER_MAP_RSRVD_SHIFT 16
	+
	+/** i2c_pld_status_high register **/
	+/* I2C pre-load status */
	+#define PBS_UNIT_I2C_PLD_STATUS_HIGH_STATUS_MASK 0x000000FF
	+#define PBS_UNIT_I2C_PLD_STATUS_HIGH_STATUS_SHIFT 0
	+
	+/** spi_dbg_status_high register **/
	+/* SPI DBG load status */
	+#define PBS_UNIT_SPI_DBG_STATUS_HIGH_STATUS_MASK 0x000000FF
	+#define PBS_UNIT_SPI_DBG_STATUS_HIGH_STATUS_SHIFT 0
	+
	+/** spi_mst_status_high register **/
	+/* SP IMST load status */
	+#define PBS_UNIT_SPI_MST_STATUS_HIGH_STATUS_MASK 0x000000FF
	+#define PBS_UNIT_SPI_MST_STATUS_HIGH_STATUS_SHIFT 0
	+
	+/** mem_pbs_parity_err_high register **/
	+/* Address latch in the case of a parity error */
	+#define PBS_UNIT_MEM_PBS_PARITY_ERR_HIGH_ADDR_MASK 0x000000FF
	+#define PBS_UNIT_MEM_PBS_PARITY_ERR_HIGH_ADDR_SHIFT 0
	+
	+/** cfg_axi_conf_0 register **/
	+/* Sets the AXI field in the I2C preloader interface. */
	+#define PBS_UNIT_CFG_AXI_CONF_0_DBG_RD_ID_MASK 0x0000007F
	+#define PBS_UNIT_CFG_AXI_CONF_0_DBG_RD_ID_SHIFT 0
	+/* Sets the AXI field in the I2C preloader interface. */
	+#define PBS_UNIT_CFG_AXI_CONF_0_DBG_WR_ID_MASK 0x00003F80
	+#define PBS_UNIT_CFG_AXI_CONF_0_DBG_WR_ID_SHIFT 7
	+/* Sets the AXI field in the I2C preloader interface. */
	+#define PBS_UNIT_CFG_AXI_CONF_0_PLD_WR_ID_MASK 0x001FC000
	+#define PBS_UNIT_CFG_AXI_CONF_0_PLD_WR_ID_SHIFT 14
	+/* Sets the AXI field in the SPI debug interface. */
	+#define PBS_UNIT_CFG_AXI_CONF_0_DBG_AWCACHE_MASK 0x01E00000
	+#define PBS_UNIT_CFG_AXI_CONF_0_DBG_AWCACHE_SHIFT 21
	+/* Sets the AXI field in the SPI debug interface. */
	+#define PBS_UNIT_CFG_AXI_CONF_0_DBG_ARCACHE_MASK 0x1E000000
	+#define PBS_UNIT_CFG_AXI_CONF_0_DBG_ARCACHE_SHIFT 25
	+/* Sets the AXI field in the SPI debug interface. */
	+#define PBS_UNIT_CFG_AXI_CONF_0_DBG_AXPROT_MASK 0xE0000000
	+#define PBS_UNIT_CFG_AXI_CONF_0_DBG_AXPROT_SHIFT 29
	+
	+/** cfg_axi_conf_1 register **/
	+/* Sets the AXI field in the SPI debug interface. */
	+#define PBS_UNIT_CFG_AXI_CONF_1_DBG_ARUSER_MASK 0x03FFFFFF
	+#define PBS_UNIT_CFG_AXI_CONF_1_DBG_ARUSER_SHIFT 0
	+/* Sets the AXI field in the SPI debug interface. */
	+#define PBS_UNIT_CFG_AXI_CONF_1_DBG_ARQOS_MASK 0x3C000000
	+#define PBS_UNIT_CFG_AXI_CONF_1_DBG_ARQOS_SHIFT 26
	+
	+/** cfg_axi_conf_2 register **/
	+/* Sets the AXI field in the SPI debug interface. */
	+#define PBS_UNIT_CFG_AXI_CONF_2_DBG_AWUSER_MASK 0x03FFFFFF
	+#define PBS_UNIT_CFG_AXI_CONF_2_DBG_AWUSER_SHIFT 0
	+/* Sets the AXI field in the SPI debug interface. */
	+#define PBS_UNIT_CFG_AXI_CONF_2_DBG_AWQOS_MASK 0x3C000000
	+#define PBS_UNIT_CFG_AXI_CONF_2_DBG_AWQOS_SHIFT 26
	+
	+/** spi_mst_conf_0 register **/
	+/*
	+ * Sets the SPI master Configuration. For details see the SPI section in the
	+ * documentation.
	+ */
	+#define PBS_UNIT_SPI_MST_CONF_0_CFG_SPI_MST_SRL (1 << 0)
	+/*
	+ * Sets the SPI master Configuration. For details see the SPI section in the
	+ * documentation.
	+ */
	+#define PBS_UNIT_SPI_MST_CONF_0_CFG_SPI_MST_SCPOL (1 << 1)
	+/*
	+ * Sets the SPI master Configuration. For details see the SPI section in the
	+ * documentation.
	+ */
	+#define PBS_UNIT_SPI_MST_CONF_0_CFG_SPI_MST_SCPH (1 << 2)
	+/*
	+ * Set the SPI master configuration. For details see the SPI section in the
	+ * documentation.
	+ */
	+#define PBS_UNIT_SPI_MST_CONF_0_CFG_SPI_MST_SER_MASK 0x00000078
	+#define PBS_UNIT_SPI_MST_CONF_0_CFG_SPI_MST_SER_SHIFT 3
	+/*
	+ * Set the SPI master configuration. For details see the SPI section in the
	+ * documentation.
	+ */
	+#define PBS_UNIT_SPI_MST_CONF_0_CFG_SPI_MST_BAUD_MASK 0x007FFF80
	+#define PBS_UNIT_SPI_MST_CONF_0_CFG_SPI_MST_BAUD_SHIFT 7
	+/*
	+ * Sets the SPI master configuration. For details see the SPI section in the
	+ * documentation.
	+ */
	+#define PBS_UNIT_SPI_MST_CONF_0_CFG_SPI_MST_RD_CMD_MASK 0x7F800000
	+#define PBS_UNIT_SPI_MST_CONF_0_CFG_SPI_MST_RD_CMD_SHIFT 23
	+
	+/** spi_mst_conf_1 register **/
	+/*
	+ * Sets the SPI master Configuration. For details see the SPI section in the
	+ * documentation.
	+ */
	+#define PBS_UNIT_SPI_MST_CONF_1_CFG_SPI_MST_WR_CMD_MASK 0x000000FF
	+#define PBS_UNIT_SPI_MST_CONF_1_CFG_SPI_MST_WR_CMD_SHIFT 0
	+/*
	+ * Sets the SPI master Configuration. For details see the SPI section in the
	+ * documentation.
	+ */
	+#define PBS_UNIT_SPI_MST_CONF_1_CFG_SPI_MST_ADDR_BYTES_NUM_MASK 0x00000700
	+#define PBS_UNIT_SPI_MST_CONF_1_CFG_SPI_MST_ADDR_BYTES_NUM_SHIFT 8
	+/*
	+ * Sets the SPI master Configuration. For details see the SPI section in the
	+ * documentation.
	+ */
	+#define PBS_UNIT_SPI_MST_CONF_1_CFG_SPI_MST_TMODE_MASK 0x00001800
	+#define PBS_UNIT_SPI_MST_CONF_1_CFG_SPI_MST_TMODE_SHIFT 11
	+/*
	+ * Sets the SPI master Configuration. For details see the SPI section in the
	+ * documentation.
	+ */
	+#define PBS_UNIT_SPI_MST_CONF_1_CFG_SPI_MST_FAST_RD (1 << 13)
	+
	+/** spi_slv_conf_0 register **/
	+/*
	+ * Sets the SPI slave configuration. For details see the SPI section in the
	+ * documentation.
	+ */
	+#define PBS_UNIT_SPI_SLV_CONF_0_CFG_SPI_SLV_BAUD_MASK 0x0000FFFF
	+#define PBS_UNIT_SPI_SLV_CONF_0_CFG_SPI_SLV_BAUD_SHIFT 0
	+/* Value. The reset value is according to bootstrap. */
	+#define PBS_UNIT_SPI_SLV_CONF_0_CFG_SPI_SLV_SCPOL (1 << 16)
	+/* Value. The reset value is according to bootstrap. */
	+#define PBS_UNIT_SPI_SLV_CONF_0_CFG_SPI_SLV_SCPH (1 << 17)
	+/*
	+ * Sets the SPI slave configuration. For details see the SPI section in the
	+ * documentation.
	+ */
	+#define PBS_UNIT_SPI_SLV_CONF_0_CFG_SPI_SLV_SER_MASK 0x03FC0000
	+#define PBS_UNIT_SPI_SLV_CONF_0_CFG_SPI_SLV_SER_SHIFT 18
	+/*
	+ * Sets the SPI slave configuration. For details see the SPI section in the
	+ * documentation.
	+ */
	+#define PBS_UNIT_SPI_SLV_CONF_0_CFG_SPI_SLV_SRL (1 << 26)
	+/*
	+ * Sets the SPI slave configuration. For details see the SPI section in the
	+ * documentation.
	+ */
	+#define PBS_UNIT_SPI_SLV_CONF_0_CFG_SPI_SLV_TMODE_MASK 0x18000000
	+#define PBS_UNIT_SPI_SLV_CONF_0_CFG_SPI_SLV_TMODE_SHIFT 27
	+
	+/** apb_mem_conf_int register **/
	+/* Value-- internal */
	+#define PBS_UNIT_APB_MEM_CONF_INT_CFG_PBS_WRR_CNT_MASK 0x00000007
	+#define PBS_UNIT_APB_MEM_CONF_INT_CFG_PBS_WRR_CNT_SHIFT 0
	+/* Value-- internal */
	+#define PBS_UNIT_APB_MEM_CONF_INT_CFG_I2C_PLD_APB_MIX_ARB (1 << 3)
	+/* Value-- internal */
	+#define PBS_UNIT_APB_MEM_CONF_INT_CFG_SPI_DBG_APB_MIX_ARB (1 << 4)
	+/* Value-- internal */
	+#define PBS_UNIT_APB_MEM_CONF_INT_CFG_SPI_MST_APB_MIX_ARB (1 << 5)
	+/* Value-- internal */
	+#define PBS_UNIT_APB_MEM_CONF_INT_CFG_I2C_PLD_CLEAR_FSM (1 << 6)
	+/* Value-- internal */
	+#define PBS_UNIT_APB_MEM_CONF_INT_CFG_SPI_DBG_CLEAR_FSM (1 << 7)
	+/* Value-- internal */
	+#define PBS_UNIT_APB_MEM_CONF_INT_CFG_SPI_MST_CLEAR_FSM (1 << 8)
	+/* Value-- internal */
	+#define PBS_UNIT_APB_MEM_CONF_INT_CFG_PBS_AXI_FSM_CLEAR (1 << 9)
	+/* Value-- internal */
	+#define PBS_UNIT_APB_MEM_CONF_INT_CFG_PBS_AXI_FIFOS_CLEAR (1 << 10)
	+/* Enables parity protection on the integrated SRAM. */
	+#define PBS_UNIT_APB_MEM_CONF_INT_CFG_BOOTROM_PARITY_EN (1 << 11)
	+/*
	+ * When set, reports a slave error whenthe slave returns an AXI slave error, for
	+ * configuration access to the internal configuration space.
	+ */
	+#define PBS_UNIT_APB_MEM_CONF_INT_CFG_RD_SLV_ERR_EN (1 << 12)
	+/*
	+ * When set, reports a decode error when timeout has occurred for configuration
	+ * access to the internal configuration space.
	+ */
	+#define PBS_UNIT_APB_MEM_CONF_INT_CFG_RD_DEC_ERR_EN (1 << 13)
	+/*
	+ * When set, reports a slave error, when the slave returns an AXI slave error,
	+ * for configuration access to the internal configuration space.
	+ */
	+#define PBS_UNIT_APB_MEM_CONF_INT_CFG_WR_SLV_ERR_EN (1 << 14)
	+/*
	+ * When set, reports a decode error when timeout has occurred for configuration
	+ * access to the internal configuration space.
	+ */
	+#define PBS_UNIT_APB_MEM_CONF_INT_CFG_WR_DEC_ERR_EN (1 << 15)
	+
	+/** sb_int_bar_low register **/
	+/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */
	+#define PBS_UNIT_SB_INT_BAR_LOW_WIN_SIZE_MASK 0x0000003F
	+#define PBS_UNIT_SB_INT_BAR_LOW_WIN_SIZE_SHIFT 0
	+/* Reserved fields */
	+#define PBS_UNIT_SB_INT_BAR_LOW_RSRVD_MASK 0x0000FFC0
	+#define PBS_UNIT_SB_INT_BAR_LOW_RSRVD_SHIFT 6
	+/* bar low address 16 MSB bits */
	+#define PBS_UNIT_SB_INT_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000
	+#define PBS_UNIT_SB_INT_BAR_LOW_ADDR_HIGH_SHIFT 16
	+
	+/** ufc_pbs_parity_err_high register **/
	+/*
	+ * Address latch in the case of a parity error in the Flash Controller internal
	+ * memories.
	+ */
	+#define PBS_UNIT_UFC_PBS_PARITY_ERR_HIGH_ADDR_MASK 0x000000FF
	+#define PBS_UNIT_UFC_PBS_PARITY_ERR_HIGH_ADDR_SHIFT 0
	+
	+/** chip_id register **/
	+/* [15:0] : Dev Rev ID */
	+#define PBS_UNIT_CHIP_ID_DEV_REV_ID_MASK 0x0000FFFF
	+#define PBS_UNIT_CHIP_ID_DEV_REV_ID_SHIFT 0
	+/* [31:16] : 0x0 - Dev ID */
	+#define PBS_UNIT_CHIP_ID_DEV_ID_MASK 0xFFFF0000
	+#define PBS_UNIT_CHIP_ID_DEV_ID_SHIFT 16
	+
	+#define PBS_UNIT_CHIP_ID_DEV_ID_ALPINE 0
	+#define PBS_UNIT_CHIP_ID_DEV_ID_PEAKROCK 1
	+#define PBS_UNIT_CHIP_ID_DEV_ID_COYOTE 2
	+
	+/** uart0_conf_status register **/
	+/*
	+ * Conf:
	+ * // [0] -- DSR_N RW bit
	+ * // [1] -- DCD_N RW bit
	+ * // [2] -- RI_N bit
	+ * // [3] -- dma_tx_ack_n
	+ * // [4] -- dma_rx_ack_n
	+ */
	+#define PBS_UNIT_UART0_CONF_STATUS_CONF_MASK 0x0000FFFF
	+#define PBS_UNIT_UART0_CONF_STATUS_CONF_SHIFT 0
	+/*
	+ * Status:
	+ * // [16] -- dtr_n RO bit
	+ * // [17] -- OUT1_N RO bit
	+ * // [18] -- OUT2_N RO bit
	+ * // [19] -- dma_tx_req_n RO bit
	+ * // [20] -- dma_tx_single_n RO bit
	+ * // [21] -- dma_rx_req_n RO bit
	+ * // [22] -- dma_rx_single_n RO bit
	+ * // [23] -- uart_lp_req_pclk RO bit
	+ * // [24] -- baudout_n RO bit
	+ */
	+#define PBS_UNIT_UART0_CONF_STATUS_STATUS_MASK 0xFFFF0000
	+#define PBS_UNIT_UART0_CONF_STATUS_STATUS_SHIFT 16
	+
	+/** uart1_conf_status register **/
	+/*
	+ * Conf: // [0] -- DSR_N RW bit // [1] -- DCD_N RW bit // [2] -- RI_N bit // [3]
	+ * -- dma_tx_ack_n // [4] - dma_rx_ack_n
	+ */
	+#define PBS_UNIT_UART1_CONF_STATUS_CONF_MASK 0x0000FFFF
	+#define PBS_UNIT_UART1_CONF_STATUS_CONF_SHIFT 0
	+/*
	+ * Status: // [16] -- dtr_n RO bit // [17] -- OUT1_N RO bit // [18] -- OUT2_N RO
	+ * bit // [19] -- dma_tx_req_n RO bit // [20] -- dma_tx_single_n RO bit // [21]
	+ * -- dma_rx_req_n RO bit // [22] -- dma_rx_single_n RO bit // [23] --
	+ * uart_lp_req_pclk RO bit // [24] -- baudout_n RO bit
	+ */
	+#define PBS_UNIT_UART1_CONF_STATUS_STATUS_MASK 0xFFFF0000
	+#define PBS_UNIT_UART1_CONF_STATUS_STATUS_SHIFT 16
	+
	+/** uart2_conf_status register **/
	+/*
	+ * Conf: // [0] -- DSR_N RW bit // [1] -- DCD_N RW bit // [2] -- RI_N bit // [3]
	+ * -- dma_tx_ack_n // [4] - dma_rx_ack_n
	+ */
	+#define PBS_UNIT_UART2_CONF_STATUS_CONF_MASK 0x0000FFFF
	+#define PBS_UNIT_UART2_CONF_STATUS_CONF_SHIFT 0
	+/*
	+ * Status: // [16] -- dtr_n RO bit // [17] -- OUT1_N RO bit // [18] -- OUT2_N RO
	+ * bit // [19] -- dma_tx_req_n RO bit // [20] -- dma_tx_single_n RO bit // [21]
	+ * -- dma_rx_req_n RO bit // [22] -- dma_rx_single_n RO bit // [23] --
	+ * uart_lp_req_pclk RO bit // [24] -- baudout_n RO bit
	+ */
	+#define PBS_UNIT_UART2_CONF_STATUS_STATUS_MASK 0xFFFF0000
	+#define PBS_UNIT_UART2_CONF_STATUS_STATUS_SHIFT 16
	+
	+/** uart3_conf_status register **/
	+/*
	+ * Conf: // [0] -- DSR_N RW bit // [1] -- DCD_N RW bit // [2] -- RI_N bit // [3]
	+ * -- dma_tx_ack_n // [4] - dma_rx_ack_n
	+ */
	+#define PBS_UNIT_UART3_CONF_STATUS_CONF_MASK 0x0000FFFF
	+#define PBS_UNIT_UART3_CONF_STATUS_CONF_SHIFT 0
	+/*
	+ * Status: // [16] -- dtr_n RO bit // [17] -- OUT1_N RO bit // [18] -- OUT2_N RO
	+ * bit // [19] -- dma_tx_req_n RO bit // [20] -- dma_tx_single_n RO bit // [21]
	+ * -- dma_rx_req_n RO bit // [22] -- dma_rx_single_n RO bit // [23] --
	+ * uart_lp_req_pclk RO bit // [24] -- baudout_n RO bit
	+ */
	+#define PBS_UNIT_UART3_CONF_STATUS_STATUS_MASK 0xFFFF0000
	+#define PBS_UNIT_UART3_CONF_STATUS_STATUS_SHIFT 16
	+
	+/** gpio0_conf_status register **/
	+/*
	+ * Cntl:
	+ * // [7:0] nGPAFEN; // from regfile
	+ * // [15:8] GPAFOUT; // from regfile
	+ */
	+#define PBS_UNIT_GPIO0_CONF_STATUS_CONF_MASK 0x0000FFFF
	+#define PBS_UNIT_GPIO0_CONF_STATUS_CONF_SHIFT 0
	+/*
	+ * Status:
	+ * // [24:16] GPAFIN; // to regfile
	+ */
	+#define PBS_UNIT_GPIO0_CONF_STATUS_STATUS_MASK 0xFFFF0000
	+#define PBS_UNIT_GPIO0_CONF_STATUS_STATUS_SHIFT 16
	+
	+/** gpio1_conf_status register **/
	+/*
	+ * Cntl:
	+ * // [7:0] nGPAFEN; // from regfile
	+ * // [15:8] GPAFOUT; // from regfile
	+ */
	+#define PBS_UNIT_GPIO1_CONF_STATUS_CONF_MASK 0x0000FFFF
	+#define PBS_UNIT_GPIO1_CONF_STATUS_CONF_SHIFT 0
	+/*
	+ * Status:
	+ * // [24:16] GPAFIN; // to regfile
	+ */
	+#define PBS_UNIT_GPIO1_CONF_STATUS_STATUS_MASK 0xFFFF0000
	+#define PBS_UNIT_GPIO1_CONF_STATUS_STATUS_SHIFT 16
	+
	+/** gpio2_conf_status register **/
	+/*
	+ * Cntl:
	+ * // [7:0] nGPAFEN; // from regfile
	+ * // [15:8] GPAFOUT; // from regfile
	+ */
	+#define PBS_UNIT_GPIO2_CONF_STATUS_CONF_MASK 0x0000FFFF
	+#define PBS_UNIT_GPIO2_CONF_STATUS_CONF_SHIFT 0
	+/*
	+ * Status:
	+ * // [24:16] GPAFIN; // to regfile
	+ */
	+#define PBS_UNIT_GPIO2_CONF_STATUS_STATUS_MASK 0xFFFF0000
	+#define PBS_UNIT_GPIO2_CONF_STATUS_STATUS_SHIFT 16
	+
	+/** gpio3_conf_status register **/
	+/*
	+ * Cntl:
	+ * // [7:0] nGPAFEN; // from regfile
	+ * // [15:8] GPAFOUT; // from regfile
	+ */
	+#define PBS_UNIT_GPIO3_CONF_STATUS_CONF_MASK 0x0000FFFF
	+#define PBS_UNIT_GPIO3_CONF_STATUS_CONF_SHIFT 0
	+/*
	+ * Status:
	+ * // [24:16] GPAFIN; // to regfile
	+ */
	+#define PBS_UNIT_GPIO3_CONF_STATUS_STATUS_MASK 0xFFFF0000
	+#define PBS_UNIT_GPIO3_CONF_STATUS_STATUS_SHIFT 16
	+
	+/** gpio4_conf_status register **/
	+/*
	+ * Cntl:
	+ * // [7:0] nGPAFEN; // from regfile
	+ * // [15:8] GPAFOUT; // from regfile
	+ */
	+#define PBS_UNIT_GPIO4_CONF_STATUS_CONF_MASK 0x0000FFFF
	+#define PBS_UNIT_GPIO4_CONF_STATUS_CONF_SHIFT 0
	+/*
	+ * Status:
	+ * // [24:16] GPAFIN; // to regfile
	+ */
	+#define PBS_UNIT_GPIO4_CONF_STATUS_STATUS_MASK 0xFFFF0000
	+#define PBS_UNIT_GPIO4_CONF_STATUS_STATUS_SHIFT 16
	+
	+/** i2c_gen_conf_status register **/
	+/*
	+ * cntl
	+ * // [0] -- dma_tx_ack
	+ * // [1] -- dma_rx_ack
	+ */
	+#define PBS_UNIT_I2C_GEN_CONF_STATUS_CONF_MASK 0x0000FFFF
	+#define PBS_UNIT_I2C_GEN_CONF_STATUS_CONF_SHIFT 0
	+/*
	+ * Status
	+ *
	+ * // [16] -- dma_tx_req RO bit
	+ * // [17] -- dma_tx_single RO bit
	+ * // [18] -- dma_rx_req RO bit
	+ * // [19] -- dma_rx_single RO bit
	+ */
	+#define PBS_UNIT_I2C_GEN_CONF_STATUS_STATUS_MASK 0xFFFF0000
	+#define PBS_UNIT_I2C_GEN_CONF_STATUS_STATUS_SHIFT 16
	+
	+/** watch_dog_reset_out register **/
	+/*
	+ * [0] If set to 1'b1, WD0 cannot generate reset_out_n
	+ * [1] If set to 1'b1, WD1 cannot generate reset_out_n
	+ * [2] If set to 1'b1, WD2 cannot generate reset_out_n
	+ * [3] If set to 1'b1, WD3 cannot generate reset_out_n
	+ * [4] If set to 1'b1, WD4 cannot generate reset_out_n
	+ * [5] If set to 1'b1, WD5 cannot generate reset_out_n
	+ * [6] If set to 1'b1, WD6 cannot generate reset_out_n
	+ * [7] If set to 1'b1, WD7 cannot generate reset_out_n
	+ */
	+#define PBS_UNIT_WATCH_DOG_RESET_OUT_DISABLE_MASK 0x000000FF
	+#define PBS_UNIT_WATCH_DOG_RESET_OUT_DISABLE_SHIFT 0
	+
	+/** otp_cntl register **/
	+/* from reg file Config To bypass the copy from OTPW to OTPR */
	+#define PBS_UNIT_OTP_CNTL_IGNORE_OTPW (1 << 0)
	+/* Not in use.Comes from bond. */
	+#define PBS_UNIT_OTP_CNTL_IGNORE_PRELOAD (1 << 1)
	+/* Margin read from the fuse box */
	+#define PBS_UNIT_OTP_CNTL_OTPW_MARGIN_READ (1 << 2)
	+/* Indicates when OTPis busy. */
	+#define PBS_UNIT_OTP_CNTL_OTP_BUSY (1 << 3)
	+
	+/** otp_cfg_0 register **/
	+/* Cfg to OTP cntl. */
	+#define PBS_UNIT_OTP_CFG_0_CFG_OTPW_PWRDN_CNT_MASK 0x0000FFFF
	+#define PBS_UNIT_OTP_CFG_0_CFG_OTPW_PWRDN_CNT_SHIFT 0
	+/* Cfg to OTP cntl. */
	+#define PBS_UNIT_OTP_CFG_0_CFG_OTPW_READ_CNT_MASK 0xFFFF0000
	+#define PBS_UNIT_OTP_CFG_0_CFG_OTPW_READ_CNT_SHIFT 16
	+
	+/** otp_cfg_1 register **/
	+/* Cfg to OTP cntl. */
	+#define PBS_UNIT_OTP_CFG_1_CFG_OTPW_PGM_CNT_MASK 0x0000FFFF
	+#define PBS_UNIT_OTP_CFG_1_CFG_OTPW_PGM_CNT_SHIFT 0
	+/* Cfg to OTP cntl. */
	+#define PBS_UNIT_OTP_CFG_1_CFG_OTPW_PREP_CNT_MASK 0xFFFF0000
	+#define PBS_UNIT_OTP_CFG_1_CFG_OTPW_PREP_CNT_SHIFT 16
	+
	+/** otp_cfg_3 register **/
	+/* Cfg to OTP cntl. */
	+#define PBS_UNIT_OTP_CFG_3_CFG_OTPW_PS18_CNT_MASK 0x0000FFFF
	+#define PBS_UNIT_OTP_CFG_3_CFG_OTPW_PS18_CNT_SHIFT 0
	+/* Cfg to OTP cntl. */
	+#define PBS_UNIT_OTP_CFG_3_CFG_OTPW_PWRUP_CNT_MASK 0xFFFF0000
	+#define PBS_UNIT_OTP_CFG_3_CFG_OTPW_PWRUP_CNT_SHIFT 16
	+
	+/** nb_nic_regs_bar_low register **/
	+/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */
	+#define PBS_UNIT_NB_NIC_REGS_BAR_LOW_WIN_SIZE_MASK 0x0000003F
	+#define PBS_UNIT_NB_NIC_REGS_BAR_LOW_WIN_SIZE_SHIFT 0
	+/* Reserved fields */
	+#define PBS_UNIT_NB_NIC_REGS_BAR_LOW_RSRVD_MASK 0x0000FFC0
	+#define PBS_UNIT_NB_NIC_REGS_BAR_LOW_RSRVD_SHIFT 6
	+/* bar low address 16 MSB bits */
	+#define PBS_UNIT_NB_NIC_REGS_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000
	+#define PBS_UNIT_NB_NIC_REGS_BAR_LOW_ADDR_HIGH_SHIFT 16
	+
	+/** sb_nic_regs_bar_low register **/
	+/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */
	+#define PBS_UNIT_SB_NIC_REGS_BAR_LOW_WIN_SIZE_MASK 0x0000003F
	+#define PBS_UNIT_SB_NIC_REGS_BAR_LOW_WIN_SIZE_SHIFT 0
	+/* Reserved fields */
	+#define PBS_UNIT_SB_NIC_REGS_BAR_LOW_RSRVD_MASK 0x0000FFC0
	+#define PBS_UNIT_SB_NIC_REGS_BAR_LOW_RSRVD_SHIFT 6
	+/* bar low address 16 MSB bits */
	+#define PBS_UNIT_SB_NIC_REGS_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000
	+#define PBS_UNIT_SB_NIC_REGS_BAR_LOW_ADDR_HIGH_SHIFT 16
	+
	+/** serdes_mux_multi_0 register **/
	+/* SerDes one hot mux control. For details see datasheet. */
	+#define PBS_UNIT_SERDES_MUX_MULTI_0_SELECT_OH_SERDES_8_MASK 0x00000007
	+#define PBS_UNIT_SERDES_MUX_MULTI_0_SELECT_OH_SERDES_8_SHIFT 0
	+/* Reserved */
	+#define PBS_UNIT_SERDES_MUX_MULTI_0_RSRVD_3 (1 << 3)
	+/* SerDes one hot mux control. For details see datasheet. */
	+#define PBS_UNIT_SERDES_MUX_MULTI_0_SELECT_OH_SERDES_9_MASK 0x00000070
	+#define PBS_UNIT_SERDES_MUX_MULTI_0_SELECT_OH_SERDES_9_SHIFT 4
	+/* Reserved */
	+#define PBS_UNIT_SERDES_MUX_MULTI_0_RSRVD_7 (1 << 7)
	+/* SerDes one hot mux control. For details see datasheet. */
	+#define PBS_UNIT_SERDES_MUX_MULTI_0_SELECT_OH_SERDES_10_MASK 0x00000700
	+#define PBS_UNIT_SERDES_MUX_MULTI_0_SELECT_OH_SERDES_10_SHIFT 8
	+/* Reserved */
	+#define PBS_UNIT_SERDES_MUX_MULTI_0_RSRVD_11 (1 << 11)
	+/* SerDes one hot mux control. For details see datasheet. */
	+#define PBS_UNIT_SERDES_MUX_MULTI_0_SELECT_OH_SERDES_11_MASK 0x00007000
	+#define PBS_UNIT_SERDES_MUX_MULTI_0_SELECT_OH_SERDES_11_SHIFT 12
	+/* Reserved */
	+#define PBS_UNIT_SERDES_MUX_MULTI_0_RSRVD_15 (1 << 15)
	+/* SerDes one hot mux control. For details see datasheet. */
	+#define PBS_UNIT_SERDES_MUX_MULTI_0_SELECT_OH_SERDES_12_MASK 0x00030000
	+#define PBS_UNIT_SERDES_MUX_MULTI_0_SELECT_OH_SERDES_12_SHIFT 16
	+/* SerDes one hot mux control. For details see datasheet. */
	+#define PBS_UNIT_SERDES_MUX_MULTI_0_SELECT_OH_SERDES_13_MASK 0x000C0000
	+#define PBS_UNIT_SERDES_MUX_MULTI_0_SELECT_OH_SERDES_13_SHIFT 18
	+/* SerDes one hot mux control. For details see datasheet. */
	+#define PBS_UNIT_SERDES_MUX_MULTI_0_SELECT_OH_SERDES_14_MASK 0x00300000
	+#define PBS_UNIT_SERDES_MUX_MULTI_0_SELECT_OH_SERDES_14_SHIFT 20
	+/* SerDes one hot mux control. For details see datasheet. */
	+#define PBS_UNIT_SERDES_MUX_MULTI_0_SELECT_OH_SERDES_15_MASK 0x00C00000
	+#define PBS_UNIT_SERDES_MUX_MULTI_0_SELECT_OH_SERDES_15_SHIFT 22
	+/* Reserved */
	+#define PBS_UNIT_SERDES_MUX_MULTI_0_RSRVD_MASK 0xFF000000
	+#define PBS_UNIT_SERDES_MUX_MULTI_0_RSRVD_SHIFT 24
	+
	+/*
	+ * 2'b01 - select sata_b[0]
	+ * 2'b10 - select eth_a[0]
	+ */
	+#define PBS_UNIT_SERDES_MUX_MULTI_0_PKR_SELECT_OH_SERDES_8_MASK 0x00000003
	+#define PBS_UNIT_SERDES_MUX_MULTI_0_PKR_SELECT_OH_SERDES_8_SHIFT 0
	+/*
	+ * 3'b001 - select sata_b[1]
	+ * 3'b010 - select eth_b[0]
	+ * 3'b100 - select eth_a[1]
	+ */
	+#define PBS_UNIT_SERDES_MUX_MULTI_0_PKR_SELECT_OH_SERDES_9_MASK 0x00000070
	+#define PBS_UNIT_SERDES_MUX_MULTI_0_PKR_SELECT_OH_SERDES_9_SHIFT 4
	+/*
	+ * 3'b001 - select sata_b[2]
	+ * 3'b010 - select eth_c[0]
	+ * 3'b100 - select eth_a[2]
	+ */
	+#define PBS_UNIT_SERDES_MUX_MULTI_0_PKR_SELECT_OH_SERDES_10_MASK 0x00000700
	+#define PBS_UNIT_SERDES_MUX_MULTI_0_PKR_SELECT_OH_SERDES_10_SHIFT 8
	+/*
	+ * 3'b001 - select sata_b[3]
	+ * 3'b010 - select eth_d[0]
	+ * 3'b100 - select eth_a[3]
	+ */
	+#define PBS_UNIT_SERDES_MUX_MULTI_0_PKR_SELECT_OH_SERDES_11_MASK 0x00007000
	+#define PBS_UNIT_SERDES_MUX_MULTI_0_PKR_SELECT_OH_SERDES_11_SHIFT 12
	+/*
	+ * 2'b01 - select eth_a[0]
	+ * 2'b10 - select sata_a[0]
	+ */
	+#define PBS_UNIT_SERDES_MUX_MULTI_0_PKR_SELECT_OH_SERDES_12_MASK 0x00030000
	+#define PBS_UNIT_SERDES_MUX_MULTI_0_PKR_SELECT_OH_SERDES_12_SHIFT 16
	+/*
	+ * 3'b001 - select eth_b[0]
	+ * 3'b010 - select eth_c[1]
	+ * 3'b100 - select sata_a[1]
	+ */
	+#define PBS_UNIT_SERDES_MUX_MULTI_0_PKR_SELECT_OH_SERDES_13_MASK 0x00700000
	+#define PBS_UNIT_SERDES_MUX_MULTI_0_PKR_SELECT_OH_SERDES_13_SHIFT 20
	+/*
	+ * 3'b001 - select eth_a[0]
	+ * 3'b010 - select eth_c[2]
	+ * 3'b100 - select sata_a[2]
	+ */
	+#define PBS_UNIT_SERDES_MUX_MULTI_0_PKR_SELECT_OH_SERDES_14_MASK 0x07000000
	+#define PBS_UNIT_SERDES_MUX_MULTI_0_PKR_SELECT_OH_SERDES_14_SHIFT 24
	+/*
	+ * 3'b001 - select eth_d[0]
	+ * 3'b010 - select eth_c[3]
	+ * 3'b100 - select sata_a[3]
	+ */
	+#define PBS_UNIT_SERDES_MUX_MULTI_0_PKR_SELECT_OH_SERDES_15_MASK 0x70000000
	+#define PBS_UNIT_SERDES_MUX_MULTI_0_PKR_SELECT_OH_SERDES_15_SHIFT 28
	+
	+/** serdes_mux_multi_1 register **/
	+/* SerDes one hot mux control. For details see datasheet. */
	+#define PBS_UNIT_SERDES_MUX_MULTI_1_SELECT_OH_ETH_A_0_MASK 0x00000003
	+#define PBS_UNIT_SERDES_MUX_MULTI_1_SELECT_OH_ETH_A_0_SHIFT 0
	+/* Reserved */
	+#define PBS_UNIT_SERDES_MUX_MULTI_1_RSRVD_3_2_MASK 0x0000000C
	+#define PBS_UNIT_SERDES_MUX_MULTI_1_RSRVD_3_2_SHIFT 2
	+/* SerDes one hot mux control. For details see datasheet. */
	+#define PBS_UNIT_SERDES_MUX_MULTI_1_SELECT_OH_ETH_B_0_MASK 0x00000070
	+#define PBS_UNIT_SERDES_MUX_MULTI_1_SELECT_OH_ETH_B_0_SHIFT 4
	+/* Reserved */
	+#define PBS_UNIT_SERDES_MUX_MULTI_1_RSRVD_7 (1 << 7)
	+/* SerDes one hot mux control. For details see datasheet. */
	+#define PBS_UNIT_SERDES_MUX_MULTI_1_SELECT_OH_ETH_C_0_MASK 0x00000300
	+#define PBS_UNIT_SERDES_MUX_MULTI_1_SELECT_OH_ETH_C_0_SHIFT 8
	+/* Reserved */
	+#define PBS_UNIT_SERDES_MUX_MULTI_1_RSRVD_11_10_MASK 0x00000C00
	+#define PBS_UNIT_SERDES_MUX_MULTI_1_RSRVD_11_10_SHIFT 10
	+/* SerDes one hot mux control. For details see datasheet. */
	+#define PBS_UNIT_SERDES_MUX_MULTI_1_SELECT_OH_ETH_D_0_MASK 0x00007000
	+#define PBS_UNIT_SERDES_MUX_MULTI_1_SELECT_OH_ETH_D_0_SHIFT 12
	+/* Reserved */
	+#define PBS_UNIT_SERDES_MUX_MULTI_1_RSRVD_MASK 0xFFFF8000
	+#define PBS_UNIT_SERDES_MUX_MULTI_1_RSRVD_SHIFT 15
	+
	+/** pbs_ulpi_mux_conf register **/
	+/*
	+ * Value 0 - Select dedicated pins for the USB-1 inputs.
	+ * Value 1 - Select PBS mux pins for the USB-1 inputs.
	+ * [0] ULPI_B_CLK
	+ * [1] ULPI_B_DIR
	+ * [2] ULPI_B_NXT
	+ * [10:3] ULPI_B_DATA[7:0]
	+ */
	+#define PBS_UNIT_PBS_ULPI_MUX_CONF_SEL_UPLI_IN_PBSMUX_MASK 0x000007FF
	+#define PBS_UNIT_PBS_ULPI_MUX_CONF_SEL_UPLI_IN_PBSMUX_SHIFT 0
	+/*
	+ * [3] - Force to zero
	+ * [2] == 1 - Force register selection
	+ * [1 : 0] -Binary selection of the input in bypass mode
	+ */
	+#define PBS_UNIT_PBS_ULPI_MUX_CONF_REG_MDIO_BYPASS_SEL_MASK 0x0000F000
	+#define PBS_UNIT_PBS_ULPI_MUX_CONF_REG_MDIO_BYPASS_SEL_SHIFT 12
	+/*
	+ * [0] Sets the clk_ulpi OE for USB0, 1'b0 set to input, 1'b1 set to output.
	+ * [1] Sets the clk_ulpi OE for USB01, 1'b0 set to input, 1'b1 set to output.
	+ */
	+#define PBS_UNIT_PBS_ULPI_MUX_CONF_RSRVD_MASK 0xFFFF0000
	+#define PBS_UNIT_PBS_ULPI_MUX_CONF_RSRVD_SHIFT 16
	+
	+/** wr_once_dbg_dis_ovrd_reg register **/
	+/* This register can be written only once. Use in the secure boot process. */
	+#define PBS_UNIT_WR_ONCE_DBG_DIS_OVRD_REG_WR_ONCE_DBG_DIS_OVRD (1 << 0)
	+
	+#define PBS_UNIT_WR_ONCE_DBG_DIS_OVRD_REG_RSRVD_MASK 0xFFFFFFFE
	+#define PBS_UNIT_WR_ONCE_DBG_DIS_OVRD_REG_RSRVD_SHIFT 1
	+
	+/** gpio5_conf_status register **/
	+/*
	+ * Cntl: // [7:0] nGPAFEN; // from regfile // [15:8] GPAFOUT; // from regfile
	+ */
	+#define PBS_UNIT_GPIO5_CONF_STATUS_CONF_MASK 0x0000FFFF
	+#define PBS_UNIT_GPIO5_CONF_STATUS_CONF_SHIFT 0
	+/* Status: // [24:16] GPAFIN; // to regfile */
	+#define PBS_UNIT_GPIO5_CONF_STATUS_STATUS_MASK 0xFFFF0000
	+#define PBS_UNIT_GPIO5_CONF_STATUS_STATUS_SHIFT 16
	+
	+/** pcie_mem3_bar_low register **/
	+/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */
	+#define PBS_UNIT_PCIE_MEM3_BAR_LOW_WIN_SIZE_MASK 0x0000003F
	+#define PBS_UNIT_PCIE_MEM3_BAR_LOW_WIN_SIZE_SHIFT 0
	+/* Reserved fields */
	+#define PBS_UNIT_PCIE_MEM3_BAR_LOW_RSRVD_MASK 0x0000FFC0
	+#define PBS_UNIT_PCIE_MEM3_BAR_LOW_RSRVD_SHIFT 6
	+/* Reserved */
	+#define PBS_UNIT_PCIE_MEM3_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000
	+#define PBS_UNIT_PCIE_MEM3_BAR_LOW_ADDR_HIGH_SHIFT 16
	+
	+/** pcie_mem4_bar_low register **/
	+/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */
	+#define PBS_UNIT_PCIE_MEM4_BAR_LOW_WIN_SIZE_MASK 0x0000003F
	+#define PBS_UNIT_PCIE_MEM4_BAR_LOW_WIN_SIZE_SHIFT 0
	+/* Reserved fields */
	+#define PBS_UNIT_PCIE_MEM4_BAR_LOW_RSRVD_MASK 0x0000FFC0
	+#define PBS_UNIT_PCIE_MEM4_BAR_LOW_RSRVD_SHIFT 6
	+/* Reserved */
	+#define PBS_UNIT_PCIE_MEM4_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000
	+#define PBS_UNIT_PCIE_MEM4_BAR_LOW_ADDR_HIGH_SHIFT 16
	+
	+/** pcie_mem5_bar_low register **/
	+/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */
	+#define PBS_UNIT_PCIE_MEM5_BAR_LOW_WIN_SIZE_MASK 0x0000003F
	+#define PBS_UNIT_PCIE_MEM5_BAR_LOW_WIN_SIZE_SHIFT 0
	+/* Reserved fields */
	+#define PBS_UNIT_PCIE_MEM5_BAR_LOW_RSRVD_MASK 0x0000FFC0
	+#define PBS_UNIT_PCIE_MEM5_BAR_LOW_RSRVD_SHIFT 6
	+/* Reserved */
	+#define PBS_UNIT_PCIE_MEM5_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000
	+#define PBS_UNIT_PCIE_MEM5_BAR_LOW_ADDR_HIGH_SHIFT 16
	+
	+/** pcie_ext_ecam3_bar_low register **/
	+/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */
	+#define PBS_UNIT_PCIE_EXT_ECAM3_BAR_LOW_WIN_SIZE_MASK 0x0000003F
	+#define PBS_UNIT_PCIE_EXT_ECAM3_BAR_LOW_WIN_SIZE_SHIFT 0
	+/* Reserved fields */
	+#define PBS_UNIT_PCIE_EXT_ECAM3_BAR_LOW_RSRVD_MASK 0x0000FFC0
	+#define PBS_UNIT_PCIE_EXT_ECAM3_BAR_LOW_RSRVD_SHIFT 6
	+/* Reserved */
	+#define PBS_UNIT_PCIE_EXT_ECAM3_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000
	+#define PBS_UNIT_PCIE_EXT_ECAM3_BAR_LOW_ADDR_HIGH_SHIFT 16
	+
	+/** pcie_ext_ecam4_bar_low register **/
	+/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */
	+#define PBS_UNIT_PCIE_EXT_ECAM4_BAR_LOW_WIN_SIZE_MASK 0x0000003F
	+#define PBS_UNIT_PCIE_EXT_ECAM4_BAR_LOW_WIN_SIZE_SHIFT 0
	+/* Reserved fields */
	+#define PBS_UNIT_PCIE_EXT_ECAM4_BAR_LOW_RSRVD_MASK 0x0000FFC0
	+#define PBS_UNIT_PCIE_EXT_ECAM4_BAR_LOW_RSRVD_SHIFT 6
	+/* Reserved */
	+#define PBS_UNIT_PCIE_EXT_ECAM4_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000
	+#define PBS_UNIT_PCIE_EXT_ECAM4_BAR_LOW_ADDR_HIGH_SHIFT 16
	+
	+/** pcie_ext_ecam5_bar_low register **/
	+/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */
	+#define PBS_UNIT_PCIE_EXT_ECAM5_BAR_LOW_WIN_SIZE_MASK 0x0000003F
	+#define PBS_UNIT_PCIE_EXT_ECAM5_BAR_LOW_WIN_SIZE_SHIFT 0
	+/* Reserved fields */
	+#define PBS_UNIT_PCIE_EXT_ECAM5_BAR_LOW_RSRVD_MASK 0x0000FFC0
	+#define PBS_UNIT_PCIE_EXT_ECAM5_BAR_LOW_RSRVD_SHIFT 6
	+/* Reserved */
	+#define PBS_UNIT_PCIE_EXT_ECAM5_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000
	+#define PBS_UNIT_PCIE_EXT_ECAM5_BAR_LOW_ADDR_HIGH_SHIFT 16
	+
	+/** low_latency_sram_bar_low register **/
	+/* Window size = 2 ^ (15 + win_size). Zero value: disable the window. */
	+#define PBS_UNIT_LOW_LATENCY_SRAM_BAR_LOW_WIN_SIZE_MASK 0x0000003F
	+#define PBS_UNIT_LOW_LATENCY_SRAM_BAR_LOW_WIN_SIZE_SHIFT 0
	+/* Reserved fields */
	+#define PBS_UNIT_LOW_LATENCY_SRAM_BAR_LOW_RSRVD_MASK 0x0000FFC0
	+#define PBS_UNIT_LOW_LATENCY_SRAM_BAR_LOW_RSRVD_SHIFT 6
	+/* Reserved */
	+#define PBS_UNIT_LOW_LATENCY_SRAM_BAR_LOW_ADDR_HIGH_MASK 0xFFFF0000
	+#define PBS_UNIT_LOW_LATENCY_SRAM_BAR_LOW_ADDR_HIGH_SHIFT 16
	+
	+/** pbs_sb2nb_cfg_dram_remap register **/
	+#define PBS_UNIT_SB2NB_REMAP_BASE_ADDR_SHIFT 5
	+#define PBS_UNIT_SB2NB_REMAP_BASE_ADDR_MASK 0x0000FFE0
	+#define PBS_UNIT_SB2NB_REMAP_TRANSL_BASE_ADDR_SHIFT 21
	+#define PBS_UNIT_SB2NB_REMAP_TRANSL_BASE_ADDR_MASK 0xFFE00000
	+
	+/* For remapping are used bits [39 - 29] of DRAM 40bit Physical address */
	+#define PBS_UNIT_DRAM_SRC_REMAP_BASE_ADDR_SHIFT 29
	+#define PBS_UNIT_DRAM_DST_REMAP_BASE_ADDR_SHIFT 29
	+#define PBS_UNIT_DRAM_REMAP_BASE_ADDR_MASK 0xFFE0000000UL
	+
	+
	+/** serdes_mux_eth register **/
	+/*
	+ * 2'b01 - eth_a[0] from serdes_8
	+ * 2'b10 - eth_a[0] from serdes_14
	+ */
	+#define PBS_UNIT_SERDES_MUX_ETH_PKR_SELECT_OH_ETH_A_0_MASK 0x00000003
	+#define PBS_UNIT_SERDES_MUX_ETH_PKR_SELECT_OH_ETH_A_0_SHIFT 0
	+/*
	+ * 2'b01 - eth_b[0] from serdes_9
	+ * 2'b10 - eth_b[0] from serdes_13
	+ */
	+#define PBS_UNIT_SERDES_MUX_ETH_PKR_SELECT_OH_ETH_B_0_MASK 0x00000030
	+#define PBS_UNIT_SERDES_MUX_ETH_PKR_SELECT_OH_ETH_B_0_SHIFT 4
	+/*
	+ * 2'b01 - eth_c[0] from serdes_10
	+ * 2'b10 - eth_c[0] from serdes_12
	+ */
	+#define PBS_UNIT_SERDES_MUX_ETH_PKR_SELECT_OH_ETH_C_0_MASK 0x00000300
	+#define PBS_UNIT_SERDES_MUX_ETH_PKR_SELECT_OH_ETH_C_0_SHIFT 8
	+/*
	+ * 2'b01 - eth_d[0] from serdes_11
	+ * 2'b10 - eth_d[0] from serdes_15
	+ */
	+#define PBS_UNIT_SERDES_MUX_ETH_PKR_SELECT_OH_ETH_D_0_MASK 0x00003000
	+#define PBS_UNIT_SERDES_MUX_ETH_PKR_SELECT_OH_ETH_D_0_SHIFT 12
	+/* which lane's is master clk */
	+#define PBS_UNIT_SERDES_MUX_ETH_PKR_SELECT_OH_ETH_A_ICK_MASTER_MASK 0x00030000
	+#define PBS_UNIT_SERDES_MUX_ETH_PKR_SELECT_OH_ETH_A_ICK_MASTER_SHIFT 16
	+/* which lane's is master clk */
	+#define PBS_UNIT_SERDES_MUX_ETH_PKR_SELECT_OH_ETH_C_ICK_MASTER_MASK 0x00300000
	+#define PBS_UNIT_SERDES_MUX_ETH_PKR_SELECT_OH_ETH_C_ICK_MASTER_SHIFT 20
	+/* enable xlaui on eth a */
	+#define PBS_UNIT_SERDES_MUX_ETH_PKR_SELECT_OH_ETH_A_XLAUI_ENABLE (1 << 24)
	+/* enable xlaui on eth c */
	+#define PBS_UNIT_SERDES_MUX_ETH_PKR_SELECT_OH_ETH_C_XLAUI_ENABLE (1 << 28)
	+
	+/** serdes_mux_pcie register **/
	+/*
	+ * 2'b01 - select pcie_b[0] from serdes 2
	+ * 2'b10 - select pcie_b[0] from serdes 4
	+ */
	+#define PBS_UNIT_SERDES_MUX_PCIE_PKR_SELECT_OH_PCIE_B_0_MASK 0x00000003
	+#define PBS_UNIT_SERDES_MUX_PCIE_PKR_SELECT_OH_PCIE_B_0_SHIFT 0
	+/*
	+ * 2'b01 - select pcie_b[1] from serdes 3
	+ * 2'b10 - select pcie_b[1] from serdes 5
	+ */
	+#define PBS_UNIT_SERDES_MUX_PCIE_PKR_SELECT_OH_PCIE_B_1_MASK 0x00000030
	+#define PBS_UNIT_SERDES_MUX_PCIE_PKR_SELECT_OH_PCIE_B_1_SHIFT 4
	+/*
	+ * 2'b01 - select pcie_d[0] from serdes 10
	+ * 2'b10 - select pcie_d[0] from serdes 12
	+ */
	+#define PBS_UNIT_SERDES_MUX_PCIE_PKR_SELECT_OH_PCIE_D_0_MASK 0x00000300
	+#define PBS_UNIT_SERDES_MUX_PCIE_PKR_SELECT_OH_PCIE_D_0_SHIFT 8
	+/*
	+ * 2'b01 - select pcie_d[1] from serdes 11
	+ * 2'b10 - select pcie_d[1] from serdes 13
	+ */
	+#define PBS_UNIT_SERDES_MUX_PCIE_PKR_SELECT_OH_PCIE_D_1_MASK 0x00003000
	+#define PBS_UNIT_SERDES_MUX_PCIE_PKR_SELECT_OH_PCIE_D_1_SHIFT 12
	+
	+/** serdes_mux_sata register **/
	+/*
	+ * 2'b01 - select sata_a from serdes group 1
	+ * 2'b10 - select sata_a from serdes group 3
	+ */
	+#define PBS_UNIT_SERDES_MUX_SATA_SELECT_OH_SATA_A_MASK 0x00000003
	+#define PBS_UNIT_SERDES_MUX_SATA_SELECT_OH_SATA_A_SHIFT 0
	+/* Reserved */
	+#define PBS_UNIT_SERDES_MUX_SATA_RESERVED_3_2_MASK 0x0000000C
	+#define PBS_UNIT_SERDES_MUX_SATA_RESERVED_3_2_SHIFT 2
	+/* Reserved */
	+#define PBS_UNIT_SERDES_MUX_SATA_RESERVED_MASK 0xFFFFFFF0
	+#define PBS_UNIT_SERDES_MUX_SATA_RESERVED_SHIFT 4
	+
	+/** bar1_orig register **/
	+/*
	+ * Window size = 2 ^ (11 + win_size).
	+ * Zero value: disable the window.
	+ */
	+#define PBS_LOW_LATENCY_SRAM_REMAP_BAR1_ORIG_WIN_SIZE_MASK 0x00000007
	+#define PBS_LOW_LATENCY_SRAM_REMAP_BAR1_ORIG_WIN_SIZE_SHIFT 0
	+/* Reserved fields */
	+#define PBS_LOW_LATENCY_SRAM_REMAP_BAR1_ORIG_RSRVD_MASK 0x00000FF8
	+#define PBS_LOW_LATENCY_SRAM_REMAP_BAR1_ORIG_RSRVD_SHIFT 3
	+/*
	+ * offset within the SRAM, in resolution of 4KB.
	+ * Only offsets which are inside the boundaries of the SRAM bar are allowed
	+ */
	+#define PBS_LOW_LATENCY_SRAM_REMAP_BAR1_ORIG_ADDR_HIGH_MASK 0xFFFFF000
	+#define PBS_LOW_LATENCY_SRAM_REMAP_BAR1_ORIG_ADDR_HIGH_SHIFT 12
	+
	+/** bar1_remap register **/
	+/* Reserved fields */
	+#define PBS_LOW_LATENCY_SRAM_REMAP_BAR1_REMAP_RSRVD_MASK 0x00000FFF
	+#define PBS_LOW_LATENCY_SRAM_REMAP_BAR1_REMAP_RSRVD_SHIFT 0
	+/* remapped address */
	+#define PBS_LOW_LATENCY_SRAM_REMAP_BAR1_REMAP_ADDR_HIGH_MASK 0xFFFFF000
	+#define PBS_LOW_LATENCY_SRAM_REMAP_BAR1_REMAP_ADDR_HIGH_SHIFT 12
	+
	+/** bar2_orig register **/
	+/*
	+ * Window size = 2 ^ (11 + win_size).
	+ * Zero value: disable the window.
	+ */
	+#define PBS_LOW_LATENCY_SRAM_REMAP_BAR2_ORIG_WIN_SIZE_MASK 0x00000007
	+#define PBS_LOW_LATENCY_SRAM_REMAP_BAR2_ORIG_WIN_SIZE_SHIFT 0
	+/* Reserved fields */
	+#define PBS_LOW_LATENCY_SRAM_REMAP_BAR2_ORIG_RSRVD_MASK 0x00000FF8
	+#define PBS_LOW_LATENCY_SRAM_REMAP_BAR2_ORIG_RSRVD_SHIFT 3
	+/*
	+ * offset within the SRAM, in resolution of 4KB.
	+ * Only offsets which are inside the boundaries of the SRAM bar are allowed
	+ */
	+#define PBS_LOW_LATENCY_SRAM_REMAP_BAR2_ORIG_ADDR_HIGH_MASK 0xFFFFF000
	+#define PBS_LOW_LATENCY_SRAM_REMAP_BAR2_ORIG_ADDR_HIGH_SHIFT 12
	+
	+/** bar2_remap register **/
	+/* Reserved fields */
	+#define PBS_LOW_LATENCY_SRAM_REMAP_BAR2_REMAP_RSRVD_MASK 0x00000FFF
	+#define PBS_LOW_LATENCY_SRAM_REMAP_BAR2_REMAP_RSRVD_SHIFT 0
	+/* remapped address */
	+#define PBS_LOW_LATENCY_SRAM_REMAP_BAR2_REMAP_ADDR_HIGH_MASK 0xFFFFF000
	+#define PBS_LOW_LATENCY_SRAM_REMAP_BAR2_REMAP_ADDR_HIGH_SHIFT 12
	+
	+/** bar3_orig register **/
	+/*
	+ * Window size = 2 ^ (11 + win_size).
	+ * Zero value: disable the window.
	+ */
	+#define PBS_LOW_LATENCY_SRAM_REMAP_BAR3_ORIG_WIN_SIZE_MASK 0x00000007
	+#define PBS_LOW_LATENCY_SRAM_REMAP_BAR3_ORIG_WIN_SIZE_SHIFT 0
	+/* Reserved fields */
	+#define PBS_LOW_LATENCY_SRAM_REMAP_BAR3_ORIG_RSRVD_MASK 0x00000FF8
	+#define PBS_LOW_LATENCY_SRAM_REMAP_BAR3_ORIG_RSRVD_SHIFT 3
	+/*
	+ * offset within the SRAM, in resolution of 4KB.
	+ * Only offsets which are inside the boundaries of the SRAM bar are allowed
	+ */
	+#define PBS_LOW_LATENCY_SRAM_REMAP_BAR3_ORIG_ADDR_HIGH_MASK 0xFFFFF000
	+#define PBS_LOW_LATENCY_SRAM_REMAP_BAR3_ORIG_ADDR_HIGH_SHIFT 12
	+
	+/** bar3_remap register **/
	+/* Reserved fields */
	+#define PBS_LOW_LATENCY_SRAM_REMAP_BAR3_REMAP_RSRVD_MASK 0x00000FFF
	+#define PBS_LOW_LATENCY_SRAM_REMAP_BAR3_REMAP_RSRVD_SHIFT 0
	+/* remapped address */
	+#define PBS_LOW_LATENCY_SRAM_REMAP_BAR3_REMAP_ADDR_HIGH_MASK 0xFFFFF000
	+#define PBS_LOW_LATENCY_SRAM_REMAP_BAR3_REMAP_ADDR_HIGH_SHIFT 12
	+
	+/** bar4_orig register **/
	+/*
	+ * Window size = 2 ^ (11 + win_size).
	+ * Zero value: disable the window.
	+ */
	+#define PBS_LOW_LATENCY_SRAM_REMAP_BAR4_ORIG_WIN_SIZE_MASK 0x00000007
	+#define PBS_LOW_LATENCY_SRAM_REMAP_BAR4_ORIG_WIN_SIZE_SHIFT 0
	+/* Reserved fields */
	+#define PBS_LOW_LATENCY_SRAM_REMAP_BAR4_ORIG_RSRVD_MASK 0x00000FF8
	+#define PBS_LOW_LATENCY_SRAM_REMAP_BAR4_ORIG_RSRVD_SHIFT 3
	+/*
	+ * offset within the SRAM, in resolution of 4KB.
	+ * Only offsets which are inside the boundaries of the SRAM bar are allowed
	+ */
	+#define PBS_LOW_LATENCY_SRAM_REMAP_BAR4_ORIG_ADDR_HIGH_MASK 0xFFFFF000
	+#define PBS_LOW_LATENCY_SRAM_REMAP_BAR4_ORIG_ADDR_HIGH_SHIFT 12
	+
	+/** bar4_remap register **/
	+/* Reserved fields */
	+#define PBS_LOW_LATENCY_SRAM_REMAP_BAR4_REMAP_RSRVD_MASK 0x00000FFF
	+#define PBS_LOW_LATENCY_SRAM_REMAP_BAR4_REMAP_RSRVD_SHIFT 0
	+/* remapped address */
	+#define PBS_LOW_LATENCY_SRAM_REMAP_BAR4_REMAP_ADDR_HIGH_MASK 0xFFFFF000
	+#define PBS_LOW_LATENCY_SRAM_REMAP_BAR4_REMAP_ADDR_HIGH_SHIFT 12
	+
	+/** bar5_orig register **/
	+/*
	+ * Window size = 2 ^ (11 + win_size).
	+ * Zero value: disable the window.
	+ */
	+#define PBS_LOW_LATENCY_SRAM_REMAP_BAR5_ORIG_WIN_SIZE_MASK 0x00000007
	+#define PBS_LOW_LATENCY_SRAM_REMAP_BAR5_ORIG_WIN_SIZE_SHIFT 0
	+/* Reserved fields */
	+#define PBS_LOW_LATENCY_SRAM_REMAP_BAR5_ORIG_RSRVD_MASK 0x00000FF8
	+#define PBS_LOW_LATENCY_SRAM_REMAP_BAR5_ORIG_RSRVD_SHIFT 3
	+/*
	+ * offset within the SRAM, in resolution of 4KB.
	+ * Only offsets which are inside the boundaries of the SRAM bar are allowed
	+ */
	+#define PBS_LOW_LATENCY_SRAM_REMAP_BAR5_ORIG_ADDR_HIGH_MASK 0xFFFFF000
	+#define PBS_LOW_LATENCY_SRAM_REMAP_BAR5_ORIG_ADDR_HIGH_SHIFT 12
	+
	+/** bar5_remap register **/
	+/* Reserved fields */
	+#define PBS_LOW_LATENCY_SRAM_REMAP_BAR5_REMAP_RSRVD_MASK 0x00000FFF
	+#define PBS_LOW_LATENCY_SRAM_REMAP_BAR5_REMAP_RSRVD_SHIFT 0
	+/* remapped address */
	+#define PBS_LOW_LATENCY_SRAM_REMAP_BAR5_REMAP_ADDR_HIGH_MASK 0xFFFFF000
	+#define PBS_LOW_LATENCY_SRAM_REMAP_BAR5_REMAP_ADDR_HIGH_SHIFT 12
	+
	+/** bar6_orig register **/
	+/*
	+ * Window size = 2 ^ (11 + win_size).
	+ * Zero value: disable the window.
	+ */
	+#define PBS_LOW_LATENCY_SRAM_REMAP_BAR6_ORIG_WIN_SIZE_MASK 0x00000007
	+#define PBS_LOW_LATENCY_SRAM_REMAP_BAR6_ORIG_WIN_SIZE_SHIFT 0
	+/* Reserved fields */
	+#define PBS_LOW_LATENCY_SRAM_REMAP_BAR6_ORIG_RSRVD_MASK 0x00000FF8
	+#define PBS_LOW_LATENCY_SRAM_REMAP_BAR6_ORIG_RSRVD_SHIFT 3
	+/*
	+ * offset within the SRAM, in resolution of 4KB.
	+ * Only offsets which are inside the boundaries of the SRAM bar are allowed
	+ */
	+#define PBS_LOW_LATENCY_SRAM_REMAP_BAR6_ORIG_ADDR_HIGH_MASK 0xFFFFF000
	+#define PBS_LOW_LATENCY_SRAM_REMAP_BAR6_ORIG_ADDR_HIGH_SHIFT 12
	+
	+/** bar6_remap register **/
	+/* Reserved fields */
	+#define PBS_LOW_LATENCY_SRAM_REMAP_BAR6_REMAP_RSRVD_MASK 0x00000FFF
	+#define PBS_LOW_LATENCY_SRAM_REMAP_BAR6_REMAP_RSRVD_SHIFT 0
	+/* remapped address */
	+#define PBS_LOW_LATENCY_SRAM_REMAP_BAR6_REMAP_ADDR_HIGH_MASK 0xFFFFF000
	+#define PBS_LOW_LATENCY_SRAM_REMAP_BAR6_REMAP_ADDR_HIGH_SHIFT 12
	+
	+/** bar7_orig register **/
	+/*
	+ * Window size = 2 ^ (11 + win_size).
	+ * Zero value: disable the window.
	+ */
	+#define PBS_LOW_LATENCY_SRAM_REMAP_BAR7_ORIG_WIN_SIZE_MASK 0x00000007
	+#define PBS_LOW_LATENCY_SRAM_REMAP_BAR7_ORIG_WIN_SIZE_SHIFT 0
	+/* Reserved fields */
	+#define PBS_LOW_LATENCY_SRAM_REMAP_BAR7_ORIG_RSRVD_MASK 0x00000FF8
	+#define PBS_LOW_LATENCY_SRAM_REMAP_BAR7_ORIG_RSRVD_SHIFT 3
	+/*
	+ * offset within the SRAM, in resolution of 4KB.
	+ * Only offsets which are inside the boundaries of the SRAM bar are allowed
	+ */
	+#define PBS_LOW_LATENCY_SRAM_REMAP_BAR7_ORIG_ADDR_HIGH_MASK 0xFFFFF000
	+#define PBS_LOW_LATENCY_SRAM_REMAP_BAR7_ORIG_ADDR_HIGH_SHIFT 12
	+
	+/** bar7_remap register **/
	+/* Reserved fields */
	+#define PBS_LOW_LATENCY_SRAM_REMAP_BAR7_REMAP_RSRVD_MASK 0x00000FFF
	+#define PBS_LOW_LATENCY_SRAM_REMAP_BAR7_REMAP_RSRVD_SHIFT 0
	+/* remapped address */
	+#define PBS_LOW_LATENCY_SRAM_REMAP_BAR7_REMAP_ADDR_HIGH_MASK 0xFFFFF000
	+#define PBS_LOW_LATENCY_SRAM_REMAP_BAR7_REMAP_ADDR_HIGH_SHIFT 12
	+
	+/** bar8_orig register **/
	+/*
	+ * Window size = 2 ^ (11 + win_size).
	+ * Zero value: disable the window.
	+ */
	+#define PBS_LOW_LATENCY_SRAM_REMAP_BAR8_ORIG_WIN_SIZE_MASK 0x00000007
	+#define PBS_LOW_LATENCY_SRAM_REMAP_BAR8_ORIG_WIN_SIZE_SHIFT 0
	+/* Reserved fields */
	+#define PBS_LOW_LATENCY_SRAM_REMAP_BAR8_ORIG_RSRVD_MASK 0x00000FF8
	+#define PBS_LOW_LATENCY_SRAM_REMAP_BAR8_ORIG_RSRVD_SHIFT 3
	+/*
	+ * offset within the SRAM, in resolution of 4KB.
	+ * Only offsets which are inside the boundaries of the SRAM bar are allowed
	+ */
	+#define PBS_LOW_LATENCY_SRAM_REMAP_BAR8_ORIG_ADDR_HIGH_MASK 0xFFFFF000
	+#define PBS_LOW_LATENCY_SRAM_REMAP_BAR8_ORIG_ADDR_HIGH_SHIFT 12
	+
	+/** bar8_remap register **/
	+/* Reserved fields */
	+#define PBS_LOW_LATENCY_SRAM_REMAP_BAR8_REMAP_RSRVD_MASK 0x00000FFF
	+#define PBS_LOW_LATENCY_SRAM_REMAP_BAR8_REMAP_RSRVD_SHIFT 0
	+/* remapped address */
	+#define PBS_LOW_LATENCY_SRAM_REMAP_BAR8_REMAP_ADDR_HIGH_MASK 0xFFFFF000
	+#define PBS_LOW_LATENCY_SRAM_REMAP_BAR8_REMAP_ADDR_HIGH_SHIFT 12
	+
	+/** bar9_orig register **/
	+/*
	+ * Window size = 2 ^ (11 + win_size).
	+ * Zero value: disable the window.
	+ */
	+#define PBS_LOW_LATENCY_SRAM_REMAP_BAR9_ORIG_WIN_SIZE_MASK 0x00000007
	+#define PBS_LOW_LATENCY_SRAM_REMAP_BAR9_ORIG_WIN_SIZE_SHIFT 0
	+/* Reserved fields */
	+#define PBS_LOW_LATENCY_SRAM_REMAP_BAR9_ORIG_RSRVD_MASK 0x00000FF8
	+#define PBS_LOW_LATENCY_SRAM_REMAP_BAR9_ORIG_RSRVD_SHIFT 3
	+/*
	+ * offset within the SRAM, in resolution of 4KB.
	+ * Only offsets which are inside the boundaries of the SRAM bar are allowed
	+ */
	+#define PBS_LOW_LATENCY_SRAM_REMAP_BAR9_ORIG_ADDR_HIGH_MASK 0xFFFFF000
	+#define PBS_LOW_LATENCY_SRAM_REMAP_BAR9_ORIG_ADDR_HIGH_SHIFT 12
	+
	+/** bar9_remap register **/
	+/* Reserved fields */
	+#define PBS_LOW_LATENCY_SRAM_REMAP_BAR9_REMAP_RSRVD_MASK 0x00000FFF
	+#define PBS_LOW_LATENCY_SRAM_REMAP_BAR9_REMAP_RSRVD_SHIFT 0
	+/* remapped address */
	+#define PBS_LOW_LATENCY_SRAM_REMAP_BAR9_REMAP_ADDR_HIGH_MASK 0xFFFFF000
	+#define PBS_LOW_LATENCY_SRAM_REMAP_BAR9_REMAP_ADDR_HIGH_SHIFT 12
	+
	+/** bar10_orig register **/
	+/*
	+ * Window size = 2 ^ (11 + win_size).
	+ * Zero value: disable the window.
	+ */
	+#define PBS_LOW_LATENCY_SRAM_REMAP_BAR10_ORIG_WIN_SIZE_MASK 0x00000007
	+#define PBS_LOW_LATENCY_SRAM_REMAP_BAR10_ORIG_WIN_SIZE_SHIFT 0
	+/* Reserved fields */
	+#define PBS_LOW_LATENCY_SRAM_REMAP_BAR10_ORIG_RSRVD_MASK 0x00000FF8
	+#define PBS_LOW_LATENCY_SRAM_REMAP_BAR10_ORIG_RSRVD_SHIFT 3
	+/*
	+ * offset within the SRAM, in resolution of 4KB.
	+ * Only offsets which are inside the boundaries of the SRAM bar are allowed
	+ */
	+#define PBS_LOW_LATENCY_SRAM_REMAP_BAR10_ORIG_ADDR_HIGH_MASK 0xFFFFF000
	+#define PBS_LOW_LATENCY_SRAM_REMAP_BAR10_ORIG_ADDR_HIGH_SHIFT 12
	+
	+/** bar10_remap register **/
	+/* Reserved fields */
	+#define PBS_LOW_LATENCY_SRAM_REMAP_BAR10_REMAP_RSRVD_MASK 0x00000FFF
	+#define PBS_LOW_LATENCY_SRAM_REMAP_BAR10_REMAP_RSRVD_SHIFT 0
	+/* remapped address */
	+#define PBS_LOW_LATENCY_SRAM_REMAP_BAR10_REMAP_ADDR_HIGH_MASK 0xFFFFF000
	+#define PBS_LOW_LATENCY_SRAM_REMAP_BAR10_REMAP_ADDR_HIGH_SHIFT 12
	+
	+/** cpu register **/
	+/* map transactions according to address decoding */
	+#define PBS_TARGET_ID_ENFORCEMENT_CPU_NO_ENFORCEMENT_MASK 0x0000000F
	+#define PBS_TARGET_ID_ENFORCEMENT_CPU_NO_ENFORCEMENT_SHIFT 0
	+/* map transactions to pcie_0 */
	+#define PBS_TARGET_ID_ENFORCEMENT_CPU_PCIE_0_MASK 0x000000F0
	+#define PBS_TARGET_ID_ENFORCEMENT_CPU_PCIE_0_SHIFT 4
	+/* map transactions to pcie_1 */
	+#define PBS_TARGET_ID_ENFORCEMENT_CPU_PCIE_1_MASK 0x00000F00
	+#define PBS_TARGET_ID_ENFORCEMENT_CPU_PCIE_1_SHIFT 8
	+/* map transactions to pcie_2 */
	+#define PBS_TARGET_ID_ENFORCEMENT_CPU_PCIE_2_MASK 0x0000F000
	+#define PBS_TARGET_ID_ENFORCEMENT_CPU_PCIE_2_SHIFT 12
	+/* map transactions to pcie_3 */
	+#define PBS_TARGET_ID_ENFORCEMENT_CPU_PCIE_3_MASK 0x000F0000
	+#define PBS_TARGET_ID_ENFORCEMENT_CPU_PCIE_3_SHIFT 16
	+/* map transactions to pcie_4 */
	+#define PBS_TARGET_ID_ENFORCEMENT_CPU_PCIE_4_MASK 0x00F00000
	+#define PBS_TARGET_ID_ENFORCEMENT_CPU_PCIE_4_SHIFT 20
	+/* map transactions to pcie_5 */
	+#define PBS_TARGET_ID_ENFORCEMENT_CPU_PCIE_5_MASK 0x0F000000
	+#define PBS_TARGET_ID_ENFORCEMENT_CPU_PCIE_5_SHIFT 24
	+/* map transactions to dram */
	+#define PBS_TARGET_ID_ENFORCEMENT_CPU_DRAM_MASK 0xF0000000
	+#define PBS_TARGET_ID_ENFORCEMENT_CPU_DRAM_SHIFT 28
	+
	+/** cpu_mask register **/
	+/* map transactions according to address decoding */
	+#define PBS_TARGET_ID_ENFORCEMENT_CPU_MASK_NO_ENFORCEMENT_MASK 0x0000000F
	+#define PBS_TARGET_ID_ENFORCEMENT_CPU_MASK_NO_ENFORCEMENT_SHIFT 0
	+/* map transactions to pcie_0 */
	+#define PBS_TARGET_ID_ENFORCEMENT_CPU_MASK_PCIE_0_MASK 0x000000F0
	+#define PBS_TARGET_ID_ENFORCEMENT_CPU_MASK_PCIE_0_SHIFT 4
	+/* map transactions to pcie_1 */
	+#define PBS_TARGET_ID_ENFORCEMENT_CPU_MASK_PCIE_1_MASK 0x00000F00
	+#define PBS_TARGET_ID_ENFORCEMENT_CPU_MASK_PCIE_1_SHIFT 8
	+/* map transactions to pcie_2 */
	+#define PBS_TARGET_ID_ENFORCEMENT_CPU_MASK_PCIE_2_MASK 0x0000F000
	+#define PBS_TARGET_ID_ENFORCEMENT_CPU_MASK_PCIE_2_SHIFT 12
	+/* map transactions to pcie_3 */
	+#define PBS_TARGET_ID_ENFORCEMENT_CPU_MASK_PCIE_3_MASK 0x000F0000
	+#define PBS_TARGET_ID_ENFORCEMENT_CPU_MASK_PCIE_3_SHIFT 16
	+/* map transactions to pcie_4 */
	+#define PBS_TARGET_ID_ENFORCEMENT_CPU_MASK_PCIE_4_MASK 0x00F00000
	+#define PBS_TARGET_ID_ENFORCEMENT_CPU_MASK_PCIE_4_SHIFT 20
	+/* map transactions to pcie_5 */
	+#define PBS_TARGET_ID_ENFORCEMENT_CPU_MASK_PCIE_5_MASK 0x0F000000
	+#define PBS_TARGET_ID_ENFORCEMENT_CPU_MASK_PCIE_5_SHIFT 24
	+/* map transactions to dram */
	+#define PBS_TARGET_ID_ENFORCEMENT_CPU_MASK_DRAM_MASK 0xF0000000
	+#define PBS_TARGET_ID_ENFORCEMENT_CPU_MASK_DRAM_SHIFT 28
	+
	+/** debug_nb register **/
	+/* map transactions according to address decoding */
	+#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_NO_ENFORCEMENT_MASK 0x0000000F
	+#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_NO_ENFORCEMENT_SHIFT 0
	+/* map transactions to pcie_0 */
	+#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_PCIE_0_MASK 0x000000F0
	+#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_PCIE_0_SHIFT 4
	+/* map transactions to pcie_1 */
	+#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_PCIE_1_MASK 0x00000F00
	+#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_PCIE_1_SHIFT 8
	+/* map transactions to pcie_2 */
	+#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_PCIE_2_MASK 0x0000F000
	+#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_PCIE_2_SHIFT 12
	+/* map transactions to pcie_3 */
	+#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_PCIE_3_MASK 0x000F0000
	+#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_PCIE_3_SHIFT 16
	+/* map transactions to pcie_4 */
	+#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_PCIE_4_MASK 0x00F00000
	+#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_PCIE_4_SHIFT 20
	+/* map transactions to pcie_5 */
	+#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_PCIE_5_MASK 0x0F000000
	+#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_PCIE_5_SHIFT 24
	+/* map transactions to dram */
	+#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_DRAM_MASK 0xF0000000
	+#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_DRAM_SHIFT 28
	+
	+/** debug_nb_mask register **/
	+/* map transactions according to address decoding */
	+#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_MASK_NO_ENFORCEMENT_MASK 0x0000000F
	+#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_MASK_NO_ENFORCEMENT_SHIFT 0
	+/* map transactions to pcie_0 */
	+#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_MASK_PCIE_0_MASK 0x000000F0
	+#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_MASK_PCIE_0_SHIFT 4
	+/* map transactions to pcie_1 */
	+#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_MASK_PCIE_1_MASK 0x00000F00
	+#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_MASK_PCIE_1_SHIFT 8
	+/* map transactions to pcie_2 */
	+#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_MASK_PCIE_2_MASK 0x0000F000
	+#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_MASK_PCIE_2_SHIFT 12
	+/* map transactions to pcie_3 */
	+#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_MASK_PCIE_3_MASK 0x000F0000
	+#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_MASK_PCIE_3_SHIFT 16
	+/* map transactions to pcie_4 */
	+#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_MASK_PCIE_4_MASK 0x00F00000
	+#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_MASK_PCIE_4_SHIFT 20
	+/* map transactions to pcie_5 */
	+#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_MASK_PCIE_5_MASK 0x0F000000
	+#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_MASK_PCIE_5_SHIFT 24
	+/* map transactions to dram */
	+#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_MASK_DRAM_MASK 0xF0000000
	+#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_NB_MASK_DRAM_SHIFT 28
	+
	+/** debug_sb register **/
	+/* map transactions according to address decoding */
	+#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_NO_ENFORCEMENT_MASK 0x0000000F
	+#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_NO_ENFORCEMENT_SHIFT 0
	+/* map transactions to pcie_0 */
	+#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_PCIE_0_MASK 0x000000F0
	+#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_PCIE_0_SHIFT 4
	+/* map transactions to pcie_1 */
	+#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_PCIE_1_MASK 0x00000F00
	+#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_PCIE_1_SHIFT 8
	+/* map transactions to pcie_2 */
	+#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_PCIE_2_MASK 0x0000F000
	+#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_PCIE_2_SHIFT 12
	+/* map transactions to pcie_3 */
	+#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_PCIE_3_MASK 0x000F0000
	+#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_PCIE_3_SHIFT 16
	+/* map transactions to pcie_4 */
	+#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_PCIE_4_MASK 0x00F00000
	+#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_PCIE_4_SHIFT 20
	+/* map transactions to pcie_5 */
	+#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_PCIE_5_MASK 0x0F000000
	+#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_PCIE_5_SHIFT 24
	+/* map transactions to dram */
	+#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_DRAM_MASK 0xF0000000
	+#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_DRAM_SHIFT 28
	+
	+/** debug_sb_mask register **/
	+/* map transactions according to address decoding */
	+#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_MASK_NO_ENFORCEMENT_MASK 0x0000000F
	+#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_MASK_NO_ENFORCEMENT_SHIFT 0
	+/* map transactions to pcie_0 */
	+#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_MASK_PCIE_0_MASK 0x000000F0
	+#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_MASK_PCIE_0_SHIFT 4
	+/* map transactions to pcie_1 */
	+#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_MASK_PCIE_1_MASK 0x00000F00
	+#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_MASK_PCIE_1_SHIFT 8
	+/* map transactions to pcie_2 */
	+#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_MASK_PCIE_2_MASK 0x0000F000
	+#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_MASK_PCIE_2_SHIFT 12
	+/* map transactions to pcie_3 */
	+#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_MASK_PCIE_3_MASK 0x000F0000
	+#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_MASK_PCIE_3_SHIFT 16
	+/* map transactions to pcie_4 */
	+#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_MASK_PCIE_4_MASK 0x00F00000
	+#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_MASK_PCIE_4_SHIFT 20
	+/* map transactions to pcie_5 */
	+#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_MASK_PCIE_5_MASK 0x0F000000
	+#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_MASK_PCIE_5_SHIFT 24
	+/* map transactions to dram */
	+#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_MASK_DRAM_MASK 0xF0000000
	+#define PBS_TARGET_ID_ENFORCEMENT_DEBUG_SB_MASK_DRAM_SHIFT 28
	+
	+/** eth_0 register **/
	+/* map transactions according to address decoding */
	+#define PBS_TARGET_ID_ENFORCEMENT_ETH_0_NO_ENFORCEMENT_MASK 0x0000000F
	+#define PBS_TARGET_ID_ENFORCEMENT_ETH_0_NO_ENFORCEMENT_SHIFT 0
	+/* map transactions to pcie_0 */
	+#define PBS_TARGET_ID_ENFORCEMENT_ETH_0_PCIE_0_MASK 0x000000F0
	+#define PBS_TARGET_ID_ENFORCEMENT_ETH_0_PCIE_0_SHIFT 4
	+/* map transactions to pcie_1 */
	+#define PBS_TARGET_ID_ENFORCEMENT_ETH_0_PCIE_1_MASK 0x00000F00
	+#define PBS_TARGET_ID_ENFORCEMENT_ETH_0_PCIE_1_SHIFT 8
	+/* map transactions to pcie_2 */
	+#define PBS_TARGET_ID_ENFORCEMENT_ETH_0_PCIE_2_MASK 0x0000F000
	+#define PBS_TARGET_ID_ENFORCEMENT_ETH_0_PCIE_2_SHIFT 12
	+/* map transactions to pcie_3 */
	+#define PBS_TARGET_ID_ENFORCEMENT_ETH_0_PCIE_3_MASK 0x000F0000
	+#define PBS_TARGET_ID_ENFORCEMENT_ETH_0_PCIE_3_SHIFT 16
	+/* map transactions to pcie_4 */
	+#define PBS_TARGET_ID_ENFORCEMENT_ETH_0_PCIE_4_MASK 0x00F00000
	+#define PBS_TARGET_ID_ENFORCEMENT_ETH_0_PCIE_4_SHIFT 20
	+/* map transactions to pcie_5 */
	+#define PBS_TARGET_ID_ENFORCEMENT_ETH_0_PCIE_5_MASK 0x0F000000
	+#define PBS_TARGET_ID_ENFORCEMENT_ETH_0_PCIE_5_SHIFT 24
	+/* map transactions to dram */
	+#define PBS_TARGET_ID_ENFORCEMENT_ETH_0_DRAM_MASK 0xF0000000
	+#define PBS_TARGET_ID_ENFORCEMENT_ETH_0_DRAM_SHIFT 28
	+
	+/** eth_0_mask register **/
	+/* map transactions according to address decoding */
	+#define PBS_TARGET_ID_ENFORCEMENT_ETH_0_MASK_NO_ENFORCEMENT_MASK 0x0000000F
	+#define PBS_TARGET_ID_ENFORCEMENT_ETH_0_MASK_NO_ENFORCEMENT_SHIFT 0
	+/* map transactions to pcie_0 */
	+#define PBS_TARGET_ID_ENFORCEMENT_ETH_0_MASK_PCIE_0_MASK 0x000000F0
	+#define PBS_TARGET_ID_ENFORCEMENT_ETH_0_MASK_PCIE_0_SHIFT 4
	+/* map transactions to pcie_1 */
	+#define PBS_TARGET_ID_ENFORCEMENT_ETH_0_MASK_PCIE_1_MASK 0x00000F00
	+#define PBS_TARGET_ID_ENFORCEMENT_ETH_0_MASK_PCIE_1_SHIFT 8
	+/* map transactions to pcie_2 */
	+#define PBS_TARGET_ID_ENFORCEMENT_ETH_0_MASK_PCIE_2_MASK 0x0000F000
	+#define PBS_TARGET_ID_ENFORCEMENT_ETH_0_MASK_PCIE_2_SHIFT 12
	+/* map transactions to pcie_3 */
	+#define PBS_TARGET_ID_ENFORCEMENT_ETH_0_MASK_PCIE_3_MASK 0x000F0000
	+#define PBS_TARGET_ID_ENFORCEMENT_ETH_0_MASK_PCIE_3_SHIFT 16
	+/* map transactions to pcie_4 */
	+#define PBS_TARGET_ID_ENFORCEMENT_ETH_0_MASK_PCIE_4_MASK 0x00F00000
	+#define PBS_TARGET_ID_ENFORCEMENT_ETH_0_MASK_PCIE_4_SHIFT 20
	+/* map transactions to pcie_5 */
	+#define PBS_TARGET_ID_ENFORCEMENT_ETH_0_MASK_PCIE_5_MASK 0x0F000000
	+#define PBS_TARGET_ID_ENFORCEMENT_ETH_0_MASK_PCIE_5_SHIFT 24
	+/* map transactions to dram */
	+#define PBS_TARGET_ID_ENFORCEMENT_ETH_0_MASK_DRAM_MASK 0xF0000000
	+#define PBS_TARGET_ID_ENFORCEMENT_ETH_0_MASK_DRAM_SHIFT 28
	+
	+/** eth_1 register **/
	+/* map transactions according to address decoding */
	+#define PBS_TARGET_ID_ENFORCEMENT_ETH_1_NO_ENFORCEMENT_MASK 0x0000000F
	+#define PBS_TARGET_ID_ENFORCEMENT_ETH_1_NO_ENFORCEMENT_SHIFT 0
	+/* map transactions to pcie_0 */
	+#define PBS_TARGET_ID_ENFORCEMENT_ETH_1_PCIE_0_MASK 0x000000F0
	+#define PBS_TARGET_ID_ENFORCEMENT_ETH_1_PCIE_0_SHIFT 4
	+/* map transactions to pcie_1 */
	+#define PBS_TARGET_ID_ENFORCEMENT_ETH_1_PCIE_1_MASK 0x00000F00
	+#define PBS_TARGET_ID_ENFORCEMENT_ETH_1_PCIE_1_SHIFT 8
	+/* map transactions to pcie_2 */
	+#define PBS_TARGET_ID_ENFORCEMENT_ETH_1_PCIE_2_MASK 0x0000F000
	+#define PBS_TARGET_ID_ENFORCEMENT_ETH_1_PCIE_2_SHIFT 12
	+/* map transactions to pcie_3 */
	+#define PBS_TARGET_ID_ENFORCEMENT_ETH_1_PCIE_3_MASK 0x000F0000
	+#define PBS_TARGET_ID_ENFORCEMENT_ETH_1_PCIE_3_SHIFT 16
	+/* map transactions to pcie_4 */
	+#define PBS_TARGET_ID_ENFORCEMENT_ETH_1_PCIE_4_MASK 0x00F00000
	+#define PBS_TARGET_ID_ENFORCEMENT_ETH_1_PCIE_4_SHIFT 20
	+/* map transactions to pcie_5 */
	+#define PBS_TARGET_ID_ENFORCEMENT_ETH_1_PCIE_5_MASK 0x0F000000
	+#define PBS_TARGET_ID_ENFORCEMENT_ETH_1_PCIE_5_SHIFT 24
	+/* map transactions to dram */
	+#define PBS_TARGET_ID_ENFORCEMENT_ETH_1_DRAM_MASK 0xF0000000
	+#define PBS_TARGET_ID_ENFORCEMENT_ETH_1_DRAM_SHIFT 28
	+
	+/** eth_1_mask register **/
	+/* map transactions according to address decoding */
	+#define PBS_TARGET_ID_ENFORCEMENT_ETH_1_MASK_NO_ENFORCEMENT_MASK 0x0000000F
	+#define PBS_TARGET_ID_ENFORCEMENT_ETH_1_MASK_NO_ENFORCEMENT_SHIFT 0
	+/* map transactions to pcie_0 */
	+#define PBS_TARGET_ID_ENFORCEMENT_ETH_1_MASK_PCIE_0_MASK 0x000000F0
	+#define PBS_TARGET_ID_ENFORCEMENT_ETH_1_MASK_PCIE_0_SHIFT 4
	+/* map transactions to pcie_1 */
	+#define PBS_TARGET_ID_ENFORCEMENT_ETH_1_MASK_PCIE_1_MASK 0x00000F00
	+#define PBS_TARGET_ID_ENFORCEMENT_ETH_1_MASK_PCIE_1_SHIFT 8
	+/* map transactions to pcie_2 */
	+#define PBS_TARGET_ID_ENFORCEMENT_ETH_1_MASK_PCIE_2_MASK 0x0000F000
	+#define PBS_TARGET_ID_ENFORCEMENT_ETH_1_MASK_PCIE_2_SHIFT 12
	+/* map transactions to pcie_3 */
	+#define PBS_TARGET_ID_ENFORCEMENT_ETH_1_MASK_PCIE_3_MASK 0x000F0000
	+#define PBS_TARGET_ID_ENFORCEMENT_ETH_1_MASK_PCIE_3_SHIFT 16
	+/* map transactions to pcie_4 */
	+#define PBS_TARGET_ID_ENFORCEMENT_ETH_1_MASK_PCIE_4_MASK 0x00F00000
	+#define PBS_TARGET_ID_ENFORCEMENT_ETH_1_MASK_PCIE_4_SHIFT 20
	+/* map transactions to pcie_5 */
	+#define PBS_TARGET_ID_ENFORCEMENT_ETH_1_MASK_PCIE_5_MASK 0x0F000000
	+#define PBS_TARGET_ID_ENFORCEMENT_ETH_1_MASK_PCIE_5_SHIFT 24
	+/* map transactions to dram */
	+#define PBS_TARGET_ID_ENFORCEMENT_ETH_1_MASK_DRAM_MASK 0xF0000000
	+#define PBS_TARGET_ID_ENFORCEMENT_ETH_1_MASK_DRAM_SHIFT 28
	+
	+/** eth_2 register **/
	+/* map transactions according to address decoding */
	+#define PBS_TARGET_ID_ENFORCEMENT_ETH_2_NO_ENFORCEMENT_MASK 0x0000000F
	+#define PBS_TARGET_ID_ENFORCEMENT_ETH_2_NO_ENFORCEMENT_SHIFT 0
	+/* map transactions to pcie_0 */
	+#define PBS_TARGET_ID_ENFORCEMENT_ETH_2_PCIE_0_MASK 0x000000F0
	+#define PBS_TARGET_ID_ENFORCEMENT_ETH_2_PCIE_0_SHIFT 4
	+/* map transactions to pcie_1 */
	+#define PBS_TARGET_ID_ENFORCEMENT_ETH_2_PCIE_1_MASK 0x00000F00
	+#define PBS_TARGET_ID_ENFORCEMENT_ETH_2_PCIE_1_SHIFT 8
	+/* map transactions to pcie_2 */
	+#define PBS_TARGET_ID_ENFORCEMENT_ETH_2_PCIE_2_MASK 0x0000F000
	+#define PBS_TARGET_ID_ENFORCEMENT_ETH_2_PCIE_2_SHIFT 12
	+/* map transactions to pcie_3 */
	+#define PBS_TARGET_ID_ENFORCEMENT_ETH_2_PCIE_3_MASK 0x000F0000
	+#define PBS_TARGET_ID_ENFORCEMENT_ETH_2_PCIE_3_SHIFT 16
	+/* map transactions to pcie_4 */
	+#define PBS_TARGET_ID_ENFORCEMENT_ETH_2_PCIE_4_MASK 0x00F00000
	+#define PBS_TARGET_ID_ENFORCEMENT_ETH_2_PCIE_4_SHIFT 20
	+/* map transactions to pcie_5 */
	+#define PBS_TARGET_ID_ENFORCEMENT_ETH_2_PCIE_5_MASK 0x0F000000
	+#define PBS_TARGET_ID_ENFORCEMENT_ETH_2_PCIE_5_SHIFT 24
	+/* map transactions to dram */
	+#define PBS_TARGET_ID_ENFORCEMENT_ETH_2_DRAM_MASK 0xF0000000
	+#define PBS_TARGET_ID_ENFORCEMENT_ETH_2_DRAM_SHIFT 28
	+
	+/** eth_2_mask register **/
	+/* map transactions according to address decoding */
	+#define PBS_TARGET_ID_ENFORCEMENT_ETH_2_MASK_NO_ENFORCEMENT_MASK 0x0000000F
	+#define PBS_TARGET_ID_ENFORCEMENT_ETH_2_MASK_NO_ENFORCEMENT_SHIFT 0
	+/* map transactions to pcie_0 */
	+#define PBS_TARGET_ID_ENFORCEMENT_ETH_2_MASK_PCIE_0_MASK 0x000000F0
	+#define PBS_TARGET_ID_ENFORCEMENT_ETH_2_MASK_PCIE_0_SHIFT 4
	+/* map transactions to pcie_1 */
	+#define PBS_TARGET_ID_ENFORCEMENT_ETH_2_MASK_PCIE_1_MASK 0x00000F00
	+#define PBS_TARGET_ID_ENFORCEMENT_ETH_2_MASK_PCIE_1_SHIFT 8
	+/* map transactions to pcie_2 */
	+#define PBS_TARGET_ID_ENFORCEMENT_ETH_2_MASK_PCIE_2_MASK 0x0000F000
	+#define PBS_TARGET_ID_ENFORCEMENT_ETH_2_MASK_PCIE_2_SHIFT 12
	+/* map transactions to pcie_3 */
	+#define PBS_TARGET_ID_ENFORCEMENT_ETH_2_MASK_PCIE_3_MASK 0x000F0000
	+#define PBS_TARGET_ID_ENFORCEMENT_ETH_2_MASK_PCIE_3_SHIFT 16
	+/* map transactions to pcie_4 */
	+#define PBS_TARGET_ID_ENFORCEMENT_ETH_2_MASK_PCIE_4_MASK 0x00F00000
	+#define PBS_TARGET_ID_ENFORCEMENT_ETH_2_MASK_PCIE_4_SHIFT 20
	+/* map transactions to pcie_5 */
	+#define PBS_TARGET_ID_ENFORCEMENT_ETH_2_MASK_PCIE_5_MASK 0x0F000000
	+#define PBS_TARGET_ID_ENFORCEMENT_ETH_2_MASK_PCIE_5_SHIFT 24
	+/* map transactions to dram */
	+#define PBS_TARGET_ID_ENFORCEMENT_ETH_2_MASK_DRAM_MASK 0xF0000000
	+#define PBS_TARGET_ID_ENFORCEMENT_ETH_2_MASK_DRAM_SHIFT 28
	+
	+/** eth_3 register **/
	+/* map transactions according to address decoding */
	+#define PBS_TARGET_ID_ENFORCEMENT_ETH_3_NO_ENFORCEMENT_MASK 0x0000000F
	+#define PBS_TARGET_ID_ENFORCEMENT_ETH_3_NO_ENFORCEMENT_SHIFT 0
	+/* map transactions to pcie_0 */
	+#define PBS_TARGET_ID_ENFORCEMENT_ETH_3_PCIE_0_MASK 0x000000F0
	+#define PBS_TARGET_ID_ENFORCEMENT_ETH_3_PCIE_0_SHIFT 4
	+/* map transactions to pcie_1 */
	+#define PBS_TARGET_ID_ENFORCEMENT_ETH_3_PCIE_1_MASK 0x00000F00
	+#define PBS_TARGET_ID_ENFORCEMENT_ETH_3_PCIE_1_SHIFT 8
	+/* map transactions to pcie_2 */
	+#define PBS_TARGET_ID_ENFORCEMENT_ETH_3_PCIE_2_MASK 0x0000F000
	+#define PBS_TARGET_ID_ENFORCEMENT_ETH_3_PCIE_2_SHIFT 12
	+/* map transactions to pcie_3 */
	+#define PBS_TARGET_ID_ENFORCEMENT_ETH_3_PCIE_3_MASK 0x000F0000
	+#define PBS_TARGET_ID_ENFORCEMENT_ETH_3_PCIE_3_SHIFT 16
	+/* map transactions to pcie_4 */
	+#define PBS_TARGET_ID_ENFORCEMENT_ETH_3_PCIE_4_MASK 0x00F00000
	+#define PBS_TARGET_ID_ENFORCEMENT_ETH_3_PCIE_4_SHIFT 20
	+/* map transactions to pcie_5 */
	+#define PBS_TARGET_ID_ENFORCEMENT_ETH_3_PCIE_5_MASK 0x0F000000
	+#define PBS_TARGET_ID_ENFORCEMENT_ETH_3_PCIE_5_SHIFT 24
	+/* map transactions to dram */
	+#define PBS_TARGET_ID_ENFORCEMENT_ETH_3_DRAM_MASK 0xF0000000
	+#define PBS_TARGET_ID_ENFORCEMENT_ETH_3_DRAM_SHIFT 28
	+
	+/** eth_3_mask register **/
	+/* map transactions according to address decoding */
	+#define PBS_TARGET_ID_ENFORCEMENT_ETH_3_MASK_NO_ENFORCEMENT_MASK 0x0000000F
	+#define PBS_TARGET_ID_ENFORCEMENT_ETH_3_MASK_NO_ENFORCEMENT_SHIFT 0
	+/* map transactions to pcie_0 */
	+#define PBS_TARGET_ID_ENFORCEMENT_ETH_3_MASK_PCIE_0_MASK 0x000000F0
	+#define PBS_TARGET_ID_ENFORCEMENT_ETH_3_MASK_PCIE_0_SHIFT 4
	+/* map transactions to pcie_1 */
	+#define PBS_TARGET_ID_ENFORCEMENT_ETH_3_MASK_PCIE_1_MASK 0x00000F00
	+#define PBS_TARGET_ID_ENFORCEMENT_ETH_3_MASK_PCIE_1_SHIFT 8
	+/* map transactions to pcie_2 */
	+#define PBS_TARGET_ID_ENFORCEMENT_ETH_3_MASK_PCIE_2_MASK 0x0000F000
	+#define PBS_TARGET_ID_ENFORCEMENT_ETH_3_MASK_PCIE_2_SHIFT 12
	+/* map transactions to pcie_3 */
	+#define PBS_TARGET_ID_ENFORCEMENT_ETH_3_MASK_PCIE_3_MASK 0x000F0000
	+#define PBS_TARGET_ID_ENFORCEMENT_ETH_3_MASK_PCIE_3_SHIFT 16
	+/* map transactions to pcie_4 */
	+#define PBS_TARGET_ID_ENFORCEMENT_ETH_3_MASK_PCIE_4_MASK 0x00F00000
	+#define PBS_TARGET_ID_ENFORCEMENT_ETH_3_MASK_PCIE_4_SHIFT 20
	+/* map transactions to pcie_5 */
	+#define PBS_TARGET_ID_ENFORCEMENT_ETH_3_MASK_PCIE_5_MASK 0x0F000000
	+#define PBS_TARGET_ID_ENFORCEMENT_ETH_3_MASK_PCIE_5_SHIFT 24
	+/* map transactions to dram */
	+#define PBS_TARGET_ID_ENFORCEMENT_ETH_3_MASK_DRAM_MASK 0xF0000000
	+#define PBS_TARGET_ID_ENFORCEMENT_ETH_3_MASK_DRAM_SHIFT 28
	+
	+/** sata_0 register **/
	+/* map transactions according to address decoding */
	+#define PBS_TARGET_ID_ENFORCEMENT_SATA_0_NO_ENFORCEMENT_MASK 0x0000000F
	+#define PBS_TARGET_ID_ENFORCEMENT_SATA_0_NO_ENFORCEMENT_SHIFT 0
	+/* map transactions to pcie_0 */
	+#define PBS_TARGET_ID_ENFORCEMENT_SATA_0_PCIE_0_MASK 0x000000F0
	+#define PBS_TARGET_ID_ENFORCEMENT_SATA_0_PCIE_0_SHIFT 4
	+/* map transactions to pcie_1 */
	+#define PBS_TARGET_ID_ENFORCEMENT_SATA_0_PCIE_1_MASK 0x00000F00
	+#define PBS_TARGET_ID_ENFORCEMENT_SATA_0_PCIE_1_SHIFT 8
	+/* map transactions to pcie_2 */
	+#define PBS_TARGET_ID_ENFORCEMENT_SATA_0_PCIE_2_MASK 0x0000F000
	+#define PBS_TARGET_ID_ENFORCEMENT_SATA_0_PCIE_2_SHIFT 12
	+/* map transactions to pcie_3 */
	+#define PBS_TARGET_ID_ENFORCEMENT_SATA_0_PCIE_3_MASK 0x000F0000
	+#define PBS_TARGET_ID_ENFORCEMENT_SATA_0_PCIE_3_SHIFT 16
	+/* map transactions to pcie_4 */
	+#define PBS_TARGET_ID_ENFORCEMENT_SATA_0_PCIE_4_MASK 0x00F00000
	+#define PBS_TARGET_ID_ENFORCEMENT_SATA_0_PCIE_4_SHIFT 20
	+/* map transactions to pcie_5 */
	+#define PBS_TARGET_ID_ENFORCEMENT_SATA_0_PCIE_5_MASK 0x0F000000
	+#define PBS_TARGET_ID_ENFORCEMENT_SATA_0_PCIE_5_SHIFT 24
	+/* map transactions to dram */
	+#define PBS_TARGET_ID_ENFORCEMENT_SATA_0_DRAM_MASK 0xF0000000
	+#define PBS_TARGET_ID_ENFORCEMENT_SATA_0_DRAM_SHIFT 28
	+
	+/** sata_0_mask register **/
	+/* map transactions according to address decoding */
	+#define PBS_TARGET_ID_ENFORCEMENT_SATA_0_MASK_NO_ENFORCEMENT_MASK 0x0000000F
	+#define PBS_TARGET_ID_ENFORCEMENT_SATA_0_MASK_NO_ENFORCEMENT_SHIFT 0
	+/* map transactions to pcie_0 */
	+#define PBS_TARGET_ID_ENFORCEMENT_SATA_0_MASK_PCIE_0_MASK 0x000000F0
	+#define PBS_TARGET_ID_ENFORCEMENT_SATA_0_MASK_PCIE_0_SHIFT 4
	+/* map transactions to pcie_1 */
	+#define PBS_TARGET_ID_ENFORCEMENT_SATA_0_MASK_PCIE_1_MASK 0x00000F00
	+#define PBS_TARGET_ID_ENFORCEMENT_SATA_0_MASK_PCIE_1_SHIFT 8
	+/* map transactions to pcie_2 */
	+#define PBS_TARGET_ID_ENFORCEMENT_SATA_0_MASK_PCIE_2_MASK 0x0000F000
	+#define PBS_TARGET_ID_ENFORCEMENT_SATA_0_MASK_PCIE_2_SHIFT 12
	+/* map transactions to pcie_3 */
	+#define PBS_TARGET_ID_ENFORCEMENT_SATA_0_MASK_PCIE_3_MASK 0x000F0000
	+#define PBS_TARGET_ID_ENFORCEMENT_SATA_0_MASK_PCIE_3_SHIFT 16
	+/* map transactions to pcie_4 */
	+#define PBS_TARGET_ID_ENFORCEMENT_SATA_0_MASK_PCIE_4_MASK 0x00F00000
	+#define PBS_TARGET_ID_ENFORCEMENT_SATA_0_MASK_PCIE_4_SHIFT 20
	+/* map transactions to pcie_5 */
	+#define PBS_TARGET_ID_ENFORCEMENT_SATA_0_MASK_PCIE_5_MASK 0x0F000000
	+#define PBS_TARGET_ID_ENFORCEMENT_SATA_0_MASK_PCIE_5_SHIFT 24
	+/* map transactions to dram */
	+#define PBS_TARGET_ID_ENFORCEMENT_SATA_0_MASK_DRAM_MASK 0xF0000000
	+#define PBS_TARGET_ID_ENFORCEMENT_SATA_0_MASK_DRAM_SHIFT 28
	+
	+/** sata_1 register **/
	+/* map transactions according to address decoding */
	+#define PBS_TARGET_ID_ENFORCEMENT_SATA_1_NO_ENFORCEMENT_MASK 0x0000000F
	+#define PBS_TARGET_ID_ENFORCEMENT_SATA_1_NO_ENFORCEMENT_SHIFT 0
	+/* map transactions to pcie_0 */
	+#define PBS_TARGET_ID_ENFORCEMENT_SATA_1_PCIE_0_MASK 0x000000F0
	+#define PBS_TARGET_ID_ENFORCEMENT_SATA_1_PCIE_0_SHIFT 4
	+/* map transactions to pcie_1 */
	+#define PBS_TARGET_ID_ENFORCEMENT_SATA_1_PCIE_1_MASK 0x00000F00
	+#define PBS_TARGET_ID_ENFORCEMENT_SATA_1_PCIE_1_SHIFT 8
	+/* map transactions to pcie_2 */
	+#define PBS_TARGET_ID_ENFORCEMENT_SATA_1_PCIE_2_MASK 0x0000F000
	+#define PBS_TARGET_ID_ENFORCEMENT_SATA_1_PCIE_2_SHIFT 12
	+/* map transactions to pcie_3 */
	+#define PBS_TARGET_ID_ENFORCEMENT_SATA_1_PCIE_3_MASK 0x000F0000
	+#define PBS_TARGET_ID_ENFORCEMENT_SATA_1_PCIE_3_SHIFT 16
	+/* map transactions to pcie_4 */
	+#define PBS_TARGET_ID_ENFORCEMENT_SATA_1_PCIE_4_MASK 0x00F00000
	+#define PBS_TARGET_ID_ENFORCEMENT_SATA_1_PCIE_4_SHIFT 20
	+/* map transactions to pcie_5 */
	+#define PBS_TARGET_ID_ENFORCEMENT_SATA_1_PCIE_5_MASK 0x0F000000
	+#define PBS_TARGET_ID_ENFORCEMENT_SATA_1_PCIE_5_SHIFT 24
	+/* map transactions to dram */
	+#define PBS_TARGET_ID_ENFORCEMENT_SATA_1_DRAM_MASK 0xF0000000
	+#define PBS_TARGET_ID_ENFORCEMENT_SATA_1_DRAM_SHIFT 28
	+
	+/** sata_1_mask register **/
	+/* map transactions according to address decoding */
	+#define PBS_TARGET_ID_ENFORCEMENT_SATA_1_MASK_NO_ENFORCEMENT_MASK 0x0000000F
	+#define PBS_TARGET_ID_ENFORCEMENT_SATA_1_MASK_NO_ENFORCEMENT_SHIFT 0
	+/* map transactions to pcie_0 */
	+#define PBS_TARGET_ID_ENFORCEMENT_SATA_1_MASK_PCIE_0_MASK 0x000000F0
	+#define PBS_TARGET_ID_ENFORCEMENT_SATA_1_MASK_PCIE_0_SHIFT 4
	+/* map transactions to pcie_1 */
	+#define PBS_TARGET_ID_ENFORCEMENT_SATA_1_MASK_PCIE_1_MASK 0x00000F00
	+#define PBS_TARGET_ID_ENFORCEMENT_SATA_1_MASK_PCIE_1_SHIFT 8
	+/* map transactions to pcie_2 */
	+#define PBS_TARGET_ID_ENFORCEMENT_SATA_1_MASK_PCIE_2_MASK 0x0000F000
	+#define PBS_TARGET_ID_ENFORCEMENT_SATA_1_MASK_PCIE_2_SHIFT 12
	+/* map transactions to pcie_3 */
	+#define PBS_TARGET_ID_ENFORCEMENT_SATA_1_MASK_PCIE_3_MASK 0x000F0000
	+#define PBS_TARGET_ID_ENFORCEMENT_SATA_1_MASK_PCIE_3_SHIFT 16
	+/* map transactions to pcie_4 */
	+#define PBS_TARGET_ID_ENFORCEMENT_SATA_1_MASK_PCIE_4_MASK 0x00F00000
	+#define PBS_TARGET_ID_ENFORCEMENT_SATA_1_MASK_PCIE_4_SHIFT 20
	+/* map transactions to pcie_5 */
	+#define PBS_TARGET_ID_ENFORCEMENT_SATA_1_MASK_PCIE_5_MASK 0x0F000000
	+#define PBS_TARGET_ID_ENFORCEMENT_SATA_1_MASK_PCIE_5_SHIFT 24
	+/* map transactions to dram */
	+#define PBS_TARGET_ID_ENFORCEMENT_SATA_1_MASK_DRAM_MASK 0xF0000000
	+#define PBS_TARGET_ID_ENFORCEMENT_SATA_1_MASK_DRAM_SHIFT 28
	+
	+/** crypto_0 register **/
	+/* map transactions according to address decoding */
	+#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_NO_ENFORCEMENT_MASK 0x0000000F
	+#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_NO_ENFORCEMENT_SHIFT 0
	+/* map transactions to pcie_0 */
	+#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_PCIE_0_MASK 0x000000F0
	+#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_PCIE_0_SHIFT 4
	+/* map transactions to pcie_1 */
	+#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_PCIE_1_MASK 0x00000F00
	+#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_PCIE_1_SHIFT 8
	+/* map transactions to pcie_2 */
	+#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_PCIE_2_MASK 0x0000F000
	+#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_PCIE_2_SHIFT 12
	+/* map transactions to pcie_3 */
	+#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_PCIE_3_MASK 0x000F0000
	+#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_PCIE_3_SHIFT 16
	+/* map transactions to pcie_4 */
	+#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_PCIE_4_MASK 0x00F00000
	+#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_PCIE_4_SHIFT 20
	+/* map transactions to pcie_5 */
	+#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_PCIE_5_MASK 0x0F000000
	+#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_PCIE_5_SHIFT 24
	+/* map transactions to dram */
	+#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_DRAM_MASK 0xF0000000
	+#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_DRAM_SHIFT 28
	+
	+/** crypto_0_mask register **/
	+/* map transactions according to address decoding */
	+#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_MASK_NO_ENFORCEMENT_MASK 0x0000000F
	+#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_MASK_NO_ENFORCEMENT_SHIFT 0
	+/* map transactions to pcie_0 */
	+#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_MASK_PCIE_0_MASK 0x000000F0
	+#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_MASK_PCIE_0_SHIFT 4
	+/* map transactions to pcie_1 */
	+#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_MASK_PCIE_1_MASK 0x00000F00
	+#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_MASK_PCIE_1_SHIFT 8
	+/* map transactions to pcie_2 */
	+#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_MASK_PCIE_2_MASK 0x0000F000
	+#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_MASK_PCIE_2_SHIFT 12
	+/* map transactions to pcie_3 */
	+#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_MASK_PCIE_3_MASK 0x000F0000
	+#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_MASK_PCIE_3_SHIFT 16
	+/* map transactions to pcie_4 */
	+#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_MASK_PCIE_4_MASK 0x00F00000
	+#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_MASK_PCIE_4_SHIFT 20
	+/* map transactions to pcie_5 */
	+#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_MASK_PCIE_5_MASK 0x0F000000
	+#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_MASK_PCIE_5_SHIFT 24
	+/* map transactions to dram */
	+#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_MASK_DRAM_MASK 0xF0000000
	+#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_0_MASK_DRAM_SHIFT 28
	+
	+/** crypto_1 register **/
	+/* map transactions according to address decoding */
	+#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_NO_ENFORCEMENT_MASK 0x0000000F
	+#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_NO_ENFORCEMENT_SHIFT 0
	+/* map transactions to pcie_0 */
	+#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_PCIE_0_MASK 0x000000F0
	+#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_PCIE_0_SHIFT 4
	+/* map transactions to pcie_1 */
	+#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_PCIE_1_MASK 0x00000F00
	+#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_PCIE_1_SHIFT 8
	+/* map transactions to pcie_2 */
	+#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_PCIE_2_MASK 0x0000F000
	+#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_PCIE_2_SHIFT 12
	+/* map transactions to pcie_3 */
	+#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_PCIE_3_MASK 0x000F0000
	+#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_PCIE_3_SHIFT 16
	+/* map transactions to pcie_4 */
	+#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_PCIE_4_MASK 0x00F00000
	+#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_PCIE_4_SHIFT 20
	+/* map transactions to pcie_5 */
	+#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_PCIE_5_MASK 0x0F000000
	+#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_PCIE_5_SHIFT 24
	+/* map transactions to dram */
	+#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_DRAM_MASK 0xF0000000
	+#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_DRAM_SHIFT 28
	+
	+/** crypto_1_mask register **/
	+/* map transactions according to address decoding */
	+#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_MASK_NO_ENFORCEMENT_MASK 0x0000000F
	+#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_MASK_NO_ENFORCEMENT_SHIFT 0
	+/* map transactions to pcie_0 */
	+#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_MASK_PCIE_0_MASK 0x000000F0
	+#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_MASK_PCIE_0_SHIFT 4
	+/* map transactions to pcie_1 */
	+#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_MASK_PCIE_1_MASK 0x00000F00
	+#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_MASK_PCIE_1_SHIFT 8
	+/* map transactions to pcie_2 */
	+#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_MASK_PCIE_2_MASK 0x0000F000
	+#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_MASK_PCIE_2_SHIFT 12
	+/* map transactions to pcie_3 */
	+#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_MASK_PCIE_3_MASK 0x000F0000
	+#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_MASK_PCIE_3_SHIFT 16
	+/* map transactions to pcie_4 */
	+#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_MASK_PCIE_4_MASK 0x00F00000
	+#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_MASK_PCIE_4_SHIFT 20
	+/* map transactions to pcie_5 */
	+#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_MASK_PCIE_5_MASK 0x0F000000
	+#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_MASK_PCIE_5_SHIFT 24
	+/* map transactions to dram */
	+#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_MASK_DRAM_MASK 0xF0000000
	+#define PBS_TARGET_ID_ENFORCEMENT_CRYPTO_1_MASK_DRAM_SHIFT 28
	+
	+/** pcie_0 register **/
	+/* map transactions according to address decoding */
	+#define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_NO_ENFORCEMENT_MASK 0x0000000F
	+#define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_NO_ENFORCEMENT_SHIFT 0
	+/* map transactions to pcie_0 */
	+#define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_PCIE_0_MASK 0x000000F0
	+#define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_PCIE_0_SHIFT 4
	+/* map transactions to pcie_1 */
	+#define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_PCIE_1_MASK 0x00000F00
	+#define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_PCIE_1_SHIFT 8
	+/* map transactions to pcie_2 */
	+#define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_PCIE_2_MASK 0x0000F000
	+#define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_PCIE_2_SHIFT 12
	+/* map transactions to pcie_3 */
	+#define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_PCIE_3_MASK 0x000F0000
	+#define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_PCIE_3_SHIFT 16
	+/* map transactions to pcie_4 */
	+#define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_PCIE_4_MASK 0x00F00000
	+#define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_PCIE_4_SHIFT 20
	+/* map transactions to pcie_5 */
	+#define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_PCIE_5_MASK 0x0F000000
	+#define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_PCIE_5_SHIFT 24
	+/* map transactions to dram */
	+#define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_DRAM_MASK 0xF0000000
	+#define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_DRAM_SHIFT 28
	+
	+/** pcie_0_mask register **/
	+/* map transactions according to address decoding */
	+#define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_MASK_NO_ENFORCEMENT_MASK 0x0000000F
	+#define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_MASK_NO_ENFORCEMENT_SHIFT 0
	+/* map transactions to pcie_0 */
	+#define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_MASK_PCIE_0_MASK 0x000000F0
	+#define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_MASK_PCIE_0_SHIFT 4
	+/* map transactions to pcie_1 */
	+#define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_MASK_PCIE_1_MASK 0x00000F00
	+#define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_MASK_PCIE_1_SHIFT 8
	+/* map transactions to pcie_2 */
	+#define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_MASK_PCIE_2_MASK 0x0000F000
	+#define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_MASK_PCIE_2_SHIFT 12
	+/* map transactions to pcie_3 */
	+#define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_MASK_PCIE_3_MASK 0x000F0000
	+#define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_MASK_PCIE_3_SHIFT 16
	+/* map transactions to pcie_4 */
	+#define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_MASK_PCIE_4_MASK 0x00F00000
	+#define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_MASK_PCIE_4_SHIFT 20
	+/* map transactions to pcie_5 */
	+#define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_MASK_PCIE_5_MASK 0x0F000000
	+#define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_MASK_PCIE_5_SHIFT 24
	+/* map transactions to dram */
	+#define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_MASK_DRAM_MASK 0xF0000000
	+#define PBS_TARGET_ID_ENFORCEMENT_PCIE_0_MASK_DRAM_SHIFT 28
	+
	+/** pcie_1 register **/
	+/* map transactions according to address decoding */
	+#define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_NO_ENFORCEMENT_MASK 0x0000000F
	+#define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_NO_ENFORCEMENT_SHIFT 0
	+/* map transactions to pcie_0 */
	+#define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_PCIE_0_MASK 0x000000F0
	+#define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_PCIE_0_SHIFT 4
	+/* map transactions to pcie_1 */
	+#define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_PCIE_1_MASK 0x00000F00
	+#define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_PCIE_1_SHIFT 8
	+/* map transactions to pcie_2 */
	+#define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_PCIE_2_MASK 0x0000F000
	+#define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_PCIE_2_SHIFT 12
	+/* map transactions to pcie_3 */
	+#define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_PCIE_3_MASK 0x000F0000
	+#define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_PCIE_3_SHIFT 16
	+/* map transactions to pcie_4 */
	+#define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_PCIE_4_MASK 0x00F00000
	+#define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_PCIE_4_SHIFT 20
	+/* map transactions to pcie_5 */
	+#define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_PCIE_5_MASK 0x0F000000
	+#define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_PCIE_5_SHIFT 24
	+/* map transactions to dram */
	+#define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_DRAM_MASK 0xF0000000
	+#define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_DRAM_SHIFT 28
	+
	+/** pcie_1_mask register **/
	+/* map transactions according to address decoding */
	+#define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_MASK_NO_ENFORCEMENT_MASK 0x0000000F
	+#define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_MASK_NO_ENFORCEMENT_SHIFT 0
	+/* map transactions to pcie_0 */
	+#define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_MASK_PCIE_0_MASK 0x000000F0
	+#define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_MASK_PCIE_0_SHIFT 4
	+/* map transactions to pcie_1 */
	+#define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_MASK_PCIE_1_MASK 0x00000F00
	+#define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_MASK_PCIE_1_SHIFT 8
	+/* map transactions to pcie_2 */
	+#define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_MASK_PCIE_2_MASK 0x0000F000
	+#define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_MASK_PCIE_2_SHIFT 12
	+/* map transactions to pcie_3 */
	+#define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_MASK_PCIE_3_MASK 0x000F0000
	+#define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_MASK_PCIE_3_SHIFT 16
	+/* map transactions to pcie_4 */
	+#define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_MASK_PCIE_4_MASK 0x00F00000
	+#define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_MASK_PCIE_4_SHIFT 20
	+/* map transactions to pcie_5 */
	+#define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_MASK_PCIE_5_MASK 0x0F000000
	+#define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_MASK_PCIE_5_SHIFT 24
	+/* map transactions to dram */
	+#define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_MASK_DRAM_MASK 0xF0000000
	+#define PBS_TARGET_ID_ENFORCEMENT_PCIE_1_MASK_DRAM_SHIFT 28
	+
	+/** pcie_2 register **/
	+/* map transactions according to address decoding */
	+#define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_NO_ENFORCEMENT_MASK 0x0000000F
	+#define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_NO_ENFORCEMENT_SHIFT 0
	+/* map transactions to pcie_0 */
	+#define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_PCIE_0_MASK 0x000000F0
	+#define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_PCIE_0_SHIFT 4
	+/* map transactions to pcie_1 */
	+#define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_PCIE_1_MASK 0x00000F00
	+#define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_PCIE_1_SHIFT 8
	+/* map transactions to pcie_2 */
	+#define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_PCIE_2_MASK 0x0000F000
	+#define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_PCIE_2_SHIFT 12
	+/* map transactions to pcie_3 */
	+#define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_PCIE_3_MASK 0x000F0000
	+#define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_PCIE_3_SHIFT 16
	+/* map transactions to pcie_4 */
	+#define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_PCIE_4_MASK 0x00F00000
	+#define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_PCIE_4_SHIFT 20
	+/* map transactions to pcie_5 */
	+#define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_PCIE_5_MASK 0x0F000000
	+#define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_PCIE_5_SHIFT 24
	+/* map transactions to dram */
	+#define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_DRAM_MASK 0xF0000000
	+#define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_DRAM_SHIFT 28
	+
	+/** pcie_2_mask register **/
	+/* map transactions according to address decoding */
	+#define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_MASK_NO_ENFORCEMENT_MASK 0x0000000F
	+#define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_MASK_NO_ENFORCEMENT_SHIFT 0
	+/* map transactions to pcie_0 */
	+#define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_MASK_PCIE_0_MASK 0x000000F0
	+#define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_MASK_PCIE_0_SHIFT 4
	+/* map transactions to pcie_1 */
	+#define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_MASK_PCIE_1_MASK 0x00000F00
	+#define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_MASK_PCIE_1_SHIFT 8
	+/* map transactions to pcie_2 */
	+#define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_MASK_PCIE_2_MASK 0x0000F000
	+#define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_MASK_PCIE_2_SHIFT 12
	+/* map transactions to pcie_3 */
	+#define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_MASK_PCIE_3_MASK 0x000F0000
	+#define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_MASK_PCIE_3_SHIFT 16
	+/* map transactions to pcie_4 */
	+#define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_MASK_PCIE_4_MASK 0x00F00000
	+#define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_MASK_PCIE_4_SHIFT 20
	+/* map transactions to pcie_5 */
	+#define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_MASK_PCIE_5_MASK 0x0F000000
	+#define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_MASK_PCIE_5_SHIFT 24
	+/* map transactions to dram */
	+#define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_MASK_DRAM_MASK 0xF0000000
	+#define PBS_TARGET_ID_ENFORCEMENT_PCIE_2_MASK_DRAM_SHIFT 28
	+
	+/** pcie_3 register **/
	+/* map transactions according to address decoding */
	+#define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_NO_ENFORCEMENT_MASK 0x0000000F
	+#define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_NO_ENFORCEMENT_SHIFT 0
	+/* map transactions to pcie_0 */
	+#define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_PCIE_0_MASK 0x000000F0
	+#define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_PCIE_0_SHIFT 4
	+/* map transactions to pcie_1 */
	+#define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_PCIE_1_MASK 0x00000F00
	+#define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_PCIE_1_SHIFT 8
	+/* map transactions to pcie_2 */
	+#define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_PCIE_2_MASK 0x0000F000
	+#define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_PCIE_2_SHIFT 12
	+/* map transactions to pcie_3 */
	+#define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_PCIE_3_MASK 0x000F0000
	+#define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_PCIE_3_SHIFT 16
	+/* map transactions to pcie_4 */
	+#define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_PCIE_4_MASK 0x00F00000
	+#define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_PCIE_4_SHIFT 20
	+/* map transactions to pcie_5 */
	+#define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_PCIE_5_MASK 0x0F000000
	+#define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_PCIE_5_SHIFT 24
	+/* map transactions to dram */
	+#define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_DRAM_MASK 0xF0000000
	+#define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_DRAM_SHIFT 28
	+
	+/** pcie_3_mask register **/
	+/* map transactions according to address decoding */
	+#define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_MASK_NO_ENFORCEMENT_MASK 0x0000000F
	+#define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_MASK_NO_ENFORCEMENT_SHIFT 0
	+/* map transactions to pcie_0 */
	+#define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_MASK_PCIE_0_MASK 0x000000F0
	+#define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_MASK_PCIE_0_SHIFT 4
	+/* map transactions to pcie_1 */
	+#define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_MASK_PCIE_1_MASK 0x00000F00
	+#define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_MASK_PCIE_1_SHIFT 8
	+/* map transactions to pcie_2 */
	+#define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_MASK_PCIE_2_MASK 0x0000F000
	+#define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_MASK_PCIE_2_SHIFT 12
	+/* map transactions to pcie_3 */
	+#define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_MASK_PCIE_3_MASK 0x000F0000
	+#define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_MASK_PCIE_3_SHIFT 16
	+/* map transactions to pcie_4 */
	+#define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_MASK_PCIE_4_MASK 0x00F00000
	+#define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_MASK_PCIE_4_SHIFT 20
	+/* map transactions to pcie_5 */
	+#define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_MASK_PCIE_5_MASK 0x0F000000
	+#define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_MASK_PCIE_5_SHIFT 24
	+/* map transactions to dram */
	+#define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_MASK_DRAM_MASK 0xF0000000
	+#define PBS_TARGET_ID_ENFORCEMENT_PCIE_3_MASK_DRAM_SHIFT 28
	+
	+/** latch register **/
	+/*
	+ * Software clears this bit before any bar update, and set it after all bars
	+ * updated.
	+ */
	+#define PBS_TARGET_ID_ENFORCEMENT_LATCH_ENABLE (1 << 0)
	+
	+#ifdef __cplusplus
	+}
	+#endif
	+
	+#endif /* __AL_HAL_PBS_REGS_H__ */
	+
	+/** @} end of ... group */
	+
	+
	Index: sys/arm/annapurna/alpine/hal/al_hal_pcie.h
	===================================================================
	--- /dev/null
	+++ sys/arm/annapurna/alpine/hal/al_hal_pcie.h
	@@ -0,0 +1,1157 @@
	+/*-
	+********************************************************************************
	+Copyright (C) 2015 Annapurna Labs Ltd.
	+
	+This file may be licensed under the terms of the Annapurna Labs Commercial
	+License Agreement.
	+
	+Alternatively, this file can be distributed under the terms of the GNU General
	+Public License V2 as published by the Free Software Foundation and can be
	+found at http://www.gnu.org/licenses/gpl-2.0.html
	+
	+Alternatively, redistribution and use in source and binary forms, with or
	+without modification, are permitted provided that the following conditions are
	+met:
	+
	+ * Redistributions of source code must retain the above copyright notice,
	+this list of conditions and the following disclaimer.
	+
	+ * Redistributions in binary form must reproduce the above copyright
	+notice, this list of conditions and the following disclaimer in
	+the documentation and/or other materials provided with the
	+distribution.
	+
	+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
	+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
	+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
	+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
	+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
	+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
	+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
	+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
	+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
	+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	+
	+*******************************************************************************/
	+
	+/**
	+ * @defgroup grouppcie PCI Express Controller
	+ * @{
	+ * @section overview Overview
	+ * This header file provide API for the HAL driver of the pcie port, the driver
	+ * provides the following functionalities:
	+ * - Port initialization
	+ * - Link operation
	+ * - Interrupts transactions generation (Endpoint mode).
	+ * - Configuration Access management functions
	+ * - Internal Translation Unit programming
	+ *
	+ * This API does not provide the following:
	+ * - PCIe transactions generation and reception (except interrupts as mentioned
	+ * above) as this functionality is done by the port without need for sw
	+ * intervention.
	+ * - Configuration Access: those transactions are generated automatically by
	+ * the port (ECAM or ATU mode) when the CPU issues memory transaction
	+ * through the fabric toward the PCIe port. This API provides management
	+ * function for controlling the Configuration Access type and bus destination
	+ * - Interrupt Handling.
	+ * - Message Generation: common used messages are automatically generated, also,
	+ * the ATU generic mechanism for generating various kind of messages.
	+ * - PCIe Port Management: both link and port power management features can be
	+ * managed using the PCI/PCIe standard power management and PCIe capabilities
	+ * registers.
	+ * - PCIe link and protocol error handling: the feature can be managed using
	+ * the Advanced Error Handling PCIe capability registers.
	+ *
	+ * @section flows Software Flows
	+ * @subsection init Initialization
	+ * - allocation and set zeros al_pcie_port and al_pcie_pf structures handles
	+ * - call al_pcie_port_handle_init() with pointer to the allocated
	+ * al_pcie_port handle, address of the port internal registers space, and
	+ * port id.
	+ * - call al_pcie_pf_handle_init() with pointer to the al_pcie_port handle
	+ * and pf_number.
	+ * - set the port mode, End-Point or Root-Compex (default).
	+ * - set number of lanes connected to the controller.
	+ * - enable the controller using the al_pcie_port_enable(). note that this
	+ * function expect the virtual address of the PBS Functional Registers.
	+ * - wait for 2000 South-bridge cycles.
	+ * - prepare al_pcie_port_config_params and al_pcie_pf_config_params
	+ * structures depending on chip, board and system configuration.
	+ * for example, when using the port as root complex, the operating_mode
	+ * field should be set to AL_PCIE_OPERATING_MODE_RC. In this example we
	+ * prepare the following configuration:
	+ * For port configuration
	+ * - Root Complex mode
	+ * - Set the Max Link Speed to Gen2
	+ * - Set the max lanes width to 2 (x2)
	+ * - Disable reversal mode
	+ * - Enable Snoops to support I/O Hardware cache coherency
	+ * - Enable pcie core RAM parity
	+ * - Enable pcie core AXI parity
	+ * - Keep transaction layer default credits
	+ * For pf configuration
	+ * - No EP parameters
	+ * - No SR-IOV parameters
	+ * so the structures we prepare:
	+ * @code
	+ * - struct al_pcie_link_params link_params = {
	+ * AL_PCIE_LINK_SPEED_GEN2,
	+ * AL_FALSE, // disable reversal mode
	+ * AL_PCIE_MPS_DEFAULT};
	+ *
	+ * - struct al_pcie_port_config_params config_params = {
	+ * &link_params,
	+ * AL_TRUE, // enable Snoop for inbound memory transactions
	+ * AL_TRUE, // enable pcie port RAM parity
	+ * AL_TRUE, // enable pcie port AXI parity
	+ * NULL, // use default latency/replay timers
	+ * NULL, // use default gen2 pipe params
	+ * NULL, // gen3_params not needed when max speed set to Gen2
	+ * NULL, // don't change TL credits
	+ * NULL, // end point params not needed
	+ * AL_FALSE, //no fast link
	+ * AL_FALSE}; //return 0xFFFFFFFF for read transactions with
	+ * //pci target error
	+ * @endcode
	+ * - now call al_pcie_port_config() with pcie_port and port_config_params
	+ * @subsection link-init Link Initialization
	+ * - once the port configured, we can start PCIe link:
	+ * - call al_pcie_link_start()
	+ * - call al_pcie_link_up_wait()
	+ * - allocate al_pcie_link_status struct and call al_pcie_link_status() and
	+ * check the link is established.
	+ *
	+ * @subsection cap Configuration Access Preparation
	+ * - Once the link is established, we can prepare the port for pci
	+ * configuration access, this stage requires system knowledge about the PCI
	+ * buses enumeration. For example, if 5 buses were discovered on previously
	+ * scanned root complex port, then we should start enumeration from bus 5 (PCI
	+ * secondary bus), the sub-ordinary bus will be temporarily set to maximum
	+ * value (255) until the scan process under this bus is finished, then it will
	+ * updated to the maximum bus value found. So we use the following sequence:
	+ * - call al_pcie_secondary_bus_set() with sec-bus = 5
	+ * - call al_pcie_subordinary_bus_set() with sub-bus = 255
	+ *
	+ * @subsection cfg Configuration (Cfg) Access Generation
	+ * - we assume using ECAM method, in this method, the software issues pcie Cfg
	+ * access by accessing the ECAM memory space of the pcie port. For example, to
	+ * issue 4 byte Cfg Read from bus B, Device D, Function F and register R, the
	+ * software issues 4 byte read access to the following physical address
	+ * ECAM base address of the port + (B << 20) + (D << 15) + (F << 12) + R.
	+ * But, as the default size of the ECAM address space is less than
	+ * needed full range (256MB), we modify the target_bus value prior to Cfg
	+ * access in order make the port generate Cfg access with bus value set to the
	+ * value of the target_bus rather than bits 27:20 of the physical address.
	+ * - call al_pcie_target_bus_set() with target_bus set to the required bus of
	+ * the next Cfg access to be issued, mask_target_bus will be set to 0xff.
	+ * no need to call that function if the next Cfg access bus equals to the last
	+ * value set to target_bus.
	+ *
	+ * @file al_hal_pcie.h
	+ * @brief HAL Driver Header for the Annapurna Labs PCI Express port.
	+ */
	+
	+#ifndef _AL_HAL_PCIE_H_
	+#define _AL_HAL_PCIE_H_
	+
	+#include "al_hal_common.h"
	+#include "al_hal_pcie_regs.h"
	+
	+/******************************************************************************/
	+/******************************* Constants ********************************/
	+/******************************************************************************/
	+
	+/** Inbound header credits sum - rev 0/1/2 */
	+#define AL_PCIE_REV_1_2_IB_HCRD_SUM 97
	+/** Inbound header credits sum - rev 3 */
	+#define AL_PCIE_REV3_IB_HCRD_SUM 259
	+
	+/** Number of extended registers */
	+#define AL_PCIE_EX_REGS_NUM 40
	+
	+/*******************************************************************************
	+ * PCIe AER uncorrectable error bits
	+ * To be used with the following functions:
	+ * - al_pcie_aer_config
	+ * - al_pcie_aer_uncorr_get_and_clear
	+ ******************************************************************************/
	+/** Data Link Protocol Error */
	+#define AL_PCIE_AER_UNCORR_DLP_ERR AL_BIT(4)
	+/** Poisoned TLP */
	+#define AL_PCIE_AER_UNCORR_POISIONED_TLP AL_BIT(12)
	+/** Flow Control Protocol Error */
	+#define AL_PCIE_AER_UNCORR_FLOW_CTRL_ERR AL_BIT(13)
	+/** Completion Timeout */
	+#define AL_PCIE_AER_UNCORR_COMPL_TO AL_BIT(14)
	+/** Completer Abort */
	+#define AL_PCIE_AER_UNCORR_COMPL_ABT AL_BIT(15)
	+/** Unexpected Completion */
	+#define AL_PCIE_AER_UNCORR_UNEXPCTED_COMPL AL_BIT(16)
	+/** Receiver Overflow */
	+#define AL_PCIE_AER_UNCORR_RCV_OVRFLW AL_BIT(17)
	+/** Malformed TLP */
	+#define AL_PCIE_AER_UNCORR_MLFRM_TLP AL_BIT(18)
	+/** ECRC Error */
	+#define AL_PCIE_AER_UNCORR_ECRC_ERR AL_BIT(19)
	+/** Unsupported Request Error */
	+#define AL_PCIE_AER_UNCORR_UNSUPRT_REQ_ERR AL_BIT(20)
	+/** Uncorrectable Internal Error */
	+#define AL_PCIE_AER_UNCORR_INT_ERR AL_BIT(22)
	+/** AtomicOp Egress Blocked */
	+#define AL_PCIE_AER_UNCORR_ATOMIC_EGRESS_BLK AL_BIT(24)
	+
	+/*******************************************************************************
	+ * PCIe AER correctable error bits
	+ * To be used with the following functions:
	+ * - al_pcie_aer_config
	+ * - al_pcie_aer_corr_get_and_clear
	+ ******************************************************************************/
	+/** Receiver Error */
	+#define AL_PCIE_AER_CORR_RCV_ERR AL_BIT(0)
	+/** Bad TLP */
	+#define AL_PCIE_AER_CORR_BAD_TLP AL_BIT(6)
	+/** Bad DLLP */
	+#define AL_PCIE_AER_CORR_BAD_DLLP AL_BIT(7)
	+/** REPLAY_NUM Rollover */
	+#define AL_PCIE_AER_CORR_RPLY_NUM_ROLL_OVR AL_BIT(8)
	+/** Replay Timer Timeout */
	+#define AL_PCIE_AER_CORR_RPLY_TMR_TO AL_BIT(12)
	+/** Advisory Non-Fatal Error */
	+#define AL_PCIE_AER_CORR_ADVISORY_NON_FTL_ERR AL_BIT(13)
	+/** Corrected Internal Error */
	+#define AL_PCIE_AER_CORR_INT_ERR AL_BIT(14)
	+
	+/** The AER erroneous TLP header length [num DWORDs] */
	+#define AL_PCIE_AER_ERR_TLP_HDR_NUM_DWORDS 4
	+
	+/******************************************************************************/
	+/*********************** Data Structures and Types ************************/
	+/******************************************************************************/
	+
	+/**
	+ * al_pcie_ib_hcrd_config: data structure internally used in order to config
	+ * inbound posted/non-posted parameters.
	+ * Note: it's required to have this structure in pcie_port handle since it has
	+ * a state (required/not-required) which is determined by outbound
	+ * outstanding configuration
	+ */
	+struct al_pcie_ib_hcrd_config {
	+ /* Internally used - see 'al_pcie_ib_hcrd_os_ob_reads_config' */
	+ unsigned int nof_np_hdr;
	+
	+ /* Internally used - see 'al_pcie_ib_hcrd_os_ob_reads_config' */
	+ unsigned int nof_p_hdr;
	+};
	+
	+/* The Max Payload Size. Measured in bytes.
	+ * DEFAULT: do not change the current MPS
	+ */
	+enum al_pcie_max_payload_size {
	+ AL_PCIE_MPS_DEFAULT,
	+ AL_PCIE_MPS_128 = 0,
	+ AL_PCIE_MPS_256 = 1,
	+ AL_PCIE_MPS_512 = 2,
	+ AL_PCIE_MPS_1024 = 3,
	+ AL_PCIE_MPS_2048 = 4,
	+ AL_PCIE_MPS_4096 = 5,
	+};
	+
	+/**
	+ * al_pcie_port: data structure used by the HAL to handle a specific pcie port.
	+ * this structure is allocated and set to zeros by the upper layer, then it is
	+ * initialized by the al_pcie_port_handle_init() that should be called before any
	+ * other function of this API. later, this handle passed to the API functions.
	+ */
	+struct al_pcie_port {
	+ void __iomem *pcie_reg_base;
	+ struct al_pcie_regs regs_ptrs;
	+ struct al_pcie_regs *regs;
	+ uint32_t *ex_regs_ptrs[AL_PCIE_EX_REGS_NUM];
	+ void *ex_regs;
	+ void __iomem *pbs_regs;
	+
	+ /* Revision ID */
	+ uint8_t rev_id;
	+ unsigned int port_id;
	+ uint8_t max_lanes;
	+ uint8_t max_num_of_pfs;
	+
	+ /* Internally used */
	+ struct al_pcie_ib_hcrd_config ib_hcrd_config;
	+};
	+
	+/**
	+ * al_pcie_pf: the pf handle, a data structure used to handle PF specific
	+ * functionality. Initialized using "al_pcie_pf_handle_init()"
	+ */
	+struct al_pcie_pf {
	+ unsigned int pf_num;
	+ struct al_pcie_port *pcie_port;
	+};
	+
	+/** Operating mode (endpoint, root complex) */
	+enum al_pcie_operating_mode {
	+ AL_PCIE_OPERATING_MODE_EP,
	+ AL_PCIE_OPERATING_MODE_RC,
	+ AL_PCIE_OPERATING_MODE_UNKNOWN
	+};
	+
	+/* The maximum link speed, measured GT/s (Giga transfer / second)
	+ * DEFAULT: do not change the current speed
	+ * GEN1: 2.5 GT/s
	+ * GEN2: 5 GT/s
	+ * GEN3: 8GT/s
	+ *
	+ * Note: The values of this enumerator are important for proper behavior
	+ */
	+enum al_pcie_link_speed {
	+ AL_PCIE_LINK_SPEED_DEFAULT,
	+ AL_PCIE_LINK_SPEED_GEN1 = 1,
	+ AL_PCIE_LINK_SPEED_GEN2 = 2,
	+ AL_PCIE_LINK_SPEED_GEN3 = 3
	+};
	+
	+/** PCIe capabilities that supported by a specific port */
	+struct al_pcie_max_capability {
	+ al_bool end_point_mode_supported;
	+ al_bool root_complex_mode_supported;
	+ enum al_pcie_link_speed max_speed;
	+ uint8_t max_lanes;
	+ al_bool reversal_supported;
	+ uint8_t atu_regions_num;
	+ uint32_t atu_min_size;
	+};
	+
	+/** PCIe link related parameters */
	+struct al_pcie_link_params {
	+ enum al_pcie_link_speed max_speed;
	+ al_bool enable_reversal;
	+ enum al_pcie_max_payload_size max_payload_size;
	+
	+};
	+
	+/** PCIe gen2 link parameters */
	+struct al_pcie_gen2_params {
	+ al_bool tx_swing_low; /* set tx swing low when true, and tx swing full when false */
	+ al_bool tx_compliance_receive_enable;
	+ al_bool set_deemphasis;
	+};
	+
	+/** PCIe gen 3 standard per lane equalization parameters */
	+struct al_pcie_gen3_lane_eq_params {
	+ uint8_t downstream_port_transmitter_preset;
	+ uint8_t downstream_port_receiver_preset_hint;
	+ uint8_t upstream_port_transmitter_preset;
	+ uint8_t upstream_port_receiver_preset_hint;
	+};
	+
	+/** PCIe gen 3 equalization parameters */
	+struct al_pcie_gen3_params {
	+ al_bool perform_eq;
	+ al_bool interrupt_enable_on_link_eq_request;
	+ struct al_pcie_gen3_lane_eq_params eq_params; / array of lanes params */
	+ int eq_params_elements; /* number of elements in the eq_params array */
	+
	+ al_bool eq_disable; /* disables the equalization feature */
	+ al_bool eq_phase2_3_disable; /* Equalization Phase 2 and Phase 3 */
	+ /* Disable (RC mode only) */
	+ uint8_t local_lf; /* Full Swing (FS) Value for Gen3 Transmit Equalization */
	+ /* Value Range: 12 through 63 (decimal).*/
	+
	+ uint8_t local_fs; /* Low Frequency (LF) Value for Gen3 Transmit Equalization */
	+};
	+
	+/** Transport Layer credits parameters */
	+struct al_pcie_tl_credits_params {
	+};
	+
	+/** Various configuration features */
	+struct al_pcie_features {
	+ /**
	+ * Enable MSI fix from the SATA to the PCIe EP
	+ * Only valid for port 0, when enabled as EP
	+ */
	+ al_bool sata_ep_msi_fix;
	+};
	+
	+/**
	+ * Inbound posted/non-posted header credits and outstanding outbound reads
	+ * completion header configuration
	+ *
	+ * Constraints:
	+ * - nof_cpl_hdr + nof_np_hdr + nof_p_hdr ==
	+ * AL_PCIE_REV_1_2_IB_HCRD_SUM/AL_PCIE_REV3_IB_HCRD_SUM
	+ * - nof_cpl_hdr > 0
	+ * - nof_p_hdr > 0
	+ * - nof_np_hdr > 0
	+ */
	+struct al_pcie_ib_hcrd_os_ob_reads_config {
	+ /** Max number of outstanding outbound reads */
	+ uint8_t nof_outstanding_ob_reads;
	+
	+ /**
	+ * This value set the possible outstanding headers CMPLs , the core
	+ * can get (the core always advertise infinite credits for CMPLs).
	+ */
	+ unsigned int nof_cpl_hdr;
	+
	+ /**
	+ * This value set the possible outstanding headers reads (non-posted
	+ * transactions), the core can get (it set the value in the init FC
	+ * process).
	+ */
	+ unsigned int nof_np_hdr;
	+
	+ /**
	+ * This value set the possible outstanding headers writes (posted
	+ * transactions), the core can get (it set the value in the init FC
	+ * process).
	+ */
	+ unsigned int nof_p_hdr;
	+};
	+
	+/** PCIe Ack/Nak Latency and Replay timers */
	+struct al_pcie_latency_replay_timers {
	+ uint16_t round_trip_lat_limit;
	+ uint16_t replay_timer_limit;
	+};
	+
	+/* SRIS KP counter values */
	+struct al_pcie_sris_params {
	+ /** set to AL_TRUE to use defaults and ignore the other parameters */
	+ al_bool use_defaults;
	+ uint16_t kp_counter_gen3; /* only for Gen3 */
	+ uint16_t kp_counter_gen21;
	+};
	+
	+/** Relaxed ordering params */
	+struct al_pcie_relaxed_ordering_params {
	+ al_bool enable_tx_relaxed_ordering;
	+ al_bool enable_rx_relaxed_ordering;
	+};
	+
	+/** PCIe port configuration parameters
	+ * This structure includes the parameters that the HAL should apply to the port
	+ * (by al_pcie_port_config()).
	+ * The fields that are pointers (e.g. link_params) can be set to NULL, in that
	+ * case, the al_pcie_port_config() will keep the current HW settings.
	+ */
	+struct al_pcie_port_config_params {
	+ struct al_pcie_link_params *link_params;
	+ al_bool enable_axi_snoop;
	+ al_bool enable_ram_parity_int;
	+ al_bool enable_axi_parity_int;
	+ struct al_pcie_latency_replay_timers *lat_rply_timers;
	+ struct al_pcie_gen2_params *gen2_params;
	+ struct al_pcie_gen3_params *gen3_params;
	+ struct al_pcie_tl_credits_params *tl_credits;
	+ struct al_pcie_features *features;
	+ /* Sets all internal timers to Fast Mode for speeding up simulation.*/
	+ al_bool fast_link_mode;
	+ /*
	+ * when true, the PCI unit will return Slave Error/Decoding Error to the master unit in case
	+ * of error. when false, the value 0xFFFFFFFF will be returned without error indication.
	+ */
	+ al_bool enable_axi_slave_err_resp;
	+ struct al_pcie_sris_params *sris_params;
	+ struct al_pcie_relaxed_ordering_params *relaxed_ordering_params;
	+};
	+
	+/** BAR register configuration parameters (Endpoint Mode only) */
	+struct al_pcie_ep_bar_params {
	+ al_bool enable;
	+ al_bool memory_space; /*< memory or io /
	+ al_bool memory_64_bit; /*< is memory space is 64 bit /
	+ al_bool memory_is_prefetchable;
	+ uint64_t size; /* the bar size in bytes */
	+};
	+
	+/** PF config params (EP mode only) */
	+struct al_pcie_pf_config_params {
	+ al_bool cap_d1_d3hot_dis;
	+ al_bool cap_flr_dis;
	+ al_bool cap_aspm_dis;
	+ al_bool bar_params_valid;
	+ struct al_pcie_ep_bar_params bar_params[6];
	+ struct al_pcie_ep_bar_params exp_bar_params;/* expansion ROM BAR*/
	+};
	+
	+/** PCIe link status */
	+struct al_pcie_link_status {
	+ al_bool link_up;
	+ enum al_pcie_link_speed speed;
	+ uint8_t lanes;
	+ uint8_t ltssm_state;
	+};
	+
	+/** PCIe lane status */
	+struct al_pcie_lane_status {
	+ al_bool is_reset;
	+ enum al_pcie_link_speed requested_speed;
	+};
	+
	+/** PCIe MSIX capability configuration parameters */
	+struct al_pcie_msix_params {
	+ uint16_t table_size;
	+ uint16_t table_offset;
	+ uint8_t table_bar;
	+ uint16_t pba_offset;
	+ uint16_t pba_bar;
	+};
	+
	+/** PCIE AER capability parameters */
	+struct al_pcie_aer_params {
	+ /** ECRC Generation Enable */
	+ al_bool ecrc_gen_en;
	+ /** ECRC Check Enable */
	+ al_bool ecrc_chk_en;
	+
	+ /**
	+ * Enabled reporting of correctable errors (bit mask)
	+ * See 'AL_PCIE_AER_CORR_*' for details
	+ * 0 - no reporting at all
	+ */
	+ unsigned int enabled_corr_err;
	+ /**
	+ * Enabled reporting of non-fatal uncorrectable errors (bit mask)
	+ * See 'AL_PCIE_AER_UNCORR_*' for details
	+ * 0 - no reporting at all
	+ */
	+ unsigned int enabled_uncorr_non_fatal_err;
	+ /**
	+ * Enabled reporting of fatal uncorrectable errors (bit mask)
	+ * See 'AL_PCIE_AER_UNCORR_*' for details
	+ * 0 - no reporting at all
	+ */
	+ unsigned int enabled_uncorr_fatal_err;
	+};
	+
	+/******************************************************************************/
	+/******************************** PCIe API ********************************/
	+/******************************************************************************/
	+
	+/************************* PCIe Initialization API ************************/
	+
	+/**
	+ * Initializes a PCIe port handle structure.
	+ *
	+ * @param pcie_port an allocated, non-initialized instance.
	+ * @param pcie_reg_base the virtual base address of the port internal
	+ * registers
	+ * @param pbs_reg_base the virtual base address of the pbs functional
	+ * registers
	+ * @param port_id the port id (used mainly for debug messages)
	+ *
	+ * @return 0 if no error found.
	+ */
	+int al_pcie_port_handle_init(struct al_pcie_port *pcie_port,
	+ void __iomem *pcie_reg_base,
	+ void __iomem *pbs_reg_base,
	+ unsigned int port_id);
	+
	+/**
	+ * Initializes a PCIe pf handle structure
	+ * @param pcie_pf an allocated, non-initialized instance of pf handle
	+ * @param pcie_port pcie port handle
	+ * @param pf_num physical function number
	+ * @return 0 if no error found
	+ */
	+int al_pcie_pf_handle_init(
	+ struct al_pcie_pf *pcie_pf,
	+ struct al_pcie_port *pcie_port,
	+ unsigned int pf_num);
	+
	+/************************ Pre PCIe Port Enable API ************************/
	+
	+/**
	+ * @brief set current pcie operating mode (root complex or endpoint)
	+ * This function can be called only before enabling the controller using
	+ * al_pcie_port_enable().
	+ *
	+ * @param pcie_port pcie port handle
	+ * @param mode pcie operating mode
	+ *
	+ * @return 0 if no error found.
	+ */
	+int al_pcie_port_operating_mode_config(struct al_pcie_port *pcie_port,
	+ enum al_pcie_operating_mode mode);
	+
	+/**
	+ * Configure number of lanes connected to this port.
	+ * This function can be called only before enabling the controller using al_pcie_port_enable().
	+ *
	+ * @param pcie_port pcie port handle
	+ * @param lanes number of lanes
	+ * Note: this function must be called before any al_pcie_port_config() calls
	+ *
	+ * @return 0 if no error found.
	+ */
	+int al_pcie_port_max_lanes_set(struct al_pcie_port *pcie_port, uint8_t lanes);
	+
	+/**
	+ * Set maximum physical function numbers
	+ * @param pcie_port pcie port handle
	+ * @param max_num_of_pfs number of physical functions
	+ * Note: this function must be called before any al_pcie_pf_config() calls
	+ */
	+int al_pcie_port_max_num_of_pfs_set(
	+ struct al_pcie_port *pcie_port,
	+ uint8_t max_num_of_pfs);
	+
	+/**
	+ * @brief Inbound posted/non-posted header credits and outstanding outbound
	+ * reads completion header configuration
	+ *
	+ * @param pcie_port pcie port handle
	+ * @param ib_hcrd_os_ob_reads_config
	+ * Inbound header credits and outstanding outbound reads
	+ * configuration
	+ */
	+int al_pcie_port_ib_hcrd_os_ob_reads_config(
	+ struct al_pcie_port *pcie_port,
	+ struct al_pcie_ib_hcrd_os_ob_reads_config *ib_hcrd_os_ob_reads_config);
	+
	+/** return PCIe operating mode
	+ * @param pcie_port pcie port handle
	+ * @return operating mode
	+ */
	+enum al_pcie_operating_mode al_pcie_operating_mode_get(
	+ struct al_pcie_port *pcie_port);
	+
	+/************************** PCIe Port Enable API **************************/
	+
	+/** Enable PCIe unit (deassert reset)
	+ *
	+ * @param pcie_port pcie port handle
	+ *
	+ * @return 0 if no error found.
	+ */
	+int al_pcie_port_enable(struct al_pcie_port *pcie_port);
	+
	+/** Disable PCIe unit (assert reset)
	+ *
	+ * @param pcie_port pcie port handle
	+ */
	+void al_pcie_port_disable(struct al_pcie_port *pcie_port);
	+
	+/**
	+ * Port memory shutdown/up
	+ * Caution: This function can be called only when the controller is disabled
	+ *
	+ * @param pcie_port pcie port handle
	+ * @param enable memory shutdown enable or disable
	+ *
	+ */
	+int al_pcie_port_memory_shutdown_set(
	+ struct al_pcie_port *pcie_port,
	+ al_bool enable);
	+
	+/**
	+ * Check if port enabled or not
	+ * @param pcie_port pcie port handle
	+ * @return AL_TRUE of port enabled and AL_FALSE otherwise
	+ */
	+al_bool al_pcie_port_is_enabled(struct al_pcie_port *pcie_port);
	+
	+/************************* PCIe Configuration API *************************/
	+
	+/**
	+ * @brief configure pcie port (mode, link params, etc..)
	+ * this function must be called before initializing the link
	+ *
	+ * @param pcie_port pcie port handle
	+ * @param params configuration structure.
	+ *
	+ * @return 0 if no error found
	+ */
	+int al_pcie_port_config(struct al_pcie_port *pcie_port,
	+ const struct al_pcie_port_config_params *params);
	+
	+/**
	+ * @brief Configure a specific PF (EP params, sriov params, ...)
	+ * this function must be called before any datapath transactions
	+ *
	+ * @param pcie_pf pcie pf handle
	+ * @param params configuration structure.
	+ *
	+ * @return 0 if no error found
	+ */
	+int al_pcie_pf_config(
	+ struct al_pcie_pf *pcie_pf,
	+ const struct al_pcie_pf_config_params *params);
	+
	+/************************ PCIe Link Operations API ************************/
	+
	+/**
	+ * @brief start pcie link
	+ *
	+ * @param pcie_port pcie port handle
	+ *
	+ * @return 0 if no error found
	+ */
	+int al_pcie_link_start(struct al_pcie_port *pcie_port);
	+
	+/**
	+ * @brief stop pcie link
	+ *
	+ * @param pcie_port pcie port handle
	+ *
	+ * @return 0 if no error found
	+ */
	+int al_pcie_link_stop(struct al_pcie_port *pcie_port);
	+
	+/**
	+ * @brief trigger link-disable
	+ *
	+ * @param pcie_port pcie port handle
	+ * @param disable AL_TRUE to disable the link and AL_FALSE to enable it
	+ *
	+ * Note: this functionality differs from "al_pcie_link_stop" as it's a spec
	+ * functionality where both sides of the PCIe agrees to disable the link
	+ * @return 0 if no error found
	+ */
	+int al_pcie_link_disable(struct al_pcie_port *pcie_port, al_bool disable);
	+
	+/**
	+ * @brief wait for link up indication
	+ * this function waits for link up indication, it polls LTSSM state until link is ready
	+ *
	+ * @param pcie_port pcie port handle
	+ * @param timeout_ms maximum timeout in milli-seconds to wait for link up
	+ *
	+ * @return 0 if link up indication detected
	+ * -ETIME if not.
	+ */
	+int al_pcie_link_up_wait(struct al_pcie_port *pcie_port, uint32_t timeout_ms);
	+
	+/**
	+ * @brief get link status
	+ *
	+ * @param pcie_port pcie port handle
	+ * @param status structure for link status
	+ *
	+ * @return 0 if no error found
	+ */
	+int al_pcie_link_status(struct al_pcie_port pcie_port, struct al_pcie_link_status status);
	+
	+/**
	+ * @brief get lane status
	+ *
	+ * @param pcie_port
	+ * pcie port handle
	+ * @param lane
	+ * PCIe lane
	+ * @param status
	+ * Pointer to returned structure for lane status
	+ *
	+ */
	+void al_pcie_lane_status_get(
	+ struct al_pcie_port *pcie_port,
	+ unsigned int lane,
	+ struct al_pcie_lane_status *status);
	+
	+/**
	+ * @brief trigger hot reset
	+ *
	+ * @param pcie_port pcie port handle
	+ * @param enable AL_TRUE to enable hot-reset and AL_FALSE to disable it
	+ *
	+ * @return 0 if no error found
	+ */
	+int al_pcie_link_hot_reset(struct al_pcie_port *pcie_port, al_bool enable);
	+
	+/**
	+ * @brief trigger link-retain
	+ * this function initiates Link retraining by directing the Physical Layer LTSSM
	+ * to the Recovery state. If the LTSSM is already in Recovery or Configuration,
	+ * re-entering Recovery is permitted but not required.
	+
	+ * @param pcie_port pcie port handle
	+ *
	+ * Note: there's no need to disable initiating link-retrain
	+ * @return 0 if no error found
	+ */
	+int al_pcie_link_retrain(struct al_pcie_port *pcie_port);
	+
	+/**
	+ * @brief change port speed
	+ * this function changes the port speed, it doesn't wait for link re-establishment
	+ *
	+ * @param pcie_port pcie port handle
	+ * @param new_speed the new speed gen to set
	+ *
	+ * @return 0 if no error found
	+ */
	+int al_pcie_link_change_speed(struct al_pcie_port *pcie_port, enum al_pcie_link_speed new_speed);
	+
	+/* TODO: check if this function needed */
	+int al_pcie_link_change_width(struct al_pcie_port *pcie_port, uint8_t width);
	+
	+/************************** Post Link Start API ***************************/
	+
	+/************************ Snoop Configuration API *************************/
	+
	+/**
	+ * @brief configure pcie port axi snoop
	+ *
	+ * @param pcie_port pcie port handle
	+ * @param enable_axi_snoop enable snoop.
	+ *
	+ * @return 0 if no error found
	+ */
	+/* TODO: Can this API be called after port enable? */
	+int al_pcie_port_snoop_config(struct al_pcie_port *pcie_port,
	+ al_bool enable_axi_snoop);
	+
	+/************************ Configuration Space API *************************/
	+
	+/**
	+ * Configuration Space Access Through PCI-E_ECAM_Ext PASW (RC mode only)
	+ */
	+
	+/**
	+ * @brief get base address of pci configuration space header
	+ * @param pcie_pf pcie pf handle
	+ * @param addr pointer for returned address;
	+ * @return 0 if no error found
	+ */
	+int al_pcie_config_space_get(
	+ struct al_pcie_pf *pcie_pf,
	+ uint8_t __iomem **addr);
	+
	+/**
	+ * Read data from the local configuration space
	+ *
	+ * @param pcie_pf pcie pf handle
	+ * @param reg_offset Configuration space register offset
	+ * @return Read data
	+ */
	+uint32_t al_pcie_local_cfg_space_read(
	+ struct al_pcie_pf *pcie_pf,
	+ unsigned int reg_offset);
	+
	+/**
	+ * Write data to the local configuration space
	+ *
	+ * @param pcie_pf PCIe pf handle
	+ * @param reg_offset Configuration space register offset
	+ * @param data Data to write
	+ * @param cs2 Should be AL_TRUE if dbi_cs2 must be asserted
	+ * to enable writing to this register, according to
	+ * the PCIe Core specifications
	+ * @param allow_ro_wr AL_TRUE to allow writing into read-only regs
	+ *
	+ */
	+void al_pcie_local_cfg_space_write(
	+ struct al_pcie_pf *pcie_pf,
	+ unsigned int reg_offset,
	+ uint32_t data,
	+ al_bool cs2,
	+ al_bool allow_ro_wr);
	+
	+/**
	+ * @brief set target_bus and mask_target_bus
	+ * @param pcie_port pcie port handle
	+ * @param target_bus
	+ * @param mask_target_bus
	+ * @return 0 if no error found
	+ */
	+int al_pcie_target_bus_set(struct al_pcie_port *pcie_port,
	+ uint8_t target_bus,
	+ uint8_t mask_target_bus);
	+
	+/**
	+ * @brief get target_bus and mask_target_bus
	+ * @param pcie_port pcie port handle
	+ * @param target_bus
	+ * @param mask_target_bus
	+ * @return 0 if no error found
	+ */
	+int al_pcie_target_bus_get(struct al_pcie_port *pcie_port,
	+ uint8_t *target_bus,
	+ uint8_t *mask_target_bus);
	+
	+/**
	+ * Set secondary bus number
	+ *
	+ * @param pcie_port pcie port handle
	+ * @param secbus pci secondary bus number
	+ *
	+ * @return 0 if no error found.
	+ */
	+int al_pcie_secondary_bus_set(struct al_pcie_port *pcie_port, uint8_t secbus);
	+
	+/**
	+ * Set subordinary bus number
	+ *
	+ * @param pcie_port pcie port handle
	+ * @param subbus the highest bus number of all of the buses that can be reached
	+ * downstream of the PCIE instance.
	+ *
	+ * @return 0 if no error found.
	+ */
	+int al_pcie_subordinary_bus_set(struct al_pcie_port *pcie_port,uint8_t subbus);
	+
	+/**
	+ * @brief Enable/disable deferring incoming configuration requests until
	+ * initialization is complete. When enabled, the core completes incoming
	+ * configuration requests with a Configuration Request Retry Status.
	+ * Other incoming Requests complete with Unsupported Request status.
	+ *
	+ * @param pcie_port pcie port handle
	+ * @param en enable/disable
	+ */
	+void al_pcie_app_req_retry_set(struct al_pcie_port *pcie_port, al_bool en);
	+
	+/************* Internal Address Translation Unit (ATU) API ****************/
	+
	+enum al_pcie_atu_dir {
	+ AL_PCIE_ATU_DIR_OUTBOUND = 0,
	+ AL_PCIE_ATU_DIR_INBOUND = 1,
	+};
	+
	+enum al_pcie_atu_tlp {
	+ AL_PCIE_TLP_TYPE_MEM = 0,
	+ AL_PCIE_TLP_TYPE_IO = 2,
	+ AL_PCIE_TLP_TYPE_CFG0 = 4,
	+ AL_PCIE_TLP_TYPE_CFG1 = 5,
	+ AL_PCIE_TLP_TYPE_MSG = 0x10,
	+ AL_PCIE_TLP_TYPE_RESERVED = 0x1f
	+};
	+
	+enum al_pcie_atu_response {
	+ AL_PCIE_RESPONSE_NORMAL = 0,
	+ AL_PCIE_RESPONSE_UR = 1,
	+ AL_PCIE_RESPONSE_CA = 2
	+};
	+
	+struct al_pcie_atu_region {
	+ al_bool enable;
	+ /* outbound or inbound */
	+ enum al_pcie_atu_dir direction;
	+ /* region index */
	+ uint8_t index;
	+ uint64_t base_addr;
	+ /** limit marks the region's end address. only bits [39:0] are valid
	+ * given the Alpine PoC maximum physical address space
	+ */
	+ uint64_t limit;
	+ /** the address that matches will be translated to this address + offset
	+ */
	+ uint64_t target_addr;
	+ al_bool invert_matching;
	+ /* pcie tlp type*/
	+ enum al_pcie_atu_tlp tlp_type;
	+ /* pcie frame header attr field*/
	+ uint8_t attr;
	+ /**
	+ * outbound specific params
	+ */
	+ /* pcie message code */
	+ uint8_t msg_code;
	+ al_bool cfg_shift_mode;
	+ /**
	+ * inbound specific params
	+ */
	+ uint8_t bar_number;
	+ /* BAR match mode, used in EP for MEM and IO tlps*/
	+ uint8_t match_mode;
	+ /**
	+ * For outbound: enables taking the function number of the translated
	+ * TLP from the PCIe core. For inbound: enables ATU function match mode
	+ * Note: this boolean is ignored in RC mode
	+ */
	+ al_bool function_match_bypass_mode;
	+ /**
	+ * The function number to match/bypass (see previous parameter)
	+ * Note: this parameter is ignored when previous param is FALSE
	+ */
	+ uint8_t function_match_bypass_mode_number;
	+ /* response code */
	+ enum al_pcie_atu_response response;
	+ al_bool enable_attr_match_mode;
	+ al_bool enable_msg_match_mode;
	+ /**
	+ * USE WITH CAUTION: setting this boolean to AL_TRUE allows setting the
	+ * outbound ATU even after link is already started. DO NOT SET this
	+ * boolean to AL_TRUE unless there have been NO traffic before calling
	+ * al_pcie_atu_region_set function
	+ */
	+ al_bool enforce_ob_atu_region_set;
	+};
	+
	+/**
	+ * @brief program internal ATU region entry
	+ * @param pcie_port pcie port handle
	+ * @param atu_region data structure that contains the region index and the
	+ * translation parameters
	+ * @return 0 if no error
	+ */
	+int al_pcie_atu_region_set(
	+ struct al_pcie_port *pcie_port,
	+ struct al_pcie_atu_region *atu_region);
	+
	+/**
	+ * @brief get internal ATU is enabled and base/target addresses
	+ * @param pcie_port pcie port handle
	+ * @param direction input: iATU direction (IB/OB)
	+ * @param index input: iATU index
	+ * @param enable output: AL_TRUE if the iATU is enabled
	+ * @param base_addr output: the iATU base address
	+ * @param target_addr output: the iATU target address
	+ */
	+void al_pcie_atu_region_get_fields(
	+ struct al_pcie_port *pcie_port,
	+ enum al_pcie_atu_dir direction, uint8_t index,
	+ al_bool enable, uint64_t base_addr, uint64_t *target_addr);
	+
	+/**
	+ * @brief Configure axi io bar.
	+ * every hit to this bar will override size to 4 bytes.
	+ * @param pcie_port pcie port handle
	+ * @param start the first address of the memory
	+ * @param end the last address of the memory
	+ * @return
	+ */
	+void al_pcie_axi_io_config(
	+ struct al_pcie_port *pcie_port,
	+ al_phys_addr_t start,
	+ al_phys_addr_t end);
	+
	+/************ Interrupt generation (Endpoint mode Only) API ***************/
	+
	+enum al_pcie_legacy_int_type{
	+ AL_PCIE_LEGACY_INTA = 0,
	+ AL_PCIE_LEGACY_INTB,
	+ AL_PCIE_LEGACY_INTC,
	+ AL_PCIE_LEGACY_INTD
	+};
	+
	+/**
	+ * @brief generate INTx Assert/DeAssert Message
	+ * @param pcie_pf pcie pf handle
	+ * @param assert when true, Assert Message is sent
	+ * @param type type of message (INTA, INTB, etc)
	+ * @return 0 if no error found
	+ */
	+int al_pcie_legacy_int_gen(
	+ struct al_pcie_pf *pcie_pf,
	+ al_bool assert,
	+ enum al_pcie_legacy_int_type type);
	+
	+/**
	+ * @brief generate MSI interrupt
	+ * @param pcie_pf pcie pf handle
	+ * @param vector the vector index to send interrupt for.
	+ * @return 0 if no error found
	+ */
	+int al_pcie_msi_int_gen(struct al_pcie_pf *pcie_pf, uint8_t vector);
	+
	+/**
	+ * @brief configure MSIX capability
	+ * @param pcie_pf pcie pf handle
	+ * @param msix_params MSIX capability configuration parameters
	+ * @return 0 if no error found
	+ */
	+int al_pcie_msix_config(
	+ struct al_pcie_pf *pcie_pf,
	+ struct al_pcie_msix_params *msix_params);
	+
	+/**
	+ * @brief check whether MSIX capability is enabled
	+ * @param pcie_pf pcie pf handle
	+ * @return AL_TRUE if MSIX capability is enabled, AL_FALSE otherwise
	+ */
	+al_bool al_pcie_msix_enabled(struct al_pcie_pf *pcie_pf);
	+
	+/**
	+ * @brief check whether MSIX capability is masked
	+ * @param pcie_pf pcie pf handle
	+ * @return AL_TRUE if MSIX capability is masked, AL_FALSE otherwise
	+ */
	+al_bool al_pcie_msix_masked(struct al_pcie_pf *pcie_pf);
	+
	+/****************** Advanced Error Reporting (AER) API ********************/
	+
	+/**
	+ * @brief configure AER capability
	+ * @param pcie_pf pcie pf handle
	+ * @param params AER capability configuration parameters
	+ * @return 0 if no error found
	+ */
	+int al_pcie_aer_config(
	+ struct al_pcie_pf *pcie_pf,
	+ struct al_pcie_aer_params *params);
	+
	+/**
	+ * @brief AER uncorretable errors get and clear
	+ * @param pcie_pf pcie pf handle
	+ * @return bit mask of uncorrectable errors - see 'AL_PCIE_AER_UNCORR_*' for
	+ * details
	+ */
	+unsigned int al_pcie_aer_uncorr_get_and_clear(struct al_pcie_pf *pcie_pf);
	+
	+/**
	+ * @brief AER corretable errors get and clear
	+ * @param pcie_pf pcie pf handle
	+ * @return bit mask of correctable errors - see 'AL_PCIE_AER_CORR_*' for
	+ * details
	+ */
	+unsigned int al_pcie_aer_corr_get_and_clear(struct al_pcie_pf *pcie_pf);
	+
	+/**
	+ * @brief AER get the header for the TLP corresponding to a detected error
	+ * @param pcie_pf pcie pf handle
	+ * @param hdr pointer to an array for getting the header
	+ */
	+void al_pcie_aer_err_tlp_hdr_get(
	+ struct al_pcie_pf *pcie_pf,
	+ uint32_t hdr[AL_PCIE_AER_ERR_TLP_HDR_NUM_DWORDS]);
	+
	+/****************** Loop-Back mode (RC and Endpoint modes) ****************/
	+
	+/**
	+ * @brief enter local pipe loop-back mode
	+ * This mode will connect the pipe RX signals to TX.
	+ * no need to start link when using this mode.
	+ * Gen3 equalization must be disabled before enabling this mode
	+ * The caller must make sure the port is ready to accept the TLPs it sends to
	+ * itself. for example, BARs should be initialized before sending memory TLPs.
	+ *
	+ * @param pcie_port pcie port handle
	+ * @return 0 if no error found
	+ */
	+int al_pcie_local_pipe_loopback_enter(struct al_pcie_port *pcie_port);
	+
	+/**
	+ * @brief exit local pipe loopback mode
	+ *
	+ * @param pcie_port pcie port handle
	+ * @return 0 if no error found
	+ */
	+int al_pcie_local_pipe_loopback_exit(struct al_pcie_port *pcie_port);
	+
	+/**
	+ * @brief enter master remote loopback mode
	+ * No need to configure the link partner to enter slave remote loopback mode
	+ * as this should be done as response to special training sequence directives
	+ * when master works in remote loopback mode.
	+ * The caller must make sure the port is ready to accept the TLPs it sends to
	+ * itself. for example, BARs should be initialized before sending memory TLPs.
	+ *
	+ * @param pcie_port pcie port handle
	+ * @return 0 if no error found
	+ */
	+int al_pcie_remote_loopback_enter(struct al_pcie_port *pcie_port);
	+
	+/**
	+ * @brief exit remote loopback mode
	+ *
	+ * @param pcie_port pcie port handle
	+ * @return 0 if no error found
	+ */
	+int al_pcie_remote_loopback_exit(struct al_pcie_port *pcie_port);
	+
	+#endif
	+/** @} end of grouppcie group */
	Index: sys/arm/annapurna/alpine/hal/al_hal_pcie.c
	===================================================================
	--- /dev/null
	+++ sys/arm/annapurna/alpine/hal/al_hal_pcie.c
	@@ -0,0 +1,2788 @@
	+/*-
	+********************************************************************************
	+Copyright (C) 2015 Annapurna Labs Ltd.
	+
	+This file may be licensed under the terms of the Annapurna Labs Commercial
	+License Agreement.
	+
	+Alternatively, this file can be distributed under the terms of the GNU General
	+Public License V2 as published by the Free Software Foundation and can be
	+found at http://www.gnu.org/licenses/gpl-2.0.html
	+
	+Alternatively, redistribution and use in source and binary forms, with or
	+without modification, are permitted provided that the following conditions are
	+met:
	+
	+ * Redistributions of source code must retain the above copyright notice,
	+this list of conditions and the following disclaimer.
	+
	+ * Redistributions in binary form must reproduce the above copyright
	+notice, this list of conditions and the following disclaimer in
	+the documentation and/or other materials provided with the
	+distribution.
	+
	+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
	+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
	+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
	+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
	+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
	+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
	+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
	+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
	+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
	+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	+
	+*******************************************************************************/
	+
	+#include <sys/cdefs.h>
	+__FBSDID("$FreeBSD$");
	+
	+#include <sys/param.h>
	+#include <sys/systm.h>
	+#include <sys/kernel.h>
	+
	+#include "al_hal_pcie.h"
	+#include "al_hal_pbs_regs.h"
	+#include "al_hal_unit_adapter_regs.h"
	+
	+/**
	+ * Parameter definitions
	+ */
	+#define AL_PCIE_AXI_REGS_OFFSET 0x0
	+
	+#define AL_PCIE_LTSSM_STATE_L0 0x11
	+#define AL_PCIE_LTSSM_STATE_L0S 0x12
	+#define AL_PCIE_DEVCTL_PAYLOAD_128B 0x00
	+#define AL_PCIE_DEVCTL_PAYLOAD_256B 0x20
	+
	+#define AL_PCIE_SECBUS_DEFAULT 0x1
	+#define AL_PCIE_SUBBUS_DEFAULT 0x1
	+#define AL_PCIE_LINKUP_WAIT_INTERVAL 50 /* measured in usec */
	+#define AL_PCIE_LINKUP_WAIT_INTERVALS_PER_SEC 20
	+
	+#define AL_PCIE_LINKUP_RETRIES 8
	+
	+#define AL_PCIE_MAX_32_MEMORY_BAR_SIZE (0x100000000ULL)
	+#define AL_PCIE_MIN_MEMORY_BAR_SIZE (1 << 12)
	+#define AL_PCIE_MIN_IO_BAR_SIZE (1 << 8)
	+
	+/**
	+ * inbound header credits and outstanding outbound reads defaults
	+ */
	+/** RC - Revisions 1/2 */
	+#define AL_PCIE_REV_1_2_RC_OB_OS_READS_DEFAULT (8)
	+#define AL_PCIE_REV_1_2_RC_NOF_CPL_HDR_DEFAULT (41)
	+#define AL_PCIE_REV_1_2_RC_NOF_NP_HDR_DEFAULT (25)
	+#define AL_PCIE_REV_1_2_RC_NOF_P_HDR_DEFAULT (31)
	+/** EP - Revisions 1/2 */
	+#define AL_PCIE_REV_1_2_EP_OB_OS_READS_DEFAULT (15)
	+#define AL_PCIE_REV_1_2_EP_NOF_CPL_HDR_DEFAULT (76)
	+#define AL_PCIE_REV_1_2_EP_NOF_NP_HDR_DEFAULT (6)
	+#define AL_PCIE_REV_1_2_EP_NOF_P_HDR_DEFAULT (15)
	+/** RC - Revision 3 */
	+#define AL_PCIE_REV_3_RC_OB_OS_READS_DEFAULT (32)
	+#define AL_PCIE_REV_3_RC_NOF_CPL_HDR_DEFAULT (161)
	+#define AL_PCIE_REV_3_RC_NOF_NP_HDR_DEFAULT (38)
	+#define AL_PCIE_REV_3_RC_NOF_P_HDR_DEFAULT (60)
	+/** EP - Revision 3 */
	+#define AL_PCIE_REV_3_EP_OB_OS_READS_DEFAULT (32)
	+#define AL_PCIE_REV_3_EP_NOF_CPL_HDR_DEFAULT (161)
	+#define AL_PCIE_REV_3_EP_NOF_NP_HDR_DEFAULT (38)
	+#define AL_PCIE_REV_3_EP_NOF_P_HDR_DEFAULT (60)
	+
	+/**
	+ * MACROS
	+ */
	+#define AL_PCIE_PARSE_LANES(v) (((1 << v) - 1) << \
	+ PCIE_REVX_AXI_MISC_PCIE_GLOBAL_CONF_NOF_ACT_LANES_SHIFT)
	+
	+/**
	+ * Static functions
	+ */
	+static void
	+al_pcie_port_wr_to_ro_set(struct al_pcie_port *pcie_port, al_bool enable)
	+{
	+ /* when disabling writes to RO, make sure any previous writes to
	+ * config space were committed
	+ */
	+ if (enable == AL_FALSE)
	+ al_local_data_memory_barrier();
	+
	+ al_reg_write32(&pcie_port->regs->port_regs->rd_only_wr_en,
	+ (enable == AL_TRUE) ? 1 : 0);
	+
	+ /* when enabling writes to RO, make sure it is committed before trying
	+ * to write to RO config space
	+ */
	+ if (enable == AL_TRUE)
	+ al_local_data_memory_barrier();
	+}
	+
	+/** helper function to access dbi_cs2 registers */
	+static void
	+al_reg_write32_dbi_cs2(
	+ struct al_pcie_port *pcie_port,
	+ uint32_t *offset,
	+ uint32_t val)
	+{
	+ uintptr_t cs2_bit =
	+ (pcie_port->rev_id == AL_PCIE_REV_ID_3) ? 0x4000 : 0x1000;
	+
	+ al_reg_write32((uint32_t *)((uintptr_t)offset \| cs2_bit), val);
	+}
	+
	+static unsigned int
	+al_pcie_speed_gen_code(enum al_pcie_link_speed speed)
	+{
	+ if (speed == AL_PCIE_LINK_SPEED_GEN1)
	+ return 1;
	+ if (speed == AL_PCIE_LINK_SPEED_GEN2)
	+ return 2;
	+ if (speed == AL_PCIE_LINK_SPEED_GEN3)
	+ return 3;
	+ /* must not be reached */
	+ return 0;
	+}
	+
	+static inline void
	+al_pcie_port_link_speed_ctrl_set(
	+ struct al_pcie_port *pcie_port,
	+ enum al_pcie_link_speed max_speed)
	+{
	+ struct al_pcie_regs *regs = pcie_port->regs;
	+
	+ al_pcie_port_wr_to_ro_set(pcie_port, AL_TRUE);
	+
	+ if (max_speed != AL_PCIE_LINK_SPEED_DEFAULT) {
	+ uint16_t max_speed_val = (uint16_t)al_pcie_speed_gen_code(max_speed);
	+ al_reg_write32_masked(
	+ (uint32_t __iomem *)(regs->core_space[0].pcie_link_cap_base),
	+ 0xF, max_speed_val);
	+ al_reg_write32_masked(
	+ (uint32_t __iomem *)(regs->core_space[0].pcie_cap_base
	+ + (AL_PCI_EXP_LNKCTL2 >> 2)),
	+ 0xF, max_speed_val);
	+ }
	+
	+ al_pcie_port_wr_to_ro_set(pcie_port, AL_FALSE);
	+}
	+
	+static int
	+al_pcie_port_link_config(
	+ struct al_pcie_port *pcie_port,
	+ const struct al_pcie_link_params *link_params)
	+{
	+ struct al_pcie_regs *regs = pcie_port->regs;
	+ uint8_t max_lanes = pcie_port->max_lanes;
	+
	+ if ((link_params->max_payload_size != AL_PCIE_MPS_DEFAULT) &&
	+ (link_params->max_payload_size != AL_PCIE_MPS_128) &&
	+ (link_params->max_payload_size != AL_PCIE_MPS_256)) {
	+ al_err("PCIe %d: unsupported Max Payload Size (%u)\n",
	+ pcie_port->port_id, link_params->max_payload_size);
	+ return -EINVAL;
	+ }
	+
	+ al_dbg("PCIe %d: link config: max speed gen %d, max lanes %d, reversal %s\n",
	+ pcie_port->port_id, link_params->max_speed,
	+ pcie_port->max_lanes, link_params->enable_reversal? "enable" : "disable");
	+
	+ al_pcie_port_link_speed_ctrl_set(pcie_port, link_params->max_speed);
	+
	+ /* Change Max Payload Size, if needed.
	+ * The Max Payload Size is only valid for PF0.
	+ */
	+ if (link_params->max_payload_size != AL_PCIE_MPS_DEFAULT)
	+ al_reg_write32_masked(regs->core_space[0].pcie_dev_ctrl_status,
	+ PCIE_PORT_DEV_CTRL_STATUS_MPS_MASK,
	+ link_params->max_payload_size <<
	+ PCIE_PORT_DEV_CTRL_STATUS_MPS_SHIFT);
	+
	+ /** Snap from PCIe core spec:
	+ * Link Mode Enable. Sets the number of lanes in the link that you want
	+ * to connect to the link partner. When you have unused lanes in your
	+ * system, then you must change the value in this register to reflect
	+ * the number of lanes. You must also change the value in the
	+ * "Predetermined Number of Lanes" field of the "Link Width and Speed
	+ * Change Control Register".
	+ * 000001: x1
	+ * 000011: x2
	+ * 000111: x4
	+ * 001111: x8
	+ * 011111: x16
	+ * 111111: x32 (not supported)
	+ */
	+ al_reg_write32_masked(&regs->port_regs->gen2_ctrl,
	+ PCIE_PORT_GEN2_CTRL_NUM_OF_LANES_MASK,
	+ max_lanes << PCIE_PORT_GEN2_CTRL_NUM_OF_LANES_SHIFT);
	+ al_reg_write32_masked(&regs->port_regs->port_link_ctrl,
	+ PCIE_PORT_LINK_CTRL_LINK_CAPABLE_MASK,
	+ (max_lanes + (max_lanes-1))
	+ << PCIE_PORT_LINK_CTRL_LINK_CAPABLE_SHIFT);
	+
	+ /* TODO: add support for reversal mode */
	+ if (link_params->enable_reversal) {
	+ al_err("PCIe %d: enabling reversal mode not implemented\n",
	+ pcie_port->port_id);
	+ return -ENOSYS;
	+ }
	+ return 0;
	+}
	+
	+static void
	+al_pcie_port_ram_parity_int_config(
	+ struct al_pcie_port *pcie_port,
	+ al_bool enable)
	+{
	+ struct al_pcie_regs *regs = pcie_port->regs;
	+
	+ al_reg_write32(&regs->app.parity->en_core,
	+ (enable == AL_TRUE) ? 0xffffffff : 0x0);
	+
	+ al_reg_write32_masked(&regs->app.int_grp_b->mask,
	+ PCIE_W_INT_GRP_B_CAUSE_B_PARITY_ERROR_CORE,
	+ (enable != AL_TRUE) ?
	+ PCIE_W_INT_GRP_B_CAUSE_B_PARITY_ERROR_CORE : 0);
	+
	+}
	+
	+static void
	+al_pcie_port_axi_parity_int_config(
	+ struct al_pcie_port *pcie_port,
	+ al_bool enable)
	+{
	+ struct al_pcie_regs *regs = pcie_port->regs;
	+ uint32_t parity_enable_mask = 0xffffffff;
	+
	+ /**
	+ * Addressing RMN: 5603
	+ *
	+ * RMN description:
	+ * u4_ram2p signal false parity error
	+ *
	+ * Software flow:
	+ * Disable parity check for this memory
	+ */
	+ if (pcie_port->rev_id >= AL_PCIE_REV_ID_3)
	+ parity_enable_mask &= ~PCIE_AXI_PARITY_EN_AXI_U4_RAM2P;
	+
	+ al_reg_write32(regs->axi.parity.en_axi,
	+ (enable == AL_TRUE) ? parity_enable_mask : 0x0);
	+
	+ if (pcie_port->rev_id == AL_PCIE_REV_ID_3) {
	+ al_reg_write32_masked(regs->axi.ctrl.global,
	+ PCIE_REV3_AXI_CTRL_GLOBAL_PARITY_CALC_EN_MSTR \|
	+ PCIE_REV3_AXI_CTRL_GLOBAL_PARITY_ERR_EN_RD \|
	+ PCIE_REV3_AXI_CTRL_GLOBAL_PARITY_CALC_EN_SLV \|
	+ PCIE_REV3_AXI_CTRL_GLOBAL_PARITY_ERR_EN_WR,
	+ (enable == AL_TRUE) ?
	+ PCIE_REV3_AXI_CTRL_GLOBAL_PARITY_CALC_EN_MSTR \|
	+ PCIE_REV3_AXI_CTRL_GLOBAL_PARITY_ERR_EN_RD \|
	+ PCIE_REV3_AXI_CTRL_GLOBAL_PARITY_CALC_EN_SLV \|
	+ PCIE_REV3_AXI_CTRL_GLOBAL_PARITY_ERR_EN_WR :
	+ PCIE_REV3_AXI_CTRL_GLOBAL_PARITY_CALC_EN_SLV);
	+ } else {
	+ al_reg_write32_masked(regs->axi.ctrl.global,
	+ PCIE_REV1_2_AXI_CTRL_GLOBAL_PARITY_CALC_EN_MSTR \|
	+ PCIE_REV1_2_AXI_CTRL_GLOBAL_PARITY_ERR_EN_RD \|
	+ PCIE_REV1_2_AXI_CTRL_GLOBAL_PARITY_CALC_EN_SLV \|
	+ PCIE_REV1_2_AXI_CTRL_GLOBAL_PARITY_ERR_EN_WR,
	+ (enable == AL_TRUE) ?
	+ PCIE_REV1_2_AXI_CTRL_GLOBAL_PARITY_CALC_EN_MSTR \|
	+ PCIE_REV1_2_AXI_CTRL_GLOBAL_PARITY_ERR_EN_RD \|
	+ PCIE_REV1_2_AXI_CTRL_GLOBAL_PARITY_CALC_EN_SLV \|
	+ PCIE_REV1_2_AXI_CTRL_GLOBAL_PARITY_ERR_EN_WR :
	+ PCIE_REV1_2_AXI_CTRL_GLOBAL_PARITY_CALC_EN_SLV);
	+ }
	+
	+ al_reg_write32_masked(&regs->axi.int_grp_a->mask,
	+ PCIE_AXI_INT_GRP_A_CAUSE_PARITY_ERR_DATA_PATH_RD \|
	+ PCIE_AXI_INT_GRP_A_CAUSE_PARITY_ERR_OUT_ADDR_RD \|
	+ PCIE_AXI_INT_GRP_A_CAUSE_PARITY_ERR_OUT_ADDR_WR \|
	+ PCIE_AXI_INT_GRP_A_CAUSE_PARITY_ERR_OUT_DATA_WR \|
	+ PCIE_AXI_INT_GRP_A_CAUSE_PARITY_ERROR_AXI,
	+ (enable != AL_TRUE) ?
	+ (PCIE_AXI_INT_GRP_A_CAUSE_PARITY_ERR_DATA_PATH_RD \|
	+ PCIE_AXI_INT_GRP_A_CAUSE_PARITY_ERR_OUT_ADDR_RD \|
	+ PCIE_AXI_INT_GRP_A_CAUSE_PARITY_ERR_OUT_ADDR_WR \|
	+ PCIE_AXI_INT_GRP_A_CAUSE_PARITY_ERR_OUT_DATA_WR \|
	+ PCIE_AXI_INT_GRP_A_CAUSE_PARITY_ERROR_AXI) : 0);
	+}
	+
	+static void
	+al_pcie_port_relaxed_pcie_ordering_config(
	+ struct al_pcie_port *pcie_port,
	+ struct al_pcie_relaxed_ordering_params *relaxed_ordering_params)
	+{
	+ struct al_pcie_regs *regs = pcie_port->regs;
	+ enum al_pcie_operating_mode op_mode = al_pcie_operating_mode_get(pcie_port);
	+ /**
	+ * Default:
	+ * - RC: Rx relaxed ordering only
	+ * - EP: TX relaxed ordering only
	+ */
	+ al_bool tx_relaxed_ordering = (op_mode == AL_PCIE_OPERATING_MODE_RC ? AL_FALSE : AL_TRUE);
	+ al_bool rx_relaxed_ordering = (op_mode == AL_PCIE_OPERATING_MODE_RC ? AL_TRUE : AL_FALSE);
	+
	+ if (relaxed_ordering_params) {
	+ tx_relaxed_ordering = relaxed_ordering_params->enable_tx_relaxed_ordering;
	+ rx_relaxed_ordering = relaxed_ordering_params->enable_rx_relaxed_ordering;
	+ }
	+
	+ /** PCIe ordering:
	+ * - disable outbound completion must be stalled behind outbound write
	+ * ordering rule enforcement is disabled for root-port
	+ * - disables read completion on the master port push slave writes for end-point
	+ */
	+ al_reg_write32_masked(
	+ regs->axi.ordering.pos_cntl,
	+ PCIE_AXI_POS_ORDER_BYPASS_CMPL_AFTER_WR_FIX \|
	+ PCIE_AXI_POS_ORDER_EP_CMPL_AFTER_WR_DIS \|
	+ PCIE_AXI_POS_ORDER_EP_CMPL_AFTER_WR_SUPPORT_INTERLV_DIS \|
	+ PCIE_AXI_POS_ORDER_SEGMENT_BUFFER_DONT_WAIT_FOR_P_WRITES,
	+ (tx_relaxed_ordering ?
	+ (PCIE_AXI_POS_ORDER_BYPASS_CMPL_AFTER_WR_FIX \|
	+ PCIE_AXI_POS_ORDER_SEGMENT_BUFFER_DONT_WAIT_FOR_P_WRITES) : 0) \|
	+ (rx_relaxed_ordering ?
	+ (PCIE_AXI_POS_ORDER_EP_CMPL_AFTER_WR_DIS \|
	+ PCIE_AXI_POS_ORDER_EP_CMPL_AFTER_WR_SUPPORT_INTERLV_DIS) : 0));
	+}
	+
	+static int
	+al_pcie_rev_id_get(
	+ void __iomem *pbs_reg_base,
	+ void __iomem *pcie_reg_base)
	+{
	+ uint32_t chip_id;
	+ uint16_t chip_id_dev;
	+ uint8_t rev_id;
	+ struct al_pbs_regs *pbs_regs = pbs_reg_base;
	+
	+ /* get revision ID from PBS' chip_id register */
	+ chip_id = al_reg_read32(&pbs_regs->unit.chip_id);
	+ chip_id_dev = AL_REG_FIELD_GET(chip_id,
	+ PBS_UNIT_CHIP_ID_DEV_ID_MASK,
	+ PBS_UNIT_CHIP_ID_DEV_ID_SHIFT);
	+
	+ if (chip_id_dev == PBS_UNIT_CHIP_ID_DEV_ID_ALPINE) {
	+ rev_id = AL_REG_FIELD_GET(
	+ chip_id,
	+ PBS_UNIT_CHIP_ID_DEV_REV_ID_MASK,
	+ PBS_UNIT_CHIP_ID_DEV_REV_ID_SHIFT);
	+ } else if (chip_id_dev == PBS_UNIT_CHIP_ID_DEV_ID_PEAKROCK) {
	+ struct al_pcie_revx_regs __iomem *regs =
	+ (struct al_pcie_revx_regs __iomem *)pcie_reg_base;
	+ uint32_t dev_id;
	+
	+ dev_id = al_reg_read32(&regs->axi.device_id.device_rev_id) &
	+ PCIE_AXI_DEVICE_ID_REG_DEV_ID_MASK;
	+ if (dev_id == PCIE_AXI_DEVICE_ID_REG_DEV_ID_X4) {
	+ rev_id = AL_PCIE_REV_ID_2;
	+ } else if (dev_id == PCIE_AXI_DEVICE_ID_REG_DEV_ID_X8) {
	+ rev_id = AL_PCIE_REV_ID_3;
	+ } else {
	+ al_warn("%s: Revision ID is unknown\n",
	+ __func__);
	+ return -EINVAL;
	+ }
	+ } else {
	+ al_warn("%s: Revision ID is unknown\n",
	+ __func__);
	+ return -EINVAL;
	+ }
	+ return rev_id;
	+}
	+
	+static int
	+al_pcie_port_lat_rply_timers_config(
	+ struct al_pcie_port *pcie_port,
	+ const struct al_pcie_latency_replay_timers *lat_rply_timers)
	+{
	+ struct al_pcie_regs *regs = pcie_port->regs;
	+ uint32_t reg = 0;
	+
	+ AL_REG_FIELD_SET(reg, 0xFFFF, 0, lat_rply_timers->round_trip_lat_limit);
	+ AL_REG_FIELD_SET(reg, 0xFFFF0000, 16, lat_rply_timers->replay_timer_limit);
	+
	+ al_reg_write32(&regs->port_regs->ack_lat_rply_timer, reg);
	+ return 0;
	+}
	+
	+static void
	+al_pcie_ib_hcrd_os_ob_reads_config_default(
	+ struct al_pcie_port *pcie_port)
	+{
	+
	+ struct al_pcie_ib_hcrd_os_ob_reads_config ib_hcrd_os_ob_reads_config;
	+
	+ switch (al_pcie_operating_mode_get(pcie_port)) {
	+ case AL_PCIE_OPERATING_MODE_RC:
	+ if (pcie_port->rev_id == AL_PCIE_REV_ID_3) {
	+ ib_hcrd_os_ob_reads_config.nof_outstanding_ob_reads =
	+ AL_PCIE_REV_3_RC_OB_OS_READS_DEFAULT;
	+ ib_hcrd_os_ob_reads_config.nof_cpl_hdr =
	+ AL_PCIE_REV_3_RC_NOF_CPL_HDR_DEFAULT;
	+ ib_hcrd_os_ob_reads_config.nof_np_hdr =
	+ AL_PCIE_REV_3_RC_NOF_NP_HDR_DEFAULT;
	+ ib_hcrd_os_ob_reads_config.nof_p_hdr =
	+ AL_PCIE_REV_3_RC_NOF_P_HDR_DEFAULT;
	+ } else {
	+ ib_hcrd_os_ob_reads_config.nof_outstanding_ob_reads =
	+ AL_PCIE_REV_1_2_RC_OB_OS_READS_DEFAULT;
	+ ib_hcrd_os_ob_reads_config.nof_cpl_hdr =
	+ AL_PCIE_REV_1_2_RC_NOF_CPL_HDR_DEFAULT;
	+ ib_hcrd_os_ob_reads_config.nof_np_hdr =
	+ AL_PCIE_REV_1_2_RC_NOF_NP_HDR_DEFAULT;
	+ ib_hcrd_os_ob_reads_config.nof_p_hdr =
	+ AL_PCIE_REV_1_2_RC_NOF_P_HDR_DEFAULT;
	+ }
	+ break;
	+
	+ case AL_PCIE_OPERATING_MODE_EP:
	+ if (pcie_port->rev_id == AL_PCIE_REV_ID_3) {
	+ ib_hcrd_os_ob_reads_config.nof_outstanding_ob_reads =
	+ AL_PCIE_REV_3_EP_OB_OS_READS_DEFAULT;
	+ ib_hcrd_os_ob_reads_config.nof_cpl_hdr =
	+ AL_PCIE_REV_3_EP_NOF_CPL_HDR_DEFAULT;
	+ ib_hcrd_os_ob_reads_config.nof_np_hdr =
	+ AL_PCIE_REV_3_EP_NOF_NP_HDR_DEFAULT;
	+ ib_hcrd_os_ob_reads_config.nof_p_hdr =
	+ AL_PCIE_REV_3_EP_NOF_P_HDR_DEFAULT;
	+ } else {
	+ ib_hcrd_os_ob_reads_config.nof_outstanding_ob_reads =
	+ AL_PCIE_REV_1_2_EP_OB_OS_READS_DEFAULT;
	+ ib_hcrd_os_ob_reads_config.nof_cpl_hdr =
	+ AL_PCIE_REV_1_2_EP_NOF_CPL_HDR_DEFAULT;
	+ ib_hcrd_os_ob_reads_config.nof_np_hdr =
	+ AL_PCIE_REV_1_2_EP_NOF_NP_HDR_DEFAULT;
	+ ib_hcrd_os_ob_reads_config.nof_p_hdr =
	+ AL_PCIE_REV_1_2_EP_NOF_P_HDR_DEFAULT;
	+ }
	+ break;
	+
	+ default:
	+ al_err("PCIe %d: outstanding outbound transactions could not be configured - unknown operating mode\n",
	+ pcie_port->port_id);
	+ al_assert(0);
	+ }
	+
	+ al_pcie_port_ib_hcrd_os_ob_reads_config(pcie_port, &ib_hcrd_os_ob_reads_config);
	+};
	+
	+/** return AL_TRUE is link started (LTSSM enabled) and AL_FALSE otherwise */
	+static al_bool
	+al_pcie_is_link_started(struct al_pcie_port *pcie_port)
	+{
	+ struct al_pcie_regs regs = (struct al_pcie_regs )pcie_port->regs;
	+
	+ uint32_t port_init = al_reg_read32(regs->app.global_ctrl.port_init);
	+ uint8_t ltssm_en = AL_REG_FIELD_GET(port_init,
	+ PCIE_W_GLOBAL_CTRL_PORT_INIT_APP_LTSSM_EN_MASK,
	+ PCIE_W_GLOBAL_CTRL_PORT_INIT_APP_LTSSM_EN_SHIFT);
	+
	+ return ltssm_en;
	+}
	+
	+/** return AL_TRUE if link is up, AL_FALSE otherwise */
	+static al_bool
	+al_pcie_check_link(
	+ struct al_pcie_port *pcie_port,
	+ uint8_t *ltssm_ret)
	+{
	+ struct al_pcie_regs regs = (struct al_pcie_regs )pcie_port->regs;
	+ uint32_t info_0;
	+ uint8_t ltssm_state;
	+
	+ info_0 = al_reg_read32(&regs->app.debug->info_0);
	+
	+ ltssm_state = AL_REG_FIELD_GET(info_0,
	+ PCIE_W_DEBUG_INFO_0_LTSSM_STATE_MASK,
	+ PCIE_W_DEBUG_INFO_0_LTSSM_STATE_SHIFT);
	+
	+ al_dbg("PCIe %d: Port Debug 0: 0x%08x. LTSSM state :0x%x\n",
	+ pcie_port->port_id, info_0, ltssm_state);
	+
	+ if (ltssm_ret)
	+ *ltssm_ret = ltssm_state;
	+
	+ if ((ltssm_state == AL_PCIE_LTSSM_STATE_L0) \|\|
	+ (ltssm_state == AL_PCIE_LTSSM_STATE_L0S))
	+ return AL_TRUE;
	+ return AL_FALSE;
	+}
	+
	+static int
	+al_pcie_port_gen2_params_config(struct al_pcie_port *pcie_port,
	+ const struct al_pcie_gen2_params *gen2_params)
	+{
	+ struct al_pcie_regs *regs = pcie_port->regs;
	+ uint32_t gen2_ctrl;
	+
	+ al_dbg("PCIe %d: Gen2 params config: Tx Swing %s, interrupt on link Eq %s, set Deemphasis %s\n",
	+ pcie_port->port_id,
	+ gen2_params->tx_swing_low ? "Low" : "Full",
	+ gen2_params->tx_compliance_receive_enable? "enable" : "disable",
	+ gen2_params->set_deemphasis? "enable" : "disable");
	+
	+ gen2_ctrl = al_reg_read32(&regs->port_regs->gen2_ctrl);
	+
	+ if (gen2_params->tx_swing_low)
	+ AL_REG_BIT_SET(gen2_ctrl, PCIE_PORT_GEN2_CTRL_TX_SWING_LOW_SHIFT);
	+ else
	+ AL_REG_BIT_CLEAR(gen2_ctrl, PCIE_PORT_GEN2_CTRL_TX_SWING_LOW_SHIFT);
	+
	+ if (gen2_params->tx_compliance_receive_enable)
	+ AL_REG_BIT_SET(gen2_ctrl, PCIE_PORT_GEN2_CTRL_TX_COMPLIANCE_RCV_SHIFT);
	+ else
	+ AL_REG_BIT_CLEAR(gen2_ctrl, PCIE_PORT_GEN2_CTRL_TX_COMPLIANCE_RCV_SHIFT);
	+
	+ if (gen2_params->set_deemphasis)
	+ AL_REG_BIT_SET(gen2_ctrl, PCIE_PORT_GEN2_CTRL_DEEMPHASIS_SET_SHIFT);
	+ else
	+ AL_REG_BIT_CLEAR(gen2_ctrl, PCIE_PORT_GEN2_CTRL_DEEMPHASIS_SET_SHIFT);
	+
	+ al_reg_write32(&regs->port_regs->gen2_ctrl, gen2_ctrl);
	+
	+ return 0;
	+}
	+
	+
	+static uint16_t
	+gen3_lane_eq_param_to_val(const struct al_pcie_gen3_lane_eq_params *eq_params)
	+{
	+ uint16_t eq_control = 0;
	+
	+ eq_control = eq_params->downstream_port_transmitter_preset & 0xF;
	+ eq_control \|= (eq_params->downstream_port_receiver_preset_hint & 0x7) << 4;
	+ eq_control \|= (eq_params->upstream_port_transmitter_preset & 0xF) << 8;
	+ eq_control \|= (eq_params->upstream_port_receiver_preset_hint & 0x7) << 12;
	+
	+ return eq_control;
	+}
	+
	+static int
	+al_pcie_port_gen3_params_config(struct al_pcie_port *pcie_port,
	+ const struct al_pcie_gen3_params *gen3_params)
	+{
	+ struct al_pcie_regs *regs = pcie_port->regs;
	+ uint32_t reg = 0;
	+ uint16_t __iomem lanes_eq_base = (uint16_t __iomem )(regs->core_space[0].pcie_sec_ext_cap_base + (0xC >> 2));
	+ int i;
	+
	+ al_dbg("PCIe %d: Gen3 params config: Equalization %s, interrupt on link Eq %s\n",
	+ pcie_port->port_id,
	+ gen3_params->perform_eq ? "enable" : "disable",
	+ gen3_params->interrupt_enable_on_link_eq_request? "enable" : "disable");
	+
	+ if (gen3_params->perform_eq)
	+ AL_REG_BIT_SET(reg, 0);
	+ if (gen3_params->interrupt_enable_on_link_eq_request)
	+ AL_REG_BIT_SET(reg, 1);
	+
	+ al_reg_write32(regs->core_space[0].pcie_sec_ext_cap_base + (4 >> 2),
	+ reg);
	+
	+ al_pcie_port_wr_to_ro_set(pcie_port, AL_TRUE);
	+
	+ for (i = 0; i < gen3_params->eq_params_elements; i += 2) {
	+ uint32_t eq_control =
	+ (uint32_t)gen3_lane_eq_param_to_val(gen3_params->eq_params + i) \|
	+ (uint32_t)gen3_lane_eq_param_to_val(gen3_params->eq_params + i + 1) << 16;
	+
	+ al_dbg("PCIe %d: Set EQ (0x%08x) for lane %d, %d\n", pcie_port->port_id, eq_control, i, i + 1);
	+ al_reg_write32((uint32_t *)(lanes_eq_base + i), eq_control);
	+ }
	+
	+ al_pcie_port_wr_to_ro_set(pcie_port, AL_FALSE);
	+
	+ reg = al_reg_read32(&regs->port_regs->gen3_ctrl);
	+ if (gen3_params->eq_disable)
	+ AL_REG_BIT_SET(reg, PCIE_PORT_GEN3_CTRL_EQ_DISABLE_SHIFT);
	+ else
	+ AL_REG_BIT_CLEAR(reg, PCIE_PORT_GEN3_CTRL_EQ_DISABLE_SHIFT);
	+
	+ if (gen3_params->eq_phase2_3_disable)
	+ AL_REG_BIT_SET(reg, PCIE_PORT_GEN3_CTRL_EQ_PHASE_2_3_DISABLE_SHIFT);
	+ else
	+ AL_REG_BIT_CLEAR(reg, PCIE_PORT_GEN3_CTRL_EQ_PHASE_2_3_DISABLE_SHIFT);
	+
	+ al_reg_write32(&regs->port_regs->gen3_ctrl, reg);
	+
	+ reg = 0;
	+ AL_REG_FIELD_SET(reg, PCIE_PORT_GEN3_EQ_LF_MASK,
	+ PCIE_PORT_GEN3_EQ_LF_SHIFT,
	+ gen3_params->local_lf);
	+ AL_REG_FIELD_SET(reg, PCIE_PORT_GEN3_EQ_FS_MASK,
	+ PCIE_PORT_GEN3_EQ_FS_SHIFT,
	+ gen3_params->local_fs);
	+
	+ al_reg_write32(&regs->port_regs->gen3_eq_fs_lf, reg);
	+
	+ reg = 0;
	+ AL_REG_FIELD_SET(reg, PCIE_AXI_MISC_ZERO_LANEX_PHY_MAC_LOCAL_LF_MASK,
	+ PCIE_AXI_MISC_ZERO_LANEX_PHY_MAC_LOCAL_LF_SHIFT,
	+ gen3_params->local_lf);
	+ AL_REG_FIELD_SET(reg, PCIE_AXI_MISC_ZERO_LANEX_PHY_MAC_LOCAL_FS_MASK,
	+ PCIE_AXI_MISC_ZERO_LANEX_PHY_MAC_LOCAL_FS_SHIFT,
	+ gen3_params->local_fs);
	+ al_reg_write32(regs->axi.conf.zero_lane0, reg);
	+ al_reg_write32(regs->axi.conf.zero_lane1, reg);
	+ al_reg_write32(regs->axi.conf.zero_lane2, reg);
	+ al_reg_write32(regs->axi.conf.zero_lane3, reg);
	+ if (pcie_port->rev_id == AL_PCIE_REV_ID_3) {
	+ al_reg_write32(regs->axi.conf.zero_lane4, reg);
	+ al_reg_write32(regs->axi.conf.zero_lane5, reg);
	+ al_reg_write32(regs->axi.conf.zero_lane6, reg);
	+ al_reg_write32(regs->axi.conf.zero_lane7, reg);
	+ }
	+
	+ /*
	+ * Gen3 EQ Control Register:
	+ * - Preset Request Vector - request 9
	+ * - Behavior After 24 ms Timeout (when optimal settings are not
	+ * found): Recovery.Equalization.RcvrLock
	+ * - Phase2_3 2 ms Timeout Disable
	+ * - Feedback Mode - Figure Of Merit
	+ */
	+ reg = 0x00020031;
	+ al_reg_write32(&regs->port_regs->gen3_eq_ctrl, reg);
	+
	+ return 0;
	+}
	+
	+static int
	+al_pcie_port_tl_credits_config(
	+ struct al_pcie_port *pcie_port,
	+ const struct al_pcie_tl_credits_params *tl_credits __attribute__((__unused__)))
	+{
	+ al_err("PCIe %d: transport layer credits config not implemented\n",
	+ pcie_port->port_id);
	+
	+ return -ENOSYS;
	+
	+}
	+
	+static int
	+al_pcie_port_pf_params_config(struct al_pcie_pf *pcie_pf,
	+ const struct al_pcie_pf_config_params *pf_params)
	+{
	+ struct al_pcie_port *pcie_port = pcie_pf->pcie_port;
	+ struct al_pcie_regs *regs = pcie_port->regs;
	+ unsigned int pf_num = pcie_pf->pf_num;
	+ int bar_idx;
	+ int ret;
	+
	+ al_pcie_port_wr_to_ro_set(pcie_port, AL_TRUE);
	+
	+ /* Disable D1 and D3hot capabilities */
	+ if (pf_params->cap_d1_d3hot_dis)
	+ al_reg_write32_masked(
	+ regs->core_space[pf_num].pcie_pm_cap_base,
	+ AL_FIELD_MASK(26, 25) \| AL_FIELD_MASK(31, 28), 0);
	+
	+ /* Disable FLR capability */
	+ if (pf_params->cap_flr_dis)
	+ al_reg_write32_masked(
	+ regs->core_space[pf_num].pcie_dev_cap_base,
	+ AL_BIT(28), 0);
	+
	+ /* Disable ASPM capability */
	+ if (pf_params->cap_aspm_dis) {
	+ al_reg_write32_masked(
	+ regs->core_space[pf_num].pcie_cap_base + (AL_PCI_EXP_LNKCAP >> 2),
	+ AL_PCI_EXP_LNKCAP_ASPMS, 0);
	+ } else if (pcie_port->rev_id == AL_PCIE_REV_ID_0) {
	+ al_warn("%s: ASPM support is enabled, please disable it\n",
	+ __func__);
	+ ret = -EINVAL;
	+ goto done;
	+ }
	+
	+ if (!pf_params->bar_params_valid) {
	+ ret = 0;
	+ goto done;
	+ }
	+
	+ for (bar_idx = 0; bar_idx < 6;){ /* bar_idx will be incremented depending on bar type */
	+ const struct al_pcie_ep_bar_params *params = pf_params->bar_params + bar_idx;
	+ uint32_t mask = 0;
	+ uint32_t ctrl = 0;
	+ uint32_t __iomem *bar_addr = &regs->core_space[pf_num].config_header[(AL_PCI_BASE_ADDRESS_0 >> 2) + bar_idx];
	+
	+ if (params->enable) {
	+ uint64_t size = params->size;
	+
	+ if (params->memory_64_bit) {
	+ const struct al_pcie_ep_bar_params *next_params = params + 1;
	+ /* 64 bars start at even index (BAR0, BAR 2 or BAR 4) */
	+ if (bar_idx & 1) {
	+ ret = -EINVAL;
	+ goto done;
	+ }
	+
	+ /* next BAR must be disabled */
	+ if (next_params->enable) {
	+ ret = -EINVAL;
	+ goto done;
	+ }
	+
	+ /* 64 bar must be memory bar */
	+ if (!params->memory_space) {
	+ ret = -EINVAL;
	+ goto done;
	+ }
	+ } else {
	+ if (size > AL_PCIE_MAX_32_MEMORY_BAR_SIZE)
	+ return -EINVAL;
	+ /* 32 bit space can't be prefetchable */
	+ if (params->memory_is_prefetchable) {
	+ ret = -EINVAL;
	+ goto done;
	+ }
	+ }
	+
	+ if (params->memory_space) {
	+ if (size < AL_PCIE_MIN_MEMORY_BAR_SIZE) {
	+ al_err("PCIe %d: memory BAR %d: size (0x%llx) less that minimal allowed value\n",
	+ pcie_port->port_id, bar_idx, size);
	+ ret = -EINVAL;
	+ goto done;
	+ }
	+ } else {
	+ /* IO can't be prefetchable */
	+ if (params->memory_is_prefetchable) {
	+ ret = -EINVAL;
	+ goto done;
	+ }
	+
	+ if (size < AL_PCIE_MIN_IO_BAR_SIZE) {
	+ al_err("PCIe %d: IO BAR %d: size (0x%llx) less that minimal allowed value\n",
	+ pcie_port->port_id, bar_idx, size);
	+ ret = -EINVAL;
	+ goto done;
	+ }
	+ }
	+
	+ /* size must be power of 2 */
	+ if (size & (size - 1)) {
	+ al_err("PCIe %d: BAR %d:size (0x%llx) must be "
	+ "power of 2\n",
	+ pcie_port->port_id, bar_idx, size);
	+ ret = -EINVAL;
	+ goto done;
	+ }
	+
	+ /* If BAR is 64-bit, disable the next BAR before
	+ * configuring this one
	+ */
	+ if (params->memory_64_bit)
	+ al_reg_write32_dbi_cs2(pcie_port, bar_addr + 1, 0);
	+
	+ mask = 1; /* enable bit*/
	+ mask \|= (params->size - 1) & 0xFFFFFFFF;
	+
	+ al_reg_write32_dbi_cs2(pcie_port, bar_addr , mask);
	+
	+ if (params->memory_space == AL_FALSE)
	+ ctrl = AL_PCI_BASE_ADDRESS_SPACE_IO;
	+ if (params->memory_64_bit)
	+ ctrl \|= AL_PCI_BASE_ADDRESS_MEM_TYPE_64;
	+ if (params->memory_is_prefetchable)
	+ ctrl \|= AL_PCI_BASE_ADDRESS_MEM_PREFETCH;
	+ al_reg_write32(bar_addr, ctrl);
	+
	+ if (params->memory_64_bit) {
	+ mask = ((params->size - 1) >> 32) & 0xFFFFFFFF;
	+ al_reg_write32_dbi_cs2(pcie_port, bar_addr + 1, mask);
	+ }
	+
	+ } else {
	+ al_reg_write32_dbi_cs2(pcie_port, bar_addr , mask);
	+ }
	+ if (params->enable && params->memory_64_bit)
	+ bar_idx += 2;
	+ else
	+ bar_idx += 1;
	+ }
	+
	+ if (pf_params->exp_bar_params.enable) {
	+ if (pcie_port->rev_id != AL_PCIE_REV_ID_3) {
	+ al_err("PCIe %d: Expansion BAR enable not supported\n", pcie_port->port_id);
	+ ret = -ENOSYS;
	+ goto done;
	+ } else {
	+ /* Enable exp ROM */
	+ uint32_t __iomem *exp_rom_bar_addr =
	+ &regs->core_space[pf_num].config_header[AL_PCI_EXP_ROM_BASE_ADDRESS >> 2];
	+ uint32_t mask = 1; /* enable bit*/
	+ mask \|= (pf_params->exp_bar_params.size - 1) & 0xFFFFFFFF;
	+ al_reg_write32_dbi_cs2(pcie_port, exp_rom_bar_addr , mask);
	+ }
	+ } else if (pcie_port->rev_id == AL_PCIE_REV_ID_3) {
	+ /* Disable exp ROM */
	+ uint32_t __iomem *exp_rom_bar_addr =
	+ &regs->core_space[pf_num].config_header[AL_PCI_EXP_ROM_BASE_ADDRESS >> 2];
	+ al_reg_write32_dbi_cs2(pcie_port, exp_rom_bar_addr , 0);
	+ }
	+
	+ /* Open CPU generated msi and legacy interrupts in pcie wrapper logic */
	+ if ((pcie_port->rev_id == AL_PCIE_REV_ID_0) \|\|
	+ (pcie_port->rev_id == AL_PCIE_REV_ID_1)) {
	+ al_reg_write32(regs->app.soc_int[pf_num].mask_inta_leg_0, (1 << 21));
	+ } else if ((pcie_port->rev_id == AL_PCIE_REV_ID_2) \|\|
	+ (pcie_port->rev_id == AL_PCIE_REV_ID_3)) {
	+ al_reg_write32(regs->app.soc_int[pf_num].mask_inta_leg_3, (1 << 18));
	+ } else {
	+ al_assert(0);
	+ ret = -ENOSYS;
	+ goto done;
	+ }
	+
	+ /**
	+ * Addressing RMN: 1547
	+ *
	+ * RMN description:
	+ * 1. Whenever writing to 0x2xx offset, the write also happens to
	+ * 0x3xx address, meaning two registers are written instead of one.
	+ * 2. Read and write from 0x3xx work ok.
	+ *
	+ * Software flow:
	+ * Backup the value of the app.int_grp_a.mask_a register, because
	+ * app.int_grp_a.mask_clear_a gets overwritten during the write to
	+ * app.soc.mask_msi_leg_0 register.
	+ * Restore the original value after the write to app.soc.mask_msi_leg_0
	+ * register.
	+ */
	+ if (pcie_port->rev_id == AL_PCIE_REV_ID_0) {
	+ uint32_t backup;
	+
	+ backup = al_reg_read32(&regs->app.int_grp_a->mask);
	+ al_reg_write32(regs->app.soc_int[pf_num].mask_msi_leg_0, (1 << 22));
	+ al_reg_write32(&regs->app.int_grp_a->mask, backup);
	+ } else if (pcie_port->rev_id == AL_PCIE_REV_ID_1) {
	+ al_reg_write32(regs->app.soc_int[pf_num].mask_msi_leg_0, (1 << 22));
	+ } else if ((pcie_port->rev_id == AL_PCIE_REV_ID_2) \|\|
	+ (pcie_port->rev_id == AL_PCIE_REV_ID_3)) {
	+ al_reg_write32(regs->app.soc_int[pf_num].mask_msi_leg_3, (1 << 19));
	+ } else {
	+ al_assert(0);
	+ ret = -ENOSYS;
	+ goto done;
	+ }
	+
	+ ret = 0;
	+
	+done:
	+ al_pcie_port_wr_to_ro_set(pcie_port, AL_FALSE);
	+
	+ return ret;
	+}
	+
	+static void
	+al_pcie_port_features_config(
	+ struct al_pcie_port *pcie_port,
	+ const struct al_pcie_features *features)
	+{
	+ struct al_pcie_regs *regs = pcie_port->regs;
	+
	+ al_assert(pcie_port->rev_id > AL_PCIE_REV_ID_0);
	+
	+ al_reg_write32_masked(
	+ &regs->app.ctrl_gen->features,
	+ PCIE_W_CTRL_GEN_FEATURES_SATA_EP_MSI_FIX,
	+ features->sata_ep_msi_fix ?
	+ PCIE_W_CTRL_GEN_FEATURES_SATA_EP_MSI_FIX : 0);
	+}
	+
	+static int
	+al_pcie_port_sris_config(
	+ struct al_pcie_port *pcie_port,
	+ struct al_pcie_sris_params *sris_params,
	+ enum al_pcie_link_speed link_speed)
	+{
	+ int rc = 0;
	+ struct al_pcie_regs *regs = pcie_port->regs;
	+
	+ if (sris_params->use_defaults) {
	+ sris_params->kp_counter_gen3 = (pcie_port->rev_id > AL_PCIE_REV_ID_1) ?
	+ PCIE_SRIS_KP_COUNTER_GEN3_DEFAULT_VAL : 0;
	+ sris_params->kp_counter_gen21 = PCIE_SRIS_KP_COUNTER_GEN21_DEFAULT_VAL;
	+
	+ al_dbg("PCIe %d: configuring SRIS with default values kp_gen3[%d] kp_gen21[%d]\n",
	+ pcie_port->port_id,
	+ sris_params->kp_counter_gen3,
	+ sris_params->kp_counter_gen21);
	+ }
	+
	+ switch (pcie_port->rev_id) {
	+ case AL_PCIE_REV_ID_3:
	+ case AL_PCIE_REV_ID_2:
	+ al_reg_write32_masked(regs->app.global_ctrl.sris_kp_counter,
	+ PCIE_W_GLOBAL_CTRL_SRIS_KP_COUNTER_VALUE_GEN3_SRIS_MASK \|
	+ PCIE_W_GLOBAL_CTRL_SRIS_KP_COUNTER_VALUE_GEN21_SRIS_MASK \|
	+ PCIE_W_GLOBAL_CTRL_SRIS_KP_COUNTER_VALUE_PCIE_X4_SRIS_EN,
	+ (sris_params->kp_counter_gen3 <<
	+ PCIE_W_GLOBAL_CTRL_SRIS_KP_COUNTER_VALUE_GEN3_SRIS_SHIFT) \|
	+ (sris_params->kp_counter_gen21 <<
	+ PCIE_W_GLOBAL_CTRL_SRIS_KP_COUNTER_VALUE_GEN21_SRIS_SHIFT) \|
	+ PCIE_W_GLOBAL_CTRL_SRIS_KP_COUNTER_VALUE_PCIE_X4_SRIS_EN);
	+ break;
	+
	+ case AL_PCIE_REV_ID_1:
	+ if ((link_speed == AL_PCIE_LINK_SPEED_GEN3) && (sris_params->kp_counter_gen3)) {
	+ al_err("PCIe %d: cannot config Gen%d SRIS with rev_id[%d]\n",
	+ pcie_port->port_id, al_pcie_speed_gen_code(link_speed),
	+ pcie_port->rev_id);
	+ return -EINVAL;
	+ }
	+
	+ al_reg_write32_masked(&regs->port_regs->filter_mask_reg_1,
	+ PCIE_FLT_MASK_SKP_INT_VAL_MASK,
	+ sris_params->kp_counter_gen21);
	+ break;
	+
	+ default:
	+ al_err("PCIe %d: SRIS config is not supported in rev_id[%d]\n",
	+ pcie_port->port_id, pcie_port->rev_id);
	+ al_assert(0);
	+ return -EINVAL;
	+ }
	+
	+ return rc;
	+}
	+
	+static void
	+al_pcie_port_ib_hcrd_config(struct al_pcie_port *pcie_port)
	+{
	+ struct al_pcie_regs *regs = pcie_port->regs;
	+
	+ al_reg_write32_masked(
	+ &regs->port_regs->vc0_posted_rcv_q_ctrl,
	+ RADM_PQ_HCRD_VC0_MASK,
	+ (pcie_port->ib_hcrd_config.nof_p_hdr - 1)
	+ << RADM_PQ_HCRD_VC0_SHIFT);
	+
	+ al_reg_write32_masked(
	+ &regs->port_regs->vc0_non_posted_rcv_q_ctrl,
	+ RADM_NPQ_HCRD_VC0_MASK,
	+ (pcie_port->ib_hcrd_config.nof_np_hdr - 1)
	+ << RADM_NPQ_HCRD_VC0_SHIFT);
	+}
	+
	+static unsigned int
	+al_pcie_port_max_num_of_pfs_get(struct al_pcie_port *pcie_port)
	+{
	+ struct al_pcie_regs *regs = pcie_port->regs;
	+ uint32_t max_func_num;
	+ uint32_t max_num_of_pfs;
	+
	+ /**
	+ * Only in REV3, when port is already enabled, max_num_of_pfs is already
	+ * initialized, return it. Otherwise, return default: 1 PF
	+ */
	+ if ((pcie_port->rev_id == AL_PCIE_REV_ID_3)
	+ && al_pcie_port_is_enabled(pcie_port)) {
	+ max_func_num = al_reg_read32(&regs->port_regs->timer_ctrl_max_func_num);
	+ max_num_of_pfs = AL_REG_FIELD_GET(max_func_num, PCIE_PORT_GEN3_MAX_FUNC_NUM, 0) + 1;
	+ return max_num_of_pfs;
	+ }
	+ return 1;
	+}
	+
	+/******************************************************************************/
	+/*************************** API Implementation ***************************/
	+/******************************************************************************/
	+
	+/************************* PCIe Initialization API ************************/
	+
	+/**
	+ * Initializes a PCIe port handle structure
	+ * Caution: this function should not read/write to any register except for
	+ * reading RO register (REV_ID for example)
	+ */
	+int
	+al_pcie_port_handle_init(
	+ struct al_pcie_port *pcie_port,
	+ void __iomem *pcie_reg_base,
	+ void __iomem *pbs_reg_base,
	+ unsigned int port_id)
	+{
	+ int i, ret;
	+
	+ pcie_port->pcie_reg_base = pcie_reg_base;
	+ pcie_port->regs = &pcie_port->regs_ptrs;
	+ pcie_port->ex_regs = NULL;
	+ pcie_port->pbs_regs = pbs_reg_base;
	+ pcie_port->port_id = port_id;
	+ pcie_port->max_lanes = 0;
	+
	+ ret = al_pcie_rev_id_get(pbs_reg_base, pcie_reg_base);
	+ if (ret < 0)
	+ return ret;
	+
	+ pcie_port->rev_id = ret;
	+
	+ /* Zero all regs */
	+ al_memset(pcie_port->regs, 0, sizeof(struct al_pcie_regs));
	+
	+ if ((pcie_port->rev_id == AL_PCIE_REV_ID_0) \|\|
	+ (pcie_port->rev_id == AL_PCIE_REV_ID_1)) {
	+ struct al_pcie_rev1_regs __iomem *regs =
	+ (struct al_pcie_rev1_regs __iomem *)pcie_reg_base;
	+
	+ pcie_port->regs->axi.ctrl.global = &regs->axi.ctrl.global;
	+ pcie_port->regs->axi.ctrl.master_arctl = &regs->axi.ctrl.master_arctl;
	+ pcie_port->regs->axi.ctrl.master_awctl = &regs->axi.ctrl.master_awctl;
	+ pcie_port->regs->axi.ctrl.slv_ctl = &regs->axi.ctrl.slv_ctl;
	+ pcie_port->regs->axi.ob_ctrl.cfg_target_bus = &regs->axi.ob_ctrl.cfg_target_bus;
	+ pcie_port->regs->axi.ob_ctrl.cfg_control = &regs->axi.ob_ctrl.cfg_control;
	+ pcie_port->regs->axi.ob_ctrl.io_start_l = &regs->axi.ob_ctrl.io_start_l;
	+ pcie_port->regs->axi.ob_ctrl.io_start_h = &regs->axi.ob_ctrl.io_start_h;
	+ pcie_port->regs->axi.ob_ctrl.io_limit_l = &regs->axi.ob_ctrl.io_limit_l;
	+ pcie_port->regs->axi.ob_ctrl.io_limit_h = &regs->axi.ob_ctrl.io_limit_h;
	+ pcie_port->regs->axi.pcie_global.conf = &regs->axi.pcie_global.conf;
	+ pcie_port->regs->axi.conf.zero_lane0 = &regs->axi.conf.zero_lane0;
	+ pcie_port->regs->axi.conf.zero_lane1 = &regs->axi.conf.zero_lane1;
	+ pcie_port->regs->axi.conf.zero_lane2 = &regs->axi.conf.zero_lane2;
	+ pcie_port->regs->axi.conf.zero_lane3 = &regs->axi.conf.zero_lane3;
	+ pcie_port->regs->axi.status.lane[0] = &regs->axi.status.lane0;
	+ pcie_port->regs->axi.status.lane[1] = &regs->axi.status.lane1;
	+ pcie_port->regs->axi.status.lane[2] = &regs->axi.status.lane2;
	+ pcie_port->regs->axi.status.lane[3] = &regs->axi.status.lane3;
	+ pcie_port->regs->axi.parity.en_axi = &regs->axi.parity.en_axi;
	+ pcie_port->regs->axi.ordering.pos_cntl = &regs->axi.ordering.pos_cntl;
	+ pcie_port->regs->axi.pre_configuration.pcie_core_setup = &regs->axi.pre_configuration.pcie_core_setup;
	+ pcie_port->regs->axi.init_fc.cfg = &regs->axi.init_fc.cfg;
	+ pcie_port->regs->axi.int_grp_a = &regs->axi.int_grp_a;
	+
	+ pcie_port->regs->app.global_ctrl.port_init = &regs->app.global_ctrl.port_init;
	+ pcie_port->regs->app.global_ctrl.pm_control = &regs->app.global_ctrl.pm_control;
	+ pcie_port->regs->app.global_ctrl.events_gen[0] = &regs->app.global_ctrl.events_gen;
	+ pcie_port->regs->app.debug = &regs->app.debug;
	+ pcie_port->regs->app.soc_int[0].mask_inta_leg_0 = &regs->app.soc_int.mask_inta_leg_0;
	+ pcie_port->regs->app.soc_int[0].mask_msi_leg_0 = &regs->app.soc_int.mask_msi_leg_0;
	+ pcie_port->regs->app.ctrl_gen = &regs->app.ctrl_gen;
	+ pcie_port->regs->app.parity = &regs->app.parity;
	+ pcie_port->regs->app.atu.in_mask_pair = regs->app.atu.in_mask_pair;
	+ pcie_port->regs->app.atu.out_mask_pair = regs->app.atu.out_mask_pair;
	+
	+ if (pcie_port->rev_id == AL_PCIE_REV_ID_0) {
	+ pcie_port->regs->app.int_grp_a = &regs->app.int_grp_a_m0;
	+ pcie_port->regs->app.int_grp_b = &regs->app.int_grp_b_m0;
	+ } else {
	+ pcie_port->regs->app.int_grp_a = &regs->app.int_grp_a;
	+ pcie_port->regs->app.int_grp_b = &regs->app.int_grp_b;
	+ }
	+
	+ pcie_port->regs->core_space[0].config_header = regs->core_space.config_header;
	+ pcie_port->regs->core_space[0].pcie_pm_cap_base = &regs->core_space.pcie_pm_cap_base;
	+ pcie_port->regs->core_space[0].pcie_cap_base = &regs->core_space.pcie_cap_base;
	+ pcie_port->regs->core_space[0].pcie_dev_cap_base = &regs->core_space.pcie_dev_cap_base;
	+ pcie_port->regs->core_space[0].pcie_dev_ctrl_status = &regs->core_space.pcie_dev_ctrl_status;
	+ pcie_port->regs->core_space[0].pcie_link_cap_base = &regs->core_space.pcie_link_cap_base;
	+ pcie_port->regs->core_space[0].msix_cap_base = &regs->core_space.msix_cap_base;
	+ pcie_port->regs->core_space[0].aer = &regs->core_space.aer;
	+ pcie_port->regs->core_space[0].pcie_sec_ext_cap_base = &regs->core_space.pcie_sec_ext_cap_base;
	+
	+ pcie_port->regs->port_regs = &regs->core_space.port_regs;
	+
	+ } else if (pcie_port->rev_id == AL_PCIE_REV_ID_2) {
	+ struct al_pcie_rev2_regs __iomem *regs =
	+ (struct al_pcie_rev2_regs __iomem *)pcie_reg_base;
	+
	+ pcie_port->regs->axi.ctrl.global = &regs->axi.ctrl.global;
	+ pcie_port->regs->axi.ctrl.master_arctl = &regs->axi.ctrl.master_arctl;
	+ pcie_port->regs->axi.ctrl.master_awctl = &regs->axi.ctrl.master_awctl;
	+ pcie_port->regs->axi.ctrl.slv_ctl = &regs->axi.ctrl.slv_ctl;
	+ pcie_port->regs->axi.ob_ctrl.cfg_target_bus = &regs->axi.ob_ctrl.cfg_target_bus;
	+ pcie_port->regs->axi.ob_ctrl.cfg_control = &regs->axi.ob_ctrl.cfg_control;
	+ pcie_port->regs->axi.ob_ctrl.io_start_l = &regs->axi.ob_ctrl.io_start_l;
	+ pcie_port->regs->axi.ob_ctrl.io_start_h = &regs->axi.ob_ctrl.io_start_h;
	+ pcie_port->regs->axi.ob_ctrl.io_limit_l = &regs->axi.ob_ctrl.io_limit_l;
	+ pcie_port->regs->axi.ob_ctrl.io_limit_h = &regs->axi.ob_ctrl.io_limit_h;
	+ pcie_port->regs->axi.pcie_global.conf = &regs->axi.pcie_global.conf;
	+ pcie_port->regs->axi.conf.zero_lane0 = &regs->axi.conf.zero_lane0;
	+ pcie_port->regs->axi.conf.zero_lane1 = &regs->axi.conf.zero_lane1;
	+ pcie_port->regs->axi.conf.zero_lane2 = &regs->axi.conf.zero_lane2;
	+ pcie_port->regs->axi.conf.zero_lane3 = &regs->axi.conf.zero_lane3;
	+ pcie_port->regs->axi.status.lane[0] = &regs->axi.status.lane0;
	+ pcie_port->regs->axi.status.lane[1] = &regs->axi.status.lane1;
	+ pcie_port->regs->axi.status.lane[2] = &regs->axi.status.lane2;
	+ pcie_port->regs->axi.status.lane[3] = &regs->axi.status.lane3;
	+ pcie_port->regs->axi.parity.en_axi = &regs->axi.parity.en_axi;
	+ pcie_port->regs->axi.ordering.pos_cntl = &regs->axi.ordering.pos_cntl;
	+ pcie_port->regs->axi.pre_configuration.pcie_core_setup = &regs->axi.pre_configuration.pcie_core_setup;
	+ pcie_port->regs->axi.init_fc.cfg = &regs->axi.init_fc.cfg;
	+ pcie_port->regs->axi.int_grp_a = &regs->axi.int_grp_a;
	+
	+ pcie_port->regs->app.global_ctrl.port_init = &regs->app.global_ctrl.port_init;
	+ pcie_port->regs->app.global_ctrl.pm_control = &regs->app.global_ctrl.pm_control;
	+ pcie_port->regs->app.global_ctrl.events_gen[0] = &regs->app.global_ctrl.events_gen;
	+ pcie_port->regs->app.global_ctrl.corr_err_sts_int = &regs->app.global_ctrl.pended_corr_err_sts_int;
	+ pcie_port->regs->app.global_ctrl.uncorr_err_sts_int = &regs->app.global_ctrl.pended_uncorr_err_sts_int;
	+ pcie_port->regs->app.debug = &regs->app.debug;
	+ pcie_port->regs->app.ap_user_send_msg = &regs->app.ap_user_send_msg;
	+ pcie_port->regs->app.soc_int[0].mask_inta_leg_0 = &regs->app.soc_int.mask_inta_leg_0;
	+ pcie_port->regs->app.soc_int[0].mask_inta_leg_3 = &regs->app.soc_int.mask_inta_leg_3;
	+ pcie_port->regs->app.soc_int[0].mask_msi_leg_0 = &regs->app.soc_int.mask_msi_leg_0;
	+ pcie_port->regs->app.soc_int[0].mask_msi_leg_3 = &regs->app.soc_int.mask_msi_leg_3;
	+ pcie_port->regs->app.ctrl_gen = &regs->app.ctrl_gen;
	+ pcie_port->regs->app.parity = &regs->app.parity;
	+ pcie_port->regs->app.atu.in_mask_pair = regs->app.atu.in_mask_pair;
	+ pcie_port->regs->app.atu.out_mask_pair = regs->app.atu.out_mask_pair;
	+ pcie_port->regs->app.status_per_func[0] = &regs->app.status_per_func;
	+ pcie_port->regs->app.int_grp_a = &regs->app.int_grp_a;
	+ pcie_port->regs->app.int_grp_b = &regs->app.int_grp_b;
	+
	+ pcie_port->regs->core_space[0].config_header = regs->core_space.config_header;
	+ pcie_port->regs->core_space[0].pcie_pm_cap_base = &regs->core_space.pcie_pm_cap_base;
	+ pcie_port->regs->core_space[0].pcie_cap_base = &regs->core_space.pcie_cap_base;
	+ pcie_port->regs->core_space[0].pcie_dev_cap_base = &regs->core_space.pcie_dev_cap_base;
	+ pcie_port->regs->core_space[0].pcie_dev_ctrl_status = &regs->core_space.pcie_dev_ctrl_status;
	+ pcie_port->regs->core_space[0].pcie_link_cap_base = &regs->core_space.pcie_link_cap_base;
	+ pcie_port->regs->core_space[0].msix_cap_base = &regs->core_space.msix_cap_base;
	+ pcie_port->regs->core_space[0].aer = &regs->core_space.aer;
	+ pcie_port->regs->core_space[0].pcie_sec_ext_cap_base = &regs->core_space.pcie_sec_ext_cap_base;
	+
	+ pcie_port->regs->port_regs = &regs->core_space.port_regs;
	+
	+ } else if (pcie_port->rev_id == AL_PCIE_REV_ID_3) {
	+ struct al_pcie_rev3_regs __iomem *regs =
	+ (struct al_pcie_rev3_regs __iomem *)pcie_reg_base;
	+ pcie_port->regs->axi.ctrl.global = &regs->axi.ctrl.global;
	+ pcie_port->regs->axi.ctrl.master_arctl = &regs->axi.ctrl.master_arctl;
	+ pcie_port->regs->axi.ctrl.master_awctl = &regs->axi.ctrl.master_awctl;
	+ pcie_port->regs->axi.ctrl.slv_ctl = &regs->axi.ctrl.slv_ctl;
	+ pcie_port->regs->axi.ob_ctrl.cfg_target_bus = &regs->axi.ob_ctrl.cfg_target_bus;
	+ pcie_port->regs->axi.ob_ctrl.cfg_control = &regs->axi.ob_ctrl.cfg_control;
	+ pcie_port->regs->axi.ob_ctrl.io_start_l = &regs->axi.ob_ctrl.io_start_l;
	+ pcie_port->regs->axi.ob_ctrl.io_start_h = &regs->axi.ob_ctrl.io_start_h;
	+ pcie_port->regs->axi.ob_ctrl.io_limit_l = &regs->axi.ob_ctrl.io_limit_l;
	+ pcie_port->regs->axi.ob_ctrl.io_limit_h = &regs->axi.ob_ctrl.io_limit_h;
	+ pcie_port->regs->axi.pcie_global.conf = &regs->axi.pcie_global.conf;
	+ pcie_port->regs->axi.conf.zero_lane0 = &regs->axi.conf.zero_lane0;
	+ pcie_port->regs->axi.conf.zero_lane1 = &regs->axi.conf.zero_lane1;
	+ pcie_port->regs->axi.conf.zero_lane2 = &regs->axi.conf.zero_lane2;
	+ pcie_port->regs->axi.conf.zero_lane3 = &regs->axi.conf.zero_lane3;
	+ pcie_port->regs->axi.conf.zero_lane4 = &regs->axi.conf.zero_lane4;
	+ pcie_port->regs->axi.conf.zero_lane5 = &regs->axi.conf.zero_lane5;
	+ pcie_port->regs->axi.conf.zero_lane6 = &regs->axi.conf.zero_lane6;
	+ pcie_port->regs->axi.conf.zero_lane7 = &regs->axi.conf.zero_lane7;
	+ pcie_port->regs->axi.status.lane[0] = &regs->axi.status.lane0;
	+ pcie_port->regs->axi.status.lane[1] = &regs->axi.status.lane1;
	+ pcie_port->regs->axi.status.lane[2] = &regs->axi.status.lane2;
	+ pcie_port->regs->axi.status.lane[3] = &regs->axi.status.lane3;
	+ pcie_port->regs->axi.status.lane[4] = &regs->axi.status.lane4;
	+ pcie_port->regs->axi.status.lane[5] = &regs->axi.status.lane5;
	+ pcie_port->regs->axi.status.lane[6] = &regs->axi.status.lane6;
	+ pcie_port->regs->axi.status.lane[7] = &regs->axi.status.lane7;
	+ pcie_port->regs->axi.parity.en_axi = &regs->axi.parity.en_axi;
	+ pcie_port->regs->axi.ordering.pos_cntl = &regs->axi.ordering.pos_cntl;
	+ pcie_port->regs->axi.pre_configuration.pcie_core_setup = &regs->axi.pre_configuration.pcie_core_setup;
	+ pcie_port->regs->axi.init_fc.cfg = &regs->axi.init_fc.cfg;
	+ pcie_port->regs->axi.int_grp_a = &regs->axi.int_grp_a;
	+ pcie_port->regs->axi.axi_attr_ovrd.write_msg_ctrl_0 = &regs->axi.axi_attr_ovrd.write_msg_ctrl_0;
	+ pcie_port->regs->axi.axi_attr_ovrd.write_msg_ctrl_1 = &regs->axi.axi_attr_ovrd.write_msg_ctrl_1;
	+ pcie_port->regs->axi.axi_attr_ovrd.pf_sel = &regs->axi.axi_attr_ovrd.pf_sel;
	+
	+ for (i = 0; i < AL_MAX_NUM_OF_PFS; i++) {
	+ pcie_port->regs->axi.pf_axi_attr_ovrd[i].func_ctrl_0 = &regs->axi.pf_axi_attr_ovrd[i].func_ctrl_0;
	+ pcie_port->regs->axi.pf_axi_attr_ovrd[i].func_ctrl_1 = &regs->axi.pf_axi_attr_ovrd[i].func_ctrl_1;
	+ pcie_port->regs->axi.pf_axi_attr_ovrd[i].func_ctrl_2 = &regs->axi.pf_axi_attr_ovrd[i].func_ctrl_2;
	+ pcie_port->regs->axi.pf_axi_attr_ovrd[i].func_ctrl_3 = &regs->axi.pf_axi_attr_ovrd[i].func_ctrl_3;
	+ pcie_port->regs->axi.pf_axi_attr_ovrd[i].func_ctrl_4 = &regs->axi.pf_axi_attr_ovrd[i].func_ctrl_4;
	+ pcie_port->regs->axi.pf_axi_attr_ovrd[i].func_ctrl_5 = &regs->axi.pf_axi_attr_ovrd[i].func_ctrl_5;
	+ pcie_port->regs->axi.pf_axi_attr_ovrd[i].func_ctrl_6 = &regs->axi.pf_axi_attr_ovrd[i].func_ctrl_6;
	+ pcie_port->regs->axi.pf_axi_attr_ovrd[i].func_ctrl_7 = &regs->axi.pf_axi_attr_ovrd[i].func_ctrl_7;
	+ pcie_port->regs->axi.pf_axi_attr_ovrd[i].func_ctrl_8 = &regs->axi.pf_axi_attr_ovrd[i].func_ctrl_8;
	+ pcie_port->regs->axi.pf_axi_attr_ovrd[i].func_ctrl_9 = &regs->axi.pf_axi_attr_ovrd[i].func_ctrl_9;
	+ }
	+
	+ pcie_port->regs->axi.msg_attr_axuser_table.entry_vec = &regs->axi.msg_attr_axuser_table.entry_vec;
	+
	+ pcie_port->regs->app.global_ctrl.port_init = &regs->app.global_ctrl.port_init;
	+ pcie_port->regs->app.global_ctrl.pm_control = &regs->app.global_ctrl.pm_control;
	+ pcie_port->regs->app.global_ctrl.corr_err_sts_int = &regs->app.global_ctrl.pended_corr_err_sts_int;
	+ pcie_port->regs->app.global_ctrl.uncorr_err_sts_int = &regs->app.global_ctrl.pended_uncorr_err_sts_int;
	+
	+ for (i = 0; i < AL_MAX_NUM_OF_PFS; i++) {
	+ pcie_port->regs->app.global_ctrl.events_gen[i] = &regs->app.events_gen_per_func[i].events_gen;
	+ }
	+
	+ pcie_port->regs->app.global_ctrl.sris_kp_counter = &regs->app.global_ctrl.sris_kp_counter_value;
	+ pcie_port->regs->app.debug = &regs->app.debug;
	+
	+ for (i = 0; i < AL_MAX_NUM_OF_PFS; i++) {
	+ pcie_port->regs->app.soc_int[i].mask_inta_leg_0 = &regs->app.soc_int_per_func[i].mask_inta_leg_0;
	+ pcie_port->regs->app.soc_int[i].mask_inta_leg_3 = &regs->app.soc_int_per_func[i].mask_inta_leg_3;
	+ pcie_port->regs->app.soc_int[i].mask_msi_leg_0 = &regs->app.soc_int_per_func[i].mask_msi_leg_0;
	+ pcie_port->regs->app.soc_int[i].mask_msi_leg_3 = &regs->app.soc_int_per_func[i].mask_msi_leg_3;
	+ }
	+
	+ pcie_port->regs->app.ap_user_send_msg = &regs->app.ap_user_send_msg;
	+ pcie_port->regs->app.ctrl_gen = &regs->app.ctrl_gen;
	+ pcie_port->regs->app.parity = &regs->app.parity;
	+ pcie_port->regs->app.atu.in_mask_pair = regs->app.atu.in_mask_pair;
	+ pcie_port->regs->app.atu.out_mask_pair = regs->app.atu.out_mask_pair;
	+
	+ for (i = 0; i < AL_MAX_NUM_OF_PFS; i++)
	+ pcie_port->regs->app.status_per_func[i] = &regs->app.status_per_func[i];
	+
	+ pcie_port->regs->app.int_grp_a = &regs->app.int_grp_a;
	+ pcie_port->regs->app.int_grp_b = &regs->app.int_grp_b;
	+ pcie_port->regs->app.int_grp_c = &regs->app.int_grp_c;
	+ pcie_port->regs->app.int_grp_d = &regs->app.int_grp_d;
	+
	+ for (i = 0; i < AL_MAX_NUM_OF_PFS; i++) {
	+ pcie_port->regs->core_space[i].config_header = regs->core_space.func[i].config_header;
	+ pcie_port->regs->core_space[i].pcie_pm_cap_base = &regs->core_space.func[i].pcie_pm_cap_base;
	+ pcie_port->regs->core_space[i].pcie_cap_base = &regs->core_space.func[i].pcie_cap_base;
	+ pcie_port->regs->core_space[i].pcie_dev_cap_base = &regs->core_space.func[i].pcie_dev_cap_base;
	+ pcie_port->regs->core_space[i].pcie_dev_ctrl_status = &regs->core_space.func[i].pcie_dev_ctrl_status;
	+ pcie_port->regs->core_space[i].pcie_link_cap_base = &regs->core_space.func[i].pcie_link_cap_base;
	+ pcie_port->regs->core_space[i].msix_cap_base = &regs->core_space.func[i].msix_cap_base;
	+ pcie_port->regs->core_space[i].aer = &regs->core_space.func[i].aer;
	+ pcie_port->regs->core_space[i].tph_cap_base = &regs->core_space.func[i].tph_cap_base;
	+
	+ }
	+
	+ /* secondary extension capability only for PF0 */
	+ pcie_port->regs->core_space[0].pcie_sec_ext_cap_base = &regs->core_space.func[0].pcie_sec_ext_cap_base;
	+
	+ pcie_port->regs->port_regs = &regs->core_space.func[0].port_regs;
	+
	+ } else {
	+ al_warn("%s: Revision ID is unknown\n",
	+ __func__);
	+ return -EINVAL;
	+ }
	+
	+ /* set maximum number of physical functions */
	+ pcie_port->max_num_of_pfs = al_pcie_port_max_num_of_pfs_get(pcie_port);
	+
	+ al_dbg("pcie port handle initialized. port id: %d, rev_id %d, regs base %p\n",
	+ port_id, pcie_port->rev_id, pcie_reg_base);
	+ return 0;
	+}
	+
	+/**
	+ * Initializes a PCIe Physical function handle structure
	+ * Caution: this function should not read/write to any register except for
	+ * reading RO register (REV_ID for example)
	+ */
	+int
	+al_pcie_pf_handle_init(
	+ struct al_pcie_pf *pcie_pf,
	+ struct al_pcie_port *pcie_port,
	+ unsigned int pf_num)
	+{
	+ enum al_pcie_operating_mode op_mode = al_pcie_operating_mode_get(pcie_port);
	+ al_assert(pf_num < pcie_port->max_num_of_pfs);
	+
	+ if (op_mode != AL_PCIE_OPERATING_MODE_EP) {
	+ al_err("PCIe %d: can't init PF handle with operating mode [%d]\n",
	+ pcie_port->port_id, op_mode);
	+ return -EINVAL;
	+ }
	+
	+ pcie_pf->pf_num = pf_num;
	+ pcie_pf->pcie_port = pcie_port;
	+
	+ al_dbg("PCIe %d: pf handle initialized. pf number: %d, rev_id %d, regs %p\n",
	+ pcie_port->port_id, pcie_pf->pf_num, pcie_port->rev_id,
	+ pcie_port->regs);
	+ return 0;
	+}
	+
	+/************************ Pre PCIe Port Enable API ************************/
	+
	+/** configure pcie operating mode (root complex or endpoint) */
	+int
	+al_pcie_port_operating_mode_config(
	+ struct al_pcie_port *pcie_port,
	+ enum al_pcie_operating_mode mode)
	+{
	+ struct al_pcie_regs *regs = pcie_port->regs;
	+ uint32_t reg, device_type, new_device_type;
	+
	+ if (al_pcie_port_is_enabled(pcie_port)) {
	+ al_err("PCIe %d: already enabled, cannot set operating mode\n",
	+ pcie_port->port_id);
	+ return -EINVAL;
	+ }
	+
	+ reg = al_reg_read32(regs->axi.pcie_global.conf);
	+
	+ device_type = AL_REG_FIELD_GET(reg,
	+ PCIE_AXI_MISC_PCIE_GLOBAL_CONF_DEV_TYPE_MASK,
	+ PCIE_AXI_MISC_PCIE_GLOBAL_CONF_DEV_TYPE_SHIFT);
	+ if (mode == AL_PCIE_OPERATING_MODE_EP) {
	+ new_device_type = PCIE_AXI_MISC_PCIE_GLOBAL_CONF_DEV_TYPE_EP;
	+ } else if (mode == AL_PCIE_OPERATING_MODE_RC) {
	+ new_device_type = PCIE_AXI_MISC_PCIE_GLOBAL_CONF_DEV_TYPE_RC;
	+
	+ if (pcie_port->rev_id == AL_PCIE_REV_ID_3) {
	+ /* config 1 PF in RC mode */
	+ al_reg_write32_masked(regs->axi.axi_attr_ovrd.pf_sel,
	+ PCIE_AXI_AXI_ATTR_OVRD_PF_SEL_PF_BIT0_OVRD_FROM_AXUSER \|
	+ PCIE_AXI_AXI_ATTR_OVRD_PF_SEL_PF_BIT0_OVRD_FROM_REG \|
	+ PCIE_AXI_AXI_ATTR_OVRD_PF_SEL_PF_BIT0_ADDR_OFFSET_MASK \|
	+ PCIE_AXI_AXI_ATTR_OVRD_PF_SEL_CFG_PF_BIT0_OVRD \|
	+ PCIE_AXI_AXI_ATTR_OVRD_PF_SEL_PF_BIT1_OVRD_FROM_AXUSER \|
	+ PCIE_AXI_AXI_ATTR_OVRD_PF_SEL_PF_BIT1_OVRD_FROM_REG \|
	+ PCIE_AXI_AXI_ATTR_OVRD_PF_SEL_PF_BIT1_ADDR_OFFSET_MASK \|
	+ PCIE_AXI_AXI_ATTR_OVRD_PF_SEL_CFG_PF_BIT1_OVRD,
	+ PCIE_AXI_AXI_ATTR_OVRD_PF_SEL_PF_BIT0_OVRD_FROM_REG \|
	+ PCIE_AXI_AXI_ATTR_OVRD_PF_SEL_PF_BIT1_OVRD_FROM_REG);
	+ }
	+ } else {
	+ al_err("PCIe %d: unknown operating mode: %d\n", pcie_port->port_id, mode);
	+ return -EINVAL;
	+ }
	+
	+ if (new_device_type == device_type) {
	+ al_dbg("PCIe %d: operating mode already set to %s\n",
	+ pcie_port->port_id, (mode == AL_PCIE_OPERATING_MODE_EP) ?
	+ "EndPoint" : "Root Complex");
	+ return 0;
	+ }
	+ al_info("PCIe %d: set operating mode to %s\n",
	+ pcie_port->port_id, (mode == AL_PCIE_OPERATING_MODE_EP) ?
	+ "EndPoint" : "Root Complex");
	+ AL_REG_FIELD_SET(reg, PCIE_AXI_MISC_PCIE_GLOBAL_CONF_DEV_TYPE_MASK,
	+ PCIE_AXI_MISC_PCIE_GLOBAL_CONF_DEV_TYPE_SHIFT,
	+ new_device_type);
	+
	+ al_reg_write32(regs->axi.pcie_global.conf, reg);
	+
	+ return 0;
	+}
	+
	+int
	+al_pcie_port_max_lanes_set(struct al_pcie_port *pcie_port, uint8_t lanes)
	+{
	+ struct al_pcie_regs *regs = pcie_port->regs;
	+
	+ if (al_pcie_port_is_enabled(pcie_port)) {
	+ al_err("PCIe %d: already enabled, cannot set max lanes\n",
	+ pcie_port->port_id);
	+ return -EINVAL;
	+ }
	+
	+ /* convert to bitmask format (4 ->'b1111, 2 ->'b11, 1 -> 'b1) */
	+ uint32_t active_lanes_val = AL_PCIE_PARSE_LANES(lanes);
	+
	+ al_reg_write32_masked(regs->axi.pcie_global.conf,
	+ (pcie_port->rev_id == AL_PCIE_REV_ID_3) ?
	+ PCIE_REV3_AXI_MISC_PCIE_GLOBAL_CONF_NOF_ACT_LANES_MASK :
	+ PCIE_REV1_2_AXI_MISC_PCIE_GLOBAL_CONF_NOF_ACT_LANES_MASK,
	+ active_lanes_val);
	+
	+ pcie_port->max_lanes = lanes;
	+ return 0;
	+}
	+
	+int
	+al_pcie_port_max_num_of_pfs_set(
	+ struct al_pcie_port *pcie_port,
	+ uint8_t max_num_of_pfs)
	+{
	+ if (al_pcie_port_is_enabled(pcie_port)) {
	+ al_err("PCIe %d: already enabled, cannot set max num of PFs\n",
	+ pcie_port->port_id);
	+ return -EINVAL;
	+ }
	+
	+ if (pcie_port->rev_id == AL_PCIE_REV_ID_3)
	+ al_assert(max_num_of_pfs <= REV3_MAX_NUM_OF_PFS);
	+ else
	+ al_assert(max_num_of_pfs == REV1_2_MAX_NUM_OF_PFS);
	+
	+ pcie_port->max_num_of_pfs = max_num_of_pfs;
	+
	+ return 0;
	+}
	+
	+/* Inbound header credits and outstanding outbound reads configuration */
	+int
	+al_pcie_port_ib_hcrd_os_ob_reads_config(
	+ struct al_pcie_port *pcie_port,
	+ struct al_pcie_ib_hcrd_os_ob_reads_config *ib_hcrd_os_ob_reads_config)
	+{
	+ struct al_pcie_regs *regs = pcie_port->regs;
	+
	+ if (al_pcie_port_is_enabled(pcie_port)) {
	+ al_err("PCIe %d: already enabled, cannot configure IB credits and OB OS reads\n",
	+ pcie_port->port_id);
	+ return -EINVAL;
	+ }
	+
	+ al_assert(ib_hcrd_os_ob_reads_config->nof_np_hdr > 0);
	+
	+ al_assert(ib_hcrd_os_ob_reads_config->nof_p_hdr > 0);
	+
	+ al_assert(ib_hcrd_os_ob_reads_config->nof_cpl_hdr > 0);
	+
	+ if (pcie_port->rev_id == AL_PCIE_REV_ID_3) {
	+ al_assert(
	+ (ib_hcrd_os_ob_reads_config->nof_cpl_hdr +
	+ ib_hcrd_os_ob_reads_config->nof_np_hdr +
	+ ib_hcrd_os_ob_reads_config->nof_p_hdr) ==
	+ AL_PCIE_REV3_IB_HCRD_SUM);
	+
	+ al_reg_write32_masked(
	+ regs->axi.init_fc.cfg,
	+ PCIE_AXI_REV3_INIT_FC_CFG_NOF_P_HDR_MASK \|
	+ PCIE_AXI_REV3_INIT_FC_CFG_NOF_NP_HDR_MASK \|
	+ PCIE_AXI_REV3_INIT_FC_CFG_NOF_CPL_HDR_MASK,
	+ (ib_hcrd_os_ob_reads_config->nof_p_hdr <<
	+ PCIE_AXI_REV3_INIT_FC_CFG_NOF_P_HDR_SHIFT) \|
	+ (ib_hcrd_os_ob_reads_config->nof_np_hdr <<
	+ PCIE_AXI_REV3_INIT_FC_CFG_NOF_NP_HDR_SHIFT) \|
	+ (ib_hcrd_os_ob_reads_config->nof_cpl_hdr <<
	+ PCIE_AXI_REV3_INIT_FC_CFG_NOF_CPL_HDR_SHIFT));
	+ } else {
	+ al_assert(
	+ (ib_hcrd_os_ob_reads_config->nof_cpl_hdr +
	+ ib_hcrd_os_ob_reads_config->nof_np_hdr +
	+ ib_hcrd_os_ob_reads_config->nof_p_hdr) ==
	+ AL_PCIE_REV_1_2_IB_HCRD_SUM);
	+
	+ al_reg_write32_masked(
	+ regs->axi.init_fc.cfg,
	+ PCIE_AXI_REV1_2_INIT_FC_CFG_NOF_P_HDR_MASK \|
	+ PCIE_AXI_REV1_2_INIT_FC_CFG_NOF_NP_HDR_MASK \|
	+ PCIE_AXI_REV1_2_INIT_FC_CFG_NOF_CPL_HDR_MASK,
	+ (ib_hcrd_os_ob_reads_config->nof_p_hdr <<
	+ PCIE_AXI_REV1_2_INIT_FC_CFG_NOF_P_HDR_SHIFT) \|
	+ (ib_hcrd_os_ob_reads_config->nof_np_hdr <<
	+ PCIE_AXI_REV1_2_INIT_FC_CFG_NOF_NP_HDR_SHIFT) \|
	+ (ib_hcrd_os_ob_reads_config->nof_cpl_hdr <<
	+ PCIE_AXI_REV1_2_INIT_FC_CFG_NOF_CPL_HDR_SHIFT));
	+ }
	+
	+ al_reg_write32_masked(
	+ regs->axi.pre_configuration.pcie_core_setup,
	+ PCIE_AXI_CORE_SETUP_NOF_READS_ONSLAVE_INTRF_PCIE_CORE_MASK,
	+ ib_hcrd_os_ob_reads_config->nof_outstanding_ob_reads <<
	+ PCIE_AXI_CORE_SETUP_NOF_READS_ONSLAVE_INTRF_PCIE_CORE_SHIFT);
	+
	+ /* Store 'nof_p_hdr' and 'nof_np_hdr' to be set in the core later */
	+ pcie_port->ib_hcrd_config.nof_np_hdr =
	+ ib_hcrd_os_ob_reads_config->nof_np_hdr;
	+ pcie_port->ib_hcrd_config.nof_p_hdr =
	+ ib_hcrd_os_ob_reads_config->nof_p_hdr;
	+
	+ return 0;
	+}
	+
	+enum al_pcie_operating_mode
	+al_pcie_operating_mode_get(
	+ struct al_pcie_port *pcie_port)
	+{
	+ struct al_pcie_regs *regs = pcie_port->regs;
	+ uint32_t reg, device_type;
	+
	+ al_assert(pcie_port);
	+
	+ reg = al_reg_read32(regs->axi.pcie_global.conf);
	+
	+ device_type = AL_REG_FIELD_GET(reg,
	+ PCIE_AXI_MISC_PCIE_GLOBAL_CONF_DEV_TYPE_MASK,
	+ PCIE_AXI_MISC_PCIE_GLOBAL_CONF_DEV_TYPE_SHIFT);
	+
	+ switch (device_type) {
	+ case PCIE_AXI_MISC_PCIE_GLOBAL_CONF_DEV_TYPE_EP:
	+ return AL_PCIE_OPERATING_MODE_EP;
	+ case PCIE_AXI_MISC_PCIE_GLOBAL_CONF_DEV_TYPE_RC:
	+ return AL_PCIE_OPERATING_MODE_RC;
	+ default:
	+ al_err("PCIe %d: unknown device type (%d) in global conf register.\n",
	+ pcie_port->port_id, device_type);
	+ }
	+ return AL_PCIE_OPERATING_MODE_UNKNOWN;
	+}
	+
	+/************************** PCIe Port Enable API **************************/
	+
	+/** Enable PCIe port (deassert reset) */
	+int
	+al_pcie_port_enable(struct al_pcie_port *pcie_port)
	+{
	+ struct al_pbs_regs *pbs_reg_base =
	+ (struct al_pbs_regs *)pcie_port->pbs_regs;
	+ struct al_pcie_regs *regs = pcie_port->regs;
	+ unsigned int port_id = pcie_port->port_id;
	+
	+ /* pre-port-enable default functionality should be here */
	+
	+ /**
	+ * Set inbound header credit and outstanding outbound reads defaults
	+ * Must be called before port enable (PCIE_EXIST)
	+ */
	+ al_pcie_ib_hcrd_os_ob_reads_config_default(pcie_port);
	+
	+ /*
	+ * Disable ATS capability
	+ * - must be done before core reset deasserted
	+ * - rev_id 0 - no effect, but no harm
	+ */
	+ if ((pcie_port->rev_id == AL_PCIE_REV_ID_0) \|\|
	+ (pcie_port->rev_id == AL_PCIE_REV_ID_1) \|\|
	+ (pcie_port->rev_id == AL_PCIE_REV_ID_2)) {
	+ al_reg_write32_masked(
	+ regs->axi.ordering.pos_cntl,
	+ PCIE_AXI_CORE_SETUP_ATS_CAP_DIS,
	+ PCIE_AXI_CORE_SETUP_ATS_CAP_DIS);
	+ }
	+
	+ /* Deassert core reset */
	+ al_reg_write32_masked(
	+ &pbs_reg_base->unit.pcie_conf_1,
	+ 1 << (port_id + PBS_UNIT_PCIE_CONF_1_PCIE_EXIST_SHIFT),
	+ 1 << (port_id + PBS_UNIT_PCIE_CONF_1_PCIE_EXIST_SHIFT));
	+
	+ return 0;
	+}
	+
	+/** Disable PCIe port (assert reset) */
	+void
	+al_pcie_port_disable(struct al_pcie_port *pcie_port)
	+{
	+ struct al_pbs_regs *pbs_reg_base =
	+ (struct al_pbs_regs *)pcie_port->pbs_regs;
	+ unsigned int port_id = pcie_port->port_id;
	+
	+ if (!al_pcie_port_is_enabled(pcie_port)) {
	+ al_warn("PCIe %d: trying to disable a non-enabled port\n",
	+ pcie_port->port_id);
	+ }
	+
	+ /* Assert core reset */
	+ al_reg_write32_masked(
	+ &pbs_reg_base->unit.pcie_conf_1,
	+ 1 << (port_id + PBS_UNIT_PCIE_CONF_1_PCIE_EXIST_SHIFT),
	+ 0);
	+}
	+
	+int
	+al_pcie_port_memory_shutdown_set(
	+ struct al_pcie_port *pcie_port,
	+ al_bool enable)
	+{
	+ struct al_pcie_regs *regs = pcie_port->regs;
	+ uint32_t mask = (pcie_port->rev_id == AL_PCIE_REV_ID_3) ?
	+ PCIE_REV3_AXI_MISC_PCIE_GLOBAL_CONF_MEM_SHUTDOWN :
	+ PCIE_REV1_2_AXI_MISC_PCIE_GLOBAL_CONF_MEM_SHUTDOWN;
	+
	+ if (!al_pcie_port_is_enabled(pcie_port)) {
	+ al_err("PCIe %d: not enabled, cannot shutdown memory\n",
	+ pcie_port->port_id);
	+ return -EINVAL;
	+ }
	+
	+ al_reg_write32_masked(regs->axi.pcie_global.conf,
	+ mask, enable == AL_TRUE ? mask : 0);
	+
	+ return 0;
	+}
	+
	+al_bool
	+al_pcie_port_is_enabled(struct al_pcie_port *pcie_port)
	+{
	+ struct al_pbs_regs pbs_reg_base = (struct al_pbs_regs )pcie_port->pbs_regs;
	+ uint32_t pcie_exist = al_reg_read32(&pbs_reg_base->unit.pcie_conf_1);
	+
	+ uint32_t ports_enabled = AL_REG_FIELD_GET(pcie_exist,
	+ PBS_UNIT_PCIE_CONF_1_PCIE_EXIST_MASK,
	+ PBS_UNIT_PCIE_CONF_1_PCIE_EXIST_SHIFT);
	+
	+ return (AL_REG_FIELD_GET(ports_enabled, AL_BIT(pcie_port->port_id),
	+ pcie_port->port_id) == 1);
	+}
	+
	+/************************* PCIe Configuration API *************************/
	+
	+/** configure pcie port (link params, etc..) */
	+int
	+al_pcie_port_config(struct al_pcie_port *pcie_port,
	+ const struct al_pcie_port_config_params *params)
	+{
	+ struct al_pcie_regs *regs = pcie_port->regs;
	+ enum al_pcie_operating_mode op_mode;
	+ int status = 0;
	+ int i;
	+
	+ if (!al_pcie_port_is_enabled(pcie_port)) {
	+ al_err("PCIe %d: port not enabled, cannot configure port\n",
	+ pcie_port->port_id);
	+ return -EINVAL;
	+ }
	+
	+ if (al_pcie_is_link_started(pcie_port)) {
	+ al_err("PCIe %d: link already started, cannot configure port\n",
	+ pcie_port->port_id);
	+ return -EINVAL;
	+ }
	+
	+ al_assert(pcie_port);
	+ al_assert(params);
	+
	+ al_dbg("PCIe %d: port config\n", pcie_port->port_id);
	+
	+ op_mode = al_pcie_operating_mode_get(pcie_port);
	+
	+ /* if max lanes not specifies, read it from register */
	+ if (pcie_port->max_lanes == 0) {
	+ uint32_t global_conf = al_reg_read32(regs->axi.pcie_global.conf);
	+ uint32_t act_lanes = AL_REG_FIELD_GET(global_conf,
	+ (pcie_port->rev_id == AL_PCIE_REV_ID_3) ?
	+ PCIE_REV3_AXI_MISC_PCIE_GLOBAL_CONF_NOF_ACT_LANES_MASK :
	+ PCIE_REV1_2_AXI_MISC_PCIE_GLOBAL_CONF_NOF_ACT_LANES_MASK,
	+ PCIE_REVX_AXI_MISC_PCIE_GLOBAL_CONF_NOF_ACT_LANES_SHIFT);
	+
	+ switch(act_lanes) {
	+ case 0x1:
	+ pcie_port->max_lanes = 1;
	+ break;
	+ case 0x3:
	+ pcie_port->max_lanes = 2;
	+ break;
	+ case 0xf:
	+ pcie_port->max_lanes = 4;
	+ break;
	+ case 0xff:
	+ pcie_port->max_lanes = 8;
	+ break;
	+ default:
	+ pcie_port->max_lanes = 0;
	+ al_err("PCIe %d: invalid max lanes val (0x%x)\n", pcie_port->port_id, act_lanes);
	+ break;
	+ }
	+ }
	+
	+ if (params->link_params)
	+ status = al_pcie_port_link_config(pcie_port, params->link_params);
	+ if (status)
	+ goto done;
	+
	+ /* Change max read request size to 256 bytes
	+ * Max Payload Size is remained untouched- it is the responsibility of
	+ * the host to change the MPS, if needed.
	+ */
	+ for (i = 0; i < AL_MAX_NUM_OF_PFS; i++) {
	+ al_reg_write32_masked(regs->core_space[i].pcie_dev_ctrl_status,
	+ PCIE_PORT_DEV_CTRL_STATUS_MRRS_MASK,
	+ PCIE_PORT_DEV_CTRL_STATUS_MRRS_VAL_256);
	+ if (pcie_port->rev_id != AL_PCIE_REV_ID_3)
	+ break;
	+ }
	+
	+ if (pcie_port->rev_id == AL_PCIE_REV_ID_3) {
	+ /* Set maximum physical function numbers */
	+ al_reg_write32_masked(
	+ &regs->port_regs->timer_ctrl_max_func_num,
	+ PCIE_PORT_GEN3_MAX_FUNC_NUM,
	+ pcie_port->max_num_of_pfs - 1);
	+
	+ al_pcie_port_wr_to_ro_set(pcie_port, AL_TRUE);
	+
	+ /**
	+ * in EP mode, when we have more than 1 PF we need to assert
	+ * multi-pf support so the host scan all PFs
	+ */
	+ if ((op_mode == AL_PCIE_OPERATING_MODE_EP) && (pcie_port->max_num_of_pfs > 1)) {
	+ al_reg_write32_masked((uint32_t __iomem *)
	+ (&regs->core_space[0].config_header[0] +
	+ (PCIE_BIST_HEADER_TYPE_BASE >> 2)),
	+ PCIE_BIST_HEADER_TYPE_MULTI_FUNC_MASK,
	+ PCIE_BIST_HEADER_TYPE_MULTI_FUNC_MASK);
	+ }
	+
	+ /* Disable TPH next pointer */
	+ for (i = 0; i < AL_MAX_NUM_OF_PFS; i++) {
	+ al_reg_write32_masked(regs->core_space[i].tph_cap_base,
	+ PCIE_TPH_NEXT_POINTER, 0);
	+ }
	+
	+ al_pcie_port_wr_to_ro_set(pcie_port, AL_FALSE);
	+ }
	+
	+
	+ status = al_pcie_port_snoop_config(pcie_port, params->enable_axi_snoop);
	+ if (status)
	+ goto done;
	+
	+ al_pcie_port_ram_parity_int_config(pcie_port, params->enable_ram_parity_int);
	+
	+ al_pcie_port_axi_parity_int_config(pcie_port, params->enable_axi_parity_int);
	+
	+ al_pcie_port_relaxed_pcie_ordering_config(pcie_port, params->relaxed_ordering_params);
	+
	+ if (params->lat_rply_timers)
	+ status = al_pcie_port_lat_rply_timers_config(pcie_port, params->lat_rply_timers);
	+ if (status)
	+ goto done;
	+
	+ if (params->gen2_params)
	+ status = al_pcie_port_gen2_params_config(pcie_port, params->gen2_params);
	+ if (status)
	+ goto done;
	+
	+ if (params->gen3_params)
	+ status = al_pcie_port_gen3_params_config(pcie_port, params->gen3_params);
	+ if (status)
	+ goto done;
	+
	+ if (params->tl_credits)
	+ status = al_pcie_port_tl_credits_config(pcie_port, params->tl_credits);
	+ if (status)
	+ goto done;
	+
	+ if (params->features)
	+ al_pcie_port_features_config(pcie_port, params->features);
	+
	+ if (params->sris_params)
	+ status = al_pcie_port_sris_config(pcie_port, params->sris_params,
	+ params->link_params->max_speed);
	+ if (status)
	+ goto done;
	+
	+ al_pcie_port_ib_hcrd_config(pcie_port);
	+
	+ if (params->fast_link_mode) {
	+ al_reg_write32_masked(&regs->port_regs->port_link_ctrl,
	+ 1 << PCIE_PORT_LINK_CTRL_FAST_LINK_EN_SHIFT,
	+ 1 << PCIE_PORT_LINK_CTRL_FAST_LINK_EN_SHIFT);
	+ }
	+
	+ if (params->enable_axi_slave_err_resp)
	+ al_reg_write32_masked(&regs->port_regs->axi_slave_err_resp,
	+ 1 << PCIE_PORT_AXI_SLAVE_ERR_RESP_ALL_MAPPING_SHIFT,
	+ 1 << PCIE_PORT_AXI_SLAVE_ERR_RESP_ALL_MAPPING_SHIFT);
	+
	+ /**
	+ * Addressing RMN: 5477
	+ *
	+ * RMN description:
	+ * address-decoder logic performs sub-target decoding even for transactions
	+ * which undergo target enforcement. thus, in case transaction's address is
	+ * inside any ECAM bar, the sub-target decoding will be set to ECAM, which
	+ * causes wrong handling by PCIe unit
	+ *
	+ * Software flow:
	+ * on EP mode only, turning on the iATU-enable bit (with the relevant mask
	+ * below) allows the PCIe unit to discard the ECAM bit which was asserted
	+ * by-mistake in the address-decoder
	+ */
	+ if (op_mode == AL_PCIE_OPERATING_MODE_EP) {
	+ al_reg_write32_masked(regs->axi.ob_ctrl.cfg_target_bus,
	+ PCIE_AXI_MISC_OB_CTRL_CFG_TARGET_BUS_MASK_MASK,
	+ (0) << PCIE_AXI_MISC_OB_CTRL_CFG_TARGET_BUS_MASK_SHIFT);
	+ al_reg_write32_masked(regs->axi.ob_ctrl.cfg_control,
	+ PCIE_AXI_MISC_OB_CTRL_CFG_CONTROL_IATU_EN,
	+ PCIE_AXI_MISC_OB_CTRL_CFG_CONTROL_IATU_EN);
	+ }
	+
	+ if (op_mode == AL_PCIE_OPERATING_MODE_RC) {
	+ /**
	+ * enable memory and I/O access from port when in RC mode
	+ * in RC mode, only core_space[0] is valid.
	+ */
	+ al_reg_write16_masked(
	+ (uint16_t __iomem *)(&regs->core_space[0].config_header[0] + (0x4 >> 2)),
	+ 0x7, /* Mem, MSE, IO */
	+ 0x7);
	+
	+ /* change the class code to match pci bridge */
	+ al_pcie_port_wr_to_ro_set(pcie_port, AL_TRUE);
	+
	+ al_reg_write32_masked(
	+ (uint32_t __iomem *)(&regs->core_space[0].config_header[0]
	+ + (PCI_CLASS_REVISION >> 2)),
	+ 0xFFFFFF00,
	+ 0x06040000);
	+
	+ al_pcie_port_wr_to_ro_set(pcie_port, AL_FALSE);
	+
	+ /**
	+ * Addressing RMN: 5702
	+ *
	+ * RMN description:
	+ * target bus mask default value in HW is: 0xFE, this enforces
	+ * setting the target bus for ports 1 and 3 when running on RC
	+ * mode since bit[20] in ECAM address in these cases is set
	+ *
	+ * Software flow:
	+ * on RC mode only, set target-bus value to 0xFF to prevent this
	+ * enforcement
	+ */
	+ al_reg_write32_masked(regs->axi.ob_ctrl.cfg_target_bus,
	+ PCIE_AXI_MISC_OB_CTRL_CFG_TARGET_BUS_MASK_MASK,
	+ PCIE_AXI_MISC_OB_CTRL_CFG_TARGET_BUS_MASK_MASK);
	+ }
	+done:
	+ al_dbg("PCIe %d: port config %s\n", pcie_port->port_id, status? "failed": "done");
	+
	+ return status;
	+}
	+
	+int
	+al_pcie_pf_config(
	+ struct al_pcie_pf *pcie_pf,
	+ const struct al_pcie_pf_config_params *params)
	+{
	+ struct al_pcie_port *pcie_port;
	+ int status = 0;
	+
	+ al_assert(pcie_pf);
	+ al_assert(params);
	+
	+ pcie_port = pcie_pf->pcie_port;
	+
	+ if (!al_pcie_port_is_enabled(pcie_port)) {
	+ al_err("PCIe %d: port not enabled, cannot configure port\n", pcie_port->port_id);
	+ return -EINVAL;
	+ }
	+
	+ al_dbg("PCIe %d: pf %d config\n", pcie_port->port_id, pcie_pf->pf_num);
	+
	+ if (params)
	+ status = al_pcie_port_pf_params_config(pcie_pf, params);
	+ if (status)
	+ goto done;
	+
	+done:
	+ al_dbg("PCIe %d: pf %d config %s\n",
	+ pcie_port->port_id, pcie_pf->pf_num, status ? "failed" : "done");
	+
	+ return status;
	+}
	+
	+/************************ PCIe Link Operations API ************************/
	+
	+/* start pcie link */
	+int
	+al_pcie_link_start(struct al_pcie_port *pcie_port)
	+{
	+ struct al_pcie_regs regs = (struct al_pcie_regs )pcie_port->regs;
	+
	+ if (!al_pcie_port_is_enabled(pcie_port)) {
	+ al_err("PCIe %d: port not enabled, cannot start link\n",
	+ pcie_port->port_id);
	+ return -EINVAL;
	+ }
	+
	+ al_dbg("PCIe_%d: start port link.\n", pcie_port->port_id);
	+
	+ al_reg_write32_masked(
	+ regs->app.global_ctrl.port_init,
	+ PCIE_W_GLOBAL_CTRL_PORT_INIT_APP_LTSSM_EN_MASK,
	+ PCIE_W_GLOBAL_CTRL_PORT_INIT_APP_LTSSM_EN_MASK);
	+
	+ return 0;
	+}
	+
	+/* stop pcie link */
	+int
	+al_pcie_link_stop(struct al_pcie_port *pcie_port)
	+{
	+ struct al_pcie_regs regs = (struct al_pcie_regs )pcie_port->regs;
	+
	+ if (!al_pcie_is_link_started(pcie_port)) {
	+ al_warn("PCIe %d: trying to stop a non-started link\n",
	+ pcie_port->port_id);
	+ }
	+
	+ al_dbg("PCIe_%d: stop port link.\n", pcie_port->port_id);
	+
	+ al_reg_write32_masked(
	+ regs->app.global_ctrl.port_init,
	+ PCIE_W_GLOBAL_CTRL_PORT_INIT_APP_LTSSM_EN_MASK,
	+ ~PCIE_W_GLOBAL_CTRL_PORT_INIT_APP_LTSSM_EN_MASK);
	+
	+ return 0;
	+}
	+
	+/* wait for link up indication */
	+int
	+al_pcie_link_up_wait(struct al_pcie_port *pcie_port, uint32_t timeout_ms)
	+{
	+ int wait_count = timeout_ms * AL_PCIE_LINKUP_WAIT_INTERVALS_PER_SEC;
	+
	+ while (wait_count-- > 0) {
	+ if (al_pcie_check_link(pcie_port, NULL)) {
	+ al_info("PCIe_%d: <<<<<<<<< Link up >>>>>>>>>\n", pcie_port->port_id);
	+ return 0;
	+ } else
	+ al_dbg("PCIe_%d: No link up, %d attempts remaining\n",
	+ pcie_port->port_id, wait_count);
	+
	+ al_udelay(AL_PCIE_LINKUP_WAIT_INTERVAL);
	+ }
	+ al_info("PCIE_%d: link is not established in time\n",
	+ pcie_port->port_id);
	+
	+ return ETIMEDOUT;
	+}
	+
	+/** get link status */
	+int
	+al_pcie_link_status(struct al_pcie_port *pcie_port,
	+ struct al_pcie_link_status *status)
	+{
	+ struct al_pcie_regs *regs = pcie_port->regs;
	+ uint16_t pcie_lnksta;
	+
	+ al_assert(status);
	+
	+ status->link_up = al_pcie_check_link(pcie_port, &status->ltssm_state);
	+
	+ if (!status->link_up) {
	+ status->speed = AL_PCIE_LINK_SPEED_DEFAULT;
	+ status->lanes = 0;
	+ return 0;
	+ }
	+
	+ pcie_lnksta = al_reg_read16((uint16_t __iomem *)regs->core_space[0].pcie_cap_base + (AL_PCI_EXP_LNKSTA >> 1));
	+
	+ switch(pcie_lnksta & AL_PCI_EXP_LNKSTA_CLS) {
	+ case AL_PCI_EXP_LNKSTA_CLS_2_5GB:
	+ status->speed = AL_PCIE_LINK_SPEED_GEN1;
	+ break;
	+ case AL_PCI_EXP_LNKSTA_CLS_5_0GB:
	+ status->speed = AL_PCIE_LINK_SPEED_GEN2;
	+ break;
	+ case AL_PCI_EXP_LNKSTA_CLS_8_0GB:
	+ status->speed = AL_PCIE_LINK_SPEED_GEN3;
	+ break;
	+ default:
	+ status->speed = AL_PCIE_LINK_SPEED_DEFAULT;
	+ al_err("PCIe %d: unknown link speed indication. PCIE LINK STATUS %x\n",
	+ pcie_port->port_id, pcie_lnksta);
	+ }
	+ status->lanes = (pcie_lnksta & AL_PCI_EXP_LNKSTA_NLW) >> AL_PCI_EXP_LNKSTA_NLW_SHIFT;
	+ al_info("PCIe %d: Link up. speed gen%d negotiated width %d\n",
	+ pcie_port->port_id, status->speed, status->lanes);
	+
	+ return 0;
	+}
	+
	+/** get lane status */
	+void
	+al_pcie_lane_status_get(
	+ struct al_pcie_port *pcie_port,
	+ unsigned int lane,
	+ struct al_pcie_lane_status *status)
	+{
	+ struct al_pcie_regs *regs = pcie_port->regs;
	+ uint32_t lane_status;
	+ uint32_t *reg_ptr;
	+
	+ al_assert(pcie_port);
	+ al_assert(status);
	+ al_assert((pcie_port->rev_id != AL_PCIE_REV_ID_1) \|\| (lane < REV1_2_MAX_NUM_LANES));
	+ al_assert((pcie_port->rev_id != AL_PCIE_REV_ID_2) \|\| (lane < REV1_2_MAX_NUM_LANES));
	+ al_assert((pcie_port->rev_id != AL_PCIE_REV_ID_3) \|\| (lane < REV3_MAX_NUM_LANES));
	+
	+ reg_ptr = regs->axi.status.lane[lane];
	+
	+ /* Reset field is valid only when same value is read twice */
	+ do {
	+ lane_status = al_reg_read32(reg_ptr);
	+ status->is_reset = !!(lane_status & PCIE_AXI_STATUS_LANE_IS_RESET);
	+ } while (status->is_reset != (!!(al_reg_read32(reg_ptr) & PCIE_AXI_STATUS_LANE_IS_RESET)));
	+
	+ status->requested_speed =
	+ (lane_status & PCIE_AXI_STATUS_LANE_REQUESTED_SPEED_MASK) >>
	+ PCIE_AXI_STATUS_LANE_REQUESTED_SPEED_SHIFT;
	+}
	+
	+/** trigger hot reset */
	+int
	+al_pcie_link_hot_reset(struct al_pcie_port *pcie_port, al_bool enable)
	+{
	+ struct al_pcie_regs *regs = pcie_port->regs;
	+ uint32_t events_gen;
	+ al_bool app_reset_state;
	+ enum al_pcie_operating_mode op_mode = al_pcie_operating_mode_get(pcie_port);
	+
	+ if (op_mode != AL_PCIE_OPERATING_MODE_RC) {
	+ al_err("PCIe %d: hot-reset is applicable only for RC mode\n", pcie_port->port_id);
	+ return -EINVAL;
	+ }
	+
	+ if (!al_pcie_is_link_started(pcie_port)) {
	+ al_err("PCIe %d: link not started, cannot trigger hot-reset\n", pcie_port->port_id);
	+ return -EINVAL;
	+ }
	+
	+ events_gen = al_reg_read32(regs->app.global_ctrl.events_gen[0]);
	+ app_reset_state = events_gen & PCIE_W_GLOBAL_CTRL_EVENTS_GEN_APP_RST_INIT;
	+
	+ if (enable && app_reset_state) {
	+ al_err("PCIe %d: link is already in hot-reset state\n", pcie_port->port_id);
	+ return -EINVAL;
	+ } else if ((!enable) && (!(app_reset_state))) {
	+ al_err("PCIe %d: link is already in non-hot-reset state\n", pcie_port->port_id);
	+ return -EINVAL;
	+ } else {
	+ al_dbg("PCIe %d: %s hot-reset\n", pcie_port->port_id,
	+ (enable ? "enabling" : "disabling"));
	+ /* hot-reset functionality is implemented only for function 0 */
	+ al_reg_write32_masked(regs->app.global_ctrl.events_gen[0],
	+ PCIE_W_GLOBAL_CTRL_EVENTS_GEN_APP_RST_INIT,
	+ (enable ? PCIE_W_GLOBAL_CTRL_EVENTS_GEN_APP_RST_INIT
	+ : ~PCIE_W_GLOBAL_CTRL_EVENTS_GEN_APP_RST_INIT));
	+ return 0;
	+ }
	+}
	+
	+/** disable port link */
	+int
	+al_pcie_link_disable(struct al_pcie_port *pcie_port, al_bool disable)
	+{
	+ struct al_pcie_regs *regs = pcie_port->regs;
	+ uint32_t pcie_lnkctl;
	+ al_bool link_disable_state;
	+ enum al_pcie_operating_mode op_mode = al_pcie_operating_mode_get(pcie_port);
	+
	+ if (op_mode != AL_PCIE_OPERATING_MODE_RC) {
	+ al_err("PCIe %d: hot-reset is applicable only for RC mode\n", pcie_port->port_id);
	+ return -EINVAL;
	+ }
	+
	+ if (!al_pcie_is_link_started(pcie_port)) {
	+ al_err("PCIe %d: link not started, cannot disable link\n", pcie_port->port_id);
	+ return -EINVAL;
	+ }
	+
	+ pcie_lnkctl = al_reg_read32(regs->core_space[0].pcie_cap_base + (AL_PCI_EXP_LNKCTL >> 1));
	+ link_disable_state = pcie_lnkctl & AL_PCI_EXP_LNKCTL_LNK_DIS;
	+
	+ if (disable && link_disable_state) {
	+ al_err("PCIe %d: link is already in disable state\n", pcie_port->port_id);
	+ return -EINVAL;
	+ } else if ((!disable) && (!(link_disable_state))) {
	+ al_err("PCIe %d: link is already in enable state\n", pcie_port->port_id);
	+ return -EINVAL;
	+ }
	+
	+ al_dbg("PCIe %d: %s port\n", pcie_port->port_id, (disable ? "disabling" : "enabling"));
	+ al_reg_write32_masked(regs->core_space[0].pcie_cap_base + (AL_PCI_EXP_LNKCTL >> 1),
	+ AL_PCI_EXP_LNKCTL_LNK_DIS,
	+ (disable ? AL_PCI_EXP_LNKCTL_LNK_DIS : ~AL_PCI_EXP_LNKCTL_LNK_DIS));
	+ return 0;
	+}
	+
	+/** retrain link */
	+int
	+al_pcie_link_retrain(struct al_pcie_port *pcie_port)
	+{
	+ struct al_pcie_regs *regs = pcie_port->regs;
	+ enum al_pcie_operating_mode op_mode = al_pcie_operating_mode_get(pcie_port);
	+
	+ if (op_mode != AL_PCIE_OPERATING_MODE_RC) {
	+ al_err("PCIe %d: link-retrain is applicable only for RC mode\n",
	+ pcie_port->port_id);
	+ return -EINVAL;
	+ }
	+
	+ if (!al_pcie_is_link_started(pcie_port)) {
	+ al_err("PCIe %d: link not started, cannot link-retrain\n", pcie_port->port_id);
	+ return -EINVAL;
	+ }
	+
	+ al_reg_write32_masked(regs->core_space[0].pcie_cap_base + (AL_PCI_EXP_LNKCTL >> 1),
	+ AL_PCI_EXP_LNKCTL_LNK_RTRN, AL_PCI_EXP_LNKCTL_LNK_RTRN);
	+
	+ return 0;
	+}
	+
	+/* trigger speed change */
	+int
	+al_pcie_link_change_speed(struct al_pcie_port *pcie_port,
	+ enum al_pcie_link_speed new_speed)
	+{
	+ struct al_pcie_regs *regs = pcie_port->regs;
	+
	+ if (!al_pcie_is_link_started(pcie_port)) {
	+ al_err("PCIe %d: link not started, cannot change speed\n", pcie_port->port_id);
	+ return -EINVAL;
	+ }
	+
	+ al_dbg("PCIe %d: changing speed to %d\n", pcie_port->port_id, new_speed);
	+
	+ al_pcie_port_link_speed_ctrl_set(pcie_port, new_speed);
	+
	+ al_reg_write32_masked(&regs->port_regs->gen2_ctrl,
	+ PCIE_PORT_GEN2_CTRL_DIRECT_SPEED_CHANGE,
	+ PCIE_PORT_GEN2_CTRL_DIRECT_SPEED_CHANGE);
	+
	+ return 0;
	+}
	+
	+/* TODO: check if this function needed */
	+int
	+al_pcie_link_change_width(struct al_pcie_port *pcie_port,
	+ uint8_t width __attribute__((__unused__)))
	+{
	+ al_err("PCIe %d: link change width not implemented\n",
	+ pcie_port->port_id);
	+
	+ return -ENOSYS;
	+}
	+
	+/************************** Post Link Start API ***************************/
	+
	+/************************ Snoop Configuration API *************************/
	+
	+int
	+al_pcie_port_snoop_config(struct al_pcie_port *pcie_port, al_bool enable_axi_snoop)
	+{
	+ struct al_pcie_regs *regs = pcie_port->regs;
	+
	+ /* Set snoop mode */
	+ al_info("PCIE_%d: snoop mode %s\n",
	+ pcie_port->port_id, enable_axi_snoop ? "enable" : "disable");
	+
	+ if (enable_axi_snoop) {
	+ al_reg_write32_masked(regs->axi.ctrl.master_arctl,
	+ PCIE_AXI_CTRL_MASTER_ARCTL_OVR_SNOOP \| PCIE_AXI_CTRL_MASTER_ARCTL_SNOOP,
	+ PCIE_AXI_CTRL_MASTER_ARCTL_OVR_SNOOP \| PCIE_AXI_CTRL_MASTER_ARCTL_SNOOP);
	+
	+ al_reg_write32_masked(regs->axi.ctrl.master_awctl,
	+ PCIE_AXI_CTRL_MASTER_AWCTL_OVR_SNOOP \| PCIE_AXI_CTRL_MASTER_AWCTL_SNOOP,
	+ PCIE_AXI_CTRL_MASTER_AWCTL_OVR_SNOOP \| PCIE_AXI_CTRL_MASTER_AWCTL_SNOOP);
	+ } else {
	+ al_reg_write32_masked(regs->axi.ctrl.master_arctl,
	+ PCIE_AXI_CTRL_MASTER_ARCTL_OVR_SNOOP \| PCIE_AXI_CTRL_MASTER_ARCTL_SNOOP,
	+ PCIE_AXI_CTRL_MASTER_ARCTL_OVR_SNOOP);
	+
	+ al_reg_write32_masked(regs->axi.ctrl.master_awctl,
	+ PCIE_AXI_CTRL_MASTER_AWCTL_OVR_SNOOP \| PCIE_AXI_CTRL_MASTER_AWCTL_SNOOP,
	+ PCIE_AXI_CTRL_MASTER_AWCTL_OVR_SNOOP);
	+ }
	+ return 0;
	+}
	+
	+/************************ Configuration Space API *************************/
	+
	+/** get base address of pci configuration space header */
	+int
	+al_pcie_config_space_get(struct al_pcie_pf *pcie_pf,
	+ uint8_t __iomem **addr)
	+{
	+ struct al_pcie_regs *regs = pcie_pf->pcie_port->regs;
	+
	+ addr = (uint8_t __iomem )&regs->core_space[pcie_pf->pf_num].config_header[0];
	+ return 0;
	+}
	+
	+/* Read data from the local configuration space */
	+uint32_t
	+al_pcie_local_cfg_space_read(
	+ struct al_pcie_pf *pcie_pf,
	+ unsigned int reg_offset)
	+{
	+ struct al_pcie_regs *regs = pcie_pf->pcie_port->regs;
	+ uint32_t data;
	+
	+ data = al_reg_read32(&regs->core_space[pcie_pf->pf_num].config_header[reg_offset]);
	+
	+ return data;
	+}
	+
	+/* Write data to the local configuration space */
	+void
	+al_pcie_local_cfg_space_write(
	+ struct al_pcie_pf *pcie_pf,
	+ unsigned int reg_offset,
	+ uint32_t data,
	+ al_bool cs2,
	+ al_bool allow_ro_wr)
	+{
	+ struct al_pcie_port *pcie_port = pcie_pf->pcie_port;
	+ struct al_pcie_regs *regs = pcie_port->regs;
	+ unsigned int pf_num = pcie_pf->pf_num;
	+ uint32_t *offset = &regs->core_space[pf_num].config_header[reg_offset];
	+
	+ if (allow_ro_wr)
	+ al_pcie_port_wr_to_ro_set(pcie_port, AL_TRUE);
	+
	+ if (cs2 == AL_FALSE)
	+ al_reg_write32(offset, data);
	+ else
	+ al_reg_write32_dbi_cs2(pcie_port, offset, data);
	+
	+ if (allow_ro_wr)
	+ al_pcie_port_wr_to_ro_set(pcie_port, AL_FALSE);
	+}
	+
	+/** set target_bus and mask_target_bus */
	+int
	+al_pcie_target_bus_set(
	+ struct al_pcie_port *pcie_port,
	+ uint8_t target_bus,
	+ uint8_t mask_target_bus)
	+{
	+ struct al_pcie_regs regs = (struct al_pcie_regs )pcie_port->regs;
	+ uint32_t reg;
	+
	+ reg = al_reg_read32(regs->axi.ob_ctrl.cfg_target_bus);
	+ AL_REG_FIELD_SET(reg, PCIE_AXI_MISC_OB_CTRL_CFG_TARGET_BUS_MASK_MASK,
	+ PCIE_AXI_MISC_OB_CTRL_CFG_TARGET_BUS_MASK_SHIFT,
	+ mask_target_bus);
	+ AL_REG_FIELD_SET(reg, PCIE_AXI_MISC_OB_CTRL_CFG_TARGET_BUS_BUSNUM_MASK,
	+ PCIE_AXI_MISC_OB_CTRL_CFG_TARGET_BUS_BUSNUM_SHIFT,
	+ target_bus);
	+ al_reg_write32(regs->axi.ob_ctrl.cfg_target_bus, reg);
	+ return 0;
	+}
	+
	+/** get target_bus and mask_target_bus */
	+int
	+al_pcie_target_bus_get(
	+ struct al_pcie_port *pcie_port,
	+ uint8_t *target_bus,
	+ uint8_t *mask_target_bus)
	+{
	+ struct al_pcie_regs regs = (struct al_pcie_regs )pcie_port->regs;
	+ uint32_t reg;
	+
	+ al_assert(target_bus);
	+ al_assert(mask_target_bus);
	+
	+ reg = al_reg_read32(regs->axi.ob_ctrl.cfg_target_bus);
	+
	+ *mask_target_bus = AL_REG_FIELD_GET(reg,
	+ PCIE_AXI_MISC_OB_CTRL_CFG_TARGET_BUS_MASK_MASK,
	+ PCIE_AXI_MISC_OB_CTRL_CFG_TARGET_BUS_MASK_SHIFT);
	+ *target_bus = AL_REG_FIELD_GET(reg,
	+ PCIE_AXI_MISC_OB_CTRL_CFG_TARGET_BUS_BUSNUM_MASK,
	+ PCIE_AXI_MISC_OB_CTRL_CFG_TARGET_BUS_BUSNUM_SHIFT);
	+ return 0;
	+}
	+
	+/** Set secondary bus number */
	+int
	+al_pcie_secondary_bus_set(struct al_pcie_port *pcie_port, uint8_t secbus)
	+{
	+ struct al_pcie_regs *regs = pcie_port->regs;
	+
	+ uint32_t secbus_val = (secbus <<
	+ PCIE_AXI_MISC_OB_CTRL_CFG_CONTROL_SEC_BUS_SHIFT);
	+
	+ al_reg_write32_masked(
	+ regs->axi.ob_ctrl.cfg_control,
	+ PCIE_AXI_MISC_OB_CTRL_CFG_CONTROL_SEC_BUS_MASK,
	+ secbus_val);
	+ return 0;
	+}
	+
	+/** Set sub-ordinary bus number */
	+int
	+al_pcie_subordinary_bus_set(struct al_pcie_port *pcie_port, uint8_t subbus)
	+{
	+ struct al_pcie_regs *regs = pcie_port->regs;
	+
	+ uint32_t subbus_val = (subbus <<
	+ PCIE_AXI_MISC_OB_CTRL_CFG_CONTROL_SUBBUS_SHIFT);
	+
	+ al_reg_write32_masked(
	+ regs->axi.ob_ctrl.cfg_control,
	+ PCIE_AXI_MISC_OB_CTRL_CFG_CONTROL_SUBBUS_MASK,
	+ subbus_val);
	+ return 0;
	+}
	+
	+/* Enable/disable deferring incoming configuration requests */
	+void
	+al_pcie_app_req_retry_set(
	+ struct al_pcie_port *pcie_port,
	+ al_bool en)
	+{
	+ struct al_pcie_regs *regs = pcie_port->regs;
	+ uint32_t mask = (pcie_port->rev_id == AL_PCIE_REV_ID_3) ?
	+ PCIE_W_REV3_GLOBAL_CTRL_PM_CONTROL_APP_REQ_RETRY_EN :
	+ PCIE_W_REV1_2_GLOBAL_CTRL_PM_CONTROL_APP_REQ_RETRY_EN;
	+
	+ al_reg_write32_masked(regs->app.global_ctrl.pm_control,
	+ mask, (en == AL_TRUE) ? mask : 0);
	+}
	+
	+/************* Internal Address Translation Unit (ATU) API ****************/
	+
	+/** program internal ATU region entry */
	+int
	+al_pcie_atu_region_set(
	+ struct al_pcie_port *pcie_port,
	+ struct al_pcie_atu_region *atu_region)
	+{
	+ struct al_pcie_regs *regs = pcie_port->regs;
	+ enum al_pcie_operating_mode op_mode = al_pcie_operating_mode_get(pcie_port);
	+ uint32_t reg = 0;
	+
	+ /**
	+ * Addressing RMN: 5384
	+ *
	+ * RMN description:
	+ * From SNPS (also included in the data book) Dynamic iATU Programming
	+ * With AHB/AXI Bridge Module When the bridge slave interface clock
	+ * (hresetn or slv_aclk) is asynchronous to the PCIe native core clock
	+ * (core_clk), you must not update the iATU registers while operations
	+ * are in progress on the AHB/AXI bridge slave interface. The iATU
	+ * registers are in the core_clk clock domain. The register outputs are
	+ * used in the AHB/AXI bridge slave interface clock domain. There is no
	+ * synchronization logic between these registers and the AHB/AXI bridge
	+ * slave interface.
	+ *
	+ * Software flow:
	+ * Do not allow configuring Outbound iATU after link is started
	+ */
	+ if ((atu_region->direction == AL_PCIE_ATU_DIR_OUTBOUND)
	+ && (al_pcie_is_link_started(pcie_port))) {
	+ if (!atu_region->enforce_ob_atu_region_set) {
	+ al_err("PCIe %d: setting OB iATU after link is started is not allowed\n",
	+ pcie_port->port_id);
	+ return -EINVAL;
	+ } else {
	+ al_info("PCIe %d: setting OB iATU even after link is started\n",
	+ pcie_port->port_id);
	+ }
	+ }
	+
	+ /TODO : add sanity check /
	+ AL_REG_FIELD_SET(reg, 0xF, 0, atu_region->index);
	+ AL_REG_BIT_VAL_SET(reg, 31, atu_region->direction);
	+ al_reg_write32(&regs->port_regs->iatu.index, reg);
	+
	+ al_reg_write32(&regs->port_regs->iatu.lower_base_addr,
	+ (uint32_t)(atu_region->base_addr & 0xFFFFFFFF));
	+ al_reg_write32(&regs->port_regs->iatu.upper_base_addr,
	+ (uint32_t)((atu_region->base_addr >> 32)& 0xFFFFFFFF));
	+ al_reg_write32(&regs->port_regs->iatu.lower_target_addr,
	+ (uint32_t)(atu_region->target_addr & 0xFFFFFFFF));
	+ al_reg_write32(&regs->port_regs->iatu.upper_target_addr,
	+ (uint32_t)((atu_region->target_addr >> 32)& 0xFFFFFFFF));
	+
	+ /* configure the limit, not needed when working in BAR match mode */
	+ if (atu_region->match_mode == 0) {
	+ uint32_t limit_reg_val;
	+ if (pcie_port->rev_id > AL_PCIE_REV_ID_0) {
	+ uint32_t *limit_ext_reg =
	+ (atu_region->direction == AL_PCIE_ATU_DIR_OUTBOUND) ?
	+ &regs->app.atu.out_mask_pair[atu_region->index / 2] :
	+ &regs->app.atu.in_mask_pair[atu_region->index / 2];
	+ uint32_t limit_ext_reg_mask =
	+ (atu_region->index % 2) ?
	+ PCIE_W_ATU_MASK_EVEN_ODD_ATU_MASK_40_32_ODD_MASK :
	+ PCIE_W_ATU_MASK_EVEN_ODD_ATU_MASK_40_32_EVEN_MASK;
	+ unsigned int limit_ext_reg_shift =
	+ (atu_region->index % 2) ?
	+ PCIE_W_ATU_MASK_EVEN_ODD_ATU_MASK_40_32_ODD_SHIFT :
	+ PCIE_W_ATU_MASK_EVEN_ODD_ATU_MASK_40_32_EVEN_SHIFT;
	+ uint64_t limit_sz_msk =
	+ atu_region->limit - atu_region->base_addr;
	+ uint32_t limit_ext_reg_val = (uint32_t)(((limit_sz_msk) >>
	+ 32) & 0xFFFFFFFF);
	+
	+ if (limit_ext_reg_val) {
	+ limit_reg_val = (uint32_t)((limit_sz_msk) & 0xFFFFFFFF);
	+ al_assert(limit_reg_val == 0xFFFFFFFF);
	+ } else {
	+ limit_reg_val = (uint32_t)(atu_region->limit &
	+ 0xFFFFFFFF);
	+ }
	+
	+ al_reg_write32_masked(
	+ limit_ext_reg,
	+ limit_ext_reg_mask,
	+ limit_ext_reg_val << limit_ext_reg_shift);
	+ } else {
	+ limit_reg_val = (uint32_t)(atu_region->limit & 0xFFFFFFFF);
	+ }
	+
	+ al_reg_write32(&regs->port_regs->iatu.limit_addr,
	+ limit_reg_val);
	+ }
	+
	+ reg = 0;
	+ AL_REG_FIELD_SET(reg, 0x1F, 0, atu_region->tlp_type);
	+ AL_REG_FIELD_SET(reg, 0x3 << 9, 9, atu_region->attr);
	+
	+
	+ if ((pcie_port->rev_id == AL_PCIE_REV_ID_3)
	+ && (op_mode == AL_PCIE_OPERATING_MODE_EP)
	+ && (atu_region->function_match_bypass_mode)) {
	+ AL_REG_FIELD_SET(reg,
	+ PCIE_IATU_CR1_FUNC_NUM_MASK,
	+ PCIE_IATU_CR1_FUNC_NUM_SHIFT,
	+ atu_region->function_match_bypass_mode_number);
	+ }
	+
	+ al_reg_write32(&regs->port_regs->iatu.cr1, reg);
	+
	+ /* Enable/disable the region. */
	+ reg = 0;
	+ AL_REG_FIELD_SET(reg, 0xFF, 0, atu_region->msg_code);
	+ AL_REG_FIELD_SET(reg, 0x700, 8, atu_region->bar_number);
	+ AL_REG_FIELD_SET(reg, 0x3 << 24, 24, atu_region->response);
	+ AL_REG_BIT_VAL_SET(reg, 16, atu_region->enable_attr_match_mode == AL_TRUE);
	+ AL_REG_BIT_VAL_SET(reg, 21, atu_region->enable_msg_match_mode == AL_TRUE);
	+ AL_REG_BIT_VAL_SET(reg, 28, atu_region->cfg_shift_mode == AL_TRUE);
	+ AL_REG_BIT_VAL_SET(reg, 29, atu_region->invert_matching == AL_TRUE);
	+ if (atu_region->tlp_type == AL_PCIE_TLP_TYPE_MEM \|\| atu_region->tlp_type == AL_PCIE_TLP_TYPE_IO)
	+ AL_REG_BIT_VAL_SET(reg, 30, !!atu_region->match_mode);
	+ AL_REG_BIT_VAL_SET(reg, 31, !!atu_region->enable);
	+
	+ /* In outbound, enable function bypass
	+ * In inbound, enable function match mode
	+ * Note: this is the same bit, has different meanings in ob/ib ATUs
	+ */
	+ if (op_mode == AL_PCIE_OPERATING_MODE_EP)
	+ AL_REG_FIELD_SET(reg,
	+ PCIE_IATU_CR2_FUNC_NUM_TRANS_BYPASS_FUNC_MATCH_ENABLE_MASK,
	+ PCIE_IATU_CR2_FUNC_NUM_TRANS_BYPASS_FUNC_MATCH_ENABLE_SHIFT,
	+ atu_region->function_match_bypass_mode ? 0x1 : 0x0);
	+
	+ al_reg_write32(&regs->port_regs->iatu.cr2, reg);
	+
	+ return 0;
	+}
	+
	+/** obtains internal ATU region base/target addresses */
	+void
	+al_pcie_atu_region_get_fields(
	+ struct al_pcie_port *pcie_port,
	+ enum al_pcie_atu_dir direction, uint8_t index,
	+ al_bool enable, uint64_t base_addr, uint64_t *target_addr)
	+{
	+ struct al_pcie_regs *regs = pcie_port->regs;
	+ uint64_t high_addr;
	+ uint32_t reg = 0;
	+
	+ AL_REG_FIELD_SET(reg, 0xF, 0, index);
	+ AL_REG_BIT_VAL_SET(reg, 31, direction);
	+ al_reg_write32(&regs->port_regs->iatu.index, reg);
	+
	+ *base_addr = al_reg_read32(&regs->port_regs->iatu.lower_base_addr);
	+ high_addr = al_reg_read32(&regs->port_regs->iatu.upper_base_addr);
	+ high_addr <<= 32;
	+ *base_addr \|= high_addr;
	+
	+ *target_addr = al_reg_read32(&regs->port_regs->iatu.lower_target_addr);
	+ high_addr = al_reg_read32(&regs->port_regs->iatu.upper_target_addr);
	+ high_addr <<= 32;
	+ *target_addr \|= high_addr;
	+
	+ reg = al_reg_read32(&regs->port_regs->iatu.cr1);
	+ *enable = AL_REG_BIT_GET(reg, 31) ? AL_TRUE : AL_FALSE;
	+}
	+
	+void
	+al_pcie_axi_io_config(
	+ struct al_pcie_port *pcie_port,
	+ al_phys_addr_t start,
	+ al_phys_addr_t end)
	+{
	+ struct al_pcie_regs *regs = pcie_port->regs;
	+
	+ al_reg_write32(regs->axi.ob_ctrl.io_start_h,
	+ (uint32_t)((start >> 32) & 0xFFFFFFFF));
	+
	+ al_reg_write32(regs->axi.ob_ctrl.io_start_l,
	+ (uint32_t)(start & 0xFFFFFFFF));
	+
	+ al_reg_write32(regs->axi.ob_ctrl.io_limit_h,
	+ (uint32_t)((end >> 32) & 0xFFFFFFFF));
	+
	+ al_reg_write32(regs->axi.ob_ctrl.io_limit_l,
	+ (uint32_t)(end & 0xFFFFFFFF));
	+
	+ al_reg_write32_masked(regs->axi.ctrl.slv_ctl,
	+ PCIE_AXI_CTRL_SLV_CTRL_IO_BAR_EN,
	+ PCIE_AXI_CTRL_SLV_CTRL_IO_BAR_EN);
	+}
	+
	+/************ Interrupt generation (Endpoint mode Only) API ***************/
	+
	+/** generate INTx Assert/DeAssert Message */
	+int
	+al_pcie_legacy_int_gen(
	+ struct al_pcie_pf *pcie_pf,
	+ al_bool assert,
	+ enum al_pcie_legacy_int_type type)
	+{
	+ struct al_pcie_regs *regs = pcie_pf->pcie_port->regs;
	+ unsigned int pf_num = pcie_pf->pf_num;
	+ uint32_t reg;
	+
	+ al_assert(type == AL_PCIE_LEGACY_INTA); /* only INTA supported */
	+ reg = al_reg_read32(regs->app.global_ctrl.events_gen[pf_num]);
	+ AL_REG_BIT_VAL_SET(reg, 3, !!assert);
	+ al_reg_write32(regs->app.global_ctrl.events_gen[pf_num], reg);
	+
	+ return 0;
	+}
	+
	+/** generate MSI interrupt */
	+int
	+al_pcie_msi_int_gen(struct al_pcie_pf *pcie_pf, uint8_t vector)
	+{
	+ struct al_pcie_regs *regs = pcie_pf->pcie_port->regs;
	+ unsigned int pf_num = pcie_pf->pf_num;
	+ uint32_t reg;
	+
	+ /* set msi vector and clear MSI request */
	+ reg = al_reg_read32(regs->app.global_ctrl.events_gen[pf_num]);
	+ AL_REG_BIT_CLEAR(reg, 4);
	+ AL_REG_FIELD_SET(reg,
	+ PCIE_W_GLOBAL_CTRL_EVENTS_GEN_MSI_VECTOR_MASK,
	+ PCIE_W_GLOBAL_CTRL_EVENTS_GEN_MSI_VECTOR_SHIFT,
	+ vector);
	+ al_reg_write32(regs->app.global_ctrl.events_gen[pf_num], reg);
	+ /* set MSI request */
	+ AL_REG_BIT_SET(reg, 4);
	+ al_reg_write32(regs->app.global_ctrl.events_gen[pf_num], reg);
	+
	+ return 0;
	+}
	+
	+/** configure MSIX capability */
	+int
	+al_pcie_msix_config(
	+ struct al_pcie_pf *pcie_pf,
	+ struct al_pcie_msix_params *msix_params)
	+{
	+ struct al_pcie_regs *regs = pcie_pf->pcie_port->regs;
	+ unsigned int pf_num = pcie_pf->pf_num;
	+ uint32_t msix_reg0;
	+
	+ al_pcie_port_wr_to_ro_set(pcie_pf->pcie_port, AL_TRUE);
	+
	+ msix_reg0 = al_reg_read32(regs->core_space[pf_num].msix_cap_base);
	+
	+ msix_reg0 &= ~(AL_PCI_MSIX_MSGCTRL_TBL_SIZE << AL_PCI_MSIX_MSGCTRL_TBL_SIZE_SHIFT);
	+ msix_reg0 \|= ((msix_params->table_size - 1) & AL_PCI_MSIX_MSGCTRL_TBL_SIZE) <<
	+ AL_PCI_MSIX_MSGCTRL_TBL_SIZE_SHIFT;
	+ al_reg_write32(regs->core_space[pf_num].msix_cap_base, msix_reg0);
	+
	+ /* Table offset & BAR */
	+ al_reg_write32(regs->core_space[pf_num].msix_cap_base + (AL_PCI_MSIX_TABLE >> 2),
	+ (msix_params->table_offset & AL_PCI_MSIX_TABLE_OFFSET) \|
	+ (msix_params->table_bar & AL_PCI_MSIX_TABLE_BAR));
	+ /* PBA offset & BAR */
	+ al_reg_write32(regs->core_space[pf_num].msix_cap_base + (AL_PCI_MSIX_PBA >> 2),
	+ (msix_params->pba_offset & AL_PCI_MSIX_PBA_OFFSET) \|
	+ (msix_params->pba_bar & AL_PCI_MSIX_PBA_BAR));
	+
	+ al_pcie_port_wr_to_ro_set(pcie_pf->pcie_port, AL_FALSE);
	+
	+ return 0;
	+}
	+
	+/** check whether MSIX is enabled */
	+al_bool
	+al_pcie_msix_enabled(struct al_pcie_pf *pcie_pf)
	+{
	+ struct al_pcie_regs *regs = pcie_pf->pcie_port->regs;
	+ uint32_t msix_reg0 = al_reg_read32(regs->core_space[pcie_pf->pf_num].msix_cap_base);
	+
	+ if (msix_reg0 & AL_PCI_MSIX_MSGCTRL_EN)
	+ return AL_TRUE;
	+ return AL_FALSE;
	+}
	+
	+/** check whether MSIX is masked */
	+al_bool
	+al_pcie_msix_masked(struct al_pcie_pf *pcie_pf)
	+{
	+ struct al_pcie_regs *regs = pcie_pf->pcie_port->regs;
	+ uint32_t msix_reg0 = al_reg_read32(regs->core_space[pcie_pf->pf_num].msix_cap_base);
	+
	+ if (msix_reg0 & AL_PCI_MSIX_MSGCTRL_MASK)
	+ return AL_TRUE;
	+ return AL_FALSE;
	+}
	+
	+/****************** Advanced Error Reporting (AER) API ********************/
	+
	+/** configure AER capability */
	+int
	+al_pcie_aer_config(
	+ struct al_pcie_pf *pcie_pf,
	+ struct al_pcie_aer_params *params)
	+{
	+ struct al_pcie_regs *regs = pcie_pf->pcie_port->regs;
	+ struct al_pcie_core_aer_regs *aer_regs = regs->core_space[pcie_pf->pf_num].aer;
	+ uint32_t reg_val;
	+
	+ reg_val = al_reg_read32(&aer_regs->header);
	+
	+ if (((reg_val & PCIE_AER_CAP_ID_MASK) >> PCIE_AER_CAP_ID_SHIFT) !=
	+ PCIE_AER_CAP_ID_VAL)
	+ return -EIO;
	+
	+ if (((reg_val & PCIE_AER_CAP_VER_MASK) >> PCIE_AER_CAP_VER_SHIFT) !=
	+ PCIE_AER_CAP_VER_VAL)
	+ return -EIO;
	+
	+ al_reg_write32(&aer_regs->corr_err_mask, ~params->enabled_corr_err);
	+
	+ al_reg_write32(&aer_regs->uncorr_err_mask,
	+ (~params->enabled_uncorr_non_fatal_err) \|
	+ (~params->enabled_uncorr_fatal_err));
	+
	+ al_reg_write32(&aer_regs->uncorr_err_severity,
	+ params->enabled_uncorr_fatal_err);
	+
	+ al_reg_write32(&aer_regs->cap_and_ctrl,
	+ (params->ecrc_gen_en ? PCIE_AER_CTRL_STAT_ECRC_GEN_EN : 0) \|
	+ (params->ecrc_chk_en ? PCIE_AER_CTRL_STAT_ECRC_CHK_EN : 0));
	+
	+ al_reg_write32_masked(
	+ regs->core_space[pcie_pf->pf_num].pcie_dev_ctrl_status,
	+ PCIE_PORT_DEV_CTRL_STATUS_CORR_ERR_REPORT_EN \|
	+ PCIE_PORT_DEV_CTRL_STATUS_NON_FTL_ERR_REPORT_EN \|
	+ PCIE_PORT_DEV_CTRL_STATUS_FTL_ERR_REPORT_EN \|
	+ PCIE_PORT_DEV_CTRL_STATUS_UNSUP_REQ_REPORT_EN,
	+ (params->enabled_corr_err ?
	+ PCIE_PORT_DEV_CTRL_STATUS_CORR_ERR_REPORT_EN : 0) \|
	+ (params->enabled_uncorr_non_fatal_err ?
	+ PCIE_PORT_DEV_CTRL_STATUS_NON_FTL_ERR_REPORT_EN : 0) \|
	+ (params->enabled_uncorr_fatal_err ?
	+ PCIE_PORT_DEV_CTRL_STATUS_FTL_ERR_REPORT_EN : 0) \|
	+ ((params->enabled_uncorr_non_fatal_err &
	+ AL_PCIE_AER_UNCORR_UNSUPRT_REQ_ERR) ?
	+ PCIE_PORT_DEV_CTRL_STATUS_UNSUP_REQ_REPORT_EN : 0) \|
	+ ((params->enabled_uncorr_fatal_err &
	+ AL_PCIE_AER_UNCORR_UNSUPRT_REQ_ERR) ?
	+ PCIE_PORT_DEV_CTRL_STATUS_UNSUP_REQ_REPORT_EN : 0));
	+
	+ return 0;
	+}
	+
	+/** AER uncorretable errors get and clear */
	+unsigned int
	+al_pcie_aer_uncorr_get_and_clear(struct al_pcie_pf *pcie_pf)
	+{
	+ struct al_pcie_regs *regs = pcie_pf->pcie_port->regs;
	+ struct al_pcie_core_aer_regs *aer_regs = regs->core_space[pcie_pf->pf_num].aer;
	+ uint32_t reg_val;
	+
	+ reg_val = al_reg_read32(&aer_regs->uncorr_err_stat);
	+ al_reg_write32(&aer_regs->uncorr_err_stat, reg_val);
	+
	+ return reg_val;
	+}
	+
	+/** AER corretable errors get and clear */
	+unsigned int
	+al_pcie_aer_corr_get_and_clear(struct al_pcie_pf *pcie_pf)
	+{
	+ struct al_pcie_regs *regs = pcie_pf->pcie_port->regs;
	+ struct al_pcie_core_aer_regs *aer_regs = regs->core_space[pcie_pf->pf_num].aer;
	+ uint32_t reg_val;
	+
	+ reg_val = al_reg_read32(&aer_regs->corr_err_stat);
	+ al_reg_write32(&aer_regs->corr_err_stat, reg_val);
	+
	+ return reg_val;
	+}
	+
	+#if (AL_PCIE_AER_ERR_TLP_HDR_NUM_DWORDS != 4)
	+#error Wrong assumption!
	+#endif
	+
	+/** AER get the header for the TLP corresponding to a detected error */
	+void
	+al_pcie_aer_err_tlp_hdr_get(
	+ struct al_pcie_pf *pcie_pf,
	+ uint32_t hdr[AL_PCIE_AER_ERR_TLP_HDR_NUM_DWORDS])
	+{
	+ struct al_pcie_regs *regs = pcie_pf->pcie_port->regs;
	+ struct al_pcie_core_aer_regs *aer_regs = regs->core_space[pcie_pf->pf_num].aer;
	+ int i;
	+
	+ for (i = 0; i < AL_PCIE_AER_ERR_TLP_HDR_NUM_DWORDS; i++)
	+ hdr[i] = al_reg_read32(&aer_regs->header_log[i]);
	+}
	+
	+/******************** Loopback mode (RC and Endpoint modes) **********/
	+
	+/** enter local pipe loopback mode */
	+int
	+al_pcie_local_pipe_loopback_enter(struct al_pcie_port *pcie_port)
	+{
	+ struct al_pcie_regs *regs = pcie_port->regs;
	+
	+ al_dbg("PCIe %d: Enter LOCAL PIPE Loopback mode", pcie_port->port_id);
	+
	+ al_reg_write32_masked(&regs->port_regs->pipe_loopback_ctrl,
	+ 1 << PCIE_PORT_PIPE_LOOPBACK_CTRL_PIPE_LB_EN_SHIFT,
	+ 1 << PCIE_PORT_PIPE_LOOPBACK_CTRL_PIPE_LB_EN_SHIFT);
	+
	+ al_reg_write32_masked(&regs->port_regs->port_link_ctrl,
	+ 1 << PCIE_PORT_LINK_CTRL_LB_EN_SHIFT,
	+ 1 << PCIE_PORT_LINK_CTRL_LB_EN_SHIFT);
	+
	+ return 0;
	+}
	+
	+/**
	+ * @brief exit local pipe loopback mode
	+ *
	+ * @param pcie_port pcie port handle
	+ * @return 0 if no error found
	+ */
	+int
	+al_pcie_local_pipe_loopback_exit(struct al_pcie_port *pcie_port)
	+{
	+ struct al_pcie_regs *regs = pcie_port->regs;
	+
	+ al_dbg("PCIe %d: Exit LOCAL PIPE Loopback mode", pcie_port->port_id);
	+
	+ al_reg_write32_masked(&regs->port_regs->pipe_loopback_ctrl,
	+ 1 << PCIE_PORT_PIPE_LOOPBACK_CTRL_PIPE_LB_EN_SHIFT,
	+ 0);
	+
	+ al_reg_write32_masked(&regs->port_regs->port_link_ctrl,
	+ 1 << PCIE_PORT_LINK_CTRL_LB_EN_SHIFT,
	+ 0);
	+ return 0;
	+}
	+
	+/** enter remote loopback mode */
	+int
	+al_pcie_remote_loopback_enter(struct al_pcie_port *pcie_port)
	+{
	+ struct al_pcie_regs *regs = pcie_port->regs;
	+
	+ al_dbg("PCIe %d: Enter REMOTE Loopback mode", pcie_port->port_id);
	+
	+ al_reg_write32_masked(&regs->port_regs->port_link_ctrl,
	+ 1 << PCIE_PORT_PIPE_LOOPBACK_CTRL_PIPE_LB_EN_SHIFT,
	+ 1 << PCIE_PORT_PIPE_LOOPBACK_CTRL_PIPE_LB_EN_SHIFT);
	+
	+ return 0;
	+}
	+
	+/**
	+ * @brief exit remote loopback mode
	+ *
	+ * @param pcie_port pcie port handle
	+ * @return 0 if no error found
	+ */
	+int
	+al_pcie_remote_loopback_exit(struct al_pcie_port *pcie_port)
	+{
	+ struct al_pcie_regs *regs = pcie_port->regs;
	+
	+ al_dbg("PCIe %d: Exit REMOTE Loopback mode", pcie_port->port_id);
	+
	+ al_reg_write32_masked(&regs->port_regs->port_link_ctrl,
	+ 1 << PCIE_PORT_LINK_CTRL_LB_EN_SHIFT,
	+ 0);
	+ return 0;
	+}
	Index: sys/arm/annapurna/alpine/hal/al_hal_pcie_axi_reg.h
	===================================================================
	--- /dev/null
	+++ sys/arm/annapurna/alpine/hal/al_hal_pcie_axi_reg.h
	@@ -0,0 +1,1501 @@
	+/*-
	+********************************************************************************
	+Copyright (C) 2015 Annapurna Labs Ltd.
	+
	+This file may be licensed under the terms of the Annapurna Labs Commercial
	+License Agreement.
	+
	+Alternatively, this file can be distributed under the terms of the GNU General
	+Public License V2 as published by the Free Software Foundation and can be
	+found at http://www.gnu.org/licenses/gpl-2.0.html
	+
	+Alternatively, redistribution and use in source and binary forms, with or
	+without modification, are permitted provided that the following conditions are
	+met:
	+
	+ * Redistributions of source code must retain the above copyright notice,
	+this list of conditions and the following disclaimer.
	+
	+ * Redistributions in binary form must reproduce the above copyright
	+notice, this list of conditions and the following disclaimer in
	+the documentation and/or other materials provided with the
	+distribution.
	+
	+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
	+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
	+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
	+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
	+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
	+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
	+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
	+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
	+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
	+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	+
	+*******************************************************************************/
	+
	+
	+#ifndef __AL_PCIE_HAL_AXI_REG_H__
	+#define __AL_PCIE_HAL_AXI_REG_H__
	+
	+#include "al_hal_plat_types.h"
	+
	+#ifdef __cplusplus
	+extern "C" {
	+#endif
	+/*
	+* Unit Registers
	+*/
	+
	+
	+
	+struct al_pcie_rev1_2_axi_ctrl {
	+ /* [0x0] */
	+ uint32_t global;
	+ uint32_t rsrvd_0;
	+ /* [0x8] */
	+ uint32_t master_bctl;
	+ /* [0xc] */
	+ uint32_t master_rctl;
	+ /* [0x10] */
	+ uint32_t master_ctl;
	+ /* [0x14] */
	+ uint32_t master_arctl;
	+ /* [0x18] */
	+ uint32_t master_awctl;
	+ /* [0x1c] */
	+ uint32_t slave_rctl;
	+ /* [0x20] */
	+ uint32_t slv_wctl;
	+ /* [0x24] */
	+ uint32_t slv_ctl;
	+ /* [0x28] */
	+ uint32_t dbi_ctl;
	+ /* [0x2c] */
	+ uint32_t vmid_mask;
	+ uint32_t rsrvd[4];
	+};
	+struct al_pcie_rev3_axi_ctrl {
	+ /* [0x0] */
	+ uint32_t global;
	+ uint32_t rsrvd_0;
	+ /* [0x8] */
	+ uint32_t master_bctl;
	+ /* [0xc] */
	+ uint32_t master_rctl;
	+ /* [0x10] */
	+ uint32_t master_ctl;
	+ /* [0x14] */
	+ uint32_t master_arctl;
	+ /* [0x18] */
	+ uint32_t master_awctl;
	+ /* [0x1c] */
	+ uint32_t slave_rctl;
	+ /* [0x20] */
	+ uint32_t slv_wctl;
	+ /* [0x24] */
	+ uint32_t slv_ctl;
	+ /* [0x28] */
	+ uint32_t dbi_ctl;
	+ /* [0x2c] */
	+ uint32_t vmid_mask;
	+};
	+struct al_pcie_rev1_axi_ob_ctrl {
	+ /* [0x0] */
	+ uint32_t cfg_target_bus;
	+ /* [0x4] */
	+ uint32_t cfg_control;
	+ /* [0x8] */
	+ uint32_t io_start_l;
	+ /* [0xc] */
	+ uint32_t io_start_h;
	+ /* [0x10] */
	+ uint32_t io_limit_l;
	+ /* [0x14] */
	+ uint32_t io_limit_h;
	+ /* [0x18] */
	+ uint32_t msg_start_l;
	+ /* [0x1c] */
	+ uint32_t msg_start_h;
	+ /* [0x20] */
	+ uint32_t msg_limit_l;
	+ /* [0x24] */
	+ uint32_t msg_limit_h;
	+ uint32_t rsrvd[6];
	+};
	+struct al_pcie_rev2_axi_ob_ctrl {
	+ /* [0x0] */
	+ uint32_t cfg_target_bus;
	+ /* [0x4] */
	+ uint32_t cfg_control;
	+ /* [0x8] */
	+ uint32_t io_start_l;
	+ /* [0xc] */
	+ uint32_t io_start_h;
	+ /* [0x10] */
	+ uint32_t io_limit_l;
	+ /* [0x14] */
	+ uint32_t io_limit_h;
	+ /* [0x18] */
	+ uint32_t msg_start_l;
	+ /* [0x1c] */
	+ uint32_t msg_start_h;
	+ /* [0x20] */
	+ uint32_t msg_limit_l;
	+ /* [0x24] */
	+ uint32_t msg_limit_h;
	+ /*
	+ * [0x28] this register override the VMID field in the AXUSER [19:4],
	+ * for the AXI master port.
	+ */
	+ uint32_t vmid_reg_ovrd;
	+ /* [0x2c] this register override the ADDR[63:32] AXI master port. */
	+ uint32_t addr_high_reg_ovrd_value;
	+ /* [0x30] this register override the ADDR[63:32] AXI master port. */
	+ uint32_t addr_high_reg_ovrd_sel;
	+ /*
	+ * [0x34] Define the size to replace in the master axi address bits
	+ * [63:32]
	+ */
	+ uint32_t addr_size_replace;
	+ uint32_t rsrvd[2];
	+};
	+struct al_pcie_rev3_axi_ob_ctrl {
	+ /* [0x0] */
	+ uint32_t cfg_target_bus;
	+ /* [0x4] */
	+ uint32_t cfg_control;
	+ /* [0x8] */
	+ uint32_t io_start_l;
	+ /* [0xc] */
	+ uint32_t io_start_h;
	+ /* [0x10] */
	+ uint32_t io_limit_l;
	+ /* [0x14] */
	+ uint32_t io_limit_h;
	+ /* [0x18] */
	+ uint32_t aw_msg_start_l;
	+ /* [0x1c] */
	+ uint32_t aw_msg_start_h;
	+ /* [0x20] */
	+ uint32_t aw_msg_limit_l;
	+ /* [0x24] */
	+ uint32_t aw_msg_limit_h;
	+ /* [0x28] */
	+ uint32_t ar_msg_start_l;
	+ /* [0x2c] */
	+ uint32_t ar_msg_start_h;
	+ /* [0x30] */
	+ uint32_t ar_msg_limit_l;
	+ /* [0x34] */
	+ uint32_t ar_msg_limit_h;
	+ /* [0x38] */
	+ uint32_t io_addr_mask_h;
	+ /* [0x3c] */
	+ uint32_t ar_msg_addr_mask_h;
	+ /* [0x40] */
	+ uint32_t aw_msg_addr_mask_h;
	+ /*
	+ * [0x44] this register override the VMID field in the AXUSER [19:4],
	+ * for the AXI master port.
	+ */
	+ uint32_t vmid_reg_ovrd;
	+ /* [0x48] this register override the ADDR[63:32] AXI master port. */
	+ uint32_t addr_high_reg_ovrd_value;
	+ /* [0x4c] this register override the ADDR[63:32] AXI master port. */
	+ uint32_t addr_high_reg_ovrd_sel;
	+ /*
	+ * [0x50] Define the size to replace in the master axi address bits
	+ * [63:32]
	+ */
	+ uint32_t addr_size_replace;
	+ uint32_t rsrvd[3];
	+};
	+struct al_pcie_revx_axi_msg {
	+ /* [0x0] */
	+ uint32_t addr_high;
	+ /* [0x4] */
	+ uint32_t addr_low;
	+ /* [0x8] */
	+ uint32_t type;
	+};
	+struct al_pcie_revx_axi_pcie_status {
	+ /* [0x0] */
	+ uint32_t debug;
	+};
	+struct al_pcie_revx_axi_rd_parity {
	+ /* [0x0] */
	+ uint32_t log_high;
	+ /* [0x4] */
	+ uint32_t log_low;
	+};
	+struct al_pcie_revx_axi_rd_cmpl {
	+ /* [0x0] */
	+ uint32_t cmpl_log_high;
	+ /* [0x4] */
	+ uint32_t cmpl_log_low;
	+};
	+struct al_pcie_revx_axi_rd_to {
	+ /* [0x0] */
	+ uint32_t to_log_high;
	+ /* [0x4] */
	+ uint32_t to_log_low;
	+};
	+struct al_pcie_revx_axi_wr_cmpl {
	+ /* [0x0] */
	+ uint32_t wr_cmpl_log_high;
	+ /* [0x4] */
	+ uint32_t wr_cmpl_log_low;
	+};
	+struct al_pcie_revx_axi_wr_to {
	+ /* [0x0] */
	+ uint32_t wr_to_log_high;
	+ /* [0x4] */
	+ uint32_t wr_to_log_low;
	+};
	+struct al_pcie_revx_axi_pcie_global {
	+ /* [0x0] */
	+ uint32_t conf;
	+};
	+struct al_pcie_rev1_2_axi_status {
	+ /* [0x0] */
	+ uint32_t lane0;
	+ /* [0x4] */
	+ uint32_t lane1;
	+ /* [0x8] */
	+ uint32_t lane2;
	+ /* [0xc] */
	+ uint32_t lane3;
	+};
	+struct al_pcie_rev3_axi_status {
	+ /* [0x0] */
	+ uint32_t lane0;
	+ /* [0x4] */
	+ uint32_t lane1;
	+ /* [0x8] */
	+ uint32_t lane2;
	+ /* [0xc] */
	+ uint32_t lane3;
	+ /* [0x10] */
	+ uint32_t lane4;
	+ /* [0x14] */
	+ uint32_t lane5;
	+ /* [0x18] */
	+ uint32_t lane6;
	+ /* [0x1c] */
	+ uint32_t lane7;
	+ uint32_t rsrvd[8];
	+};
	+struct al_pcie_rev1_2_axi_conf {
	+ /* [0x0] */
	+ uint32_t zero_lane0;
	+ /* [0x4] */
	+ uint32_t zero_lane1;
	+ /* [0x8] */
	+ uint32_t zero_lane2;
	+ /* [0xc] */
	+ uint32_t zero_lane3;
	+ /* [0x10] */
	+ uint32_t one_lane0;
	+ /* [0x14] */
	+ uint32_t one_lane1;
	+ /* [0x18] */
	+ uint32_t one_lane2;
	+ /* [0x1c] */
	+ uint32_t one_lane3;
	+};
	+struct al_pcie_rev3_axi_conf {
	+ /* [0x0] */
	+ uint32_t zero_lane0;
	+ /* [0x4] */
	+ uint32_t zero_lane1;
	+ /* [0x8] */
	+ uint32_t zero_lane2;
	+ /* [0xc] */
	+ uint32_t zero_lane3;
	+ /* [0x10] */
	+ uint32_t zero_lane4;
	+ /* [0x14] */
	+ uint32_t zero_lane5;
	+ /* [0x18] */
	+ uint32_t zero_lane6;
	+ /* [0x1c] */
	+ uint32_t zero_lane7;
	+ /* [0x20] */
	+ uint32_t one_lane0;
	+ /* [0x24] */
	+ uint32_t one_lane1;
	+ /* [0x28] */
	+ uint32_t one_lane2;
	+ /* [0x2c] */
	+ uint32_t one_lane3;
	+ /* [0x30] */
	+ uint32_t one_lane4;
	+ /* [0x34] */
	+ uint32_t one_lane5;
	+ /* [0x38] */
	+ uint32_t one_lane6;
	+ /* [0x3c] */
	+ uint32_t one_lane7;
	+ uint32_t rsrvd[16];
	+};
	+
	+struct al_pcie_revx_axi_msg_attr_axuser_table {
	+ /* [0x0] 4 option, the index comes from */
	+ uint32_t entry_vec;
	+};
	+
	+struct al_pcie_revx_axi_parity {
	+ /* [0x0] */
	+ uint32_t en_axi;
	+ /* [0x4] */
	+ uint32_t status_axi;
	+};
	+struct al_pcie_revx_axi_pos_logged {
	+ /* [0x0] */
	+ uint32_t error_low;
	+ /* [0x4] */
	+ uint32_t error_high;
	+};
	+struct al_pcie_revx_axi_ordering {
	+ /* [0x0] */
	+ uint32_t pos_cntl;
	+};
	+struct al_pcie_revx_axi_link_down {
	+ /* [0x0] */
	+ uint32_t reset_extend;
	+};
	+struct al_pcie_revx_axi_pre_configuration {
	+ /* [0x0] */
	+ uint32_t pcie_core_setup;
	+};
	+struct al_pcie_revx_axi_init_fc {
	+ /*
	+ * Revision 1/2:
	+ * [0x0] The sum of all the fields below must be 97
	+ * Revision 3:
	+ * [0x0] The sum of all the fields below must be 259
	+ * */
	+ uint32_t cfg;
	+};
	+struct al_pcie_revx_axi_int_grp_a_axi {
	+ /*
	+ * [0x0] Interrupt Cause Register
	+ * Set by hardware.
	+ * - If MSI-X is enabled, and auto_clear control bit =TRUE,
	+ * automatically cleared after MSI-X message associated with this
	+ * specific interrupt bit is sent (MSI-X acknowledge is received).
	+ * - Software can set a bit in this register by writing 1 to the
	+ * associated bit in the Interrupt Cause Set register.
	+ * Write-0 clears a bit. Write-1 has no effect.
	+ * - On CPU Read -- If clear_on_read control bit =TRUE, automatically
	+ * cleared (all bits are cleared).
	+ * When there is a conflict, and on the same clock cycle hardware tries
	+ * to set a bit in the Interrupt Cause register, the specific bit is set
	+ * to ensure the interrupt indication is not lost.
	+ */
	+ uint32_t cause;
	+ uint32_t rsrvd_0;
	+ /*
	+ * [0x8] Interrupt Cause Set Register
	+ * Writing 1 to a bit in this register sets its corresponding cause bit,
	+ * enabling software to generate a hardware interrupt. Write 0 has no
	+ * effect.
	+ */
	+ uint32_t cause_set;
	+ uint32_t rsrvd_1;
	+ /*
	+ * [0x10] Interrupt Mask Register
	+ * If Auto-mask control bit =TRUE, automatically set to 1 after MSI-X
	+ * message associate to the associate interrupt bit is sent (AXI write
	+ * acknowledge is received)
	+ */
	+ uint32_t mask;
	+ uint32_t rsrvd_2;
	+ /*
	+ * [0x18] Interrupt Mask Clear Register
	+ * Used when auto-mask control bit=True. It enables the CPU to clear a
	+ * specific bit, preventing a scenario in which the CPU overrides
	+ * another bit with 1 (old value) that hardware has just cleared to 0.
	+ * Writing 0 to this register clears its corresponding mask bit. Write 1
	+ * has no effect.
	+ */
	+ uint32_t mask_clear;
	+ uint32_t rsrvd_3;
	+ /*
	+ * [0x20] Interrupt Status Register
	+ * This register latches the status of the interrupt source.
	+ */
	+ uint32_t status;
	+ uint32_t rsrvd_4;
	+ /* [0x28] Interrupt Control Register */
	+ uint32_t control;
	+ uint32_t rsrvd_5;
	+ /*
	+ * [0x30] Interrupt Mask Register
	+ * Each bit in this register masks the corresponding cause bit for
	+ * generating an Abort signal. Its default value is determined by unit
	+ * instantiation.
	+ * Abort = Wire-OR of Cause & !Interrupt_Abort_Mask).
	+ * This register provides an error handling configuration for error
	+ * interrupts.
	+ */
	+ uint32_t abort_mask;
	+ uint32_t rsrvd_6;
	+ /*
	+ * [0x38] Interrupt Log Register
	+ * Each bit in this register masks the corresponding cause bit for
	+ * capturing the log registers. Its default value is determined by unit
	+ * instantiatio.n
	+ * Log_capture = Wire-OR of Cause & !Interrupt_Log_Mask).
	+ * This register provides an error handling configuration for error
	+ * interrupts.
	+ */
	+ uint32_t log_mask;
	+ uint32_t rsrvd;
	+};
	+
	+struct al_pcie_rev3_axi_eq_ovrd_tx_rx_values {
	+ /* [0x0] */
	+ uint32_t cfg_0;
	+ /* [0x4] */
	+ uint32_t cfg_1;
	+ /* [0x8] */
	+ uint32_t cfg_2;
	+ /* [0xc] */
	+ uint32_t cfg_3;
	+ /* [0x10] */
	+ uint32_t cfg_4;
	+ /* [0x14] */
	+ uint32_t cfg_5;
	+ /* [0x18] */
	+ uint32_t cfg_6;
	+ /* [0x1c] */
	+ uint32_t cfg_7;
	+ /* [0x20] */
	+ uint32_t cfg_8;
	+ /* [0x24] */
	+ uint32_t cfg_9;
	+ /* [0x28] */
	+ uint32_t cfg_10;
	+ /* [0x2c] */
	+ uint32_t cfg_11;
	+ uint32_t rsrvd[12];
	+};
	+struct al_pcie_rev3_axi_dbg_outstading_trans_axi {
	+ /* [0x0] */
	+ uint32_t read_master_counter;
	+ /* [0x4] */
	+ uint32_t write_master_counter;
	+ /* [0x8] */
	+ uint32_t read_slave_counter;
	+};
	+struct al_pcie_revx_axi_device_id {
	+ /* [0x0] */
	+ uint32_t device_rev_id;
	+};
	+struct al_pcie_revx_axi_power_mang_ovrd_cntl {
	+ /* [0x0] */
	+ uint32_t cfg_static_nof_elidle;
	+ /* [0x4] */
	+ uint32_t cfg_l0s_wait_ovrd;
	+ /* [0x8] */
	+ uint32_t cfg_l12_wait_ovrd;
	+ /* [0xc] */
	+ uint32_t cfg_l0s_delay_in_p0s;
	+ /* [0x10] */
	+ uint32_t cfg_l12_delay_in_p12;
	+ /* [0x14] */
	+ uint32_t cfg_l12_delay_in_p12_clk_rst;
	+ /* [0x18] */
	+ uint32_t cfg_delay_powerdown_bus;
	+ uint32_t rsrvd;
	+};
	+struct al_pcie_rev3_axi_dbg_outstading_trans_axi_write {
	+ /* [0x0] */
	+ uint32_t slave_counter;
	+};
	+struct al_pcie_rev3_axi_attr_ovrd {
	+ /*
	+ * [0x0] In case of hit on the io message bar and
	+ * a*_cfg_outbound_msg_no_snoop_n, the message attributes come from this
	+ * register
	+ */
	+ uint32_t write_msg_ctrl_0;
	+ /* [0x4] in case of message this register set the below attributes */
	+ uint32_t write_msg_ctrl_1;
	+ /*
	+ * [0x8] In case of hit on the io message bar and
	+ * a*_cfg_outbound_msg_no_snoop_n, the message attributes come from this
	+ * register
	+ */
	+ uint32_t read_msg_ctrl_0;
	+ /* [0xc] in case of message this register set the below attributes */
	+ uint32_t read_msg_ctrl_1;
	+ /* [0x10] in case of message this register set the below attributes */
	+ uint32_t pf_sel;
	+ uint32_t rsrvd[3];
	+};
	+struct al_pcie_rev3_axi_pf_axi_attr_ovrd {
	+ /*
	+ * [0x0] In case of hit on the io message bar and
	+ * a*_cfg_outbound_msg_no_snoop_n, the message attributes come from this
	+ * register
	+ */
	+ uint32_t func_ctrl_0;
	+ /* [0x4] in case of message this register set the below attributes */
	+ uint32_t func_ctrl_1;
	+ /*
	+ * [0x8] In case of hit on the io message bar and
	+ * a*_cfg_outbound_msg_no_snoop_n, the message attributes come from this
	+ * register
	+ */
	+ uint32_t func_ctrl_2;
	+ /*
	+ * [0xc] In case of hit on the io message bar and
	+ * a*_cfg_outbound_msg_no_snoop_n, the message attributes come from this
	+ * register
	+ */
	+ uint32_t func_ctrl_3;
	+ /*
	+ * [0x10] In case of hit on the io message bar and
	+ * a*_cfg_outbound_msg_no_snoop_n, the message attributes come from this
	+ * register
	+ */
	+ uint32_t func_ctrl_4;
	+ /*
	+ * [0x14] In case of hit on the io message bar and
	+ * a*_cfg_outbound_msg_no_snoop_n, the message attributes come from this
	+ * register
	+ */
	+ uint32_t func_ctrl_5;
	+ /*
	+ * [0x18] In case of hit on the io message bar and
	+ * a*_cfg_outbound_msg_no_snoop_n, the message attributes come from this
	+ * register
	+ */
	+ uint32_t func_ctrl_6;
	+ /*
	+ * [0x1c] In case of hit on the io message bar and
	+ * a*_cfg_outbound_msg_no_snoop_n, the message attributes come from this
	+ * register
	+ */
	+ uint32_t func_ctrl_7;
	+ /*
	+ * [0x20] In case of hit on the io message bar and
	+ * a*_cfg_outbound_msg_no_snoop_n, the message attributes come from this
	+ * register
	+ */
	+ uint32_t func_ctrl_8;
	+ /*
	+ * [0x24] In case of hit on the io message bar and
	+ * a*_cfg_outbound_msg_no_snoop_n, the message attributes come from this
	+ * register
	+ */
	+ uint32_t func_ctrl_9;
	+ uint32_t rsrvd[6];
	+};
	+
	+struct al_pcie_revx_axi_regs {
	+ uint32_t rsrvd_0[91];
	+ struct al_pcie_revx_axi_device_id device_id; /* [0x16c] */
	+};
	+
	+struct al_pcie_rev1_axi_regs {
	+ struct al_pcie_rev1_2_axi_ctrl ctrl; /* [0x0] */
	+ struct al_pcie_rev1_axi_ob_ctrl ob_ctrl; /* [0x40] */
	+ uint32_t rsrvd_0[4];
	+ struct al_pcie_revx_axi_msg msg; /* [0x90] */
	+ struct al_pcie_revx_axi_pcie_status pcie_status; /* [0x9c] */
	+ struct al_pcie_revx_axi_rd_parity rd_parity; /* [0xa0] */
	+ struct al_pcie_revx_axi_rd_cmpl rd_cmpl; /* [0xa8] */
	+ struct al_pcie_revx_axi_rd_to rd_to; /* [0xb0] */
	+ struct al_pcie_revx_axi_wr_cmpl wr_cmpl; /* [0xb8] */
	+ struct al_pcie_revx_axi_wr_to wr_to; /* [0xc0] */
	+ struct al_pcie_revx_axi_pcie_global pcie_global; /* [0xc8] */
	+ struct al_pcie_rev1_2_axi_status status; /* [0xcc] */
	+ struct al_pcie_rev1_2_axi_conf conf; /* [0xdc] */
	+ struct al_pcie_revx_axi_parity parity; /* [0xfc] */
	+ struct al_pcie_revx_axi_pos_logged pos_logged; /* [0x104] */
	+ struct al_pcie_revx_axi_ordering ordering; /* [0x10c] */
	+ struct al_pcie_revx_axi_link_down link_down; /* [0x110] */
	+ struct al_pcie_revx_axi_pre_configuration pre_configuration; /* [0x114] */
	+ struct al_pcie_revx_axi_init_fc init_fc; /* [0x118] */
	+ uint32_t rsrvd_1[20];
	+ struct al_pcie_revx_axi_device_id device_id; /* [0x16c] */
	+ uint32_t rsrvd_2[36];
	+ struct al_pcie_revx_axi_int_grp_a_axi int_grp_a; /* [0x200] */
	+};
	+
	+struct al_pcie_rev2_axi_regs {
	+ struct al_pcie_rev1_2_axi_ctrl ctrl; /* [0x0] */
	+ struct al_pcie_rev2_axi_ob_ctrl ob_ctrl; /* [0x40] */
	+ uint32_t rsrvd_0[4];
	+ struct al_pcie_revx_axi_msg msg; /* [0x90] */
	+ struct al_pcie_revx_axi_pcie_status pcie_status; /* [0x9c] */
	+ struct al_pcie_revx_axi_rd_parity rd_parity; /* [0xa0] */
	+ struct al_pcie_revx_axi_rd_cmpl rd_cmpl; /* [0xa8] */
	+ struct al_pcie_revx_axi_rd_to rd_to; /* [0xb0] */
	+ struct al_pcie_revx_axi_wr_cmpl wr_cmpl; /* [0xb8] */
	+ struct al_pcie_revx_axi_wr_to wr_to; /* [0xc0] */
	+ struct al_pcie_revx_axi_pcie_global pcie_global; /* [0xc8] */
	+ struct al_pcie_rev1_2_axi_status status; /* [0xcc] */
	+ struct al_pcie_rev1_2_axi_conf conf; /* [0xdc] */
	+ struct al_pcie_revx_axi_parity parity; /* [0xfc] */
	+ struct al_pcie_revx_axi_pos_logged pos_logged; /* [0x104] */
	+ struct al_pcie_revx_axi_ordering ordering; /* [0x10c] */
	+ struct al_pcie_revx_axi_link_down link_down; /* [0x110] */
	+ struct al_pcie_revx_axi_pre_configuration pre_configuration; /* [0x114] */
	+ struct al_pcie_revx_axi_init_fc init_fc; /* [0x118] */
	+ uint32_t rsrvd_1[20];
	+ struct al_pcie_revx_axi_device_id device_id; /* [0x16c] */
	+ uint32_t rsrvd_2[36];
	+ struct al_pcie_revx_axi_int_grp_a_axi int_grp_a; /* [0x200] */
	+};
	+
	+struct al_pcie_rev3_axi_regs {
	+ struct al_pcie_rev3_axi_ctrl ctrl; /* [0x0] */
	+ struct al_pcie_rev3_axi_ob_ctrl ob_ctrl;/* [0x30] */
	+ struct al_pcie_revx_axi_msg msg; /* [0x90] */
	+ struct al_pcie_revx_axi_pcie_status pcie_status; /* [0x9c] */
	+ struct al_pcie_revx_axi_rd_parity rd_parity; /* [0xa0] */
	+ struct al_pcie_revx_axi_rd_cmpl rd_cmpl; /* [0xa8] */
	+ struct al_pcie_revx_axi_rd_to rd_to; /* [0xb0] */
	+ struct al_pcie_revx_axi_wr_cmpl wr_cmpl; /* [0xb8] */
	+ struct al_pcie_revx_axi_wr_to wr_to; /* [0xc0] */
	+ struct al_pcie_revx_axi_pcie_global pcie_global; /* [0xc8] */
	+ uint32_t rsrvd_0;
	+ struct al_pcie_revx_axi_parity parity; /* [0xd0] */
	+ struct al_pcie_revx_axi_pos_logged pos_logged; /* [0xd8] */
	+ struct al_pcie_revx_axi_ordering ordering; /* [0xe0] */
	+ struct al_pcie_revx_axi_link_down link_down; /* [0xe4] */
	+ struct al_pcie_revx_axi_pre_configuration pre_configuration;/* [0xe8] */
	+ struct al_pcie_revx_axi_init_fc init_fc; /* [0xec] */
	+ uint32_t rsrvd_1[4];
	+ struct al_pcie_rev3_axi_eq_ovrd_tx_rx_values eq_ovrd_tx_rx_values;/* [0x100] */
	+ struct al_pcie_rev3_axi_dbg_outstading_trans_axi dbg_outstading_trans_axi;/* [0x160] */
	+ struct al_pcie_revx_axi_device_id device_id; /* [0x16c] */
	+ struct al_pcie_revx_axi_power_mang_ovrd_cntl power_mang_ovrd_cntl;/* [0x170] */
	+ struct al_pcie_rev3_axi_dbg_outstading_trans_axi_write dbg_outstading_trans_axi_write;/* [0x190] */
	+ uint32_t rsrvd_2[3];
	+ struct al_pcie_rev3_axi_attr_ovrd axi_attr_ovrd; /* [0x1a0] */
	+ struct al_pcie_rev3_axi_pf_axi_attr_ovrd pf_axi_attr_ovrd[REV3_MAX_NUM_OF_PFS];/* [0x1c0] */
	+ uint32_t rsrvd_3[64];
	+ struct al_pcie_rev3_axi_status status; /* [0x3c0] */
	+ struct al_pcie_rev3_axi_conf conf; /* [0x400] */
	+ uint32_t rsrvd_4[32];
	+ struct al_pcie_revx_axi_msg_attr_axuser_table msg_attr_axuser_table; /* [0x500] */
	+ uint32_t rsrvd_5[191];
	+ struct al_pcie_revx_axi_int_grp_a_axi int_grp_a; /* [0x800] */
	+};
	+
	+/*
	+* Registers Fields
	+*/
	+
	+/** Device ID register **/
	+#define PCIE_AXI_DEVICE_ID_REG_DEV_ID_MASK AL_FIELD_MASK(31, 16)
	+#define PCIE_AXI_DEVICE_ID_REG_DEV_ID_SHIFT 16
	+#define PCIE_AXI_DEVICE_ID_REG_DEV_ID_X4 (0 << PCIE_AXI_DEVICE_ID_REG_DEV_ID_SHIFT)
	+#define PCIE_AXI_DEVICE_ID_REG_DEV_ID_X8 (2 << PCIE_AXI_DEVICE_ID_REG_DEV_ID_SHIFT)
	+#define PCIE_AXI_DEVICE_ID_REG_REV_ID_MASK AL_FIELD_MASK(15, 0)
	+#define PCIE_AXI_DEVICE_ID_REG_REV_ID_SHIFT 0
	+
	+/** Global register **/
	+/*
	+ * Not in use.
	+ * Disable completion after inbound posted ordering enforcement to AXI bridge.
	+ */
	+#define PCIE_AXI_CTRL_GLOBAL_CPL_AFTER_P_ORDER_DIS (1 << 0)
	+/*
	+ * Not in use.
	+ * Enforce completion after write ordering on AXI bridge. Only for CPU read
	+ * requests.
	+ */
	+#define PCIE_AXI_CTRL_GLOBAL_CPU_CPL_ONLY_EN (1 << 1)
	+/* When linked down, map all transactions to PCIe to DEC ERR. */
	+#define PCIE_AXI_CTRL_GLOBAL_BLOCK_PCIE_SLAVE_EN (1 << 2)
	+/*
	+ * Wait for the NIC to flush before enabling reset to the PCIe core, on a link
	+ * down event.
	+ */
	+#define PCIE_AXI_CTRL_GLOBAL_WAIT_SLV_FLUSH_EN (1 << 3)
	+/*
	+ * When the BME is cleared and this bit is set, it causes all transactions that
	+ * do not get to the PCIe to be returned with DECERR.
	+ */
	+#define PCIE_REV1_2_AXI_CTRL_GLOBAL_MEM_BAR_MAP_TO_ERR (1 << 4)
	+#define PCIE_REV3_AXI_CTRL_GLOBAL_MEM_BAR_MAP_TO_ERR_MASK 0x00000FF0
	+#define PCIE_REV3_AXI_CTRL_GLOBAL_MEM_BAR_MAP_TO_ERR_SHIFT 4
	+/*
	+ * Wait for the DBI port (the port that enables access to the internal PCIe core
	+ * registers) to flush before enabling reset to the PCIe core on link down
	+ * event.
	+ */
	+#define PCIE_REV1_2_AXI_CTRL_GLOBAL_WAIT_DBI_FLUSH_EN (1 << 5)
	+#define PCIE_REV3_AXI_CTRL_GLOBAL_WAIT_DBI_FLUSH_EN (1 << 12)
	+/* Reserved. Read undefined; must read as zeros. */
	+#define PCIE_REV3_AXI_CTRL_GLOBAL_CFG_FLUSH_DBI_AXI (1 << 13)
	+/* Reserved. Read undefined; must read as zeros. */
	+#define PCIE_REV3_AXI_CTRL_GLOBAL_CFG_HOLD_LNKDWN_RESET_SW (1 << 14)
	+/* Reserved. Read undefined; must read as zeros. */
	+#define PCIE_REV3_AXI_CTRL_GLOBAL_CFG_MASK_CORECLK_ACT_CLK_RST (1 << 15)
	+/* Reserved. Read undefined; must read as zeros. */
	+#define PCIE_REV3_AXI_CTRL_GLOBAL_CFG_MASK_RXELECIDLE_CLK_RST (1 << 16)
	+/* Reserved. Read undefined; must read as zeros. */
	+#define PCIE_REV3_AXI_CTRL_GLOBAL_CFG_ALLOW_NONSTICKY_RESET_WHEN_LNKDOWN_CLK_RST (1 << 17)
	+
	+/*
	+ * When set, adds parity on the write and read address channels, and write data
	+ * channel.
	+ */
	+#define PCIE_REV1_2_AXI_CTRL_GLOBAL_PARITY_CALC_EN_MSTR (1 << 16)
	+#define PCIE_REV3_AXI_CTRL_GLOBAL_PARITY_CALC_EN_MSTR (1 << 18)
	+/* When set, enables parity check on the read data. */
	+#define PCIE_REV1_2_AXI_CTRL_GLOBAL_PARITY_ERR_EN_RD (1 << 17)
	+#define PCIE_REV3_AXI_CTRL_GLOBAL_PARITY_ERR_EN_RD (1 << 19)
	+/*
	+ * When set, adds parity on the RD data channel.
	+ */
	+#define PCIE_REV1_2_AXI_CTRL_GLOBAL_PARITY_CALC_EN_SLV (1 << 18)
	+#define PCIE_REV3_AXI_CTRL_GLOBAL_PARITY_CALC_EN_SLV (1 << 20)
	+/*
	+ * When set, enables parity check on the write data.
	+ */
	+#define PCIE_REV1_2_AXI_CTRL_GLOBAL_PARITY_ERR_EN_WR (1 << 19)
	+#define PCIE_REV3_AXI_CTRL_GLOBAL_PARITY_ERR_EN_WR (1 << 21)
	+/*
	+ * When set, error track for timeout and parity is disabled, i.e., the logged
	+ * address for parity/timeout/cmpl errors on the AXI master port is not valid,
	+ * and timeout and completion errors check are disabled.
	+ */
	+#define PCIE_REV1_2_AXI_CTRL_GLOBAL_ERROR_TRACK_DIS (1 << 20)
	+#define PCIE_REV3_AXI_CTRL_GLOBAL_ERROR_TRACK_DIS (1 << 22)
	+
	+/** Master_Arctl register **/
	+/* override arcache */
	+#define PCIE_AXI_CTRL_MASTER_ARCTL_OVR_ARCACHE (1 << 0)
	+/* arache value */
	+#define PCIE_AXI_CTRL_MASTER_ARCTL_ARACHE_VA_MASK 0x0000001E
	+#define PCIE_AXI_CTRL_MASTER_ARCTL_ARACHE_VA_SHIFT 1
	+/* arprot override */
	+#define PCIE_AXI_CTRL_MASTER_ARCTL_ARPROT_OVR (1 << 5)
	+/* arprot value */
	+#define PCIE_AXI_CTRL_MASTER_ARCTL_ARPROT_VALUE_MASK 0x000001C0
	+#define PCIE_AXI_CTRL_MASTER_ARCTL_ARPROT_VALUE_SHIFT 6
	+/* vmid val */
	+#define PCIE_AXI_CTRL_MASTER_ARCTL_VMID_VAL_MASK 0x01FFFE00
	+#define PCIE_AXI_CTRL_MASTER_ARCTL_VMID_VAL_SHIFT 9
	+/* IPA value */
	+#define PCIE_AXI_CTRL_MASTER_ARCTL_IPA_VAL (1 << 25)
	+/* overide snoop inidcation, if not set take it from mstr_armisc ... */
	+#define PCIE_AXI_CTRL_MASTER_ARCTL_OVR_SNOOP (1 << 26)
	+/*
	+snoop indication value when override */
	+#define PCIE_AXI_CTRL_MASTER_ARCTL_SNOOP (1 << 27)
	+/*
	+arqos value */
	+#define PCIE_AXI_CTRL_MASTER_ARCTL_ARQOS_MASK 0xF0000000
	+#define PCIE_AXI_CTRL_MASTER_ARCTL_ARQOS_SHIFT 28
	+
	+/** Master_Awctl register **/
	+/* override arcache */
	+#define PCIE_AXI_CTRL_MASTER_AWCTL_OVR_ARCACHE (1 << 0)
	+/* awache value */
	+#define PCIE_AXI_CTRL_MASTER_AWCTL_AWACHE_VA_MASK 0x0000001E
	+#define PCIE_AXI_CTRL_MASTER_AWCTL_AWACHE_VA_SHIFT 1
	+/* awprot override */
	+#define PCIE_AXI_CTRL_MASTER_AWCTL_AWPROT_OVR (1 << 5)
	+/* awprot value */
	+#define PCIE_AXI_CTRL_MASTER_AWCTL_AWPROT_VALUE_MASK 0x000001C0
	+#define PCIE_AXI_CTRL_MASTER_AWCTL_AWPROT_VALUE_SHIFT 6
	+/* vmid val */
	+#define PCIE_AXI_CTRL_MASTER_AWCTL_VMID_VAL_MASK 0x01FFFE00
	+#define PCIE_AXI_CTRL_MASTER_AWCTL_VMID_VAL_SHIFT 9
	+/* IPA value */
	+#define PCIE_AXI_CTRL_MASTER_AWCTL_IPA_VAL (1 << 25)
	+/* overide snoop inidcation, if not set take it from mstr_armisc ... */
	+#define PCIE_AXI_CTRL_MASTER_AWCTL_OVR_SNOOP (1 << 26)
	+/*
	+snoop indication value when override */
	+#define PCIE_AXI_CTRL_MASTER_AWCTL_SNOOP (1 << 27)
	+/*
	+awqos value */
	+#define PCIE_AXI_CTRL_MASTER_AWCTL_AWQOS_MASK 0xF0000000
	+#define PCIE_AXI_CTRL_MASTER_AWCTL_AWQOS_SHIFT 28
	+
	+/** slv_ctl register **/
	+#define PCIE_AXI_CTRL_SLV_CTRL_IO_BAR_EN (1 << 6)
	+
	+/** Cfg_Target_Bus register **/
	+/*
	+ * Defines which MSBs to complete the number of the bust that arrived from ECAM.
	+ * If set to 0, take the bit from the ECAM bar, otherwise from the busnum of
	+ * this register.
	+ * The LSB for the bus number comes on the addr[*:20].
	+ */
	+#define PCIE_AXI_MISC_OB_CTRL_CFG_TARGET_BUS_MASK_MASK 0x000000FF
	+#define PCIE_AXI_MISC_OB_CTRL_CFG_TARGET_BUS_MASK_SHIFT 0
	+/* Target bus number for outbound configuration type0 and type1 access */
	+#define PCIE_AXI_MISC_OB_CTRL_CFG_TARGET_BUS_BUSNUM_MASK 0x0000FF00
	+#define PCIE_AXI_MISC_OB_CTRL_CFG_TARGET_BUS_BUSNUM_SHIFT 8
	+
	+/** Cfg_Control register **/
	+/* Primary bus number */
	+#define PCIE_AXI_MISC_OB_CTRL_CFG_CONTROL_PBUS_MASK 0x000000FF
	+#define PCIE_AXI_MISC_OB_CTRL_CFG_CONTROL_PBUS_SHIFT 0
	+/*
	+ *
	+ * Subordinate bus number
	+ */
	+#define PCIE_AXI_MISC_OB_CTRL_CFG_CONTROL_SUBBUS_MASK 0x0000FF00
	+#define PCIE_AXI_MISC_OB_CTRL_CFG_CONTROL_SUBBUS_SHIFT 8
	+/* Secondary bus nnumber */
	+#define PCIE_AXI_MISC_OB_CTRL_CFG_CONTROL_SEC_BUS_MASK 0x00FF0000
	+#define PCIE_AXI_MISC_OB_CTRL_CFG_CONTROL_SEC_BUS_SHIFT 16
	+/* Enable outbound configuration access through iATU. */
	+#define PCIE_AXI_MISC_OB_CTRL_CFG_CONTROL_IATU_EN (1 << 31)
	+
	+/** IO_Start_H register **/
	+/*
	+ *
	+ * Outbound ATIU I/O start address high
	+ */
	+#define PCIE_AXI_MISC_OB_CTRL_IO_START_H_ADDR_MASK 0x000003FF
	+#define PCIE_AXI_MISC_OB_CTRL_IO_START_H_ADDR_SHIFT 0
	+
	+/** IO_Limit_H register **/
	+/*
	+ *
	+ * Outbound ATIU I/O limit address high
	+ */
	+#define PCIE_AXI_MISC_OB_CTRL_IO_LIMIT_H_ADDR_MASK 0x000003FF
	+#define PCIE_AXI_MISC_OB_CTRL_IO_LIMIT_H_ADDR_SHIFT 0
	+
	+/** Msg_Start_H register **/
	+/*
	+ *
	+ * Outbound ATIU msg-no-data start address high
	+ */
	+#define PCIE_AXI_MISC_OB_CTRL_MSG_START_H_ADDR_MASK 0x000003FF
	+#define PCIE_AXI_MISC_OB_CTRL_MSG_START_H_ADDR_SHIFT 0
	+
	+/** Msg_Limit_H register **/
	+/*
	+ *
	+ * Outbound ATIU msg-no-data limit address high
	+ */
	+#define PCIE_AXI_MISC_OB_CTRL_MSG_LIMIT_H_ADDR_MASK 0x000003FF
	+#define PCIE_AXI_MISC_OB_CTRL_MSG_LIMIT_H_ADDR_SHIFT 0
	+
	+/** vmid_reg_ovrd register **/
	+/*
	+ * select if to take the value from register or from address[63:48]:
	+ * 1'b1: register value.
	+ * 1'b0: from address[63:48]
	+ */
	+#define PCIE_AXI_MISC_OB_CTRL_VMID_REG_OVRD_SEL_MASK 0x0000FFFF
	+#define PCIE_AXI_MISC_OB_CTRL_VMID_REG_OVRD_SEL_SHIFT 0
	+/* vmid override value. */
	+#define PCIE_AXI_MISC_OB_CTRL_VMID_REG_OVRD_VALUE_MASK 0xFFFF0000
	+#define PCIE_AXI_MISC_OB_CTRL_VMID_REG_OVRD_VALUE_SHIFT 16
	+
	+/** addr_size_replace register **/
	+/*
	+ * Size in bits to replace from bit [63:64-N], when equal zero no replace is
	+ * done.
	+ */
	+#define PCIE_AXI_MISC_OB_CTRL_ADDR_SIZE_REPLACE_VALUE_MASK 0x0000FFFF
	+#define PCIE_AXI_MISC_OB_CTRL_ADDR_SIZE_REPLACE_VALUE_SHIFT 0
	+/* Reserved. */
	+#define PCIE_AXI_MISC_OB_CTRL_ADDR_SIZE_REPLACE_RSRVD_MASK 0xFFFF0000
	+#define PCIE_AXI_MISC_OB_CTRL_ADDR_SIZE_REPLACE_RSRVD_SHIFT 16
	+
	+/** type register **/
	+/* Type of message */
	+#define PCIE_AXI_MISC_MSG_TYPE_TYPE_MASK 0x00FFFFFF
	+#define PCIE_AXI_MISC_MSG_TYPE_TYPE_SHIFT 0
	+/* Reserved */
	+#define PCIE_AXI_MISC_MSG_TYPE_RSRVD_MASK 0xFF000000
	+#define PCIE_AXI_MISC_MSG_TYPE_RSRVD_SHIFT 24
	+
	+/** debug register **/
	+/* Causes ACI PCIe reset, including ,master/slave/DBI (registers). */
	+#define PCIE_AXI_MISC_PCIE_STATUS_DEBUG_AXI_BRIDGE_RESET (1 << 0)
	+/*
	+ * Causes reset of the entire PCIe core (including the AXI bridge).
	+ * When set, the software must not address the PCI core (through the MEM space
	+ * and REG space).
	+ */
	+#define PCIE_AXI_MISC_PCIE_STATUS_DEBUG_CORE_RESET (1 << 1)
	+/*
	+ * Indicates that the SB is empty from the request to the PCIe (not including
	+ * registers).
	+ */
	+#define PCIE_AXI_MISC_PCIE_STATUS_DEBUG_SB_FLUSH_OB_STATUS (1 << 2)
	+/* MAP and transaction to the PCIe core to ERROR. */
	+#define PCIE_AXI_MISC_PCIE_STATUS_DEBUG_SB_MAP_TO_ERR (1 << 3)
	+/* Indicates that the pcie_core clock is gated off */
	+#define PCIE_AXI_MISC_PCIE_STATUS_DEBUG_CORE_CLK_GATE_OFF (1 << 4)
	+/* Reserved */
	+#define PCIE_AXI_MISC_PCIE_STATUS_DEBUG_RSRVD_MASK 0xFFFFFFE0
	+#define PCIE_AXI_MISC_PCIE_STATUS_DEBUG_RSRVD_SHIFT 5
	+
	+/** conf register **/
	+/*
	+ * Device Type
	+ * Indicates the specific type of this PCI Express Function. It is also used to
	+ * set the
	+ * Device/Port Type field.
	+ *
	+ * 4'b0000: PCI Express Endpoint
	+ * 4'b0001: Legacy PCI Express Endpoint
	+ * 4'b0100: Root Port of PCI Express Root Complex
	+ *
	+ * Must be programmed before link training sequence, according to the reset
	+ * strap.
	+ * Change this register should be when the pci_exist (in the PBS regfile) is
	+ * zero.
	+ */
	+#define PCIE_AXI_MISC_PCIE_GLOBAL_CONF_DEV_TYPE_MASK 0x0000000F
	+#define PCIE_AXI_MISC_PCIE_GLOBAL_CONF_DEV_TYPE_SHIFT 0
	+/*
	+ * [i] - Lane i active
	+ * Change this register should be when the pci_exist (in the PBS regfile) is
	+ * zero.
	+ */
	+#define PCIE_REV1_2_AXI_MISC_PCIE_GLOBAL_CONF_NOF_ACT_LANES_MASK 0x000000F0
	+#define PCIE_REV1_2_AXI_MISC_PCIE_GLOBAL_CONF_RESERVED_MASK 0xFFFFFF00
	+#define PCIE_REV1_2_AXI_MISC_PCIE_GLOBAL_CONF_RESERVED_SHIFT 8
	+#define PCIE_REVX_AXI_MISC_PCIE_GLOBAL_CONF_NOF_ACT_LANES_SHIFT 4
	+#define PCIE_REV3_AXI_MISC_PCIE_GLOBAL_CONF_NOF_ACT_LANES_MASK 0x000FFFF0
	+#define PCIE_REV3_AXI_MISC_PCIE_GLOBAL_CONF_RESERVED_MASK 0xFFF00000
	+#define PCIE_REV3_AXI_MISC_PCIE_GLOBAL_CONF_RESERVED_SHIFT 20
	+
	+#define PCIE_REV1_2_AXI_MISC_PCIE_GLOBAL_CONF_MEM_SHUTDOWN 0x100
	+#define PCIE_REV3_AXI_MISC_PCIE_GLOBAL_CONF_MEM_SHUTDOWN 0x100000
	+
	+/** laneX register **/
	+#define PCIE_AXI_STATUS_LANE_IS_RESET AL_BIT(13)
	+#define PCIE_AXI_STATUS_LANE_REQUESTED_SPEED_MASK AL_FIELD_MASK(2, 0)
	+#define PCIE_AXI_STATUS_LANE_REQUESTED_SPEED_SHIFT 0
	+
	+/** zero_laneX register **/
	+/* phy_mac_local_fs */
	+#define PCIE_AXI_MISC_ZERO_LANEX_PHY_MAC_LOCAL_FS_MASK 0x0000003f
	+#define PCIE_AXI_MISC_ZERO_LANEX_PHY_MAC_LOCAL_FS_SHIFT 0
	+/* phy_mac_local_lf */
	+#define PCIE_AXI_MISC_ZERO_LANEX_PHY_MAC_LOCAL_LF_MASK 0x00000fc0
	+#define PCIE_AXI_MISC_ZERO_LANEX_PHY_MAC_LOCAL_LF_SHIFT 6
	+
	+/** en_axi register **/
	+/* u4_ram2p */
	+#define PCIE_AXI_PARITY_EN_AXI_U4_RAM2P AL_BIT(1)
	+
	+/** pos_cntl register **/
	+/* Disables POS. */
	+#define PCIE_AXI_POS_ORDER_AXI_POS_BYPASS (1 << 0)
	+/* Clear the POS data structure. */
	+#define PCIE_AXI_POS_ORDER_AXI_POS_CLEAR (1 << 1)
	+/* Read push all write. */
	+#define PCIE_AXI_POS_ORDER_AXI_POS_RSO_ENABLE (1 << 2)
	+/*
	+ * Causes the PCIe core to wait for all the BRESPs before issuing a read
	+ * request.
	+ */
	+#define PCIE_AXI_POS_ORDER_AXI_DW_RD_FLUSH_WR (1 << 3)
	+/*
	+ * When set, to 1'b1 supports interleaving data return from the PCIe core. Valid
	+ * only when cfg_bypass_cmpl_after_write_fix is set.
	+ */
	+#define PCIE_AXI_POS_ORDER_RD_CMPL_AFTER_WR_SUPPORT_RD_INTERLV (1 << 4)
	+/* When set, to 1'b1 disables read completion after write ordering. */
	+#define PCIE_AXI_POS_ORDER_BYPASS_CMPL_AFTER_WR_FIX (1 << 5)
	+/*
	+ * When set, disables EP mode read cmpl on the master port push slave writes,
	+ * when each read response from the master is not interleaved.
	+ */
	+#define PCIE_AXI_POS_ORDER_EP_CMPL_AFTER_WR_DIS (1 << 6)
	+/* When set, disables EP mode read cmpl on the master port push slave writes. */
	+#define PCIE_AXI_POS_ORDER_EP_CMPL_AFTER_WR_SUPPORT_INTERLV_DIS (1 << 7)
	+/* should be zero */
	+#define PCIE_AXI_POS_ORDER_9_8 AL_FIELD_MASK(9, 8)
	+/* Give the segmentation buffer not to wait for P writes to end in the AXI
	+ * bridge before releasing the CMPL.
	+ */
	+#define PCIE_AXI_POS_ORDER_SEGMENT_BUFFER_DONT_WAIT_FOR_P_WRITES AL_BIT(10)
	+/* should be zero */
	+#define PCIE_AXI_POS_ORDER_11 AL_BIT(11)
	+/**
	+ * When set cause pcie core to send ready in the middle of the read data
	+ * burst returning from the DRAM to the PCIe core
	+ */
	+#define PCIE_AXI_POS_ORDER_SEND_READY_ON_READ_DATA_BURST AL_BIT(12)
	+/* When set disable the ATS CAP. */
	+#define PCIE_AXI_CORE_SETUP_ATS_CAP_DIS AL_BIT(13)
	+/* When set disable D3/D2/D1 PME support */
	+#define PCIE_AXI_POS_ORDER_DISABLE_DX_PME AL_BIT(14)
	+/* When set enable nonsticky reset when linkdown hot reset */
	+#define PCIE_AXI_POS_ORDER_ENABLE_NONSTICKY_RESET_ON_HOT_RESET AL_BIT(15)
	+/* When set, terminate message with data as UR request */
	+#define PCIE_AXI_TERMINATE_DATA_MSG_AS_UR_REQ AL_BIT(16)
	+
	+/** pcie_core_setup register **/
	+/*
	+ * This Value delay the rate change to the serdes, until the EIOS is sent by the
	+ * serdes. Should be program before the pcie_exist, is asserted.
	+ */
	+#define PCIE_AXI_CORE_SETUP_DELAY_MAC_PHY_RATE_MASK 0x000000FF
	+#define PCIE_AXI_CORE_SETUP_DELAY_MAC_PHY_RATE_SHIFT 0
	+/*
	+ * Limit the number of outstanding AXI reads that the PCIe core can get. Should
	+ * be program before the pcie_exist, is asserted.
	+ */
	+#define PCIE_AXI_CORE_SETUP_NOF_READS_ONSLAVE_INTRF_PCIE_CORE_MASK 0x0000FF00
	+#define PCIE_AXI_CORE_SETUP_NOF_READS_ONSLAVE_INTRF_PCIE_CORE_SHIFT 8
	+/* Enable the sriov feature. */
	+#define PCIE_AXI_REV1_2_CORE_SETUP_SRIOV_ENABLE AL_BIT(16)
	+/* not in use */
	+#define PCIE_AXI_REV3_CORE_SETUP_NOT_IN_USE (1 << 16)
	+/* Reserved. Read undefined; must read as zeros. */
	+#define PCIE_AXI_REV3_CORE_SETUP_CFG_DELAY_AFTER_PCIE_EXIST_MASK 0x0FFE0000
	+#define PCIE_AXI_REV3_CORE_SETUP_CFG_DELAY_AFTER_PCIE_EXIST_SHIFT 17
	+
	+/** cfg register **/
	+/* This value set the possible out standing headers writes (post ... */
	+#define PCIE_AXI_REV1_2_INIT_FC_CFG_NOF_P_HDR_MASK 0x0000007F
	+#define PCIE_AXI_REV1_2_INIT_FC_CFG_NOF_P_HDR_SHIFT 0
	+/* This value set the possible out standing headers reads (non-p ... */
	+#define PCIE_AXI_REV1_2_INIT_FC_CFG_NOF_NP_HDR_MASK 0x00003F80
	+#define PCIE_AXI_REV1_2_INIT_FC_CFG_NOF_NP_HDR_SHIFT 7
	+/* This value set the possible out standing headers CMPLs , the ... */
	+#define PCIE_AXI_REV1_2_INIT_FC_CFG_NOF_CPL_HDR_MASK 0x001FC000
	+#define PCIE_AXI_REV1_2_INIT_FC_CFG_NOF_CPL_HDR_SHIFT 14
	+
	+#define PCIE_AXI_REV1_2_INIT_FC_CFG_RSRVD_MASK 0xFFE00000
	+#define PCIE_AXI_REV1_2_INIT_FC_CFG_RSRVD_SHIFT 21
	+
	+/* This value set the possible out standing headers writes (post ... */
	+#define PCIE_AXI_REV3_INIT_FC_CFG_NOF_P_HDR_MASK 0x000001FF
	+#define PCIE_AXI_REV3_INIT_FC_CFG_NOF_P_HDR_SHIFT 0
	+/* This value set the possible out standing headers reads (non-p ... */
	+#define PCIE_AXI_REV3_INIT_FC_CFG_NOF_NP_HDR_MASK 0x0003FE00
	+#define PCIE_AXI_REV3_INIT_FC_CFG_NOF_NP_HDR_SHIFT 9
	+/* This value set the possible out standing headers CMPLs , the ... */
	+#define PCIE_AXI_REV3_INIT_FC_CFG_NOF_CPL_HDR_MASK 0x07FC0000
	+#define PCIE_AXI_REV3_INIT_FC_CFG_NOF_CPL_HDR_SHIFT 18
	+ /*
	+ * [27] cfg_cpl_p_rr: do round robin on the SB output btw Posted and CPL.
	+ * [28] cfg_np_pass_p_rr, in case RR between CPL AND P, allow to pass NP in case
	+ * p is empty.
	+ * [29] cfg_np_part_of_rr_arb: NP also is a part of the round robin arbiter.
	+ */
	+#define PCIE_AXI_REV3_INIT_FC_CFG_RSRVD_MASK 0xF8000000
	+#define PCIE_AXI_REV3_INIT_FC_CFG_RSRVD_SHIFT 27
	+
	+/** write_msg_ctrl_0 register **/
	+/*
	+ * choose if 17 in the AXUSER indicate message hint (1'b1) or no snoop
	+ * indication (1'b0)
	+ */
	+#define PCIE_AXI_AXI_ATTR_OVRD_WR_MSG_CTRL_0_AW_CFG_OUTBOUND_MSG_NO_SNOOP_N (1 << 0)
	+/* this bit define if the message is with data or without */
	+#define PCIE_AXI_AXI_ATTR_OVRD_WR_MSG_CTRL_0_AW_CFG_MSG_WITH_DATA (1 << 1)
	+/* message code for message with data. */
	+#define PCIE_AXI_AXI_ATTR_OVRD_WR_MSG_CTRL_0_AW_CFG_MSG_CODE_DATA_MASK 0x000003FC
	+#define PCIE_AXI_AXI_ATTR_OVRD_WR_MSG_CTRL_0_AW_CFG_MSG_CODE_DATA_SHIFT 2
	+/* message code for message without data. */
	+#define PCIE_AXI_AXI_ATTR_OVRD_WR_MSG_CTRL_0_AW_CFG_MSG_CODE_MASK 0x0003FC00
	+#define PCIE_AXI_AXI_ATTR_OVRD_WR_MSG_CTRL_0_AW_CFG_MSG_CODE_SHIFT 10
	+/* message ST value */
	+#define PCIE_AXI_AXI_ATTR_OVRD_WR_MSG_CTRL_0_AW_CFG_MSG_ST_MASK 0x03FC0000
	+#define PCIE_AXI_AXI_ATTR_OVRD_WR_MSG_CTRL_0_AW_CFG_MSG_ST_SHIFT 18
	+/* message NO-SNOOP */
	+#define PCIE_AXI_AXI_ATTR_OVRD_WR_MSG_CTRL_0_AW_CFG_MSG_NO_SNOOP (1 << 26)
	+/* message TH bit */
	+#define PCIE_AXI_AXI_ATTR_OVRD_WR_MSG_CTRL_0_AW_CFG_MSG_TH (1 << 27)
	+/* message PH bits */
	+#define PCIE_AXI_AXI_ATTR_OVRD_WR_MSG_CTRL_0_AW_CFG_MSG_PH_MASK 0x30000000
	+#define PCIE_AXI_AXI_ATTR_OVRD_WR_MSG_CTRL_0_AW_CFG_MSG_PH_SHIFT 28
	+/* Rsrvd */
	+#define PCIE_AXI_AXI_ATTR_OVRD_WR_MSG_CTRL_0_RSRVD_MASK 0xC0000000
	+#define PCIE_AXI_AXI_ATTR_OVRD_WR_MSG_CTRL_0_RSRVD_SHIFT 30
	+
	+/** write_msg_ctrl_1 register **/
	+/* message type */
	+#define PCIE_AXI_AXI_ATTR_OVRD_WR_MSG_CTRL_1_AW_CFG_MISC_MSG_TYPE_VALUE_MASK 0x0000001F
	+#define PCIE_AXI_AXI_ATTR_OVRD_WR_MSG_CTRL_1_AW_CFG_MISC_MSG_TYPE_VALUE_SHIFT 0
	+/* this bit define if the message is with data or without */
	+#define PCIE_AXI_AXI_ATTR_OVRD_WR_MSG_CTRL_1_AW_CFG_MSG_DATA_TYPE_VALUE_MASK 0x000003E0
	+#define PCIE_AXI_AXI_ATTR_OVRD_WR_MSG_CTRL_1_AW_CFG_MSG_DATA_TYPE_VALUE_SHIFT 5
	+/* override axi size for message with no data. */
	+#define PCIE_AXI_AXI_ATTR_OVRD_WR_MSG_CTRL_1_AW_CFG_MSG_NO_DATA_AXI_SIZE_OVRD (1 << 10)
	+/* override the AXI size to the pcie core for message with no data. */
	+#define PCIE_AXI_AXI_ATTR_OVRD_WR_MSG_CTRL_1_AW_CFG_MSG_NO_DATA_AXI_SIZE_MSG_MASK 0x00003800
	+#define PCIE_AXI_AXI_ATTR_OVRD_WR_MSG_CTRL_1_AW_CFG_MSG_NO_DATA_AXI_SIZE_MSG_SHIFT 11
	+/* override axi size for message with data. */
	+#define PCIE_AXI_AXI_ATTR_OVRD_WR_MSG_CTRL_1_AW_CFG_MSG_DATA_AXI_SIZE_OVRD (1 << 14)
	+/* override the AXI size to the pcie core for message with data. */
	+#define PCIE_AXI_AXI_ATTR_OVRD_WR_MSG_CTRL_1_AW_CFG_MSG_DATA_AXI_SIZE_MSG_MASK 0x00038000
	+#define PCIE_AXI_AXI_ATTR_OVRD_WR_MSG_CTRL_1_AW_CFG_MSG_DATA_AXI_SIZE_MSG_SHIFT 15
	+/* Rsrvd */
	+#define PCIE_AXI_AXI_ATTR_OVRD_WR_MSG_CTRL_1_RSRVD_MASK 0xFFFC0000
	+#define PCIE_AXI_AXI_ATTR_OVRD_WR_MSG_CTRL_1_RSRVD_SHIFT 18
	+
	+/** read_msg_ctrl_0 register **/
	+/*
	+ * choose if 17 in the AXUSER indicate message hint (1'b1) or no snoop
	+ * indication (1'b0)
	+ */
	+#define PCIE_AXI_AXI_ATTR_OVRD_READ_MSG_CTRL_0_AR_CFG_OUTBOUND_MSG_NO_SNOOP_N (1 << 0)
	+/* this bit define if the message is with data or without */
	+#define PCIE_AXI_AXI_ATTR_OVRD_READ_MSG_CTRL_0_AR_CFG_MSG_WITH_DATA (1 << 1)
	+/* message code for message with data. */
	+#define PCIE_AXI_AXI_ATTR_OVRD_READ_MSG_CTRL_0_AR_CFG_MSG_CODE_DATA_MASK 0x000003FC
	+#define PCIE_AXI_AXI_ATTR_OVRD_READ_MSG_CTRL_0_AR_CFG_MSG_CODE_DATA_SHIFT 2
	+/* message code for message without data. */
	+#define PCIE_AXI_AXI_ATTR_OVRD_READ_MSG_CTRL_0_AR_CFG_MSG_CODE_MASK 0x0003FC00
	+#define PCIE_AXI_AXI_ATTR_OVRD_READ_MSG_CTRL_0_AR_CFG_MSG_CODE_SHIFT 10
	+/* message ST value */
	+#define PCIE_AXI_AXI_ATTR_OVRD_READ_MSG_CTRL_0_AR_CFG_MSG_ST_MASK 0x03FC0000
	+#define PCIE_AXI_AXI_ATTR_OVRD_READ_MSG_CTRL_0_AR_CFG_MSG_ST_SHIFT 18
	+/* message NO-SNOOP */
	+#define PCIE_AXI_AXI_ATTR_OVRD_READ_MSG_CTRL_0_AR_CFG_MSG_NO_SNOOP (1 << 26)
	+/* message TH bit */
	+#define PCIE_AXI_AXI_ATTR_OVRD_READ_MSG_CTRL_0_AR_CFG_MSG_TH (1 << 27)
	+/* message PH bits */
	+#define PCIE_AXI_AXI_ATTR_OVRD_READ_MSG_CTRL_0_AR_CFG_MSG_PH_MASK 0x30000000
	+#define PCIE_AXI_AXI_ATTR_OVRD_READ_MSG_CTRL_0_AR_CFG_MSG_PH_SHIFT 28
	+/* Rsrvd */
	+#define PCIE_AXI_AXI_ATTR_OVRD_READ_MSG_CTRL_0_RSRVD_MASK 0xC0000000
	+#define PCIE_AXI_AXI_ATTR_OVRD_READ_MSG_CTRL_0_RSRVD_SHIFT 30
	+
	+/** read_msg_ctrl_1 register **/
	+/* message type */
	+#define PCIE_AXI_AXI_ATTR_OVRD_READ_MSG_CTRL_1_AR_CFG_MISC_MSG_TYPE_VALUE_MASK 0x0000001F
	+#define PCIE_AXI_AXI_ATTR_OVRD_READ_MSG_CTRL_1_AR_CFG_MISC_MSG_TYPE_VALUE_SHIFT 0
	+/* this bit define if the message is with data or without */
	+#define PCIE_AXI_AXI_ATTR_OVRD_READ_MSG_CTRL_1_AR_CFG_MSG_DATA_TYPE_VALUE_MASK 0x000003E0
	+#define PCIE_AXI_AXI_ATTR_OVRD_READ_MSG_CTRL_1_AR_CFG_MSG_DATA_TYPE_VALUE_SHIFT 5
	+/* override axi size for message with no data. */
	+#define PCIE_AXI_AXI_ATTR_OVRD_READ_MSG_CTRL_1_AR_CFG_MSG_NO_DATA_AXI_SIZE_OVRD (1 << 10)
	+/* override the AXI size to the pcie core for message with no data. */
	+#define PCIE_AXI_AXI_ATTR_OVRD_READ_MSG_CTRL_1_AR_CFG_MSG_NO_DATA_AXI_SIZE_MSG_MASK 0x00003800
	+#define PCIE_AXI_AXI_ATTR_OVRD_READ_MSG_CTRL_1_AR_CFG_MSG_NO_DATA_AXI_SIZE_MSG_SHIFT 11
	+/* override axi size for message with data. */
	+#define PCIE_AXI_AXI_ATTR_OVRD_READ_MSG_CTRL_1_AR_CFG_MSG_DATA_AXI_SIZE_OVRD (1 << 14)
	+/* override the AXI size to the pcie core for message with data. */
	+#define PCIE_AXI_AXI_ATTR_OVRD_READ_MSG_CTRL_1_AR_CFG_MSG_DATA_AXI_SIZE_MSG_MASK 0x00038000
	+#define PCIE_AXI_AXI_ATTR_OVRD_READ_MSG_CTRL_1_AR_CFG_MSG_DATA_AXI_SIZE_MSG_SHIFT 15
	+/* Rsrvd */
	+#define PCIE_AXI_AXI_ATTR_OVRD_READ_MSG_CTRL_1_RSRVD_MASK 0xFFFC0000
	+#define PCIE_AXI_AXI_ATTR_OVRD_READ_MSG_CTRL_1_RSRVD_SHIFT 18
	+
	+/** pf_sel register **/
	+/* message type */
	+#define PCIE_AXI_AXI_ATTR_OVRD_PF_SEL_PF_BIT0_OVRD_FROM_AXUSER (1 << 0)
	+/* this bit define if the message is with data or without */
	+#define PCIE_AXI_AXI_ATTR_OVRD_PF_SEL_PF_BIT0_OVRD_FROM_REG (1 << 1)
	+/* override axi size for message with no data. */
	+#define PCIE_AXI_AXI_ATTR_OVRD_PF_SEL_PF_BIT0_ADDR_OFFSET_MASK 0x0000003C
	+#define PCIE_AXI_AXI_ATTR_OVRD_PF_SEL_PF_BIT0_ADDR_OFFSET_SHIFT 2
	+/* override the AXI size to the pcie core for message with no data. */
	+#define PCIE_AXI_AXI_ATTR_OVRD_PF_SEL_CFG_PF_BIT0_OVRD (1 << 6)
	+/* Rsrvd */
	+#define PCIE_AXI_AXI_ATTR_OVRD_PF_SEL_RSRVD_7 (1 << 7)
	+/* message type */
	+#define PCIE_AXI_AXI_ATTR_OVRD_PF_SEL_PF_BIT1_OVRD_FROM_AXUSER (1 << 8)
	+/* this bit define if the message is with data or without */
	+#define PCIE_AXI_AXI_ATTR_OVRD_PF_SEL_PF_BIT1_OVRD_FROM_REG (1 << 9)
	+/* override axi size for message with no data. */
	+#define PCIE_AXI_AXI_ATTR_OVRD_PF_SEL_PF_BIT1_ADDR_OFFSET_MASK 0x00003C00
	+#define PCIE_AXI_AXI_ATTR_OVRD_PF_SEL_PF_BIT1_ADDR_OFFSET_SHIFT 10
	+/* override the AXI size to the pcie core for message with no data. */
	+#define PCIE_AXI_AXI_ATTR_OVRD_PF_SEL_CFG_PF_BIT1_OVRD (1 << 14)
	+/* Rsrvd */
	+#define PCIE_AXI_AXI_ATTR_OVRD_PF_SEL_RSRVD_MASK 0xFFFF8000
	+#define PCIE_AXI_AXI_ATTR_OVRD_PF_SEL_RSRVD_SHIFT 15
	+
	+ /** func_ctrl_0 register **/
	+/* choose the field from the axuser */
	+#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_0_PF_VEC_TH_OVRD_FROM_AXUSER (1 << 0)
	+/* choose the field from register */
	+#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_0_PF_VEC_TH_OVRD_FROM_REG (1 << 1)
	+/* field offset from the address portions according to the spec */
	+#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_0_PF_VEC_TH_ADDR_OFFSET_MASK 0x0000003C
	+#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_0_PF_VEC_TH_ADDR_OFFSET_SHIFT 2
	+/* register value override */
	+#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_0_CFG_TH_OVRD (1 << 6)
	+/* choose the field from the axuser */
	+#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_0_PF_VEC_ST_VEC_OVRD_FROM_AXUSER_MASK 0x00007F80
	+#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_0_PF_VEC_ST_VEC_OVRD_FROM_AXUSER_SHIFT 7
	+/* choose the field from register */
	+#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_0_PF_VEC_ST_VEC_OVRD_FROM_REG_MASK 0x007F8000
	+#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_0_PF_VEC_ST_VEC_OVRD_FROM_REG_SHIFT 15
	+/* register value override */
	+#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_0_CFG_ST_VEC_OVRD_MASK 0x7F800000
	+#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_0_CFG_ST_VEC_OVRD_SHIFT 23
	+/* Rsrvd */
	+#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_0_RSRVD (1 << 31)
	+
	+/** func_ctrl_2 register **/
	+/* choose the field from the axuser */
	+#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_2_PF_VEC_PH_VEC_OVRD_FROM_AXUSER_MASK 0x00000003
	+#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_2_PF_VEC_PH_VEC_OVRD_FROM_AXUSER_SHIFT 0
	+/* choose the field from register */
	+#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_2_PF_VEC_PH_VEC_OVRD_FROM_REG_MASK 0x0000000C
	+#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_2_PF_VEC_PH_VEC_OVRD_FROM_REG_SHIFT 2
	+/* in case the field take from the address, offset field for each bit. */
	+#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_2_PF_VEC_PH_VEC_ADDR_OFFSET_MASK 0x00000FF0
	+#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_2_PF_VEC_PH_VEC_ADDR_OFFSET_SHIFT 4
	+/* register value override */
	+#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_2_CFG_PH_VEC_OVRD_MASK 0x00003000
	+#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_2_CFG_PH_VEC_OVRD_SHIFT 12
	+/* Rsrvd */
	+#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_2_RSRVD_14_15_MASK 0x0000C000
	+#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_2_RSRVD_14_15_SHIFT 14
	+/* choose the field from the axuser */
	+#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_2_PF_VEC_VMID89_VEC_OVRD_FROM_AXUSER_MASK 0x00030000
	+#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_2_PF_VEC_VMID89_VEC_OVRD_FROM_AXUSER_SHIFT 16
	+/* choose the field from register */
	+#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_2_PF_VEC_VMID89_VEC_OVRD_FROM_REG_MASK 0x000C0000
	+#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_2_PF_VEC_VMID89_VEC_OVRD_FROM_REG_SHIFT 18
	+/* in case the field take from the address, offset field for each bit. */
	+#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_2_PF_VEC_VMID89_VEC_ADDR_OFFSET_MASK 0x0FF00000
	+#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_2_PF_VEC_VMID89_VEC_ADDR_OFFSET_SHIFT 20
	+/* register value override */
	+#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_2_CFG_VMID89_VEC_OVRD_MASK 0x30000000
	+#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_2_CFG_VMID89_VEC_OVRD_SHIFT 28
	+/* Rsrvd */
	+#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_2_RSRVD_MASK 0xC0000000
	+#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_2_RSRVD_SHIFT 30
	+
	+/** func_ctrl_3 register **/
	+/*
	+ * When set take the corresponding bit address from register
	+ * pf_vec_mem_addr44_53_ovrd
	+ */
	+#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_3_PF_VEC_MEM_ADDR44_53_SEL_MASK 0x000003FF
	+#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_3_PF_VEC_MEM_ADDR44_53_SEL_SHIFT 0
	+/* override value. */
	+#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_3_PF_VEC_MEM_ADDR44_53_OVRD_MASK 0x000FFC00
	+#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_3_PF_VEC_MEM_ADDR44_53_OVRD_SHIFT 10
	+/*
	+ * When set take the corresponding bit address from register
	+ * pf_vec_mem_addr54_63_ovrd
	+ */
	+#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_3_PF_VEC_MEM_ADDR54_63_SEL_MASK 0x3FF00000
	+#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_3_PF_VEC_MEM_ADDR54_63_SEL_SHIFT 20
	+/* Rsrvd */
	+#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_3_RSRVD_MASK 0xC0000000
	+#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_3_RSRVD_SHIFT 30
	+
	+/** func_ctrl_4 register **/
	+/* When set take the corresponding bit address from vmid value. */
	+#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_4_PF_VEC_MEM_ADDR54_63_SEL_VMID_MASK 0x000003FF
	+#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_4_PF_VEC_MEM_ADDR54_63_SEL_VMID_SHIFT 0
	+/* override value. */
	+#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_4_PF_VEC_MEM_ADDR54_63_OVRD_MASK 0x000FFC00
	+#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_4_PF_VEC_MEM_ADDR54_63_OVRD_SHIFT 10
	+/* Rsrvd */
	+#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_4_RSRVD_MASK 0xFFF00000
	+#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_4_RSRVD_SHIFT 20
	+
	+/** func_ctrl_5 register **/
	+/*
	+ * When set take the corresponding bit address [63:44] from
	+ * aw_pf_vec_msg_addr_ovrd
	+ */
	+#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_5_AW_PF_VEC_MSG_ADDR_SEL_MASK 0x000FFFFF
	+#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_5_AW_PF_VEC_MSG_ADDR_SEL_SHIFT 0
	+/* Rsrvd */
	+#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_5_RSRVD_MASK 0xFFF00000
	+#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_5_RSRVD_SHIFT 20
	+
	+/** func_ctrl_6 register **/
	+/* override value. */
	+#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_6_AW_PF_VEC_MSG_ADDR_OVRD_MASK 0x000FFFFF
	+#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_6_AW_PF_VEC_MSG_ADDR_OVRD_SHIFT 0
	+/* Rsrvd */
	+#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_6_RSRVD_MASK 0xFFF00000
	+#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_6_RSRVD_SHIFT 20
	+
	+/** func_ctrl_7 register **/
	+/*
	+ * When set take the corresponding bit address [63:44] from
	+ * ar_pf_vec_msg_addr_ovrd
	+ */
	+#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_7_AR_PF_VEC_MSG_ADDR_SEL_MASK 0x000FFFFF
	+#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_7_AR_PF_VEC_MSG_ADDR_SEL_SHIFT 0
	+/* Rsrvd */
	+#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_7_RSRVD_MASK 0xFFF00000
	+#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_7_RSRVD_SHIFT 20
	+
	+/** func_ctrl_8 register **/
	+/* override value. */
	+#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_8_AR_PF_VEC_MSG_ADDR_OVRD_MASK 0x000FFFFF
	+#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_8_AR_PF_VEC_MSG_ADDR_OVRD_SHIFT 0
	+/* Rsrvd */
	+#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_8_RSRVD_MASK 0xFFF00000
	+#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_8_RSRVD_SHIFT 20
	+
	+/** func_ctrl_9 register **/
	+/* no snoop override */
	+#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_9_PF_VEC_NO_SNOOP_OVRD (1 << 0)
	+/* no snoop override value */
	+#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_9_PF_VEC_NO_SNOOP_OVRD_VALUE (1 << 1)
	+/* atu bypass override */
	+#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_9_PF_VEC_ATU_BYPASS_OVRD (1 << 2)
	+/* atu bypass override value */
	+#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_9_PF_VEC_ATU_BYPASS_OVRD_VALUE (1 << 3)
	+/* Rsrvd */
	+#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_9_RSRVD_MASK 0xFFFFFFF0
	+#define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_9_RSRVD_SHIFT 4
	+
	+/** entry_vec register **/
	+/* entry0 */
	+#define PCIE_AXI_MSG_ATTR_AXUSER_TABLE_ENTRY_VEC_ENTRY_0_MASK 0x0000001F
	+#define PCIE_AXI_MSG_ATTR_AXUSER_TABLE_ENTRY_VEC_ENTRY_0_SHIFT 0
	+/* entry1 */
	+#define PCIE_AXI_MSG_ATTR_AXUSER_TABLE_ENTRY_VEC_ENTRY_1_MASK 0x000003E0
	+#define PCIE_AXI_MSG_ATTR_AXUSER_TABLE_ENTRY_VEC_ENTRY_1_SHIFT 5
	+/* entry2 */
	+#define PCIE_AXI_MSG_ATTR_AXUSER_TABLE_ENTRY_VEC_ENTRY_2_MASK 0x00007C00
	+#define PCIE_AXI_MSG_ATTR_AXUSER_TABLE_ENTRY_VEC_ENTRY_2_SHIFT 10
	+/* entry3 */
	+#define PCIE_AXI_MSG_ATTR_AXUSER_TABLE_ENTRY_VEC_ENTRY_3_MASK 0x000F8000
	+#define PCIE_AXI_MSG_ATTR_AXUSER_TABLE_ENTRY_VEC_ENTRY_3_SHIFT 15
	+/* atu bypass for message "write" */
	+#define PCIE_AXI_MSG_ATTR_AXUSER_TABLE_ENTRY_VEC_AW_MSG_ATU_BYPASS (1 << 20)
	+/* atu bypass for message "read" */
	+#define PCIE_AXI_MSG_ATTR_AXUSER_TABLE_ENTRY_VEC_AR_MSG_ATU_BYPASS (1 << 21)
	+/* Rsrvd */
	+#define PCIE_AXI_MSG_ATTR_AXUSER_TABLE_ENTRY_VEC_RSRVD_MASK 0xFFC00000
	+#define PCIE_AXI_MSG_ATTR_AXUSER_TABLE_ENTRY_VEC_RSRVD_SHIFT 22
	+
	+/** int_cause_grp_A_axi register **/
	+/*
	+ * Master Response Composer Lookup Error
	+ * Overflow that occurred in a lookup table of the Outbound responses. This
	+ * indicates that there was a violation for the number of outstanding NP
	+ * requests issued for the Inbound direction.
	+ * Write zero to clear.
	+ */
	+#define PCIE_AXI_INT_GRP_A_CAUSE_GM_COMPOSER_LOOKUP_ERR (1 << 0)
	+/*
	+ * Indicates a PARITY ERROR on the master data read channel.
	+ * Write zero to clear.
	+ */
	+#define PCIE_AXI_INT_GRP_A_CAUSE_PARITY_ERR_DATA_PATH_RD (1 << 2)
	+/*
	+ * Indicates a PARITY ERROR on the slave addr read channel.
	+ * Write zero to clear.
	+ */
	+#define PCIE_AXI_INT_GRP_A_CAUSE_PARITY_ERR_OUT_ADDR_RD (1 << 3)
	+/*
	+ * Indicates a PARITY ERROR on the slave addr write channel.
	+ * Write zero to clear.
	+ */
	+#define PCIE_AXI_INT_GRP_A_CAUSE_PARITY_ERR_OUT_ADDR_WR (1 << 4)
	+/*
	+ * Indicates a PARITY ERROR on the slave data write channel.
	+ * Write zero to clear.
	+ */
	+#define PCIE_AXI_INT_GRP_A_CAUSE_PARITY_ERR_OUT_DATA_WR (1 << 5)
	+/* Reserved */
	+#define PCIE_AXI_INT_GRP_A_CAUSE_RESERVED_6 (1 << 6)
	+/*
	+ * Software error: ECAM write request with invalid bus number.
	+ * Write Zero to clear
	+ */
	+#define PCIE_AXI_INT_GRP_A_CAUSE_SW_ECAM_ERR_RD (1 << 7)
	+/*
	+ * Software error: ECAM read request with invalid bus number.
	+ * Write Zero to clear.
	+ */
	+#define PCIE_AXI_INT_GRP_A_CAUSE_SW_ECAM_ERR_WR (1 << 8)
	+/* Indicates an ERROR in the PCIe application cause register. */
	+#define PCIE_AXI_INT_GRP_A_CAUSE_PCIE_CORE_INT (1 << 9)
	+/*
	+ * Whenever the Master AXI finishes writing a message, it sets this bit.
	+ * Whenever the int is cleared, the message information MSG_* regs are no longer
	+ * valid.
	+ */
	+#define PCIE_AXI_INT_GRP_A_CAUSE_MSTR_AXI_GETOUT_MSG (1 << 10)
	+/* Read AXI compilation has ERROR. */
	+#define PCIE_AXI_INT_GRP_A_CAUSE_RD_CMPL_ERR (1 << 11)
	+/* Write AXI compilation has ERROR. */
	+#define PCIE_AXI_INT_GRP_A_CAUSE_WR_CMPL_ERR (1 << 12)
	+/* Read AXI compilation has timed out. */
	+#define PCIE_AXI_INT_GRP_A_CAUSE_RD_CMPL_TO (1 << 13)
	+/* Write AXI compilation has timed out. */
	+#define PCIE_AXI_INT_GRP_A_CAUSE_WR_CMPL_TO (1 << 14)
	+/* Parity error AXI domain */
	+#define PCIE_AXI_INT_GRP_A_CAUSE_PARITY_ERROR_AXI (1 << 15)
	+/* POS error interrupt */
	+#define PCIE_AXI_INT_GRP_A_CAUSE_POS_AXI_BRESP (1 << 16)
	+/* The outstanding write counter become full should never happen */
	+#define PCIE_AXI_INT_GRP_A_CAUSE_WRITE_CNT_FULL_ERR (1 << 17)
	+/* BRESP received before the write counter increment. */
	+#define PCIE_AXI_INT_GRP_A_CAUSE_BRESP_BEFORE_WR_CNT_INC_ERR (1 << 18)
	+
	+/** int_control_grp_A_axi register **/
	+/* When Clear_on_Read =1, all bits of the Cause register are cleared on read. */
	+#define PCIE_AXI_INT_GRP_A_CTRL_CLEAR_ON_READ (1 << 0)
	+/*
	+ * (Must be set only when MSIX is enabled.)
	+ * When Auto-Mask =1 and an MSI-X ACK for this bit is received, its
	+ * corresponding bit in the mask register is set, masking future interrupts.
	+ */
	+#define PCIE_AXI_INT_GRP_A_CTRL_AUTO_MASK (1 << 1)
	+/*
	+ * Auto_Clear (RW)
	+ * When Auto-Clear =1, the bits in the Interrupt Cause register are auto-cleared
	+ * after MSI-X is acknowledged. Must be used only if MSI-X is enabled.
	+ */
	+#define PCIE_AXI_INT_GRP_A_CTRL_AUTO_CLEAR (1 << 2)
	+/*
	+ * When set,_on_Posedge =1, the bits in the Interrupt Cause register are set on
	+ * the posedge of the interrupt source, i.e., when interrupt source =1 and
	+ * Interrupt Status = 0.
	+ * When set,_on_Posedge =0, the bits in the Interrupt Cause register are set
	+ * when interrupt source =1.
	+ */
	+#define PCIE_AXI_INT_GRP_A_CTRL_SET_ON_POS (1 << 3)
	+/*
	+ * When Moderation_Reset =1, all Moderation timers associated with the interrupt
	+ * cause bits are cleared to 0, enabling immediate interrupt assertion if any
	+ * unmasked cause bit is set to 1. This bit is self-negated.
	+ */
	+#define PCIE_AXI_INT_GRP_A_CTRL_MOD_RST (1 << 4)
	+/*
	+ * When mask_msi_x =1, no MSI-X from this group is sent. This bit is set to 1
	+ * when the associate summary bit in this group is used to generate a single
	+ * MSI-X for this group.
	+ */
	+#define PCIE_AXI_INT_GRP_A_CTRL_MASK_MSI_X (1 << 5)
	+/* MSI-X AWID value. Same ID for all cause bits. */
	+#define PCIE_AXI_INT_GRP_A_CTRL_AWID_MASK 0x00000F00
	+#define PCIE_AXI_INT_GRP_A_CTRL_AWID_SHIFT 8
	+/*
	+ * This value determines the interval between interrupts. Writing ZERO disables
	+ * Moderation.
	+ */
	+#define PCIE_AXI_INT_GRP_A_CTRL_MOD_INTV_MASK 0x00FF0000
	+#define PCIE_AXI_INT_GRP_A_CTRL_MOD_INTV_SHIFT 16
	+/*
	+ * This value determines the Moderation_Timer_Clock speed.
	+ * 0- Moderation-timer is decremented every 1x256 SB clock cycles ~1uS.
	+ * 1- Moderation-timer is decremented every 2x256 SB clock cycles ~2uS.
	+ * N- Moderation-timer is decremented every Nx256 SB clock cycles ~(N+1) uS.
	+ */
	+#define PCIE_AXI_INT_GRP_A_CTRL_MOD_RES_MASK 0x0F000000
	+#define PCIE_AXI_INT_GRP_A_CTRL_MOD_RES_SHIFT 24
	+
	+#ifdef __cplusplus
	+}
	+#endif
	+
	+#endif /* __AL_HAL_pcie_axi_REG_H */
	+
	+/** @} end of ... group */
	Index: sys/arm/annapurna/alpine/hal/al_hal_pcie_interrupts.h
	===================================================================
	--- /dev/null
	+++ sys/arm/annapurna/alpine/hal/al_hal_pcie_interrupts.h
	@@ -0,0 +1,271 @@
	+/*-
	+********************************************************************************
	+Copyright (C) 2015 Annapurna Labs Ltd.
	+
	+This file may be licensed under the terms of the Annapurna Labs Commercial
	+License Agreement.
	+
	+Alternatively, this file can be distributed under the terms of the GNU General
	+Public License V2 as published by the Free Software Foundation and can be
	+found at http://www.gnu.org/licenses/gpl-2.0.html
	+
	+Alternatively, redistribution and use in source and binary forms, with or
	+without modification, are permitted provided that the following conditions are
	+met:
	+
	+ * Redistributions of source code must retain the above copyright notice,
	+this list of conditions and the following disclaimer.
	+
	+ * Redistributions in binary form must reproduce the above copyright
	+notice, this list of conditions and the following disclaimer in
	+the documentation and/or other materials provided with the
	+distribution.
	+
	+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
	+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
	+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
	+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
	+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
	+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
	+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
	+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
	+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
	+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	+
	+*******************************************************************************/
	+
	+#ifndef _AL_HAL_PCIE_INTERRUPTS_H_
	+#define _AL_HAL_PCIE_INTERRUPTS_H_
	+
	+#include "al_hal_common.h"
	+#include "al_hal_pcie.h"
	+#include "al_hal_iofic.h"
	+
	+/**
	+ * @defgroup group_pcie_interrupts PCIe interrupts
	+ * @ingroup grouppcie
	+ * @{
	+ * The PCIe interrupts HAL can be used to control PCIe unit interrupts.
	+ * There are 5 groups of interrupts: app group A, B, C, D and AXI.
	+ * Only 2 interrupts go from the pcie unit to the GIC:
	+ * 1. Summary for all the int groups (AXI+APP CORE).
	+ * 2. INTA assert/deassert (RC only).
	+ * For the specific GIC interrupt line, please check the architecture reference
	+ * manual.
	+ * The reset mask state of all interrupts is: Masked
	+ *
	+ * @file al_hal_pcie_interrupts.h
	+ *
	+ */
	+
	+/**
	+ * PCIe interrupt groups
	+ */
	+enum al_pcie_int_group {
	+ AL_PCIE_INT_GRP_A,
	+ AL_PCIE_INT_GRP_B,
	+ AL_PCIE_INT_GRP_C, /* Rev3 only */
	+ AL_PCIE_INT_GRP_D, /* Rev3 only */
	+ AL_PCIE_INT_GRP_AXI_A,
	+};
	+
	+/**
	+ * App group A interrupts mask - don't change
	+ * All interrupts not listed below should be masked
	+ */
	+enum al_pcie_app_int_grp_a {
	+ /** [RC only] Deassert_INTD received */
	+ AL_PCIE_APP_INT_DEASSERT_INTD = AL_BIT(0),
	+ /** [RC only] Deassert_INTC received */
	+ AL_PCIE_APP_INT_DEASSERT_INTC = AL_BIT(1),
	+ /** [RC only] Deassert_INTB received */
	+ AL_PCIE_APP_INT_DEASSERT_INTB = AL_BIT(2),
	+ /**
	+ * [RC only] Deassert_INTA received - there's a didcated GIC interrupt
	+ * line that reflects the status of ASSERT/DEASSERT of INTA
	+ */
	+ AL_PCIE_APP_INT_DEASSERT_INTA = AL_BIT(3),
	+ /** [RC only] Assert_INTD received */
	+ AL_PCIE_APP_INT_ASSERT_INTD = AL_BIT(4),
	+ /** [RC only] Assert_INTC received */
	+ AL_PCIE_APP_INT_ASSERT_INTC = AL_BIT(5),
	+ /** [RC only] Assert_INTB received */
	+ AL_PCIE_APP_INT_ASSERT_INTB = AL_BIT(6),
	+ /**
	+ * [RC only] Assert_INTA received - there's a didcated GIC interrupt
	+ * line that reflects the status of ASSERT/DEASSERT of INTA
	+ */
	+ AL_PCIE_APP_INT_ASSERT_INTA = AL_BIT(7),
	+ /** [RC only] MSI Controller Interrupt */
	+ AL_PCIE_APP_INT_MSI_CNTR_RCV_INT = AL_BIT(8),
	+ /** [EP only] MSI sent grant */
	+ AL_PCIE_APP_INT_MSI_TRNS_GNT = AL_BIT(9),
	+ /** [RC only] System error detected (ERR_COR, ERR_FATAL, ERR_NONFATAL) */
	+ AL_PCIE_APP_INT_SYS_ERR_RC = AL_BIT(10),
	+ /** [EP only] Software initiates FLR on a Physical Function */
	+ AL_PCIE_APP_INT_FLR_PF_ACTIVE = AL_BIT(11),
	+ /** [RC only] Root Error Command register assertion notification */
	+ AL_PCIE_APP_INT_AER_RC_ERR = AL_BIT(12),
	+ /** [RC only] Root Error Command register assertion notification With MSI or MSIX enabled */
	+ AL_PCIE_APP_INT_AER_RC_ERR_MSI = AL_BIT(13),
	+ /** [RC only] PME Status bit assertion in the Root Status register With INTA */
	+ AL_PCIE_APP_INT_PME_INT = AL_BIT(15),
	+ /** [RC only] PME Status bit assertion in the Root Status register With MSI or MSIX enabled */
	+ AL_PCIE_APP_INT_PME_MSI = AL_BIT(16),
	+ /** [RC/EP] The core assert link down event, whenever the link is going down */
	+ AL_PCIE_APP_INT_LINK_DOWN = AL_BIT(21),
	+ /** [EP only] When the EP gets a command to shut down, signal the software to block any new TLP. */
	+ AL_PCIE_APP_INT_PM_XTLH_BLOCK_TLP = AL_BIT(22),
	+ /** [RC/EP] PHY/MAC link up */
	+ AL_PCIE_APP_INT_XMLH_LINK_UP = AL_BIT(23),
	+ /** [RC/EP] Data link up */
	+ AL_PCIE_APP_INT_RDLH_LINK_UP = AL_BIT(24),
	+ /** [RC/EP] The LTSSM is in RCVRY_LOCK state. */
	+ AL_PCIE_APP_INT_LTSSM_RCVRY_STATE = AL_BIT(25),
	+ /**
	+ * [RC/EP] CFG write transaction to the configuration space by the RC peer
	+ * For RC the int/ will be set from DBI write (internal SoC write)]
	+ */
	+ AL_PCIE_APP_INT_CFG_WR = AL_BIT(26),
	+ /** [EP only] CFG access in EP mode */
	+ AL_PCIE_APP_INT_CFG_ACCESS = AL_BIT(31),
	+};
	+
	+/**
	+ * App group B interrupts mask - don't change
	+ * All interrupts not listed below should be masked
	+ */
	+enum al_pcie_app_int_grp_b {
	+ /** [RC only] PM_PME Message received */
	+ AL_PCIE_APP_INT_GRP_B_PM_PME_MSG_RCVD = AL_BIT(0),
	+ /** [RC only] PME_TO_Ack Message received */
	+ AL_PCIE_APP_INT_GRP_B_PME_TO_ACK_MSG_RCVD = AL_BIT(1),
	+ /** [EP only] PME_Turn_Off Message received */
	+ AL_PCIE_APP_INT_GRP_B_PME_TURN_OFF_MSG_RCVD = AL_BIT(2),
	+ /** [RC only] ERR_CORR Message received */
	+ AL_PCIE_APP_INT_GRP_B_CORR_ERR_MSG_RCVD = AL_BIT(3),
	+ /** [RC only] ERR_NONFATAL Message received */
	+ AL_PCIE_APP_INT_GRP_B_NON_FTL_ERR_MSG_RCVD = AL_BIT(4),
	+ /** [RC only] ERR_FATAL Message received */
	+ AL_PCIE_APP_INT_GRP_B_FTL_ERR_MSG_RCVD = AL_BIT(5),
	+ /**
	+ * [RC/EP] Vendor Defined Message received
	+ * Asserted when a vevdor message is received (with no data), buffers 2
	+ * messages only, and latch the headers in registers
	+ */
	+ AL_PCIE_APP_INT_GRP_B_VNDR_MSG_A_RCVD = AL_BIT(6),
	+ /**
	+ * [RC/EP] Vendor Defined Message received
	+ * Asserted when a vevdor message is received (with no data), buffers 2
	+ * messages only, and latch the headers in registers
	+ */
	+ AL_PCIE_APP_INT_GRP_B_VNDR_MSG_B_RCVD = AL_BIT(7),
	+ /** [EP only] Link Autonomous Bandwidth Status is updated */
	+ AL_PCIE_APP_INT_GRP_B_LNK_BW_UPD = AL_BIT(12),
	+ /** [EP only] Link Equalization Request bit in the Link Status 2 Register has been set */
	+ AL_PCIE_APP_INT_GRP_B_LNK_EQ_REQ = AL_BIT(13),
	+ /** [RC/EP] OB Vendor message request is granted by the PCIe core */
	+ AL_PCIE_APP_INT_GRP_B_OB_VNDR_MSG_REQ_GRNT = AL_BIT(14),
	+ /** [RC only] CPL timeout from the PCIe core indiication */
	+ AL_PCIE_APP_INT_GRP_B_CPL_TO = AL_BIT(15),
	+ /** [RC/EP] Slave Response Composer Lookup Error */
	+ AL_PCIE_APP_INT_GRP_B_SLV_RESP_COMP_LKUP_ERR = AL_BIT(16),
	+ /** [RC/EP] Parity Error */
	+ AL_PCIE_APP_INT_GRP_B_PARITY_ERR = AL_BIT(17),
	+ /** [EP only] Speed change request */
	+ AL_PCIE_APP_INT_GRP_B_SPEED_CHANGE = AL_BIT(31),
	+};
	+
	+/**
	+ * AXI interrupts mask - don't change
	+ * These are internal errors that can happen on the internal chip interface
	+ * between the PCIe port and the I/O Fabric over the AXI bus. The notion of
	+ * master and slave refer to the PCIe port master interface towards the I/O
	+ * Fabric (i.e. for inbound PCIe writes/reads toward the I/O Fabric), while the
	+ * slave interface refer to the I/O Fabric to PCIe port interface where the
	+ * internal chip DMAs and CPU cluster is initiating transactions.
	+ * All interrupts not listed below should be masked.
	+ */
	+enum al_pcie_axi_int {
	+ /** [RC/EP] Master Response Composer Lookup Error */
	+ AL_PCIE_AXI_INT_MSTR_RESP_COMP_LKUP_ERR = AL_BIT(0),
	+ /** [RC/EP] PARITY ERROR on the master data read channel */
	+ AL_PCIE_AXI_INT_PARITY_ERR_MSTR_DATA_RD_CHNL = AL_BIT(2),
	+ /** [RC/EP] PARITY ERROR on the slave addr read channel */
	+ AL_PCIE_AXI_INT_PARITY_ERR_SLV_ADDR_RD_CHNL = AL_BIT(3),
	+ /** [RC/EP] PARITY ERROR on the slave addr write channel */
	+ AL_PCIE_AXI_INT_PARITY_ERR_SLV_ADDR_WR_CHNL = AL_BIT(4),
	+ /** [RC/EP] PARITY ERROR on the slave data write channel */
	+ AL_PCIE_AXI_INT_PARITY_ERR_SLV_DATA_WR_CHNL = AL_BIT(5),
	+ /** [RC only] Software error: ECAM write request with invalid bus number */
	+ AL_PCIE_AXI_INT_ECAM_WR_REQ_INVLD_BUS_NUM = AL_BIT(7),
	+ /** [RC only] Software error: ECAM read request with invalid bus number */
	+ AL_PCIE_AXI_INT_ECAM_RD_REQ_INVLD_BUS_NUM = AL_BIT(8),
	+ /** [RC/EP] Read AXI completion has ERROR */
	+ AL_PCIE_AXI_INT_RD_AXI_COMPL_ERR = AL_BIT(11),
	+ /** [RC/EP] Write AXI completion has ERROR */
	+ AL_PCIE_AXI_INT_WR_AXI_COMPL_ERR = AL_BIT(12),
	+ /** [RC/EP] Read AXI completion has timed out */
	+ AL_PCIE_AXI_INT_RD_AXI_COMPL_TO = AL_BIT(13),
	+ /** [RC/EP] Write AXI completion has timed out */
	+ AL_PCIE_AXI_INT_WR_AXI_COMPL_TO = AL_BIT(14),
	+ /** [RC/EP] Parity error AXI domain */
	+ AL_PCIE_AXI_INT_AXI_DOM_PARITY_ERR = AL_BIT(15),
	+ /** [RC/EP] POS error interrupt */
	+ AL_PCIE_AXI_INT_POS_ERR = AL_BIT(16),
	+};
	+
	+/**
	+ * @brief Initialize and configure PCIe controller interrupts
	+ * Doesn't change the mask state of the interrupts
	+ * The reset mask state of all interrupts is: Masked
	+ *
	+ * @param pcie_port pcie port handle
	+ */
	+void al_pcie_ints_config(struct al_pcie_port *pcie_port);
	+
	+/**
	+ * Unmask PCIe app group interrupts
	+ * @param pcie_port pcie_port pcie port handle
	+ * @param int_group interrupt group
	+ * @param int_mask int_mask interrupts to unmask ('1' to unmask)
	+ */
	+void al_pcie_app_int_grp_unmask(
	+ struct al_pcie_port *pcie_port,
	+ enum al_pcie_int_group int_group,
	+ uint32_t int_mask);
	+
	+/**
	+ * Mask PCIe app group interrupts
	+ * @param pcie_port pcie_port pcie port handle
	+ * @param int_group interrupt group
	+ * @param int_mask int_mask interrupts to unmask ('1' to mask)
	+ */
	+void al_pcie_app_int_grp_mask(
	+ struct al_pcie_port *pcie_port,
	+ enum al_pcie_int_group int_group,
	+ uint32_t int_mask);
	+
	+/**
	+ * Clear the PCIe app group interrupt cause
	+ * @param pcie_port pcie port handle
	+ * @param int_group interrupt group
	+ * @param int_cause interrupt cause
	+ */
	+void al_pcie_app_int_grp_cause_clear(
	+ struct al_pcie_port *pcie_port,
	+ enum al_pcie_int_group int_group,
	+ uint32_t int_cause);
	+
	+/**
	+ * Read PCIe app group interrupt cause
	+ * @param pcie_port pcie port handle
	+ * @param int_group interrupt group
	+ * @return interrupt cause or 0 in case the group is not supported
	+ */
	+uint32_t al_pcie_app_int_grp_cause_read(
	+ struct al_pcie_port *pcie_port,
	+ enum al_pcie_int_group int_group);
	+
	+#endif
	+/** @} end of group_pcie_interrupts group */
	Index: sys/arm/annapurna/alpine/hal/al_hal_pcie_regs.h
	===================================================================
	--- /dev/null
	+++ sys/arm/annapurna/alpine/hal/al_hal_pcie_regs.h
	@@ -0,0 +1,594 @@
	+/*-
	+********************************************************************************
	+Copyright (C) 2015 Annapurna Labs Ltd.
	+
	+This file may be licensed under the terms of the Annapurna Labs Commercial
	+License Agreement.
	+
	+Alternatively, this file can be distributed under the terms of the GNU General
	+Public License V2 as published by the Free Software Foundation and can be
	+found at http://www.gnu.org/licenses/gpl-2.0.html
	+
	+Alternatively, redistribution and use in source and binary forms, with or
	+without modification, are permitted provided that the following conditions are
	+met:
	+
	+ * Redistributions of source code must retain the above copyright notice,
	+this list of conditions and the following disclaimer.
	+
	+ * Redistributions in binary form must reproduce the above copyright
	+notice, this list of conditions and the following disclaimer in
	+the documentation and/or other materials provided with the
	+distribution.
	+
	+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
	+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
	+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
	+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
	+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
	+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
	+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
	+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
	+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
	+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	+
	+*******************************************************************************/
	+
	+#ifndef __AL_HAL_PCIE_REGS_H__
	+#define __AL_HAL_PCIE_REGS_H__
	+
	+/* Note: Definitions before the includes so axi/wrapper regs sees them */
	+
	+/** Maximum physical functions supported */
	+#define REV1_2_MAX_NUM_OF_PFS 1
	+#define REV3_MAX_NUM_OF_PFS 4
	+#define AL_MAX_NUM_OF_PFS 4 /* the maximum between all Revisions */
	+
	+#include "al_hal_pcie_axi_reg.h"
	+#ifndef AL_PCIE_EX
	+#include "al_hal_pcie_w_reg.h"
	+#else
	+#include "al_hal_pcie_w_reg_ex.h"
	+#endif
	+
	+/**
	+ * Revision IDs:
	+ * ID_0: SlickRock M0
	+ * ID_1: SlickRock A0
	+ * ID_2: PeakRock x4
	+ * ID_3: PeakRock x8
	+ */
	+#define AL_PCIE_REV_ID_0 0
	+#define AL_PCIE_REV_ID_1 1
	+#define AL_PCIE_REV_ID_2 2
	+#define AL_PCIE_REV_ID_3 3
	+
	+#define AL_PCIE_AXI_REGS_OFFSET 0x0
	+#define AL_PCIE_REV_1_2_APP_REGS_OFFSET 0x1000
	+#define AL_PCIE_REV_3_APP_REGS_OFFSET 0x2000
	+#define AL_PCIE_REV_1_2_CORE_CONF_BASE_OFFSET 0x2000
	+#define AL_PCIE_REV_3_CORE_CONF_BASE_OFFSET 0x10000
	+
	+/** Maximum number of lanes supported */
	+#define REV1_2_MAX_NUM_LANES 4
	+#define REV3_MAX_NUM_LANES 8
	+#define AL_MAX_NUM_OF_LANES 8 /* the maximum between all Revisions */
	+
	+struct al_pcie_core_iatu_regs {
	+ uint32_t index;
	+ uint32_t cr1;
	+ uint32_t cr2;
	+ uint32_t lower_base_addr;
	+ uint32_t upper_base_addr;
	+ uint32_t limit_addr;
	+ uint32_t lower_target_addr;
	+ uint32_t upper_target_addr;
	+ uint32_t cr3;
	+ uint32_t rsrvd[(0x270 - 0x224) >> 2];
	+};
	+
	+struct al_pcie_core_port_regs {
	+ uint32_t ack_lat_rply_timer;
	+ uint32_t reserved1[(0x10 - 0x4) >> 2];
	+ uint32_t port_link_ctrl;
	+ uint32_t reserved2[(0x18 - 0x14) >> 2];
	+ uint32_t timer_ctrl_max_func_num;
	+ uint32_t filter_mask_reg_1;
	+ uint32_t reserved3[(0x48 - 0x20) >> 2];
	+ uint32_t vc0_posted_rcv_q_ctrl;
	+ uint32_t vc0_non_posted_rcv_q_ctrl;
	+ uint32_t vc0_comp_rcv_q_ctrl;
	+ uint32_t reserved4[(0x10C - 0x54) >> 2];
	+ uint32_t gen2_ctrl;
	+ uint32_t reserved5[(0x190 - 0x110) >> 2];
	+ uint32_t gen3_ctrl;
	+ uint32_t gen3_eq_fs_lf;
	+ uint32_t gen3_eq_preset_to_coef_map;
	+ uint32_t gen3_eq_preset_idx;
	+ uint32_t reserved6;
	+ uint32_t gen3_eq_status;
	+ uint32_t gen3_eq_ctrl;
	+ uint32_t reserved7[(0x1B8 - 0x1AC) >> 2];
	+ uint32_t pipe_loopback_ctrl;
	+ uint32_t rd_only_wr_en;
	+ uint32_t reserved8[(0x1D0 - 0x1C0) >> 2];
	+ uint32_t axi_slave_err_resp;
	+ uint32_t reserved9[(0x200 - 0x1D4) >> 2];
	+ struct al_pcie_core_iatu_regs iatu;
	+ uint32_t reserved10[(0x448 - 0x270) >> 2];
	+};
	+
	+struct al_pcie_core_aer_regs {
	+ /* 0x0 - PCI Express Extended Capability Header */
	+ uint32_t header;
	+ /* 0x4 - Uncorrectable Error Status Register */
	+ uint32_t uncorr_err_stat;
	+ /* 0x8 - Uncorrectable Error Mask Register */
	+ uint32_t uncorr_err_mask;
	+ /* 0xc - Uncorrectable Error Severity Register */
	+ uint32_t uncorr_err_severity;
	+ /* 0x10 - Correctable Error Status Register */
	+ uint32_t corr_err_stat;
	+ /* 0x14 - Correctable Error Mask Register */
	+ uint32_t corr_err_mask;
	+ /* 0x18 - Advanced Error Capabilities and Control Register */
	+ uint32_t cap_and_ctrl;
	+ /* 0x1c - Header Log Registers */
	+ uint32_t header_log[4];
	+ /* 0x2c - Root Error Command Register */
	+ uint32_t root_err_cmd;
	+ /* 0x30 - Root Error Status Register */
	+ uint32_t root_err_stat;
	+ /* 0x34 - Error Source Identification Register */
	+ uint32_t err_src_id;
	+};
	+
	+struct al_pcie_core_reg_space_rev_1_2 {
	+ uint32_t config_header[0x40 >> 2];
	+ uint32_t pcie_pm_cap_base;
	+ uint32_t reserved1[(0x70 - 0x44) >> 2];
	+ uint32_t pcie_cap_base;
	+ uint32_t pcie_dev_cap_base;
	+ uint32_t pcie_dev_ctrl_status;
	+ uint32_t pcie_link_cap_base;
	+ uint32_t reserved2[(0xB0 - 0x80) >> 2];
	+ uint32_t msix_cap_base;
	+ uint32_t reserved3[(0x100 - 0xB4) >> 2];
	+ struct al_pcie_core_aer_regs aer;
	+ uint32_t reserved4[(0x150 -
	+ (0x100 +
	+ sizeof(struct al_pcie_core_aer_regs))) >> 2];
	+ uint32_t pcie_sec_ext_cap_base;
	+ uint32_t reserved5[(0x700 - 0x154) >> 2];
	+ struct al_pcie_core_port_regs port_regs;
	+ uint32_t reserved6[(0x1000 -
	+ (0x700 +
	+ sizeof(struct al_pcie_core_port_regs))) >> 2];
	+};
	+
	+struct al_pcie_core_reg_space_rev_3 {
	+ uint32_t config_header[0x40 >> 2];
	+ uint32_t pcie_pm_cap_base;
	+ uint32_t reserved1[(0x70 - 0x44) >> 2];
	+ uint32_t pcie_cap_base;
	+ uint32_t pcie_dev_cap_base;
	+ uint32_t pcie_dev_ctrl_status;
	+ uint32_t pcie_link_cap_base;
	+ uint32_t reserved2[(0xB0 - 0x80) >> 2];
	+ uint32_t msix_cap_base;
	+ uint32_t reserved3[(0x100 - 0xB4) >> 2];
	+ struct al_pcie_core_aer_regs aer;
	+ uint32_t reserved4[(0x158 -
	+ (0x100 +
	+ sizeof(struct al_pcie_core_aer_regs))) >> 2];
	+ /* pcie_sec_cap is only applicable for function 0 */
	+ uint32_t pcie_sec_ext_cap_base;
	+ uint32_t reserved5[(0x178 - 0x15C) >> 2];
	+ /* tph capability is only applicable for rev3 */
	+ uint32_t tph_cap_base;
	+ uint32_t reserved6[(0x700 - 0x17C) >> 2];
	+ /* port_regs is only applicable for function 0 */
	+ struct al_pcie_core_port_regs port_regs;
	+ uint32_t reserved7[(0x1000 -
	+ (0x700 +
	+ sizeof(struct al_pcie_core_port_regs))) >> 2];
	+};
	+
	+struct al_pcie_rev3_core_reg_space {
	+ struct al_pcie_core_reg_space_rev_3 func[REV3_MAX_NUM_OF_PFS];
	+};
	+
	+struct al_pcie_core_reg_space {
	+ uint32_t *config_header;
	+ uint32_t *pcie_pm_cap_base;
	+ uint32_t *pcie_cap_base;
	+ uint32_t *pcie_dev_cap_base;
	+ uint32_t *pcie_dev_ctrl_status;
	+ uint32_t *pcie_link_cap_base;
	+ uint32_t *msix_cap_base;
	+ struct al_pcie_core_aer_regs *aer;
	+ uint32_t *pcie_sec_ext_cap_base;
	+ uint32_t *tph_cap_base;
	+};
	+
	+struct al_pcie_revx_regs {
	+ struct al_pcie_revx_axi_regs __iomem axi;
	+};
	+
	+struct al_pcie_rev1_regs {
	+ struct al_pcie_rev1_axi_regs __iomem axi;
	+ uint32_t reserved1[(AL_PCIE_REV_1_2_APP_REGS_OFFSET -
	+ (AL_PCIE_AXI_REGS_OFFSET +
	+ sizeof(struct al_pcie_rev1_axi_regs))) >> 2];
	+ struct al_pcie_rev1_w_regs __iomem app;
	+ uint32_t reserved2[(AL_PCIE_REV_1_2_CORE_CONF_BASE_OFFSET -
	+ (AL_PCIE_REV_1_2_APP_REGS_OFFSET +
	+ sizeof(struct al_pcie_rev1_w_regs))) >> 2];
	+ struct al_pcie_core_reg_space_rev_1_2 core_space;
	+};
	+
	+struct al_pcie_rev2_regs {
	+ struct al_pcie_rev2_axi_regs __iomem axi;
	+ uint32_t reserved1[(AL_PCIE_REV_1_2_APP_REGS_OFFSET -
	+ (AL_PCIE_AXI_REGS_OFFSET +
	+ sizeof(struct al_pcie_rev2_axi_regs))) >> 2];
	+ struct al_pcie_rev2_w_regs __iomem app;
	+ uint32_t reserved2[(AL_PCIE_REV_1_2_CORE_CONF_BASE_OFFSET -
	+ (AL_PCIE_REV_1_2_APP_REGS_OFFSET +
	+ sizeof(struct al_pcie_rev2_w_regs))) >> 2];
	+ struct al_pcie_core_reg_space_rev_1_2 core_space;
	+};
	+
	+struct al_pcie_rev3_regs {
	+ struct al_pcie_rev3_axi_regs __iomem axi;
	+ uint32_t reserved1[(AL_PCIE_REV_3_APP_REGS_OFFSET -
	+ (AL_PCIE_AXI_REGS_OFFSET +
	+ sizeof(struct al_pcie_rev3_axi_regs))) >> 2];
	+ struct al_pcie_rev3_w_regs __iomem app;
	+ uint32_t reserved2[(AL_PCIE_REV_3_CORE_CONF_BASE_OFFSET -
	+ (AL_PCIE_REV_3_APP_REGS_OFFSET +
	+ sizeof(struct al_pcie_rev3_w_regs))) >> 2];
	+ struct al_pcie_rev3_core_reg_space core_space;
	+};
	+
	+struct al_pcie_axi_ctrl {
	+ uint32_t *global;
	+ uint32_t *master_arctl;
	+ uint32_t *master_awctl;
	+ uint32_t *slv_ctl;
	+};
	+
	+struct al_pcie_axi_ob_ctrl {
	+ uint32_t *cfg_target_bus;
	+ uint32_t *cfg_control;
	+ uint32_t *io_start_l;
	+ uint32_t *io_start_h;
	+ uint32_t *io_limit_l;
	+ uint32_t *io_limit_h;
	+};
	+
	+struct al_pcie_axi_pcie_global {
	+ uint32_t *conf;
	+};
	+
	+struct al_pcie_axi_conf {
	+ uint32_t *zero_lane0;
	+ uint32_t *zero_lane1;
	+ uint32_t *zero_lane2;
	+ uint32_t *zero_lane3;
	+ uint32_t *zero_lane4;
	+ uint32_t *zero_lane5;
	+ uint32_t *zero_lane6;
	+ uint32_t *zero_lane7;
	+};
	+
	+struct al_pcie_axi_status {
	+ uint32_t *lane[AL_MAX_NUM_OF_LANES];
	+};
	+
	+struct al_pcie_axi_parity {
	+ uint32_t *en_axi;
	+};
	+
	+struct al_pcie_axi_ordering {
	+ uint32_t *pos_cntl;
	+};
	+
	+struct al_pcie_axi_pre_configuration {
	+ uint32_t *pcie_core_setup;
	+};
	+
	+struct al_pcie_axi_init_fc {
	+ uint32_t *cfg;
	+};
	+
	+struct al_pcie_axi_attr_ovrd {
	+ uint32_t *write_msg_ctrl_0;
	+ uint32_t *write_msg_ctrl_1;
	+ uint32_t *pf_sel;
	+};
	+
	+struct al_pcie_axi_pf_axi_attr_ovrd {
	+ uint32_t *func_ctrl_0;
	+ uint32_t *func_ctrl_1;
	+ uint32_t *func_ctrl_2;
	+ uint32_t *func_ctrl_3;
	+ uint32_t *func_ctrl_4;
	+ uint32_t *func_ctrl_5;
	+ uint32_t *func_ctrl_6;
	+ uint32_t *func_ctrl_7;
	+ uint32_t *func_ctrl_8;
	+ uint32_t *func_ctrl_9;
	+};
	+
	+struct al_pcie_axi_msg_attr_axuser_table {
	+ uint32_t *entry_vec;
	+};
	+
	+struct al_pcie_axi_regs {
	+ struct al_pcie_axi_ctrl ctrl;
	+ struct al_pcie_axi_ob_ctrl ob_ctrl;
	+ struct al_pcie_axi_pcie_global pcie_global;
	+ struct al_pcie_axi_conf conf;
	+ struct al_pcie_axi_status status;
	+ struct al_pcie_axi_parity parity;
	+ struct al_pcie_axi_ordering ordering;
	+ struct al_pcie_axi_pre_configuration pre_configuration;
	+ struct al_pcie_axi_init_fc init_fc;
	+ struct al_pcie_revx_axi_int_grp_a_axi *int_grp_a;
	+ /* Rev3 only */
	+ struct al_pcie_axi_attr_ovrd axi_attr_ovrd;
	+ struct al_pcie_axi_pf_axi_attr_ovrd pf_axi_attr_ovrd[REV3_MAX_NUM_OF_PFS];
	+ struct al_pcie_axi_msg_attr_axuser_table msg_attr_axuser_table;
	+};
	+
	+struct al_pcie_w_global_ctrl {
	+ uint32_t *port_init;
	+ uint32_t *pm_control;
	+ uint32_t *events_gen[REV3_MAX_NUM_OF_PFS];
	+ uint32_t *corr_err_sts_int;
	+ uint32_t *uncorr_err_sts_int;
	+ uint32_t *sris_kp_counter;
	+};
	+
	+struct al_pcie_w_soc_int {
	+ uint32_t *mask_inta_leg_0;
	+ uint32_t mask_inta_leg_3; / Rev 2/3 only */
	+ uint32_t *mask_msi_leg_0;
	+ uint32_t mask_msi_leg_3; / Rev 2/3 only */
	+};
	+struct al_pcie_w_atu {
	+ uint32_t *in_mask_pair;
	+ uint32_t *out_mask_pair;
	+};
	+
	+struct al_pcie_w_regs {
	+ struct al_pcie_w_global_ctrl global_ctrl;
	+ struct al_pcie_revx_w_debug *debug;
	+ struct al_pcie_revx_w_ap_user_send_msg *ap_user_send_msg;
	+ struct al_pcie_w_soc_int soc_int[REV3_MAX_NUM_OF_PFS];
	+ struct al_pcie_revx_w_cntl_gen *ctrl_gen;
	+ struct al_pcie_revx_w_parity *parity;
	+ struct al_pcie_w_atu atu;
	+ struct al_pcie_revx_w_status_per_func *status_per_func[REV3_MAX_NUM_OF_PFS];
	+ struct al_pcie_revx_w_int_grp *int_grp_a;
	+ struct al_pcie_revx_w_int_grp *int_grp_b;
	+ struct al_pcie_revx_w_int_grp *int_grp_c;
	+ struct al_pcie_revx_w_int_grp *int_grp_d;
	+};
	+
	+struct al_pcie_regs {
	+ struct al_pcie_axi_regs axi;
	+ struct al_pcie_w_regs app;
	+ struct al_pcie_core_port_regs *port_regs;
	+ struct al_pcie_core_reg_space core_space[REV3_MAX_NUM_OF_PFS];
	+};
	+
	+#define PCIE_AXI_MISC_PCIE_GLOBAL_CONF_DEV_TYPE_EP 0
	+#define PCIE_AXI_MISC_PCIE_GLOBAL_CONF_DEV_TYPE_RC 4
	+
	+#define PCIE_PORT_GEN2_CTRL_DIRECT_SPEED_CHANGE AL_BIT(17)
	+#define PCIE_PORT_GEN2_CTRL_TX_SWING_LOW_SHIFT 18
	+#define PCIE_PORT_GEN2_CTRL_TX_COMPLIANCE_RCV_SHIFT 19
	+#define PCIE_PORT_GEN2_CTRL_DEEMPHASIS_SET_SHIFT 20
	+#define PCIE_PORT_GEN2_CTRL_NUM_OF_LANES_MASK AL_FIELD_MASK(12, 8)
	+#define PCIE_PORT_GEN2_CTRL_NUM_OF_LANES_SHIFT 8
	+
	+#define PCIE_PORT_GEN3_CTRL_EQ_PHASE_2_3_DISABLE_SHIFT 9
	+#define PCIE_PORT_GEN3_CTRL_EQ_DISABLE_SHIFT 16
	+
	+#define PCIE_PORT_GEN3_EQ_LF_SHIFT 0
	+#define PCIE_PORT_GEN3_EQ_LF_MASK 0x3f
	+#define PCIE_PORT_GEN3_EQ_FS_SHIFT 6
	+#define PCIE_PORT_GEN3_EQ_FS_MASK (0x3f << PCIE_PORT_GEN3_EQ_FS_SHIFT)
	+
	+#define PCIE_PORT_LINK_CTRL_LB_EN_SHIFT 2
	+#define PCIE_PORT_LINK_CTRL_FAST_LINK_EN_SHIFT 7
	+#define PCIE_PORT_LINK_CTRL_LINK_CAPABLE_MASK AL_FIELD_MASK(21, 16)
	+#define PCIE_PORT_LINK_CTRL_LINK_CAPABLE_SHIFT 16
	+
	+#define PCIE_PORT_PIPE_LOOPBACK_CTRL_PIPE_LB_EN_SHIFT 31
	+
	+#define PCIE_PORT_AXI_SLAVE_ERR_RESP_ALL_MAPPING_SHIFT 0
	+
	+/** timer_ctrl_max_func_num register
	+ * Max physical function number (for example: 0 for 1PF, 3 for 4PFs)
	+ */
	+#define PCIE_PORT_GEN3_MAX_FUNC_NUM AL_FIELD_MASK(7, 0)
	+
	+/* filter_mask_reg_1 register */
	+/**
	+ * SKP Interval Value.
	+ * The number of symbol times to wait between transmitting SKP ordered sets
	+ */
	+#define PCIE_FLT_MASK_SKP_INT_VAL_MASK AL_FIELD_MASK(10, 0)
	+
	+/*
	+ * 0: Treat Function MisMatched TLPs as UR
	+ * 1: Treat Function MisMatched TLPs as Supported
	+ */
	+#define CX_FLT_MASK_UR_FUNC_MISMATCH AL_BIT(16)
	+
	+/*
	+ * 0: Treat CFG type1 TLPs as UR for EP; Supported for RC
	+ * 1: Treat CFG type1 TLPs as Supported for EP; UR for RC
	+ */
	+#define CX_FLT_MASK_CFG_TYPE1_RE_AS_UR AL_BIT(19)
	+
	+/*
	+ * 0: Enforce requester id match for received CPL TLPs.
	+ * A violation results in cpl_abort, and possibly AER of unexp_cpl_err,
	+ * cpl_rcvd_ur, cpl_rcvd_ca
	+ * 1: Mask requester id match for received CPL TLPs
	+ */
	+#define CX_FLT_MASK_CPL_REQID_MATCH AL_BIT(22)
	+
	+/*
	+ * 0: Enforce function match for received CPL TLPs.
	+ * A violation results in cpl_abort, and possibly AER of unexp_cpl_err,
	+ * cpl_rcvd_ur, cpl_rcvd_ca
	+ * 1: Mask function match for received CPL TLPs
	+ */
	+#define CX_FLT_MASK_CPL_FUNC_MATCH AL_BIT(23)
	+
	+/* vc0_posted_rcv_q_ctrl register */
	+#define RADM_PQ_HCRD_VC0_MASK AL_FIELD_MASK(19, 12)
	+#define RADM_PQ_HCRD_VC0_SHIFT 12
	+
	+/* vc0_non_posted_rcv_q_ctrl register */
	+#define RADM_NPQ_HCRD_VC0_MASK AL_FIELD_MASK(19, 12)
	+#define RADM_NPQ_HCRD_VC0_SHIFT 12
	+
	+/* vc0_comp_rcv_q_ctrl register */
	+#define RADM_CPLQ_HCRD_VC0_MASK AL_FIELD_MASK(19, 12)
	+#define RADM_CPLQ_HCRD_VC0_SHIFT 12
	+
	+/** iATU, Control Register 1 **/
	+
	+/**
	+ * When the Address and BAR matching logic in the core indicate that a MEM-I/O
	+ * transaction matches a BAR in the function corresponding to this value, then
	+ * address translation proceeds. This check is only performed if the "Function
	+ * Number Match Enable" bit of the "iATU Control 2 Register" is set
	+ */
	+#define PCIE_IATU_CR1_FUNC_NUM_MASK AL_FIELD_MASK(24, 20)
	+#define PCIE_IATU_CR1_FUNC_NUM_SHIFT 20
	+
	+/** iATU, Control Register 2 **/
	+/** For outbound regions, the Function Number Translation Bypass mode enables
	+ * taking the function number of the translated TLP from the PCIe core
	+ * interface and not from the "Function Number" field of CR1.
	+ * For inbound regions, this bit should be asserted when physical function
	+ * match mode needs to be enabled
	+ */
	+#define PCIE_IATU_CR2_FUNC_NUM_TRANS_BYPASS_FUNC_MATCH_ENABLE_MASK AL_BIT(19)
	+#define PCIE_IATU_CR2_FUNC_NUM_TRANS_BYPASS_FUNC_MATCH_ENABLE_SHIFT 19
	+
	+/* pcie_dev_ctrl_status register */
	+#define PCIE_PORT_DEV_CTRL_STATUS_CORR_ERR_REPORT_EN AL_BIT(0)
	+#define PCIE_PORT_DEV_CTRL_STATUS_NON_FTL_ERR_REPORT_EN AL_BIT(1)
	+#define PCIE_PORT_DEV_CTRL_STATUS_FTL_ERR_REPORT_EN AL_BIT(2)
	+#define PCIE_PORT_DEV_CTRL_STATUS_UNSUP_REQ_REPORT_EN AL_BIT(3)
	+
	+#define PCIE_PORT_DEV_CTRL_STATUS_MPS_MASK AL_FIELD_MASK(7, 5)
	+#define PCIE_PORT_DEV_CTRL_STATUS_MPS_SHIFT 5
	+#define PCIE_PORT_DEV_CTRL_STATUS_MPS_VAL_256 (1 << PCIE_PORT_DEV_CTRL_STATUS_MPS_SHIFT)
	+
	+#define PCIE_PORT_DEV_CTRL_STATUS_MRRS_MASK AL_FIELD_MASK(14, 12)
	+#define PCIE_PORT_DEV_CTRL_STATUS_MRRS_SHIFT 12
	+#define PCIE_PORT_DEV_CTRL_STATUS_MRRS_VAL_256 (1 << PCIE_PORT_DEV_CTRL_STATUS_MRRS_SHIFT)
	+
	+/******************************************************************************
	+ * AER registers
	+ ******************************************************************************/
	+/* PCI Express Extended Capability ID */
	+#define PCIE_AER_CAP_ID_MASK AL_FIELD_MASK(15, 0)
	+#define PCIE_AER_CAP_ID_SHIFT 0
	+#define PCIE_AER_CAP_ID_VAL 1
	+/* Capability Version */
	+#define PCIE_AER_CAP_VER_MASK AL_FIELD_MASK(19, 16)
	+#define PCIE_AER_CAP_VER_SHIFT 16
	+#define PCIE_AER_CAP_VER_VAL 2
	+
	+/* First Error Pointer */
	+#define PCIE_AER_CTRL_STAT_FIRST_ERR_PTR_MASK AL_FIELD_MASK(4, 0)
	+#define PCIE_AER_CTRL_STAT_FIRST_ERR_PTR_SHIFT 0
	+/* ECRC Generation Capability */
	+#define PCIE_AER_CTRL_STAT_ECRC_GEN_SUPPORTED AL_BIT(5)
	+/* ECRC Generation Enable */
	+#define PCIE_AER_CTRL_STAT_ECRC_GEN_EN AL_BIT(6)
	+/* ECRC Check Capable */
	+#define PCIE_AER_CTRL_STAT_ECRC_CHK_SUPPORTED AL_BIT(7)
	+/* ECRC Check Enable */
	+#define PCIE_AER_CTRL_STAT_ECRC_CHK_EN AL_BIT(8)
	+
	+/* Correctable Error Reporting Enable */
	+#define PCIE_AER_ROOT_ERR_CMD_CORR_ERR_RPRT_EN AL_BIT(0)
	+/* Non-Fatal Error Reporting Enable */
	+#define PCIE_AER_ROOT_ERR_CMD_NON_FTL_ERR_RPRT_EN AL_BIT(1)
	+/* Fatal Error Reporting Enable */
	+#define PCIE_AER_ROOT_ERR_CMD_FTL_ERR_RPRT_EN AL_BIT(2)
	+
	+/* ERR_COR Received */
	+#define PCIE_AER_ROOT_ERR_STAT_CORR_ERR AL_BIT(0)
	+/* Multiple ERR_COR Received */
	+#define PCIE_AER_ROOT_ERR_STAT_CORR_ERR_MULTI AL_BIT(1)
	+/* ERR_FATAL/NONFATAL Received */
	+#define PCIE_AER_ROOT_ERR_STAT_FTL_NON_FTL_ERR AL_BIT(2)
	+/* Multiple ERR_FATAL/NONFATAL Received */
	+#define PCIE_AER_ROOT_ERR_STAT_FTL_NON_FTL_ERR_MULTI AL_BIT(3)
	+/* First Uncorrectable Fatal */
	+#define PCIE_AER_ROOT_ERR_STAT_FIRST_UNCORR_FTL AL_BIT(4)
	+/* Non-Fatal Error Messages Received */
	+#define PCIE_AER_ROOT_ERR_STAT_NON_FTL_RCVD AL_BIT(5)
	+/* Fatal Error Messages Received */
	+#define PCIE_AER_ROOT_ERR_STAT_FTL_RCVD AL_BIT(6)
	+/* Advanced Error Interrupt Message Number */
	+#define PCIE_AER_ROOT_ERR_STAT_ERR_INT_MSG_NUM_MASK AL_FIELD_MASK(31, 27)
	+#define PCIE_AER_ROOT_ERR_STAT_ERR_INT_MSG_NUM_SHIFT 27
	+
	+/* ERR_COR Source Identification */
	+#define PCIE_AER_SRC_ID_CORR_ERR_MASK AL_FIELD_MASK(15, 0)
	+#define PCIE_AER_SRC_ID_CORR_ERR_SHIFT 0
	+/* ERR_FATAL/NONFATAL Source Identification */
	+#define PCIE_AER_SRC_ID_CORR_ERR_FTL_NON_FTL_MASK AL_FIELD_MASK(31, 16)
	+#define PCIE_AER_SRC_ID_CORR_ERR_FTL_NON_FTL_SHIFT 16
	+
	+/* AER message */
	+#define PCIE_AER_MSG_REQID_MASK AL_FIELD_MASK(31, 16)
	+#define PCIE_AER_MSG_REQID_SHIFT 16
	+#define PCIE_AER_MSG_TYPE_MASK AL_FIELD_MASK(15, 8)
	+#define PCIE_AER_MSG_TYPE_SHIFT 8
	+#define PCIE_AER_MSG_RESERVED AL_FIELD_MASK(7, 1)
	+#define PCIE_AER_MSG_VALID AL_BIT(0)
	+/* AER message ack */
	+#define PCIE_AER_MSG_ACK AL_BIT(0)
	+/* AER errors definitions */
	+#define AL_PCIE_AER_TYPE_CORR (0x30)
	+#define AL_PCIE_AER_TYPE_NON_FATAL (0x31)
	+#define AL_PCIE_AER_TYPE_FATAL (0x33)
	+/* Requester ID Bus */
	+#define AL_PCIE_REQID_BUS_NUM_SHIFT (8)
	+
	+/******************************************************************************
	+ * TPH registers
	+ ******************************************************************************/
	+#define PCIE_TPH_NEXT_POINTER AL_FIELD_MASK(31, 20)
	+
	+/******************************************************************************
	+ * Config Header registers
	+ ******************************************************************************/
	+/**
	+ * see BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG in core spec
	+ * Note: valid only for EP mode
	+ */
	+#define PCIE_BIST_HEADER_TYPE_BASE 0xc
	+#define PCIE_BIST_HEADER_TYPE_MULTI_FUNC_MASK AL_BIT(23)
	+
	+/******************************************************************************
	+ * SRIS KP counters default values
	+ ******************************************************************************/
	+#define PCIE_SRIS_KP_COUNTER_GEN3_DEFAULT_VAL (0x24)
	+#define PCIE_SRIS_KP_COUNTER_GEN21_DEFAULT_VAL (0x4B)
	+
	+#endif
	Index: sys/arm/annapurna/alpine/hal/al_hal_pcie_w_reg.h
	===================================================================
	--- /dev/null
	+++ sys/arm/annapurna/alpine/hal/al_hal_pcie_w_reg.h
	@@ -0,0 +1,1505 @@
	+/*-
	+********************************************************************************
	+Copyright (C) 2015 Annapurna Labs Ltd.
	+
	+This file may be licensed under the terms of the Annapurna Labs Commercial
	+License Agreement.
	+
	+Alternatively, this file can be distributed under the terms of the GNU General
	+Public License V2 as published by the Free Software Foundation and can be
	+found at http://www.gnu.org/licenses/gpl-2.0.html
	+
	+Alternatively, redistribution and use in source and binary forms, with or
	+without modification, are permitted provided that the following conditions are
	+met:
	+
	+ * Redistributions of source code must retain the above copyright notice,
	+this list of conditions and the following disclaimer.
	+
	+ * Redistributions in binary form must reproduce the above copyright
	+notice, this list of conditions and the following disclaimer in
	+the documentation and/or other materials provided with the
	+distribution.
	+
	+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
	+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
	+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
	+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
	+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
	+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
	+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
	+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
	+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
	+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	+
	+*******************************************************************************/
	+
	+
	+#ifndef __AL_HAL_PCIE_W_REG_H__
	+#define __AL_HAL_PCIE_W_REG_H__
	+
	+#ifdef __cplusplus
	+extern "C" {
	+#endif
	+/*
	+* Unit Registers
	+*/
	+
	+
	+
	+struct al_pcie_rev1_w_global_ctrl {
	+ /* [0x0] */
	+ uint32_t port_init;
	+ /* [0x4] */
	+ uint32_t port_status;
	+ /* [0x8] */
	+ uint32_t pm_control;
	+ uint32_t rsrvd_0;
	+ /* [0x10] */
	+ uint32_t events_gen;
	+ uint32_t rsrvd[3];
	+};
	+struct al_pcie_rev2_w_global_ctrl {
	+ /* [0x0] */
	+ uint32_t port_init;
	+ /* [0x4] */
	+ uint32_t port_status;
	+ /* [0x8] */
	+ uint32_t pm_control;
	+ uint32_t rsrvd_0;
	+ /* [0x10] */
	+ uint32_t events_gen;
	+ /* [0x14] */
	+ uint32_t pended_corr_err_sts_int;
	+ /* [0x18] */
	+ uint32_t pended_uncorr_err_sts_int;
	+ /* [0x1c] */
	+ uint32_t sris_kp_counter_value;
	+};
	+struct al_pcie_rev3_w_global_ctrl {
	+ /* [0x0] */
	+ uint32_t port_init;
	+ /* [0x4] */
	+ uint32_t port_status;
	+ /* [0x8] */
	+ uint32_t pm_control;
	+ /* [0xc] */
	+ uint32_t pended_corr_err_sts_int;
	+ /* [0x10] */
	+ uint32_t pended_uncorr_err_sts_int;
	+ /* [0x14] */
	+ uint32_t sris_kp_counter_value;
	+ uint32_t rsrvd[2];
	+};
	+
	+struct al_pcie_rev3_w_events_gen_per_func {
	+ /* [0x0] */
	+ uint32_t events_gen;
	+};
	+struct al_pcie_rev3_w_pm_state_per_func {
	+ /* [0x0] */
	+ uint32_t pm_state_per_func;
	+};
	+struct al_pcie_rev3_w_cfg_bars_ovrd {
	+ /* [0x0] */
	+ uint32_t bar0_mask_lsb;
	+ /* [0x4] */
	+ uint32_t bar0_mask_msb;
	+ /* [0x8] */
	+ uint32_t bar0_limit_lsb;
	+ /* [0xc] */
	+ uint32_t bar0_limit_msb;
	+ /* [0x10] */
	+ uint32_t bar0_start_lsb;
	+ /* [0x14] */
	+ uint32_t bar0_start_msb;
	+ /* [0x18] */
	+ uint32_t bar0_ctrl;
	+ /* [0x1c] */
	+ uint32_t bar1_mask_lsb;
	+ /* [0x20] */
	+ uint32_t bar1_mask_msb;
	+ /* [0x24] */
	+ uint32_t bar1_limit_lsb;
	+ /* [0x28] */
	+ uint32_t bar1_limit_msb;
	+ /* [0x2c] */
	+ uint32_t bar1_start_lsb;
	+ /* [0x30] */
	+ uint32_t bar1_start_msb;
	+ /* [0x34] */
	+ uint32_t bar1_ctrl;
	+ /* [0x38] */
	+ uint32_t bar2_mask_lsb;
	+ /* [0x3c] */
	+ uint32_t bar2_mask_msb;
	+ /* [0x40] */
	+ uint32_t bar2_limit_lsb;
	+ /* [0x44] */
	+ uint32_t bar2_limit_msb;
	+ /* [0x48] */
	+ uint32_t bar2_start_lsb;
	+ /* [0x4c] */
	+ uint32_t bar2_start_msb;
	+ /* [0x50] */
	+ uint32_t bar2_ctrl;
	+ /* [0x54] */
	+ uint32_t bar3_mask_lsb;
	+ /* [0x58] */
	+ uint32_t bar3_mask_msb;
	+ /* [0x5c] */
	+ uint32_t bar3_limit_lsb;
	+ /* [0x60] */
	+ uint32_t bar3_limit_msb;
	+ /* [0x64] */
	+ uint32_t bar3_start_lsb;
	+ /* [0x68] */
	+ uint32_t bar3_start_msb;
	+ /* [0x6c] */
	+ uint32_t bar3_ctrl;
	+ /* [0x70] */
	+ uint32_t bar4_mask_lsb;
	+ /* [0x74] */
	+ uint32_t bar4_mask_msb;
	+ /* [0x78] */
	+ uint32_t bar4_limit_lsb;
	+ /* [0x7c] */
	+ uint32_t bar4_limit_msb;
	+ /* [0x80] */
	+ uint32_t bar4_start_lsb;
	+ /* [0x84] */
	+ uint32_t bar4_start_msb;
	+ /* [0x88] */
	+ uint32_t bar4_ctrl;
	+ /* [0x8c] */
	+ uint32_t bar5_mask_lsb;
	+ /* [0x90] */
	+ uint32_t bar5_mask_msb;
	+ /* [0x94] */
	+ uint32_t bar5_limit_lsb;
	+ /* [0x98] */
	+ uint32_t bar5_limit_msb;
	+ /* [0x9c] */
	+ uint32_t bar5_start_lsb;
	+ /* [0xa0] */
	+ uint32_t bar5_start_msb;
	+ /* [0xa4] */
	+ uint32_t bar5_ctrl;
	+ uint32_t rsrvd[2];
	+};
	+
	+struct al_pcie_revx_w_debug {
	+ /* [0x0] */
	+ uint32_t info_0;
	+ /* [0x4] */
	+ uint32_t info_1;
	+ /* [0x8] */
	+ uint32_t info_2;
	+ /* [0xc] */
	+ uint32_t info_3;
	+};
	+struct al_pcie_revx_w_ob_ven_msg {
	+ /* [0x0] */
	+ uint32_t control;
	+ /* [0x4] */
	+ uint32_t param_1;
	+ /* [0x8] */
	+ uint32_t param_2;
	+ /* [0xc] */
	+ uint32_t data_high;
	+ uint32_t rsrvd_0;
	+ /* [0x14] */
	+ uint32_t data_low;
	+};
	+struct al_pcie_revx_w_ap_user_send_msg {
	+ /* [0x0] */
	+ uint32_t req_info;
	+ /* [0x4] */
	+ uint32_t ack_info;
	+};
	+struct al_pcie_revx_w_link_down {
	+ /* [0x0] */
	+ uint32_t reset_delay;
	+ /* [0x4] */
	+ uint32_t reset_extend_rsrvd;
	+};
	+struct al_pcie_revx_w_cntl_gen {
	+ /* [0x0] */
	+ uint32_t features;
	+};
	+struct al_pcie_revx_w_parity {
	+ /* [0x0] */
	+ uint32_t en_core;
	+ /* [0x4] */
	+ uint32_t status_core;
	+};
	+struct al_pcie_revx_w_last_wr {
	+ /* [0x0] */
	+ uint32_t cfg_addr;
	+};
	+struct al_pcie_rev1_2_w_atu {
	+ /* [0x0] */
	+ uint32_t in_mask_pair[6];
	+ /* [0x18] */
	+ uint32_t out_mask_pair[6];
	+};
	+struct al_pcie_rev3_w_atu {
	+ /* [0x0] */
	+ uint32_t in_mask_pair[12];
	+ /* [0x30] */
	+ uint32_t out_mask_pair[8];
	+ /* [0x50] */
	+ uint32_t reg_out_mask;
	+ uint32_t rsrvd[11];
	+};
	+struct al_pcie_rev3_w_cfg_func_ext {
	+ /* [0x0] */
	+ uint32_t cfg;
	+};
	+struct al_pcie_rev3_w_app_hdr_interface_send {
	+ /* [0x0] */
	+ uint32_t app_hdr_31_0;
	+ /* [0x4] */
	+ uint32_t app_hdr_63_32;
	+ /* [0x8] */
	+ uint32_t app_hdr_95_64;
	+ /* [0xc] */
	+ uint32_t app_hdr_127_96;
	+ /* [0x10] */
	+ uint32_t app_err_bus;
	+ /* [0x14] */
	+ uint32_t app_func_num_advisory;
	+ /* [0x18] */
	+ uint32_t app_hdr_cmd;
	+};
	+struct al_pcie_rev3_w_diag_command {
	+ /* [0x0] */
	+ uint32_t diag_ctrl;
	+};
	+struct al_pcie_rev1_w_soc_int {
	+ /* [0x0] */
	+ uint32_t status_0;
	+ /* [0x4] */
	+ uint32_t status_1;
	+ /* [0x8] */
	+ uint32_t status_2;
	+ /* [0xc] */
	+ uint32_t mask_inta_leg_0;
	+ /* [0x10] */
	+ uint32_t mask_inta_leg_1;
	+ /* [0x14] */
	+ uint32_t mask_inta_leg_2;
	+ /* [0x18] */
	+ uint32_t mask_msi_leg_0;
	+ /* [0x1c] */
	+ uint32_t mask_msi_leg_1;
	+ /* [0x20] */
	+ uint32_t mask_msi_leg_2;
	+ /* [0x24] */
	+ uint32_t msi_leg_cntl;
	+};
	+struct al_pcie_rev2_w_soc_int {
	+ /* [0x0] */
	+ uint32_t status_0;
	+ /* [0x4] */
	+ uint32_t status_1;
	+ /* [0x8] */
	+ uint32_t status_2;
	+ /* [0xc] */
	+ uint32_t status_3;
	+ /* [0x10] */
	+ uint32_t mask_inta_leg_0;
	+ /* [0x14] */
	+ uint32_t mask_inta_leg_1;
	+ /* [0x18] */
	+ uint32_t mask_inta_leg_2;
	+ /* [0x1c] */
	+ uint32_t mask_inta_leg_3;
	+ /* [0x20] */
	+ uint32_t mask_msi_leg_0;
	+ /* [0x24] */
	+ uint32_t mask_msi_leg_1;
	+ /* [0x28] */
	+ uint32_t mask_msi_leg_2;
	+ /* [0x2c] */
	+ uint32_t mask_msi_leg_3;
	+ /* [0x30] */
	+ uint32_t msi_leg_cntl;
	+};
	+struct al_pcie_rev3_w_soc_int_per_func {
	+ /* [0x0] */
	+ uint32_t status_0;
	+ /* [0x4] */
	+ uint32_t status_1;
	+ /* [0x8] */
	+ uint32_t status_2;
	+ /* [0xc] */
	+ uint32_t status_3;
	+ /* [0x10] */
	+ uint32_t mask_inta_leg_0;
	+ /* [0x14] */
	+ uint32_t mask_inta_leg_1;
	+ /* [0x18] */
	+ uint32_t mask_inta_leg_2;
	+ /* [0x1c] */
	+ uint32_t mask_inta_leg_3;
	+ /* [0x20] */
	+ uint32_t mask_msi_leg_0;
	+ /* [0x24] */
	+ uint32_t mask_msi_leg_1;
	+ /* [0x28] */
	+ uint32_t mask_msi_leg_2;
	+ /* [0x2c] */
	+ uint32_t mask_msi_leg_3;
	+ /* [0x30] */
	+ uint32_t msi_leg_cntl;
	+};
	+
	+struct al_pcie_revx_w_ap_err {
	+ /*
	+ * [0x0] latch the header in case of any error occur in the core, read
	+ * on clear of the last register in the bind.
	+ */
	+ uint32_t hdr_log;
	+};
	+struct al_pcie_revx_w_status_per_func {
	+ /*
	+ * [0x0] latch the header in case of any error occure in the core, read
	+ * on clear of the last register in the bind.
	+ */
	+ uint32_t status_per_func;
	+};
	+struct al_pcie_revx_w_int_grp {
	+ /*
	+ * [0x0] Interrupt Cause Register
	+ * Set by hardware
	+ * - If MSI-X is enabled and auto_clear control bit =TRUE, automatically
	+ * cleared after MSI-X message associated with this specific interrupt
	+ * bit is sent (MSI-X acknowledge is received).
	+ * - Software can set a bit in this register by writing 1 to the
	+ * associated bit in the Interrupt Cause Set register
	+ * Write-0 clears a bit. Write-1 has no effect.
	+ * - On CPU Read - If clear_on_read control bit =TRUE, automatically
	+ * cleared (all bits are cleared).
	+ * When there is a conflict and on the same clock cycle, hardware tries
	+ * to set a bit in the Interrupt Cause register, the specific bit is set
	+ * to ensure the interrupt indication is not lost.
	+ */
	+ uint32_t cause;
	+ uint32_t rsrvd_0;
	+ /*
	+ * [0x8] Interrupt Cause Set Register
	+ * Writing 1 to a bit in this register sets its corresponding cause bit,
	+ * enabling software to generate a hardware interrupt. Write 0 has no
	+ * effect.
	+ */
	+ uint32_t cause_set;
	+ uint32_t rsrvd_1;
	+ /*
	+ * [0x10] Interrupt Mask Register
	+ * If Auto-mask control bit =TRUE, automatically set to 1 after MSI-X
	+ * message associatd with the associated interrupt bit is sent (AXI
	+ * write acknowledge is received).
	+ */
	+ uint32_t mask;
	+ uint32_t rsrvd_2;
	+ /*
	+ * [0x18] Interrupt Mask Clear Register
	+ * Used when auto-mask control bit=True. Enables CPU to clear a specific
	+ * bit. It prevents a scenario in which the CPU overrides another bit
	+ * with 1 (old value) that hardware has just cleared to 0.
	+ * Write 0 to this register clears its corresponding mask bit. Write 1
	+ * has no effect.
	+ */
	+ uint32_t mask_clear;
	+ uint32_t rsrvd_3;
	+ /*
	+ * [0x20] Interrupt Status Register
	+ * This register latches the status of the interrupt source.
	+ */
	+ uint32_t status;
	+ uint32_t rsrvd_4;
	+ /* [0x28] Interrupt Control Register */
	+ uint32_t control;
	+ uint32_t rsrvd_5;
	+ /*
	+ * [0x30] Interrupt Mask Register
	+ * Each bit in this register masks the corresponding cause bit for
	+ * generating an Abort signal. Its default value is determined by unit
	+ * instantiation.
	+ * (Abort = Wire-OR of Cause & !Interrupt_Abort_Mask)
	+ * This register provides error handling configuration for error
	+ * interrupts
	+ */
	+ uint32_t abort_mask;
	+ uint32_t rsrvd_6;
	+ /*
	+ * [0x38] Interrupt Log Register
	+ * Each bit in this register masks the corresponding cause bit for
	+ * capturing the log registers. Its default value is determined by unit
	+ * instantiation.
	+ * (Log_capture = Wire-OR of Cause & !Interrupt_Log_Mask)
	+ * This register provides error handling configuration for error
	+ * interrupts.
	+ */
	+ uint32_t log_mask;
	+ uint32_t rsrvd;
	+};
	+
	+struct al_pcie_rev1_w_regs {
	+ struct al_pcie_rev1_w_global_ctrl global_ctrl; /* [0x0] */
	+ uint32_t rsrvd_0[24];
	+ struct al_pcie_revx_w_debug debug; /* [0x80] */
	+ struct al_pcie_revx_w_ob_ven_msg ob_ven_msg; /* [0x90] */
	+ uint32_t rsrvd_1[86];
	+ struct al_pcie_rev1_w_soc_int soc_int; /* [0x200] */
	+ struct al_pcie_revx_w_link_down link_down; /* [0x228] */
	+ struct al_pcie_revx_w_cntl_gen ctrl_gen; /* [0x230] */
	+ struct al_pcie_revx_w_parity parity; /* [0x234] */
	+ struct al_pcie_revx_w_last_wr last_wr; /* [0x23c] */
	+ struct al_pcie_rev1_2_w_atu atu; /* [0x240] */
	+ uint32_t rsrvd_2[36];
	+ struct al_pcie_revx_w_int_grp int_grp_a_m0; /* [0x300] */
	+ struct al_pcie_revx_w_int_grp int_grp_b_m0; /* [0x340] */
	+ uint32_t rsrvd_3[32];
	+ struct al_pcie_revx_w_int_grp int_grp_a; /* [0x400] */
	+ struct al_pcie_revx_w_int_grp int_grp_b; /* [0x440] */
	+};
	+
	+struct al_pcie_rev2_w_regs {
	+ struct al_pcie_rev2_w_global_ctrl global_ctrl; /* [0x0] */
	+ uint32_t rsrvd_0[24];
	+ struct al_pcie_revx_w_debug debug; /* [0x80] */
	+ struct al_pcie_revx_w_ob_ven_msg ob_ven_msg; /* [0x90] */
	+ struct al_pcie_revx_w_ap_user_send_msg ap_user_send_msg; /* [0xa8] */
	+ uint32_t rsrvd_1[20];
	+ struct al_pcie_rev2_w_soc_int soc_int; /* [0x100] */
	+ uint32_t rsrvd_2[61];
	+ struct al_pcie_revx_w_link_down link_down; /* [0x228] */
	+ struct al_pcie_revx_w_cntl_gen ctrl_gen; /* [0x230] */
	+ struct al_pcie_revx_w_parity parity; /* [0x234] */
	+ struct al_pcie_revx_w_last_wr last_wr; /* [0x23c] */
	+ struct al_pcie_rev1_2_w_atu atu; /* [0x240] */
	+ uint32_t rsrvd_3[6];
	+ struct al_pcie_revx_w_ap_err ap_err[4]; /* [0x288] */
	+ uint32_t rsrvd_4[26];
	+ struct al_pcie_revx_w_status_per_func status_per_func; /* [0x300] */
	+ uint32_t rsrvd_5[63];
	+ struct al_pcie_revx_w_int_grp int_grp_a; /* [0x400] */
	+ struct al_pcie_revx_w_int_grp int_grp_b; /* [0x440] */
	+};
	+
	+struct al_pcie_rev3_w_regs {
	+ struct al_pcie_rev3_w_global_ctrl global_ctrl; /* [0x0] */
	+ uint32_t rsrvd_0[24];
	+ struct al_pcie_revx_w_debug debug; /* [0x80] */
	+ struct al_pcie_revx_w_ob_ven_msg ob_ven_msg; /* [0x90] */
	+ struct al_pcie_revx_w_ap_user_send_msg ap_user_send_msg; /* [0xa8] */
	+ uint32_t rsrvd_1[94];
	+ struct al_pcie_revx_w_link_down link_down; /* [0x228] */
	+ struct al_pcie_revx_w_cntl_gen ctrl_gen; /* [0x230] */
	+ struct al_pcie_revx_w_parity parity; /* [0x234] */
	+ struct al_pcie_revx_w_last_wr last_wr; /* [0x23c] */
	+ struct al_pcie_rev3_w_atu atu; /* [0x240] */
	+ uint32_t rsrvd_2[8];
	+ struct al_pcie_rev3_w_cfg_func_ext cfg_func_ext; /* [0x2e0] */
	+ struct al_pcie_rev3_w_app_hdr_interface_send app_hdr_interface_send;/* [0x2e4] */
	+ struct al_pcie_rev3_w_diag_command diag_command; /* [0x300] */
	+ uint32_t rsrvd_3[3];
	+ struct al_pcie_rev3_w_soc_int_per_func soc_int_per_func[REV3_MAX_NUM_OF_PFS]; /* [0x310] */
	+ uint32_t rsrvd_4[44];
	+ struct al_pcie_rev3_w_events_gen_per_func events_gen_per_func[REV3_MAX_NUM_OF_PFS]; /* [0x490] */
	+ uint32_t rsrvd_5[4];
	+ struct al_pcie_rev3_w_pm_state_per_func pm_state_per_func[REV3_MAX_NUM_OF_PFS];/* [0x4b0] */
	+ uint32_t rsrvd_6[16];
	+ struct al_pcie_rev3_w_cfg_bars_ovrd cfg_bars_ovrd[REV3_MAX_NUM_OF_PFS]; /* [0x500] */
	+ uint32_t rsrvd_7[176];
	+ uint32_t rsrvd_8[16];
	+ struct al_pcie_revx_w_ap_err ap_err[5]; /* [0xac0] */
	+ uint32_t rsrvd_9[11];
	+ struct al_pcie_revx_w_status_per_func status_per_func[4]; /* [0xb00] */
	+ uint32_t rsrvd_10[316];
	+ struct al_pcie_revx_w_int_grp int_grp_a; /* [0x1000] */
	+ struct al_pcie_revx_w_int_grp int_grp_b; /* [0x1040] */
	+ struct al_pcie_revx_w_int_grp int_grp_c; /* [0x1080] */
	+ struct al_pcie_revx_w_int_grp int_grp_d; /* [0x10c0] */
	+};
	+
	+/*
	+* Registers Fields
	+*/
	+
	+
	+/** Port_Init register **/
	+/* Enable port to start LTSSM Link Training */
	+#define PCIE_W_GLOBAL_CTRL_PORT_INIT_APP_LTSSM_EN_MASK (1 << 0)
	+#define PCIE_W_GLOBAL_CTRL_PORT_INIT_APP_LTSSM_EN_SHIFT (0)
	+/*
	+ * Device Type
	+ * Indicates the specific type of this PCIe Function. It is also used to set the
	+ * Device/Port Type field.
	+ * 4'b0000: PCIe Endpoint
	+ * 4'b0001: Legacy PCIe Endpoint
	+ * 4'b0100: Root Port of PCIe Root Complex
	+ * Must be programmed before link training sequence. According to the reset
	+ * strap
	+ */
	+#define PCIE_W_GLOBAL_CTRL_PORT_INIT_DEVICE_TYPE_MASK 0x000000F0
	+#define PCIE_W_GLOBAL_CTRL_PORT_INIT_DEVICE_TYPE_SHIFT 4
	+/*
	+ * Performs Manual Lane reversal for transmit Lanes.
	+ * Must be programmed before link training sequence.
	+ */
	+#define PCIE_W_GLOBAL_CTRL_PORT_INIT_TX_LANE_FLIP_EN (1 << 8)
	+/*
	+ * Performs Manual Lane reversal for receive Lanes.
	+ * Must be programmed before link training sequence.
	+ */
	+#define PCIE_W_GLOBAL_CTRL_PORT_INIT_RX_LANE_FLIP_EN (1 << 9)
	+/*
	+ * Auxiliary Power Detected
	+ * Indicates that auxiliary power (Vaux) is present. This one move to reset
	+ * strap from
	+ */
	+#define PCIE_W_GLOBAL_CTRL_PORT_INIT_SYS_AUX_PWR_DET_NOT_USE (1 << 10)
	+
	+/** Port_Status register **/
	+/* PHY Link up/down indicator */
	+#define PCIE_W_GLOBAL_CTRL_PORT_STS_PHY_LINK_UP (1 << 0)
	+/*
	+ * Data Link Layer up/down indicator
	+ * This status from the Flow Control Initialization State Machine indicates that
	+ * Flow Control has been initiated and the Data Link Layer is ready to transmit
	+ * and receive packets.
	+ */
	+#define PCIE_W_GLOBAL_CTRL_PORT_STS_DL_LINK_UP (1 << 1)
	+/* Reset request due to link down status. */
	+#define PCIE_W_GLOBAL_CTRL_PORT_STS_LINK_REQ_RST (1 << 2)
	+/* Power management is in L0s state.. */
	+#define PCIE_W_GLOBAL_CTRL_PORT_STS_PM_LINKST_IN_L0S (1 << 3)
	+/* Power management is in L1 state. */
	+#define PCIE_W_GLOBAL_CTRL_PORT_STS_PM_LINKST_IN_L1 (1 << 4)
	+/* Power management is in L2 state. */
	+#define PCIE_W_GLOBAL_CTRL_PORT_STS_PM_LINKST_IN_L2 (1 << 5)
	+/* Power management is exiting L2 state. */
	+#define PCIE_W_GLOBAL_CTRL_PORT_STS_PM_LINKST_L2_EXIT (1 << 6)
	+/* Power state of the device. */
	+#define PCIE_W_GLOBAL_CTRL_PORT_STS_PM_DSTATE_MASK 0x00000380
	+#define PCIE_W_GLOBAL_CTRL_PORT_STS_PM_DSTATE_SHIFT 7
	+/* tie to zero. */
	+#define PCIE_W_GLOBAL_CTRL_PORT_STS_XMLH_IN_RL0S (1 << 10)
	+/* Timeout count before flush */
	+#define PCIE_W_GLOBAL_CTRL_PORT_STS_LINK_TOUT_FLUSH_NOT (1 << 11)
	+/* Segmentation buffer not empty */
	+#define PCIE_W_GLOBAL_CTRL_PORT_STS_RADM_Q_NOT_EMPTY (1 << 12)
	+/*
	+ * Clock Turnoff Request
	+ * Allows clock generation module to turn off core_clk based on the current
	+ * power management state:
	+ * 0: core_clk is required to be active for the current power state.
	+ * 1: The current power state allows core_clk to be shut down.
	+ * This does not indicate the clock requirement for the PHY.
	+ */
	+#define PCIE_W_GLOBAL_CTRL_PORT_STS_CORE_CLK_REQ_N (1 << 31)
	+
	+/** PM_Control register **/
	+/*
	+ * Wake Up. Used by application logic to wake up the PMC state machine from a
	+ * D1, D2, or D3 power state. EP mode only. Change the value from 0 to 1 to send
	+ * the message. Per function the upper bits are not use for ocie core less than
	+ * 8 functions
	+ */
	+#define PCIE_W_REV1_2_GLOBAL_CTRL_PM_CONTROL_PM_XMT_PME (1 << 0)
	+#define PCIE_W_REV3_GLOBAL_CTRL_PM_CONTROL_PM_XMT_PME_FUNC_MASK 0x000000FF
	+#define PCIE_W_REV3_GLOBAL_CTRL_PM_CONTROL_PM_XMT_PME_FUNC_SHIFT 0
	+/*
	+ * Request to Enter ASPM L1.
	+ * The core ignores the L1 entry request on app_req_entr_l1 when it is busy
	+ * processing a transaction.
	+ */
	+#define PCIE_W_REV1_2_GLOBAL_CTRL_PM_CONTROL_REQ_ENTR_L1 (1 << 3)
	+#define PCIE_W_REV3_GLOBAL_CTRL_PM_CONTROL_REQ_ENTR_L1 (1 << 8)
	+/*
	+ * Request to exit ASPM L1.
	+ * Only effective if L1 is enabled.
	+ */
	+#define PCIE_W_REV1_2_GLOBAL_CTRL_PM_CONTROL_REQ_EXIT_L1 (1 << 4)
	+#define PCIE_W_REV3_GLOBAL_CTRL_PM_CONTROL_REQ_EXIT_L1 (1 << 9)
	+/*
	+ * Indication that component is ready to enter the L23 state. The core delays
	+ * sending PM_Enter_L23 (in response to PM_Turn_Off) until this signal becomes
	+ * active.
	+ * EP mode
	+ */
	+#define PCIE_W_REV1_2_GLOBAL_CTRL_PM_CONTROL_READY_ENTR_L23 (1 << 5)
	+#define PCIE_W_REV3_GLOBAL_CTRL_PM_CONTROL_READY_ENTR_L23 (1 << 10)
	+/*
	+ * Request to generate a PM_Turn_Off Message to communicate transition to L2/L3
	+ * Ready state to downstream components. Host must wait PM_Turn_Off_Ack messages
	+ * acceptance RC mode.
	+ */
	+#define PCIE_W_REV1_2_GLOBAL_CTRL_PM_CONTROL_PM_XMT_TURNOFF (1 << 6)
	+#define PCIE_W_REV3_GLOBAL_CTRL_PM_CONTROL_PM_XMT_TURNOFF (1 << 11)
	+/*
	+ * Provides a capability to defer incoming Configuration Requests until
	+ * initialization is complete. When app_req_retry_en is asserted, the core
	+ * completes incoming Configuration Requests with a Configuration Request Retry
	+ * Status. Other incoming Requests complete with Unsupported Request status.
	+ */
	+#define PCIE_W_REV1_2_GLOBAL_CTRL_PM_CONTROL_APP_REQ_RETRY_EN (1 << 7)
	+#define PCIE_W_REV3_GLOBAL_CTRL_PM_CONTROL_APP_REQ_RETRY_EN (1 << 12)
	+/*
	+ * Core core gate enable
	+ * If set, core_clk is gated off whenever a clock turnoff request allows the
	+ * clock generation module to turn off core_clk (Port_Status.core_clk_req_n
	+ * field), and the PHY supports a request to disable clock gating. If not, the
	+ * core clock turns off in P2 mode in any case (PIPE).
	+ */
	+#define PCIE_W_GLOBAL_CTRL_PM_CONTROL_CORE_CLK_GATE (1 << 31)
	+
	+/** sris_kp_counter_value register **/
	+/* skp counter when SRIS disable */
	+#define PCIE_W_GLOBAL_CTRL_SRIS_KP_COUNTER_VALUE_GEN3_NO_SRIS_MASK 0x000001FF
	+#define PCIE_W_GLOBAL_CTRL_SRIS_KP_COUNTER_VALUE_GEN3_NO_SRIS_SHIFT 0
	+/* skp counter when SRIS enable */
	+#define PCIE_W_GLOBAL_CTRL_SRIS_KP_COUNTER_VALUE_GEN3_SRIS_MASK 0x0003FE00
	+#define PCIE_W_GLOBAL_CTRL_SRIS_KP_COUNTER_VALUE_GEN3_SRIS_SHIFT 9
	+/* skp counter when SRIS enable for gen3 */
	+#define PCIE_W_GLOBAL_CTRL_SRIS_KP_COUNTER_VALUE_GEN21_SRIS_MASK 0x1FFC0000
	+#define PCIE_W_GLOBAL_CTRL_SRIS_KP_COUNTER_VALUE_GEN21_SRIS_SHIFT 18
	+/* mask the interrupt to the soc in case correctable error occur in the ARI. */
	+#define PCIE_W_GLOBAL_CTRL_SRIS_KP_COUNTER_VALUE_RSRVD_MASK 0x60000000
	+#define PCIE_W_GLOBAL_CTRL_SRIS_KP_COUNTER_VALUE_RSRVD_SHIFT 29
	+/* not in use in the pcie_x8 core. */
	+#define PCIE_W_GLOBAL_CTRL_SRIS_KP_COUNTER_VALUE_PCIE_X4_SRIS_EN (1 << 31)
	+
	+/** Events_Gen register **/
	+/* INT_D. Not supported */
	+#define PCIE_W_GLOBAL_CTRL_EVENTS_GEN_ASSERT_INTD (1 << 0)
	+/* INT_C. Not supported */
	+#define PCIE_W_GLOBAL_CTRL_EVENTS_GEN_ASSERT_INTC (1 << 1)
	+/* INT_B. Not supported */
	+#define PCIE_W_GLOBAL_CTRL_EVENTS_GEN_ASSERT_INTB (1 << 2)
	+/* Transmit INT_A Interrupt ControlEvery transition from 0 to 1 ... */
	+#define PCIE_W_GLOBAL_CTRL_EVENTS_GEN_ASSERT_INTA (1 << 3)
	+/* A request to generate an outbound MSI interrupt when MSI is e ... */
	+#define PCIE_W_GLOBAL_CTRL_EVENTS_GEN_MSI_TRNS_REQ (1 << 4)
	+/* Set the MSI vector before issuing msi_trans_req. */
	+#define PCIE_W_GLOBAL_CTRL_EVENTS_GEN_MSI_VECTOR_MASK 0x000003E0
	+#define PCIE_W_GLOBAL_CTRL_EVENTS_GEN_MSI_VECTOR_SHIFT 5
	+/* The application requests hot reset to a downstream device */
	+#define PCIE_W_GLOBAL_CTRL_EVENTS_GEN_APP_RST_INIT (1 << 10)
	+/* The application request unlock message to be sent */
	+#define PCIE_W_GLOBAL_CTRL_EVENTS_GEN_UNLOCK_GEN (1 << 30)
	+/* Indicates that FLR on a Physical Function has been completed */
	+#define PCIE_W_GLOBAL_CTRL_EVENTS_GEN_FLR_PF_DONE (1 << 31)
	+
	+/** Cpl_TO_Info register **/
	+/* The Traffic Class of the timed out CPL */
	+#define PCIE_W_LCL_LOG_CPL_TO_INFO_TC_MASK 0x00000003
	+#define PCIE_W_LCL_LOG_CPL_TO_INFO_TC_SHIFT 0
	+/* Indicates which Virtual Function (VF) had a CPL timeout */
	+#define PCIE_W_LCL_LOG_CPL_TO_INFO_FUN_NUM_MASK 0x000000FC
	+#define PCIE_W_LCL_LOG_CPL_TO_INFO_FUN_NUM_SHIFT 2
	+/* The Tag field of the timed out CPL */
	+#define PCIE_W_LCL_LOG_CPL_TO_INFO_TAG_MASK 0x0000FF00
	+#define PCIE_W_LCL_LOG_CPL_TO_INFO_TAG_SHIFT 8
	+/* The Attributes field of the timed out CPL */
	+#define PCIE_W_LCL_LOG_CPL_TO_INFO_ATTR_MASK 0x00030000
	+#define PCIE_W_LCL_LOG_CPL_TO_INFO_ATTR_SHIFT 16
	+/* The Len field of the timed out CPL */
	+#define PCIE_W_LCL_LOG_CPL_TO_INFO_LEN_MASK 0x3FFC0000
	+#define PCIE_W_LCL_LOG_CPL_TO_INFO_LEN_SHIFT 18
	+/*
	+ * Write 1 to this field to clear the information logged in the register. New
	+ * logged information will only be valid when the interrupt is cleared .
	+ */
	+#define PCIE_W_LCL_LOG_CPL_TO_INFO_VALID (1 << 31)
	+#define PCIE_W_LCL_LOG_CPL_TO_INFO_VALID_SHIFT (31)
	+
	+/** Rcv_Msg0_0 register **/
	+/* The Requester ID of the received message */
	+#define PCIE_W_LCL_LOG_RCV_MSG0_0_REQ_ID_MASK 0x0000FFFF
	+#define PCIE_W_LCL_LOG_RCV_MSG0_0_REQ_ID_SHIFT 0
	+/*
	+ * Valid logged message
	+ * Writing 1 to this bit enables new message capturing. Write one to clear
	+ */
	+#define PCIE_W_LCL_LOG_RCV_MSG0_0_VALID (1 << 31)
	+
	+/** Rcv_Msg1_0 register **/
	+/* The Requester ID of the received message */
	+#define PCIE_W_LCL_LOG_RCV_MSG1_0_REQ_ID_MASK 0x0000FFFF
	+#define PCIE_W_LCL_LOG_RCV_MSG1_0_REQ_ID_SHIFT 0
	+/*
	+ * Valid logged message
	+ * Writing 1 to this bit enables new message capturing. Write one to clear
	+ */
	+#define PCIE_W_LCL_LOG_RCV_MSG1_0_VALID (1 << 31)
	+
	+/** Core_Queues_Status register **/
	+/*
	+ * Indicates which entries in the CPL lookup table
	+ * have valid entries stored. NOT supported.
	+ */
	+#define PCIE_W_LCL_LOG_CORE_Q_STATUS_CPL_LUT_VALID_MASK 0x0000FFFF
	+#define PCIE_W_LCL_LOG_CORE_Q_STATUS_CPL_LUT_VALID_SHIFT 0
	+
	+/** Cpl_to register **/
	+#define PCIE_W_LCL_LOG_CPL_TO_REQID_MASK 0x0000FFFF
	+#define PCIE_W_LCL_LOG_CPL_TO_REQID_SHIFT 0
	+
	+/** Debug_Info_0 register **/
	+/* Indicates the current power state */
	+#define PCIE_W_DEBUG_INFO_0_PM_CURRENT_STATE_MASK 0x00000007
	+#define PCIE_W_DEBUG_INFO_0_PM_CURRENT_STATE_SHIFT 0
	+/* Current state of the LTSSM */
	+#define PCIE_W_DEBUG_INFO_0_LTSSM_STATE_MASK 0x000001F8
	+#define PCIE_W_DEBUG_INFO_0_LTSSM_STATE_SHIFT 3
	+/* Decode of the Recovery. Equalization LTSSM state */
	+#define PCIE_W_DEBUG_INFO_0_LTSSM_STATE_RCVRY_EQ (1 << 9)
	+/* State of selected internal signals, for debug purposes only */
	+#define PCIE_W_DEBUG_INFO_0_CXPL_DEBUG_INFO_EI_MASK 0x03FFFC00
	+#define PCIE_W_DEBUG_INFO_0_CXPL_DEBUG_INFO_EI_SHIFT 10
	+
	+/** control register **/
	+/* Indication to send vendor message; when clear the message was sent. */
	+#define PCIE_W_OB_VEN_MSG_CONTROL_REQ (1 << 0)
	+
	+/** param_1 register **/
	+/* Vendor message parameters */
	+#define PCIE_W_OB_VEN_MSG_PARAM_1_FMT_MASK 0x00000003
	+#define PCIE_W_OB_VEN_MSG_PARAM_1_FMT_SHIFT 0
	+/* Vendor message parameters */
	+#define PCIE_W_OB_VEN_MSG_PARAM_1_TYPE_MASK 0x0000007C
	+#define PCIE_W_OB_VEN_MSG_PARAM_1_TYPE_SHIFT 2
	+/* Vendor message parameters */
	+#define PCIE_W_OB_VEN_MSG_PARAM_1_TC_MASK 0x00000380
	+#define PCIE_W_OB_VEN_MSG_PARAM_1_TC_SHIFT 7
	+/* Vendor message parameters */
	+#define PCIE_W_OB_VEN_MSG_PARAM_1_TD (1 << 10)
	+/* Vendor message parameters */
	+#define PCIE_W_OB_VEN_MSG_PARAM_1_EP (1 << 11)
	+/* Vendor message parameters */
	+#define PCIE_W_OB_VEN_MSG_PARAM_1_ATTR_MASK 0x00003000
	+#define PCIE_W_OB_VEN_MSG_PARAM_1_ATTR_SHIFT 12
	+/* Vendor message parameters */
	+#define PCIE_W_OB_VEN_MSG_PARAM_1_LEN_MASK 0x00FFC000
	+#define PCIE_W_OB_VEN_MSG_PARAM_1_LEN_SHIFT 14
	+/* Vendor message parameters */
	+#define PCIE_W_OB_VEN_MSG_PARAM_1_TAG_MASK 0xFF000000
	+#define PCIE_W_OB_VEN_MSG_PARAM_1_TAG_SHIFT 24
	+
	+/** param_2 register **/
	+/* Vendor message parameters */
	+#define PCIE_W_OB_VEN_MSG_PARAM_2_REQ_ID_MASK 0x0000FFFF
	+#define PCIE_W_OB_VEN_MSG_PARAM_2_REQ_ID_SHIFT 0
	+/* Vendor message parameters */
	+#define PCIE_W_OB_VEN_MSG_PARAM_2_CODE_MASK 0x00FF0000
	+#define PCIE_W_OB_VEN_MSG_PARAM_2_CODE_SHIFT 16
	+/* Vendor message parameters */
	+#define PCIE_W_OB_VEN_MSG_PARAM_2_RSVD_31_24_MASK 0xFF000000
	+#define PCIE_W_OB_VEN_MSG_PARAM_2_RSVD_31_24_SHIFT 24
	+
	+/** ack_info register **/
	+/* Vendor message parameters */
	+#define PCIE_W_AP_USER_SEND_MSG_ACK_INFO_ACK (1 << 0)
	+
	+/** features register **/
	+/* Enable MSI fix from the SATA to the PCIe EP - Only valid for port zero */
	+#define PCIE_W_CTRL_GEN_FEATURES_SATA_EP_MSI_FIX AL_BIT(16)
	+
	+/** in/out_mask_x_y register **/
	+/* When bit [i] set to 1 it maks the compare in the atu_in/out wind ... */
	+#define PCIE_W_ATU_MASK_EVEN_ODD_ATU_MASK_40_32_EVEN_MASK 0x0000FFFF
	+#define PCIE_W_ATU_MASK_EVEN_ODD_ATU_MASK_40_32_EVEN_SHIFT 0
	+/* When bit [i] set to 1 it maks the compare in the atu_in/out wind ... */
	+#define PCIE_W_ATU_MASK_EVEN_ODD_ATU_MASK_40_32_ODD_MASK 0xFFFF0000
	+#define PCIE_W_ATU_MASK_EVEN_ODD_ATU_MASK_40_32_ODD_SHIFT 16
	+
	+/** cfg register **/
	+/*
	+ * The 2-bit TPH Requester Enabled field of each TPH
	+ * Requester Control register.
	+ */
	+#define PCIE_W_CFG_FUNC_EXT_CFG_CFG_TPH_REQ_EN_MASK 0x000000FF
	+#define PCIE_W_CFG_FUNC_EXT_CFG_CFG_TPH_REQ_EN_SHIFT 0
	+/* SRIS mode enable. */
	+#define PCIE_W_CFG_FUNC_EXT_CFG_APP_SRIS_MODE (1 << 8)
	+/*
	+ *
	+ */
	+#define PCIE_W_CFG_FUNC_EXT_CFG_RSRVD_MASK 0xFFFFFE00
	+#define PCIE_W_CFG_FUNC_EXT_CFG_RSRVD_SHIFT 9
	+
	+/** app_func_num_advisory register **/
	+/*
	+ * The number of the function that is reporting the error
	+ * indicated app_err_bus, valid when app_hdr_valid is asserted.
	+ * Correctable and Uncorrected Internal errors (app_err_bus[10:9]) are
	+ * not function specific, and are recorded for all physical functions,
	+ * regardless of the value this bus. Function numbering starts at '0'.
	+ */
	+#define PCIE_W_APP_HDR_INTERFACE_SEND_APP_FUNC_NUM_ADVISORY_APP_ERR_FUNC_NUM_MASK 0x0000FFFF
	+#define PCIE_W_APP_HDR_INTERFACE_SEND_APP_FUNC_NUM_ADVISORY_APP_ERR_FUNC_NUM_SHIFT 0
	+/*
	+ * Description: Indicates that your application error is an advisory
	+ * error. Your application should assert app_err_advisory under either
	+ * of the following conditions:
	+ * - The core is configured to mask completion timeout errors, your
	+ * application is reporting a completion timeout error app_err_bus,
	+ * and your application intends to resend the request. In such cases
	+ * the error is an advisory error, as described in PCI Express 3.0
	+ * Specification. When your application does not intend to resend
	+ * the request, then your application must keep app_err_advisory
	+ * de-asserted when reporting a completion timeout error.
	+ * - The core is configured to forward poisoned TLPs to your
	+ * application and your application is going to treat the poisoned
	+ * TLP as a normal TLP, as described in PCI Express 3.0
	+ * Specification. Upon receipt of a poisoned TLP, your application
	+ * must report the error app_err_bus, and either assert
	+ * app_err_advisory (to indicate an advisory error) or de-assert
	+ * app_err_advisory (to indicate that your application is dropping the
	+ * TLP).
	+ * For more details, see the PCI Express 3.0 Specification to determine
	+ * when an application error is an advisory error.
	+ */
	+#define PCIE_W_APP_HDR_INTERFACE_SEND_APP_FUNC_NUM_ADVISORY_APP_ERR_ADVISORY (1 << 16)
	+/*
	+ * Rsrvd.
	+ */
	+#define PCIE_W_APP_HDR_INTERFACE_SEND_APP_FUNC_NUM_ADVISORY_RSRVD_MASK 0xFFFE0000
	+#define PCIE_W_APP_HDR_INTERFACE_SEND_APP_FUNC_NUM_ADVISORY_RSRVD_SHIFT 17
	+
	+/** app_hdr_cmd register **/
	+/*
	+ * When set the header is send (need to clear before sending the next message).
	+ */
	+#define PCIE_W_APP_HDR_INTERFACE_SEND_APP_HDR_CMD_APP_HDR_VALID (1 << 0)
	+/*
	+ * Rsrvd.
	+ */
	+#define PCIE_W_APP_HDR_INTERFACE_SEND_APP_HDR_CMD_RSRVD_MASK 0xFFFFFFFE
	+#define PCIE_W_APP_HDR_INTERFACE_SEND_APP_HDR_CMD_RSRVD_SHIFT 1
	+
	+/** diag_ctrl register **/
	+/*
	+ * The 2-bit TPH Requester Enabled field of each TPH
	+ * Requester Control register.
	+ */
	+#define PCIE_W_DIAG_COMMAND_DIAG_CTRL_DIAG_CTRL_BUS_MASK 0x00000007
	+#define PCIE_W_DIAG_COMMAND_DIAG_CTRL_DIAG_CTRL_BUS_SHIFT 0
	+/*
	+ *
	+ */
	+#define PCIE_W_DIAG_COMMAND_DIAG_CTRL_RSRVD_MASK 0xFFFFFFF8
	+#define PCIE_W_DIAG_COMMAND_DIAG_CTRL_RSRVD_SHIFT 3
	+
	+
	+/** Events_Gen register **/
	+/* INT_D. Not supported */
	+#define PCIE_W_GLOBAL_CTRL_EVENTS_GEN_ASSERT_INTD (1 << 0)
	+/* INT_C. Not supported */
	+#define PCIE_W_GLOBAL_CTRL_EVENTS_GEN_ASSERT_INTC (1 << 1)
	+/* INT_B. Not supported */
	+#define PCIE_W_GLOBAL_CTRL_EVENTS_GEN_ASSERT_INTB (1 << 2)
	+/*
	+ * Transmit INT_A Interrupt Control
	+ * Every transition from 0 to 1 schedules an Assert_ INT interrupt message for
	+ * transmit.
	+ * Every transition from 1 to 0, schedules a Deassert_INT interrupt message for
	+ * transmit. Which interrupt, the PCIe only use INTA message.
	+ */
	+#define PCIE_W_GLOBAL_CTRL_EVENTS_GEN_ASSERT_INTA (1 << 3)
	+/*
	+ * A request to generate an outbound MSI interrupt when MSI is enabled. Change
	+ * from 1'b0 to 1'b1 to create an MSI write to be sent.
	+ */
	+#define PCIE_W_GLOBAL_CTRL_EVENTS_GEN_MSI_TRNS_REQ (1 << 4)
	+/* Set the MSI vector before issuing msi_trans_req. */
	+#define PCIE_W_GLOBAL_CTRL_EVENTS_GEN_MSI_VECTOR_MASK 0x000003E0
	+#define PCIE_W_GLOBAL_CTRL_EVENTS_GEN_MSI_VECTOR_SHIFT 5
	+/*
	+ * The application requests hot reset to a downstream device. Change the value
	+ * from 0 to 1 to send hot reset. Only func 0 is supported.
	+ */
	+#define PCIE_W_GLOBAL_CTRL_EVENTS_GEN_APP_RST_INIT (1 << 10)
	+/*
	+ * The application request unlock message to be sent. Change the value from 0 to
	+ * 1 to send the message. Only func 0 is supported.
	+ */
	+#define PCIE_W_GLOBAL_CTRL_EVENTS_GEN_UNLOCK_GEN (1 << 30)
	+/* Indicates that FLR on a Physical Function has been completed. */
	+#define PCIE_W_GLOBAL_CTRL_EVENTS_GEN_FLR_PF_DONE (1 << 31)
	+
	+/** pm_state_per_func register **/
	+/*
	+ * Description: The current power management D-state of the
	+ * function:
	+ * \u25a0 000b: D0
	+ * \u25a0 001b: D1
	+ * \u25a0 010b: D2
	+ * \u25a0 011b: D3
	+ * \u25a0 100b: Uninitialized
	+ * \u25a0 Other values: Not applicable
	+ * There are 3 bits of pm_dstate for each configured function.
	+ */
	+#define PCIE_W_PM_STATE_PER_FUNC_PM_STATE_PER_FUNC_PM_DSTATE_MASK 0x0000000F
	+#define PCIE_W_PM_STATE_PER_FUNC_PM_STATE_PER_FUNC_PM_DSTATE_SHIFT 0
	+/*
	+ * PME Status bit from the PMCSR. There is 1 bit of
	+ * pm_status for each configured function
	+ */
	+#define PCIE_W_PM_STATE_PER_FUNC_PM_STATE_PER_FUNC_PM_STATUS (1 << 4)
	+/*
	+ * PME Enable bit in the PMCSR. There is 1 bit of
	+ * pm_pme_en for each configured function.
	+ */
	+#define PCIE_W_PM_STATE_PER_FUNC_PM_STATE_PER_FUNC_PM_PME_EN (1 << 5)
	+/*
	+ * Auxiliary Power Enable bit in the Device Control
	+ * register. There is 1 bit of aux_pm_en for each configured function.
	+ */
	+#define PCIE_W_PM_STATE_PER_FUNC_PM_STATE_PER_FUNC_AUX_PME_EN (1 << 6)
	+/*
	+ * This field should be set according to the MAX_FUNC_NUM set in the PCIe core,
	+ * it uses as mask (bit per function) to the dsate when set to zero.
	+ */
	+#define PCIE_W_PM_STATE_PER_FUNC_PM_STATE_PER_FUNC_ASPM_PF_ENABLE_MAX_FUNC_NUMBER (1 << 7)
	+/*
	+ * This field should be set according to the MAX_FUNC_NUM set in the PCIe core,
	+ * it uses as mask (bit per function) to the ASPM contrl bit, when set to zero.
	+ */
	+#define PCIE_W_PM_STATE_PER_FUNC_PM_STATE_PER_FUNC_DSATE_PF_ENABLE_MAX_FUNC_NUMBER (1 << 8)
	+
	+/** bar0_ctrl register **/
	+/* bar is en and override the internal PF bar. */
	+#define PCIE_W_CFG_BARS_OVRD_BAR0_CTRL_BAR_EN_MASK 0x00000003
	+#define PCIE_W_CFG_BARS_OVRD_BAR0_CTRL_BAR_EN_SHIFT 0
	+/* bar is io */
	+#define PCIE_W_CFG_BARS_OVRD_BAR0_CTRL_BAR_IO_MASK 0x0000000C
	+#define PCIE_W_CFG_BARS_OVRD_BAR0_CTRL_BAR_IO_SHIFT 2
	+/* Reserved. */
	+#define PCIE_W_CFG_BARS_OVRD_BAR0_CTRL_RSRVS_MASK 0xFFFFFFF0
	+#define PCIE_W_CFG_BARS_OVRD_BAR0_CTRL_RSRVS_SHIFT 4
	+
	+/** bar1_ctrl register **/
	+/* bar is en and override the internal PF bar. */
	+#define PCIE_W_CFG_BARS_OVRD_BAR1_CTRL_BAR_EN_MASK 0x00000003
	+#define PCIE_W_CFG_BARS_OVRD_BAR1_CTRL_BAR_EN_SHIFT 0
	+/* bar is io */
	+#define PCIE_W_CFG_BARS_OVRD_BAR1_CTRL_BAR_IO_MASK 0x0000000C
	+#define PCIE_W_CFG_BARS_OVRD_BAR1_CTRL_BAR_IO_SHIFT 2
	+/* Reserved. */
	+#define PCIE_W_CFG_BARS_OVRD_BAR1_CTRL_RSRVS_MASK 0xFFFFFFF0
	+#define PCIE_W_CFG_BARS_OVRD_BAR1_CTRL_RSRVS_SHIFT 4
	+
	+/** bar2_ctrl register **/
	+/* bar is en and override the internal PF bar. */
	+#define PCIE_W_CFG_BARS_OVRD_BAR2_CTRL_BAR_EN_MASK 0x00000003
	+#define PCIE_W_CFG_BARS_OVRD_BAR2_CTRL_BAR_EN_SHIFT 0
	+/* bar is io */
	+#define PCIE_W_CFG_BARS_OVRD_BAR2_CTRL_BAR_IO_MASK 0x0000000C
	+#define PCIE_W_CFG_BARS_OVRD_BAR2_CTRL_BAR_IO_SHIFT 2
	+/* Reserved. */
	+#define PCIE_W_CFG_BARS_OVRD_BAR2_CTRL_RSRVS_MASK 0xFFFFFFF0
	+#define PCIE_W_CFG_BARS_OVRD_BAR2_CTRL_RSRVS_SHIFT 4
	+
	+/** bar3_ctrl register **/
	+/* bar is en and override the internal PF bar. */
	+#define PCIE_W_CFG_BARS_OVRD_BAR3_CTRL_BAR_EN_MASK 0x00000003
	+#define PCIE_W_CFG_BARS_OVRD_BAR3_CTRL_BAR_EN_SHIFT 0
	+/* bar is io */
	+#define PCIE_W_CFG_BARS_OVRD_BAR3_CTRL_BAR_IO_MASK 0x0000000C
	+#define PCIE_W_CFG_BARS_OVRD_BAR3_CTRL_BAR_IO_SHIFT 2
	+/* Reserved. */
	+#define PCIE_W_CFG_BARS_OVRD_BAR3_CTRL_RSRVS_MASK 0xFFFFFFF0
	+#define PCIE_W_CFG_BARS_OVRD_BAR3_CTRL_RSRVS_SHIFT 4
	+
	+/** bar4_ctrl register **/
	+/* bar is en and override the internal PF bar. */
	+#define PCIE_W_CFG_BARS_OVRD_BAR4_CTRL_BAR_EN_MASK 0x00000003
	+#define PCIE_W_CFG_BARS_OVRD_BAR4_CTRL_BAR_EN_SHIFT 0
	+/* bar is io */
	+#define PCIE_W_CFG_BARS_OVRD_BAR4_CTRL_BAR_IO_MASK 0x0000000C
	+#define PCIE_W_CFG_BARS_OVRD_BAR4_CTRL_BAR_IO_SHIFT 2
	+/* Reserved. */
	+#define PCIE_W_CFG_BARS_OVRD_BAR4_CTRL_RSRVS_MASK 0xFFFFFFF0
	+#define PCIE_W_CFG_BARS_OVRD_BAR4_CTRL_RSRVS_SHIFT 4
	+
	+/** bar5_ctrl register **/
	+/* bar is en and override the internal PF bar. */
	+#define PCIE_W_CFG_BARS_OVRD_BAR5_CTRL_BAR_EN_MASK 0x00000003
	+#define PCIE_W_CFG_BARS_OVRD_BAR5_CTRL_BAR_EN_SHIFT 0
	+/* bar is io */
	+#define PCIE_W_CFG_BARS_OVRD_BAR5_CTRL_BAR_IO_MASK 0x0000000C
	+#define PCIE_W_CFG_BARS_OVRD_BAR5_CTRL_BAR_IO_SHIFT 2
	+/* Reserved. */
	+#define PCIE_W_CFG_BARS_OVRD_BAR5_CTRL_RSRVS_MASK 0xFFFFFFF0
	+#define PCIE_W_CFG_BARS_OVRD_BAR5_CTRL_RSRVS_SHIFT 4
	+
	+/** cause_A register **/
	+/* Deassert_INTD received. Write zero to clear this bit. */
	+#define PCIE_W_INT_GRP_A_CAUSE_A_DEASSERT_INTD (1 << 0)
	+/* Deassert_INTC received. Write zero to clear this bit. */
	+#define PCIE_W_INT_GRP_A_CAUSE_A_DEASSERT_INTC (1 << 1)
	+/* Deassert_INTB received. Write zero to clear this bit. */
	+#define PCIE_W_INT_GRP_A_CAUSE_A_DEASSERT_INTB (1 << 2)
	+/* Deassert_INTA received. Write zero to clear this bit. */
	+#define PCIE_W_INT_GRP_A_CAUSE_A_DEASSERT_INTA (1 << 3)
	+/* Assert_INTD received. Write zero to clear this bit. */
	+#define PCIE_W_INT_GRP_A_CAUSE_A_ASSERT_INTD (1 << 4)
	+/* Assert_INTC received. Write zero to clear this bit. */
	+#define PCIE_W_INT_GRP_A_CAUSE_A_ASSERT_INTC (1 << 5)
	+/* Assert_INTC received. Write zero to clear this bit. */
	+#define PCIE_W_INT_GRP_A_CAUSE_A_ASSERT_INTB (1 << 6)
	+/* Assert_INTA received. Write zero to clear this bit. */
	+#define PCIE_W_INT_GRP_A_CAUSE_A_ASSERT_INTA (1 << 7)
	+/*
	+ * MSI Controller Interrupt
	+ * MSI interrupt is being received. Write zero to clear this bit
	+ */
	+#define PCIE_W_INT_GRP_A_CAUSE_A_MSI_CNTR_RCV_INT (1 << 8)
	+/*
	+ * MSI sent grant. Write zero to clear this bit.
	+ */
	+#define PCIE_W_INT_GRP_A_CAUSE_A_MSI_TRNS_GNT (1 << 9)
	+/*
	+ * System error detected
	+ * Indicates if any device in the hierarchy reports any of the following errors
	+ * and the associated enable bit is set in the Root Control register:
	+ * ERR_COR
	+ * ERR_FATAL
	+ * ERR_NONFATAL
	+ * Also asserted when an internal error is detected. Write zero to clear this
	+ * bit.
	+ */
	+#define PCIE_W_INT_GRP_A_CAUSE_A_SYS_ERR_RC (1 << 10)
	+/*
	+ * Set when software initiates FLR on a Physical Function by writing to the
	+ * Initiate FLR register bit of that function Write zero to clear this bit.
	+ */
	+#define PCIE_W_REV1_2_INT_GRP_A_CAUSE_A_FLR_PF_ACTIVE (1 << 11)
	+#define PCIE_W_REV3_INT_GRP_A_CAUSE_A_RSRVD_11 (1 << 11)
	+/*
	+ * Reported error condition causes a bit to be set in the Root Error Status
	+ * register and the associated error message reporting enable bit is set in the
	+ * Root Error Command Register. Write zero to clear this bit.
	+ */
	+#define PCIE_W_REV1_2_INT_GRP_A_CAUSE_A_AER_RC_ERR (1 << 12)
	+#define PCIE_W_REV3_INT_GRP_A_CAUSE_A_RSRVD_12 (1 << 12)
	+/*
	+ * The core asserts aer_rc_err_msi when all of the following conditions are
	+ * true:
	+ * - MSI or MSI-X is enabled.
	+ * - A reported error condition causes a bit to be set in the Root Error Status
	+ * register.
	+ * - The associated error message reporting enable bit is set in the Root Error
	+ * Command register Write zero to clear this bit
	+ */
	+#define PCIE_W_REV1_2_INT_GRP_A_CAUSE_A_AER_RC_ERR_MSI (1 << 13)
	+#define PCIE_W_REV3_INT_GRP_A_CAUSE_A_RSRVD_13 (1 << 13)
	+/*
	+ * Wake Up. Wake up from power management unit.
	+ * The core generates wake to request the system to restore power and clock when
	+ * a beacon has been detected. wake is an active high signal and its rising edge
	+ * should be detected to drive the WAKE# on the connector Write zero to clear
	+ * this bit
	+ */
	+#define PCIE_W_INT_GRP_A_CAUSE_A_WAKE (1 << 14)
	+/*
	+ * The core asserts cfg_pme_int when all of the following conditions are true:
	+ * - INTx Assertion Disable bit in the Command register is 0.
	+ * - PME Interrupt Enable bit in the Root Control register is set to 1.
	+ * - PME Status bit in the Root Status register is set to 1. Write zero to clear
	+ * this bit
	+ */
	+#define PCIE_W_REV1_2_INT_GRP_A_CAUSE_A_PME_INT (1 << 15)
	+#define PCIE_W_REV3_INT_GRP_A_CAUSE_A_RSRVD_15 (1 << 15)
	+/*
	+ * The core asserts cfg_pme_msi when all of the following conditions are true:
	+ * - MSI or MSI-X is enabled.
	+ * - PME Interrupt Enable bit in the Root Control register is set to 1.
	+ * - PME Status bit in the Root Status register is set to 1. Write zero to clear
	+ * this bit
	+ */
	+#define PCIE_W_REV1_2_INT_GRP_A_CAUSE_A_PME_MSI (1 << 16)
	+#define PCIE_W_REV3_INT_GRP_A_CAUSE_A_RSRVD_16 (1 << 16)
	+/*
	+ * The core asserts hp_pme when all of the following conditions are true:
	+ * - The PME Enable bit in the Power Management Control and Status register is
	+ * set to 1.
	+ * - Any bit in the Slot Status register transitions from 0 to 1 and the
	+ * associated event notification is enabled in the Slot Control register. Write
	+ * zero to clear this bit
	+ */
	+#define PCIE_W_INT_GRP_A_CAUSE_A_HP_PME (1 << 17)
	+/*
	+ * The core asserts hp_int when all of the following conditions are true:
	+ * - INTx Assertion Disable bit in the Command register is 0.
	+ * - Hot-Plug interrupts are enabled in the Slot Control register.
	+ * - Any bit in the Slot Status register is equal to 1, and the associated event
	+ * notification is enabled in the Slot Control register. Write zero to clear
	+ * this bit
	+ */
	+#define PCIE_W_REV1_2_INT_GRP_A_CAUSE_A_HP_INT (1 << 18)
	+/* The outstanding write counter become full should never happen */
	+#define PCIE_W_REV3_INT_GRP_A_CAUSE_A_WRITE_COUNTER_FULL_ERR (1 << 18)
	+
	+
	+/*
	+ * The core asserts hp_msi when the logical AND of the following conditions
	+ * transitions from false to true:
	+ * - MSI or MSI-X is enabled.
	+ * - Hot-Plug interrupts are enabled in the Slot Control register.
	+ * - Any bit in the Slot Status register transitions from 0 to 1 and the
	+ * associated event notification is enabled in the Slot Control register.
	+ */
	+#define PCIE_W_INT_GRP_A_CAUSE_A_HP_MSI (1 << 19)
	+/* Read VPD registers notification */
	+#define PCIE_W_REV1_2_INT_GRP_A_CAUSE_A_VPD_INT (1 << 20)
	+/* not use */
	+#define PCIE_W_REV3_INT_GRP_A_CAUSE_A_NOT_USE (1 << 20)
	+
	+/*
	+ * The core assert link down event, whenever the link is going down. Write zero
	+ * to clear this bit, pulse signal
	+ */
	+#define PCIE_W_INT_GRP_A_CAUSE_A_LINK_DOWN_EVENT (1 << 21)
	+/*
	+ * When the EP gets a command to shut down, signal the software to block any new
	+ * TLP.
	+ */
	+#define PCIE_W_INT_GRP_A_CAUSE_A_PM_XTLH_BLOCK_TLP (1 << 22)
	+/* PHY/MAC link up */
	+#define PCIE_W_INT_GRP_A_CAUSE_A_XMLH_LINK_UP (1 << 23)
	+/* Data link up */
	+#define PCIE_W_INT_GRP_A_CAUSE_A_RDLH_LINK_UP (1 << 24)
	+/* The ltssm is in RCVRY_LOCK state. */
	+#define PCIE_W_INT_GRP_A_CAUSE_A_LTSSM_RCVRY_STATE (1 << 25)
	+/*
	+ * Config write transaction to the config space by the RC peer, enable this
	+ * interrupt only for EP mode.
	+ */
	+#define PCIE_W_INT_GRP_A_CAUSE_A_CFG_WR_EVENT (1 << 26)
	+/* AER error */
	+#define PCIE_W_INT_GRP_A_CAUSE_A_AP_PENDED_CORR_ERR_STS_INT (1 << 28)
	+/* AER error */
	+#define PCIE_W_INT_GRP_A_CAUSE_A_AP_PENDED_UNCORR_ERR_STS_INT (1 << 29)
	+
	+/** control_A register **/
	+/* When Clear_on_Read =1, all bits of Cause register are cleared on read. */
	+#define PCIE_W_INT_GRP_A_CONTROL_A_CLEAR_ON_READ (1 << 0)
	+/*
	+ * (Must be set only when MSIX is enabled.)
	+ * When Auto-Mask =1 and an MSI-X ACK for this bit is received, its
	+ * corresponding bit in the Mask register is set, masking future interrupts.
	+ */
	+#define PCIE_W_INT_GRP_A_CONTROL_A_AUTO_MASK (1 << 1)
	+/*
	+ * Auto_Clear (RW)
	+ * When Auto-Clear =1, the bits in the Interrupt Cause register are auto-cleared
	+ * after MSI-X is acknowledged. Must be used only if MSI-X is enabled.
	+ */
	+#define PCIE_W_INT_GRP_A_CONTROL_A_AUTO_CLEAR (1 << 2)
	+/*
	+ * When Set_on_Posedge =1, the bits in the Interrupt Cause register are set on
	+ * the posedge of the interrupt source, i.e., when interrupt source =1 and
	+ * Interrupt Status = 0.
	+ * When Set_on_Posedge =0, the bits in the Interrupt Cause register are set when
	+ * interrupt source =1.
	+ */
	+#define PCIE_W_INT_GRP_A_CONTROL_A_SET_ON_POSEDGE (1 << 3)
	+/*
	+ * When Moderation_Reset =1, all Moderation timers associated with the interrupt
	+ * cause bits are cleared to 0, enabling immediate interrupt assertion if any
	+ * unmasked cause bit is set to 1. This bit is self-negated.
	+ */
	+#define PCIE_W_INT_GRP_A_CONTROL_A_MOD_RST (1 << 4)
	+/*
	+ * When mask_msi_x =1, no MSI-X from this group is sent. This bit must be set to
	+ * 1 when the associated summary bit in this group is used to generate a single
	+ * MSI-X for this group.
	+ */
	+#define PCIE_W_INT_GRP_A_CONTROL_A_MASK_MSI_X (1 << 5)
	+/* MSI-X AWID value. Same ID for all cause bits. */
	+#define PCIE_W_INT_GRP_A_CONTROL_A_AWID_MASK 0x00000F00
	+#define PCIE_W_INT_GRP_A_CONTROL_A_AWID_SHIFT 8
	+/*
	+ * This value determines the interval between interrupts; writing ZERO disables
	+ * Moderation.
	+ */
	+#define PCIE_W_INT_GRP_A_CONTROL_A_MOD_INTV_MASK 0x00FF0000
	+#define PCIE_W_INT_GRP_A_CONTROL_A_MOD_INTV_SHIFT 16
	+/*
	+ * This value determines the Moderation_Timer_Clock speed.
	+ * 0- Moderation-timer is decremented every 1x256 SB clock cycles ~1uS.
	+ * 1- Moderation-timer is decremented every 2x256 SB clock cycles ~2uS.
	+ * N- Moderation-timer is decremented every Nx256 SB clock cycles ~(N+1) uS.
	+ */
	+#define PCIE_W_INT_GRP_A_CONTROL_A_MOD_RES_MASK 0x0F000000
	+#define PCIE_W_INT_GRP_A_CONTROL_A_MOD_RES_SHIFT 24
	+
	+/** cause_B register **/
	+/* Indicates that the core received a PM_PME Message. Write Zero to clear. */
	+#define PCIE_W_INT_GRP_B_CAUSE_B_MSG_PM_PME (1 << 0)
	+/*
	+ * Indicates that the core received a PME_TO_Ack Message. Write Zero to clear.
	+ */
	+#define PCIE_W_INT_GRP_B_CAUSE_B_MSG_PM_TO_ACK (1 << 1)
	+/*
	+ * Indicates that the core received an PME_Turn_Off Message. Write Zero to
	+ * clear.
	+ * EP mode only
	+ */
	+#define PCIE_W_INT_GRP_B_CAUSE_B_MSG_PM_TURNOFF (1 << 2)
	+/* Indicates that the core received an ERR_CORR Message. Write Zero to clear. */
	+#define PCIE_W_INT_GRP_B_CAUSE_B_MSG_CORRECTABLE_ERR (1 << 3)
	+/*
	+ * Indicates that the core received an ERR_NONFATAL Message. Write Zero to
	+ * clear.
	+ */
	+#define PCIE_W_INT_GRP_B_CAUSE_B_MSG_NONFATAL_ERR (1 << 4)
	+/*
	+ * Indicates that the core received an ERR_FATAL Message. Write Zero to clear.
	+ */
	+#define PCIE_W_INT_GRP_B_CAUSE_B_MSG_FATAL_ERR (1 << 5)
	+/*
	+ * Indicates that the core received a Vendor Defined Message. Write Zero to
	+ * clear.
	+ */
	+#define PCIE_W_INT_GRP_B_CAUSE_B_MSG_VENDOR_0 (1 << 6)
	+/*
	+ * Indicates that the core received a Vendor Defined Message. Write Zero to
	+ * clear.
	+ */
	+#define PCIE_W_INT_GRP_B_CAUSE_B_MSG_VENDOR_1 (1 << 7)
	+/* Indicates that the core received an Unlock Message. Write Zero to clear. */
	+#define PCIE_W_INT_GRP_B_CAUSE_B_MSG_UNLOCK (1 << 8)
	+/*
	+ * Notification when the Link Autonomous Bandwidth Status register (Link Status
	+ * register bit 15) is updated and the Link Autonomous Bandwidth Interrupt
	+ * Enable (Link Control register bit 11) is set. This bit is not applicable to,
	+ * and is reserved, for Endpoint device. Write Zero to clear
	+ */
	+#define PCIE_W_INT_GRP_B_CAUSE_B_LINK_AUTO_BW_INT (1 << 12)
	+/*
	+ * Notification that the Link Equalization Request bit in the Link Status 2
	+ * Register has been set. Write Zero to clear.
	+ */
	+#define PCIE_W_INT_GRP_B_CAUSE_B_LINK_EQ_REQ_INT (1 << 13)
	+/*
	+ * OB Vendor message request is granted by the PCIe core Write Zero to clear.
	+ */
	+#define PCIE_W_INT_GRP_B_CAUSE_B_VENDOR_MSG_GRANT (1 << 14)
	+/* CPL timeout from the PCIe core inidication. Write Zero to clear */
	+#define PCIE_W_INT_GRP_B_CAUSE_B_CMP_TIME_OUT (1 << 15)
	+/*
	+ * Slave Response Composer Lookup Error
	+ * Indicates that an overflow occurred in a lookup table of the Inbound
	+ * responses. This indicates that there was a violation of the number of
	+ * outstanding NP requests issued for the Outbound direction. Write zero to
	+ * clear
	+ */
	+#define PCIE_W_INT_GRP_B_CAUSE_B_RADMX_CMPOSER_LOOKUP_ERR (1 << 16)
	+/* Parity Error */
	+#define PCIE_W_INT_GRP_B_CAUSE_B_PARITY_ERROR_CORE (1 << 17)
	+
	+/** control_B register **/
	+/* When Clear_on_Read =1, all bits of the Cause register are cleared on read. */
	+#define PCIE_W_INT_GRP_B_CONTROL_B_CLEAR_ON_READ (1 << 0)
	+/*
	+ * (Must be set only when MSIX is enabled.)
	+ * When Auto-Mask =1 and an MSI-X ACK for this bit is received, its
	+ * corresponding bit in the Mask register is set, masking future interrupts.
	+ */
	+#define PCIE_W_INT_GRP_B_CONTROL_B_AUTO_MASK (1 << 1)
	+/*
	+ * Auto_Clear (RW)
	+ * When Auto-Clear =1, the bits in the Interrupt Cause register are auto-cleared
	+ * after MSI-X is acknowledged. Must be used only if MSI-X is enabled.
	+ */
	+#define PCIE_W_INT_GRP_B_CONTROL_B_AUTO_CLEAR (1 << 2)
	+/*
	+ * When Set_on_Posedge =1, the bits in the interrupt Cause register are set on
	+ * the posedge of the interrupt source, i.e., when Interrupt Source =1 and
	+ * Interrupt Status = 0.
	+ * When Set_on_Posedge =0, the bits in the Interrupt Cause register are set when
	+ * Interrupt Source =1.
	+ */
	+#define PCIE_W_INT_GRP_B_CONTROL_B_SET_ON_POSEDGE (1 << 3)
	+/*
	+ * When Moderation_Reset =1, all Moderation timers associated with the interrupt
	+ * cause bits are cleared to 0, enabling an immediate interrupt assertion if any
	+ * unmasked cause bit is set to 1. This bit is self-negated.
	+ */
	+#define PCIE_W_INT_GRP_B_CONTROL_B_MOD_RST (1 << 4)
	+/*
	+ * When mask_msi_x =1, no MSI-X from this group is sent. This bit must be set to
	+ * 1 when the associated summary bit in this group is used to generate a single
	+ * MSI-X for this group.
	+ */
	+#define PCIE_W_INT_GRP_B_CONTROL_B_MASK_MSI_X (1 << 5)
	+/* MSI-X AWID value. Same ID for all cause bits. */
	+#define PCIE_W_INT_GRP_B_CONTROL_B_AWID_MASK 0x00000F00
	+#define PCIE_W_INT_GRP_B_CONTROL_B_AWID_SHIFT 8
	+/*
	+ * This value determines the interval between interrupts. Writing ZERO disables
	+ * Moderation.
	+ */
	+#define PCIE_W_INT_GRP_B_CONTROL_B_MOD_INTV_MASK 0x00FF0000
	+#define PCIE_W_INT_GRP_B_CONTROL_B_MOD_INTV_SHIFT 16
	+/*
	+ * This value determines the Moderation_Timer_Clock speed.
	+ * 0- Moderation-timer is decremented every 1x256 SB clock cycles ~1uS.
	+ * 1- Moderation-timer is decremented every 2x256 SB clock cycles ~2uS.
	+ * N- Moderation-timer is decremented every Nx256 SB clock cycles ~(N+1) uS.
	+ */
	+#define PCIE_W_INT_GRP_B_CONTROL_B_MOD_RES_MASK 0x0F000000
	+#define PCIE_W_INT_GRP_B_CONTROL_B_MOD_RES_SHIFT 24
	+
	+/** cause_C register **/
	+/* VPD interrupt, ot read/write frpm EEPROM */
	+#define PCIE_W_INTERRUPT_GRP_C_INT_CAUSE_GRP_C_VPD_INT_FUNC_MASK 0x0000000F
	+#define PCIE_W_INTERRUPT_GRP_C_INT_CAUSE_GRP_C_VPD_INT_FUNC_SHIFT 0
	+/* flr PF active */
	+#define PCIE_W_INTERRUPT_GRP_C_INT_CAUSE_GRP_C_CFG_FLR_PF_ACTIVE_MASK 0x000000F0
	+#define PCIE_W_INTERRUPT_GRP_C_INT_CAUSE_GRP_C_CFG_FLR_PF_ACTIVE_SHIFT 4
	+/* System ERR RC. */
	+#define PCIE_W_INTERRUPT_GRP_C_INT_CAUSE_GRP_C_CFG_SYS_ERR_RC_MASK 0x00000F00
	+#define PCIE_W_INTERRUPT_GRP_C_INT_CAUSE_GRP_C_CFG_SYS_ERR_RC_SHIFT 8
	+/* AER RC INT */
	+#define PCIE_W_INTERRUPT_GRP_C_INT_CAUSE_GRP_C_CFG_AER_RC_ERR_INT_MASK 0x0000F000
	+#define PCIE_W_INTERRUPT_GRP_C_INT_CAUSE_GRP_C_CFG_AER_RC_ERR_INT_SHIFT 12
	+/* AER RC MSI */
	+#define PCIE_W_INTERRUPT_GRP_C_INT_CAUSE_GRP_C_CFG_AER_RC_ERR_MSI_MASK 0x000F0000
	+#define PCIE_W_INTERRUPT_GRP_C_INT_CAUSE_GRP_C_CFG_AER_RC_ERR_MSI_SHIFT 16
	+/* PME MSI */
	+#define PCIE_W_INTERRUPT_GRP_C_INT_CAUSE_GRP_C_CFG_PME_MSI_MASK 0x00F00000
	+#define PCIE_W_INTERRUPT_GRP_C_INT_CAUSE_GRP_C_CFG_PME_MSI_SHIFT 20
	+/* PME int */
	+#define PCIE_W_INTERRUPT_GRP_C_INT_CAUSE_GRP_C_CFG_PME_INT_MASK 0x0F000000
	+#define PCIE_W_INTERRUPT_GRP_C_INT_CAUSE_GRP_C_CFG_PME_INT_SHIFT 24
	+/* SB overflow */
	+#define PCIE_W_INTERRUPT_GRP_C_INT_CAUSE_GRP_C_RADM_QOVERFLOW (1 << 28)
	+/* ecrc was injected through the diag_ctrl bus */
	+#define PCIE_W_INTERRUPT_GRP_C_INT_CAUSE_GRP_C_ECRC_INJECTED (1 << 29)
	+/* lcrc was injected through the diag_ctrl bus */
	+#define PCIE_W_INTERRUPT_GRP_C_INT_CAUSE_GRP_C_LCRC_INJECTED (1 << 30)
	+/* lcrc was injected through the diag_ctrl bus */
	+#define PCIE_W_INTERRUPT_GRP_C_INT_CAUSE_GRP_C_RSRVD (1 << 31)
	+
	+/** control_C register **/
	+/* When Clear_on_Read =1, all bits of Cause register are cleared on read. */
	+#define PCIE_W_INTERRUPT_GRP_C_INT_CONTROL_GRP_C_CLEAR_ON_READ (1 << 0)
	+/*
	+ * (Must be set only when MSIX is enabled.)
	+ * When Auto-Mask =1 and an MSI-X ACK for this bit is received, its
	+ * corresponding bit in the Mask register is set, masking future interrupts.
	+ */
	+#define PCIE_W_INTERRUPT_GRP_C_INT_CONTROL_GRP_C_AUTO_MASK (1 << 1)
	+/*
	+ * Auto_Clear (RW)
	+ * When Auto-Clear =1, the bits in the Interrupt Cause register are auto-cleared
	+ * after MSI-X is acknowledged. Must be used only if MSI-X is enabled.
	+ */
	+#define PCIE_W_INTERRUPT_GRP_C_INT_CONTROL_GRP_C_AUTO_CLEAR (1 << 2)
	+/*
	+ * When Set_on_Posedge =1, the bits in the Interrupt Cause register are set on
	+ * the posedge of the interrupt source, i.e., when interrupt source =1 and
	+ * Interrupt Status = 0.
	+ * When Set_on_Posedge =0, the bits in the Interrupt Cause register are set when
	+ * interrupt source =1.
	+ */
	+#define PCIE_W_INTERRUPT_GRP_C_INT_CONTROL_GRP_C_SET_ON_POSEDGE (1 << 3)
	+/*
	+ * When Moderation_Reset =1, all Moderation timers associated with the interrupt
	+ * cause bits are cleared to 0, enabling immediate interrupt assertion if any
	+ * unmasked cause bit is set to 1. This bit is self-negated.
	+ */
	+#define PCIE_W_INTERRUPT_GRP_C_INT_CONTROL_GRP_C_MOD_RST (1 << 4)
	+/*
	+ * When mask_msi_x =1, no MSI-X from this group is sent. This bit must be set to
	+ * 1 when the associated summary bit in this group is used to generate a single
	+ * MSI-X for this group.
	+ */
	+#define PCIE_W_INTERRUPT_GRP_C_INT_CONTROL_GRP_C_MASK_MSI_X (1 << 5)
	+/* MSI-X AWID value. Same ID for all cause bits. */
	+#define PCIE_W_INTERRUPT_GRP_C_INT_CONTROL_GRP_C_AWID_MASK 0x00000F00
	+#define PCIE_W_INTERRUPT_GRP_C_INT_CONTROL_GRP_C_AWID_SHIFT 8
	+/*
	+ * This value determines the interval between interrupts; writing ZERO disables
	+ * Moderation.
	+ */
	+#define PCIE_W_INTERRUPT_GRP_C_INT_CONTROL_GRP_C_MOD_INTV_MASK 0x00FF0000
	+#define PCIE_W_INTERRUPT_GRP_C_INT_CONTROL_GRP_C_MOD_INTV_SHIFT 16
	+/*
	+ * This value determines the Moderation_Timer_Clock speed.
	+ * 0- Moderation-timer is decremented every 1x256 SB clock cycles ~1uS.
	+ * 1- Moderation-timer is decremented every 2x256 SB clock cycles ~2uS.
	+ * N- Moderation-timer is decremented every Nx256 SB clock cycles ~(N+1) uS.
	+ */
	+#define PCIE_W_INTERRUPT_GRP_C_INT_CONTROL_GRP_C_MOD_RES_MASK 0x0F000000
	+#define PCIE_W_INTERRUPT_GRP_C_INT_CONTROL_GRP_C_MOD_RES_SHIFT 24
	+
	+/** control_D register **/
	+/* When Clear_on_Read =1, all bits of Cause register are cleared on read. */
	+#define PCIE_W_INTERRUPT_GRP_D_INT_CONTROL_GRP_D_CLEAR_ON_READ (1 << 0)
	+/*
	+ * (Must be set only when MSIX is enabled.)
	+ * When Auto-Mask =1 and an MSI-X ACK for this bit is received, its
	+ * corresponding bit in the Mask register is set, masking future interrupts.
	+ */
	+#define PCIE_W_INTERRUPT_GRP_D_INT_CONTROL_GRP_D_AUTO_MASK (1 << 1)
	+/*
	+ * Auto_Clear (RW)
	+ * When Auto-Clear =1, the bits in the Interrupt Cause register are auto-cleared
	+ * after MSI-X is acknowledged. Must be used only if MSI-X is enabled.
	+ */
	+#define PCIE_W_INTERRUPT_GRP_D_INT_CONTROL_GRP_D_AUTO_CLEAR (1 << 2)
	+/*
	+ * When Set_on_Posedge =1, the bits in the Interrupt Cause register are set on
	+ * the posedge of the interrupt source, i.e., when interrupt source =1 and
	+ * Interrupt Status = 0.
	+ * When Set_on_Posedge =0, the bits in the Interrupt Cause register are set when
	+ * interrupt source =1.
	+ */
	+#define PCIE_W_INTERRUPT_GRP_D_INT_CONTROL_GRP_D_SET_ON_POSEDGE (1 << 3)
	+/*
	+ * When Moderation_Reset =1, all Moderation timers associated with the interrupt
	+ * cause bits are cleared to 0, enabling immediate interrupt assertion if any
	+ * unmasked cause bit is set to 1. This bit is self-negated.
	+ */
	+#define PCIE_W_INTERRUPT_GRP_D_INT_CONTROL_GRP_D_MOD_RST (1 << 4)
	+/*
	+ * When mask_msi_x =1, no MSI-X from this group is sent. This bit must be set to
	+ * 1 when the associated summary bit in this group is used to generate a single
	+ * MSI-X for this group.
	+ */
	+#define PCIE_W_INTERRUPT_GRP_D_INT_CONTROL_GRP_D_MASK_MSI_X (1 << 5)
	+/* MSI-X AWID value. Same ID for all cause bits. */
	+#define PCIE_W_INTERRUPT_GRP_D_INT_CONTROL_GRP_D_AWID_MASK 0x00000F00
	+#define PCIE_W_INTERRUPT_GRP_D_INT_CONTROL_GRP_D_AWID_SHIFT 8
	+/*
	+ * This value determines the interval between interrupts; writing ZERO disables
	+ * Moderation.
	+ */
	+#define PCIE_W_INTERRUPT_GRP_D_INT_CONTROL_GRP_D_MOD_INTV_MASK 0x00FF0000
	+#define PCIE_W_INTERRUPT_GRP_D_INT_CONTROL_GRP_D_MOD_INTV_SHIFT 16
	+/*
	+ * This value determines the Moderation_Timer_Clock speed.
	+ * 0- Moderation-timer is decremented every 1x256 SB clock cycles ~1uS.
	+ * 1- Moderation-timer is decremented every 2x256 SB clock cycles ~2uS.
	+ * N- Moderation-timer is decremented every Nx256 SB clock cycles ~(N+1) uS.
	+ */
	+#define PCIE_W_INTERRUPT_GRP_D_INT_CONTROL_GRP_D_MOD_RES_MASK 0x0F000000
	+#define PCIE_W_INTERRUPT_GRP_D_INT_CONTROL_GRP_D_MOD_RES_SHIFT 24
	+#ifdef __cplusplus
	+}
	+#endif
	+
	+#endif /* __AL_HAL_PCIE_W_REG_H */
	+
	+/** @} end of ... group */
	+
	+
	Index: sys/arm/annapurna/alpine/hal/al_hal_plat_services.h
	===================================================================
	--- /dev/null
	+++ sys/arm/annapurna/alpine/hal/al_hal_plat_services.h
	@@ -0,0 +1,419 @@
	+/*-
	+*******************************************************************************
	+Copyright (C) 2015 Annapurna Labs Ltd.
	+
	+This file may be licensed under the terms of the Annapurna Labs Commercial
	+License Agreement.
	+
	+Alternatively, this file can be distributed under the terms of the GNU General
	+Public License V2 as published by the Free Software Foundation and can be
	+found at http://www.gnu.org/licenses/gpl-2.0.html
	+
	+Alternatively, redistribution and use in source and binary forms, with or
	+without modification, are permitted provided that the following conditions are
	+met:
	+
	+ * Redistributions of source code must retain the above copyright notice,
	+this list of conditions and the following disclaimer.
	+
	+ * Redistributions in binary form must reproduce the above copyright
	+notice, this list of conditions and the following disclaimer in
	+the documentation and/or other materials provided with the
	+distribution.
	+
	+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
	+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
	+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
	+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
	+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
	+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
	+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
	+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
	+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
	+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	+
	+*******************************************************************************/
	+
	+/**
	+ * @defgroup group_services Platform Services API
	+ * @{
	+ * The Platform Services API provides miscellaneous system services to HAL
	+ * drivers, such as:
	+ * - Registers read/write
	+ * - Assertions
	+ * - Memory barriers
	+ * - Endianness conversions
	+ *
	+ * And more.
	+ * @file plat_api/sample/al_hal_plat_services.h
	+ *
	+ * @brief API for Platform services provided for to HAL drivers
	+ *
	+ *
	+ */
	+
	+#ifndef __PLAT_SERVICES_H__
	+#define __PLAT_SERVICES_H__
	+
	+#include <machine/atomic.h>
	+#include <sys/cdefs.h>
	+__FBSDID("$FreeBSD$");
	+
	+#include <sys/param.h>
	+#include <sys/systm.h>
	+#include <sys/kernel.h>
	+#include <sys/endian.h>
	+#include <sys/errno.h>
	+#include <sys/lock.h>
	+#include <sys/mutex.h>
	+
	+/* Prototypes for all the bus_space structure functions */
	+bs_protos(generic);
	+bs_protos(generic_armv4);
	+
	+#define __UNUSED __attribute__((unused))
	+
	+/* INDENT-OFF */
	+#ifdef __cplusplus
	+extern "C" {
	+#endif
	+/* INDENT-ON */
	+
	+/*
	+ * WMA: This is a hack which allows not modifying the __iomem accessing HAL code.
	+ * On ARMv7, bus_handle holds the information about VA of accessed memory. It
	+ * is possible to use direct load/store instruction instead of bus_dma machinery.
	+ * WARNING: This is not guaranteed to stay that way forever, nor that
	+ * on other architectures these variables behave similarly. Keep that
	+ * in mind during porting to other systems.
	+ */
	+/**
	+ * Read MMIO 8 bits register
	+ * @param offset register offset
	+ *
	+ * @return register value
	+ */
	+static uint8_t al_reg_read8(uint8_t * offset);
	+
	+/**
	+ * Read MMIO 16 bits register
	+ * @param offset register offset
	+ *
	+ * @return register value
	+ */
	+static uint16_t al_reg_read16(uint16_t * offset);
	+
	+/**
	+ * Read MMIO 32 bits register
	+ * @param offset register offset
	+ *
	+ * @return register value
	+ */
	+static uint32_t al_reg_read32(uint32_t * offset);
	+
	+/**
	+ * Read MMIO 64 bits register
	+ * @param offset register offset
	+ *
	+ * @return register value
	+ */
	+uint64_t al_reg_read64(uint64_t * offset);
	+
	+/**
	+ * Relaxed read MMIO 32 bits register
	+ *
	+ * Relaxed register read/write functions don't involve cpu instructions that
	+ * force syncronization, nor ordering between the register access and memory
	+ * data access.
	+ * These instructions are used in performance critical code to avoid the
	+ * overhead of the synchronization instructions.
	+ *
	+ * @param offset register offset
	+ *
	+ * @return register value
	+ */
	+#define al_bus_dma_to_va(bus_tag, bus_handle) ((void*)bus_handle)
	+
	+/**
	+ * Relaxed read MMIO 32 bits register
	+ *
	+ * Relaxed register read/write functions don't involve cpu instructions that
	+ * force syncronization, nor ordering between the register access and memory
	+ * data access.
	+ * These instructions are used in performance critical code to avoid the
	+ * overhead of the synchronization instructions.
	+ *
	+ * @param offset register offset
	+ *
	+ * @return register value
	+ */
	+#define al_reg_read32_relaxed(l) generic_bs_r_4(NULL, (bus_space_handle_t)l, 0)
	+
	+/**
	+ * Relaxed write to MMIO 32 bits register
	+ *
	+ * Relaxed register read/write functions don't involve cpu instructions that
	+ * force syncronization, nor ordering between the register access and memory
	+ * data access.
	+ * These instructions are used in performance critical code to avoid the
	+ * overhead of the synchronization instructions.
	+ *
	+ * @param offset register offset
	+ * @param val value to write to the register
	+ */
	+#define al_reg_write32_relaxed(l,v) generic_bs_w_4(NULL, (bus_space_handle_t)l, 0, v)
	+
	+/**
	+ * Write to MMIO 8 bits register
	+ * @param offset register offset
	+ * @param val value to write to the register
	+ */
	+#define al_reg_write8(l,v) do { dsb(); generic_bs_w_1(NULL, (bus_space_handle_t)l, 0, v); dmb(); } while (0)
	+
	+/**
	+ * Write to MMIO 16 bits register
	+ * @param offset register offset
	+ * @param val value to write to the register
	+ */
	+#define al_reg_write16(l,v) do { dsb(); generic_bs_w_2(NULL, (bus_space_handle_t)l, 0, v); dmb(); } while (0)
	+
	+/**
	+ * Write to MMIO 32 bits register
	+ * @param offset register offset
	+ * @param val value to write to the register
	+ */
	+#define al_reg_write32(l,v) do { dsb(); generic_bs_w_4(NULL, (bus_space_handle_t)l, 0, v); dmb(); } while (0)
	+
	+/**
	+ * Write to MMIO 64 bits register
	+ * @param offset register offset
	+ * @param val value to write to the register
	+ */
	+#define al_reg_write64(l,v) do { dsb(); generic_bs_w_8(NULL, (bus_space_handle_t)l, 0, v); dmb(); } while (0)
	+
	+static inline uint8_t
	+al_reg_read8(uint8_t *l)
	+{
	+ dsb();
	+
	+ return (generic_bs_r_1(NULL, (bus_space_handle_t)l, 0));
	+}
	+
	+static inline uint16_t
	+al_reg_read16(uint16_t *l)
	+{
	+ dsb();
	+
	+ return (generic_bs_r_2(NULL, (bus_space_handle_t)l, 0));
	+}
	+
	+static inline uint32_t
	+al_reg_read32(uint32_t *l)
	+{
	+ dsb();
	+
	+ return (generic_bs_r_4(NULL, (bus_space_handle_t)l, 0));
	+}
	+
	+#define AL_DBG_LEVEL_NONE 0
	+#define AL_DBG_LEVEL_ERR 1
	+#define AL_DBG_LEVEL_WARN 2
	+#define AL_DBG_LEVEL_INFO 3
	+#define AL_DBG_LEVEL_DBG 4
	+
	+#define AL_DBG_LEVEL AL_DBG_LEVEL_ERR
	+
	+extern struct mtx al_dbg_lock;
	+
	+#define AL_DBG_LOCK() mtx_lock_spin(&al_dbg_lock)
	+#define AL_DBG_UNLOCK() mtx_unlock_spin(&al_dbg_lock)
	+
	+/**
	+ * print message
	+ *
	+ * @param format The format string
	+ * @param ... Additional arguments
	+ */
	+#define al_print(type, fmt, ...) do { if (AL_DBG_LEVEL >= AL_DBG_LEVEL_NONE) { AL_DBG_LOCK(); printf(fmt, ##__VA_ARGS__); AL_DBG_UNLOCK(); } } while(0)
	+
	+/**
	+ * print error message
	+ *
	+ * @param format
	+ */
	+#define al_err(...) do { if (AL_DBG_LEVEL >= AL_DBG_LEVEL_ERR) { AL_DBG_LOCK(); printf(__VA_ARGS__); AL_DBG_UNLOCK(); } } while(0)
	+
	+/**
	+ * print warning message
	+ *
	+ * @param format
	+ */
	+#define al_warn(...) do { if (AL_DBG_LEVEL >= AL_DBG_LEVEL_WARN) { AL_DBG_LOCK(); printf(__VA_ARGS__); AL_DBG_UNLOCK(); } } while(0)
	+
	+/**
	+ * print info message
	+ *
	+ * @param format
	+ */
	+#define al_info(...) do { if (AL_DBG_LEVEL >= AL_DBG_LEVEL_INFO) { AL_DBG_LOCK(); printf(__VA_ARGS__); AL_DBG_UNLOCK(); } } while(0)
	+
	+/**
	+ * print debug message
	+ *
	+ * @param format
	+ */
	+#define al_dbg(...) do { if (AL_DBG_LEVEL >= AL_DBG_LEVEL_DBG) { AL_DBG_LOCK(); printf(__VA_ARGS__); AL_DBG_UNLOCK(); } } while(0)
	+
	+/**
	+ * Assertion
	+ *
	+ * @param condition
	+ */
	+#define al_assert(COND) \
	+ do { \
	+ if (!(COND)) \
	+ al_err( \
	+ "%s:%d:%s: Assertion failed! (%s)\n", \
	+ __FILE__, __LINE__, __func__, #COND); \
	+ } while(AL_FALSE)
	+
	+/**
	+ * Make sure data will be visible by other masters (other CPUS and DMA).
	+ * usually this is achieved by the ARM DMB instruction.
	+ */
	+static void al_data_memory_barrier(void);
	+
	+/**
	+ * Make sure data will be visible by DMA masters, no restriction for other cpus
	+ */
	+static inline void
	+al_data_memory_barrier(void)
	+{
	+ dsb();
	+}
	+
	+/**
	+ * Make sure data will be visible in order by other cpus masters.
	+ */
	+static inline void
	+al_smp_data_memory_barrier(void)
	+{
	+ dsb();
	+}
	+
	+/**
	+ * Make sure write data will be visible in order by other cpus masters.
	+ */
	+static inline void
	+al_local_data_memory_barrier(void)
	+{
	+ dsb();
	+}
	+
	+/**
	+ * al_udelay - micro sec delay
	+ */
	+#define al_udelay(u) DELAY(u)
	+
	+/**
	+ * al_msleep - mili sec delay
	+ */
	+#define al_msleep(m) DELAY((m) * 1000)
	+
	+/**
	+ * swap half word to little endian
	+ *
	+ * @param x 16 bit value
	+ *
	+ * @return the value in little endian
	+ */
	+#define swap16_to_le(x) htole16(x)
	+/**
	+ * swap word to little endian
	+ *
	+ * @param x 32 bit value
	+ *
	+ * @return the value in little endian
	+ */
	+#define swap32_to_le(x) htole32(x)
	+
	+/**
	+ * swap 8 bytes to little endian
	+ *
	+ * @param x 64 bit value
	+ *
	+ * @return the value in little endian
	+ */
	+#define swap64_to_le(x) htole64(x)
	+
	+/**
	+ * swap half word from little endian
	+ *
	+ * @param x 16 bit value
	+ *
	+ * @return the value in the cpu endianess
	+ */
	+#define swap16_from_le(x) le16toh(x)
	+
	+/**
	+ * swap word from little endian
	+ *
	+ * @param x 32 bit value
	+ *
	+ * @return the value in the cpu endianess
	+ */
	+#define swap32_from_le(x) le32toh(x)
	+
	+/**
	+ * swap 8 bytes from little endian
	+ *
	+ * @param x 64 bit value
	+ *
	+ * @return the value in the cpu endianess
	+ */
	+#define swap64_from_le(x) le64toh(x)
	+
	+/**
	+ * Memory set
	+ *
	+ * @param p memory pointer
	+ * @param val value for setting
	+ * @param cnt number of bytes to set
	+ */
	+#define al_memset(p, val, cnt) memset(p, val, cnt)
	+
	+/**
	+ * Memory copy
	+ *
	+ * @param p1 memory pointer
	+ * @param p2 memory pointer
	+ * @param cnt number of bytes to copy
	+ */
	+#define al_memcpy(p1, p2, cnt) memcpy(p1, p2, cnt)
	+
	+/**
	+ * Memory compare
	+ *
	+ * @param p1 memory pointer
	+ * @param p2 memory pointer
	+ * @param cnt number of bytes to compare
	+ */
	+#define al_memcmp(p1, p2, cnt) memcmp(p1, p2, cnt)
	+
	+/**
	+ * String compare
	+ *
	+ * @param s1 string pointer
	+ * @param s2 string pointer
	+ */
	+#define al_strcmp(s1, s2) strcmp(s1, s2)
	+
	+#define al_get_cpu_id() 0
	+
	+/* INDENT-OFF */
	+#ifdef __cplusplus
	+}
	+#endif
	+/* INDENT-ON */
	+/** @} end of Platform Services API group */
	+#endif /* __PLAT_SERVICES_H__ */
	Index: sys/arm/annapurna/alpine/hal/al_hal_plat_types.h
	===================================================================
	--- /dev/null
	+++ sys/arm/annapurna/alpine/hal/al_hal_plat_types.h
	@@ -0,0 +1,94 @@
	+/*-
	+********************************************************************************
	+Copyright (C) 2015 Annapurna Labs Ltd.
	+
	+This file may be licensed under the terms of the Annapurna Labs Commercial
	+License Agreement.
	+
	+Alternatively, this file can be distributed under the terms of the GNU General
	+Public License V2 as published by the Free Software Foundation and can be
	+found at http://www.gnu.org/licenses/gpl-2.0.html
	+
	+Alternatively, redistribution and use in source and binary forms, with or
	+without modification, are permitted provided that the following conditions are
	+met:
	+
	+ * Redistributions of source code must retain the above copyright notice,
	+this list of conditions and the following disclaimer.
	+
	+ * Redistributions in binary form must reproduce the above copyright
	+notice, this list of conditions and the following disclaimer in
	+the documentation and/or other materials provided with the
	+distribution.
	+
	+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
	+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
	+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
	+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
	+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
	+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
	+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
	+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
	+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
	+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	+
	+*******************************************************************************/
	+
	+/**
	+ * @defgroup group_services Platform Services API
	+ * @{
	+ * @file plat_api/sample/al_hal_plat_types.h
	+ *
	+ */
	+
	+#ifndef __PLAT_TYPES_H__
	+#define __PLAT_TYPES_H__
	+
	+#include <sys/cdefs.h>
	+#include <sys/param.h>
	+#include <machine/bus.h>
	+#include <sys/bus.h>
	+
	+/* INDENT-OFF */
	+#ifdef __cplusplus
	+extern "C" {
	+#endif
	+/* INDENT-ON */
	+
	+/* Basic data types */
	+typedef int al_bool; /** boolean */
	+#define AL_TRUE 1
	+#define AL_FALSE 0
	+
	+
	+/* define types */
	+#ifndef AL_HAVE_TYPES
	+typedef unsigned char uint8_t; /** unsigned 8 bits */
	+typedef unsigned short uint16_t; /** unsigned 16 bits */
	+typedef unsigned int uint32_t; /** unsigned 32 bits */
	+typedef unsigned long long uint64_t; /** unsigned 64 bits */
	+
	+typedef signed char int8_t; /** signed 8 bits */
	+typedef short int int16_t; /** signed 16 bits */
	+typedef signed int int32_t; /** signed 32 bits */
	+
	+/** An unsigned int that is guaranteed to be the same size as a pointer */
	+/** C99 standard */
	+typedef unsigned long uintptr_t;
	+#endif
	+
	+
	+/** in LPAE mode, the address address is 40 bit, we extend it to 64 bit */
	+typedef uint64_t al_phys_addr_t;
	+
	+/** this defines the cpu endiancess. */
	+#define PLAT_ARCH_IS_LITTLE() AL_TRUE
	+
	+/* INDENT-OFF */
	+#ifdef __cplusplus
	+}
	+#endif
	+/* INDENT-ON */
	+/** @} end of Platform Services API group */
	+
	+#endif /* __PLAT_TYPES_H__ */
	Index: sys/arm/annapurna/alpine/hal/al_hal_reg_utils.h
	===================================================================
	--- /dev/null
	+++ sys/arm/annapurna/alpine/hal/al_hal_reg_utils.h
	@@ -0,0 +1,188 @@
	+/*-
	+********************************************************************************
	+Copyright (C) 2015 Annapurna Labs Ltd.
	+
	+This file may be licensed under the terms of the Annapurna Labs Commercial
	+License Agreement.
	+
	+Alternatively, this file can be distributed under the terms of the GNU General
	+Public License V2 as published by the Free Software Foundation and can be
	+found at http://www.gnu.org/licenses/gpl-2.0.html
	+
	+Alternatively, redistribution and use in source and binary forms, with or
	+without modification, are permitted provided that the following conditions are
	+met:
	+
	+ * Redistributions of source code must retain the above copyright notice,
	+this list of conditions and the following disclaimer.
	+
	+ * Redistributions in binary form must reproduce the above copyright
	+notice, this list of conditions and the following disclaimer in
	+the documentation and/or other materials provided with the
	+distribution.
	+
	+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
	+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
	+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
	+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
	+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
	+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
	+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
	+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
	+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
	+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	+
	+*******************************************************************************/
	+
	+/**
	+ * @defgroup group_common HAL Common Layer
	+ * @{
	+ * @file al_hal_reg_utils.h
	+ *
	+ * @brief Register utilities used by HALs and platform layer
	+ *
	+ *
	+ */
	+
	+#ifndef __AL_HAL_REG_UTILS_H__
	+#define __AL_HAL_REG_UTILS_H__
	+
	+#include "al_hal_plat_types.h"
	+#include "al_hal_plat_services.h"
	+
	+/* INDENT-OFF */
	+#ifdef __cplusplus
	+extern "C" {
	+#endif
	+/* INDENT-ON */
	+
	+#define AL_BIT(b) (1UL << (b))
	+
	+#define AL_ADDR_LOW(x) ((uint32_t)((al_phys_addr_t)(x)))
	+#define AL_ADDR_HIGH(x) ((uint32_t)((((al_phys_addr_t)(x)) >> 16) >> 16))
	+
	+/** get field out of 32 bit register */
	+#define AL_REG_FIELD_GET(reg, mask, shift) (((reg) & (mask)) >> (shift))
	+
	+/** set field of 32 bit register */
	+#define AL_REG_FIELD_SET(reg, mask, shift, val) \
	+ (reg) = \
	+ (((reg) & (~(mask))) \| \
	+ ((((unsigned)(val)) << (shift)) & (mask)))
	+
	+/** set field of 64 bit register */
	+#define AL_REG_FIELD_SET_64(reg, mask, shift, val) \
	+ ((reg) = \
	+ (((reg) & (~(mask))) \| \
	+ ((((uint64_t)(val)) << (shift)) & (mask))))
	+
	+/** get single bit out of 32 bit register */
	+#define AL_REG_BIT_GET(reg, shift) \
	+ AL_REG_FIELD_GET(reg, AL_BIT(shift), shift)
	+
	+#define AL_REG_BITS_FIELD(shift, val) \
	+ (((unsigned)(val)) << (shift))
	+
	+/** set single bit field of 32 bit register to a given value */
	+#define AL_REG_BIT_VAL_SET(reg, shift, val) \
	+ AL_REG_FIELD_SET(reg, AL_BIT(shift), shift, val)
	+
	+/** set single bit of 32 bit register to 1 */
	+#define AL_REG_BIT_SET(reg, shift) \
	+ AL_REG_BIT_VAL_SET(reg, shift, 1)
	+
	+/** clear single bit of 32 bit register */
	+#define AL_REG_BIT_CLEAR(reg, shift) \
	+ AL_REG_BIT_VAL_SET(reg, shift, 0)
	+
	+
	+#define AL_BIT_MASK(n) \
	+ (AL_BIT(n) - 1)
	+
	+#define AL_FIELD_MASK(msb, lsb) \
	+ (AL_BIT(msb) + AL_BIT_MASK(msb) - AL_BIT_MASK(lsb))
	+
	+/** clear bits specified by clear_mask */
	+#define AL_REG_MASK_CLEAR(reg, clear_mask) \
	+ ((reg) = (((reg) & (~(clear_mask)))))
	+
	+/** set bits specified by clear_mask */
	+#define AL_REG_MASK_SET(reg, clear_mask) \
	+ ((reg) = (((reg) \| (clear_mask))))
	+
	+
	+/** clear bits specified by clear_mask, and set bits specified by set_mask */
	+#define AL_REG_CLEAR_AND_SET(reg, clear_mask, set_mask) \
	+ (reg) = (((reg) & (~(clear_mask))) \| (set_mask))
	+
	+#define AL_ALIGN_UP(val, size) \
	+ ((size) * (((val) + (size) - 1) / (size)))
	+
	+/** take bits selected by mask from one data, the rest from background */
	+#define AL_MASK_VAL(mask, data, background) \
	+ (((mask) & (data)) \| ((~mask) & (background)))
	+
	+/**
	+ * 8 bits register masked write
	+ *
	+ * @param reg
	+ * register address
	+ * @param mask
	+ * bits not selected (1) by mask will be left unchanged
	+ * @param data
	+ * data to write. bits not selected by mask ignored.
	+ */
	+static inline void
	+al_reg_write8_masked(uint8_t __iomem *reg, uint8_t mask, uint8_t data)
	+{
	+ uint8_t temp;
	+ temp = al_reg_read8(reg);
	+ al_reg_write8(reg, AL_MASK_VAL(mask, data, temp));
	+}
	+
	+
	+/**
	+ * 16 bits register masked write
	+ *
	+ * @param reg
	+ * register address
	+ * @param mask
	+ * bits not selected (1) by mask will be left unchanged
	+ * @param data
	+ * data to write. bits not selected by mask ignored.
	+ */
	+static inline void
	+al_reg_write16_masked(uint16_t __iomem *reg, uint16_t mask, uint16_t data)
	+{
	+ uint16_t temp;
	+ temp = al_reg_read16(reg);
	+ al_reg_write16(reg, AL_MASK_VAL(mask, data, temp));
	+}
	+
	+
	+/**
	+ * 32 bits register masked write
	+ *
	+ * @param reg
	+ * register address
	+ * @param mask
	+ * bits not selected (1) by mask will be left unchanged
	+ * @param data
	+ * data to write. bits not selected by mask ignored.
	+ */
	+static inline void
	+al_reg_write32_masked(uint32_t __iomem *reg, uint32_t mask, uint32_t data)
	+{
	+ uint32_t temp;
	+ temp = al_reg_read32(reg);
	+ al_reg_write32(reg, AL_MASK_VAL(mask, data, temp));
	+}
	+
	+/* INDENT-OFF */
	+#ifdef __cplusplus
	+}
	+#endif
	+/* INDENT-ON */
	+/** @} end of Common group */
	+#endif
	+
	Index: sys/arm/annapurna/alpine/hal/al_hal_types.h
	===================================================================
	--- /dev/null
	+++ sys/arm/annapurna/alpine/hal/al_hal_types.h
	@@ -0,0 +1,117 @@
	+/*-
	+********************************************************************************
	+Copyright (C) 2015 Annapurna Labs Ltd.
	+
	+This file may be licensed under the terms of the Annapurna Labs Commercial
	+License Agreement.
	+
	+Alternatively, this file can be distributed under the terms of the GNU General
	+Public License V2 as published by the Free Software Foundation and can be
	+found at http://www.gnu.org/licenses/gpl-2.0.html
	+
	+Alternatively, redistribution and use in source and binary forms, with or
	+without modification, are permitted provided that the following conditions are
	+met:
	+
	+ * Redistributions of source code must retain the above copyright notice,
	+this list of conditions and the following disclaimer.
	+
	+ * Redistributions in binary form must reproduce the above copyright
	+notice, this list of conditions and the following disclaimer in
	+the documentation and/or other materials provided with the
	+distribution.
	+
	+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
	+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
	+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
	+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
	+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
	+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
	+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
	+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
	+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
	+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	+
	+*******************************************************************************/
	+
	+/**
	+ * @defgroup group_common HAL Common Layer
	+ * @{
	+ * @file al_hal_types.h
	+ *
	+ * @brief macros used by HALs and platform layer
	+ *
	+ */
	+
	+#ifndef __AL_HAL_TYPES_H__
	+#define __AL_HAL_TYPES_H__
	+
	+#include "al_hal_plat_types.h"
	+#include "al_hal_plat_services.h"
	+
	+/* INDENT-OFF */
	+#ifdef __cplusplus
	+extern "C" {
	+#endif
	+/* INDENT-ON */
	+
	+/* Common defines */
	+
	+#if (!AL_TRUE) \|\| (AL_FALSE)
	+#error "AL_TRUE must be non zero and AL_FALSE must be zero"
	+#endif
	+
	+typedef int AL_RETURN;
	+
	+#if !defined(NULL)
	+#define NULL (void *)0
	+#endif
	+
	+#if !defined(likely)
	+#define likely(x) (__builtin_expect(!!(x), 1))
	+#define unlikely(x) (__builtin_expect(!!(x), 0))
	+#endif
	+
	+
	+#ifdef __GNUC__
	+#if !defined(__packed)
	+#define __packed __attribute__ ((packed))
	+#endif
	+ /* packed and alinged types */
	+#define __packed_a4 __attribute__ ((packed, aligned(4)))
	+#define __packed_a8 __attribute__ ((packed, aligned(8)))
	+#define __packed_a16 __attribute__ ((packed, aligned(16)))
	+
	+#else
	+#if !defined(__packed)
	+#error "__packed is not defined!!"
	+#endif
	+#endif
	+
	+#if !defined(__iomem)
	+#define __iomem
	+#endif
	+
	+#if !defined(__cache_aligned)
	+#ifdef __GNUC__
	+#define __cache_aligned __attribute__ ((__aligned__(64)))
	+#else
	+#define __cache_aligned
	+#endif
	+#endif
	+
	+#if !defined(INLINE)
	+#ifdef __GNUC__
	+#define INLINE inline
	+#else
	+#define INLINE
	+#endif
	+#endif
	+
	+/* INDENT-OFF */
	+#ifdef __cplusplus
	+}
	+#endif
	+/* INDENT-ON */
	+/** @} end of Common group */
	+#endif /* __TYPES_H__ */
	Index: sys/arm/annapurna/alpine/hal/al_hal_unit_adapter_regs.h
	===================================================================
	--- /dev/null
	+++ sys/arm/annapurna/alpine/hal/al_hal_unit_adapter_regs.h
	@@ -0,0 +1,314 @@
	+/*-
	+********************************************************************************
	+Copyright (C) 2015 Annapurna Labs Ltd.
	+
	+This file may be licensed under the terms of the Annapurna Labs Commercial
	+License Agreement.
	+
	+Alternatively, this file can be distributed under the terms of the GNU General
	+Public License V2 as published by the Free Software Foundation and can be
	+found at http://www.gnu.org/licenses/gpl-2.0.html
	+
	+Alternatively, redistribution and use in source and binary forms, with or
	+without modification, are permitted provided that the following conditions are
	+met:
	+
	+ * Redistributions of source code must retain the above copyright notice,
	+this list of conditions and the following disclaimer.
	+
	+ * Redistributions in binary form must reproduce the above copyright
	+notice, this list of conditions and the following disclaimer in
	+the documentation and/or other materials provided with the
	+distribution.
	+
	+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
	+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
	+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
	+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
	+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
	+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
	+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
	+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
	+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
	+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	+
	+*******************************************************************************/
	+
	+#ifndef __AL_HAL_UNIT_ADAPTER_REGS_H__
	+#define __AL_HAL_UNIT_ADAPTER_REGS_H__
	+
	+#ifdef __cplusplus
	+extern "C" {
	+#endif
	+
	+#define AL_PCI_COMMAND 0x04 /* 16 bits */
	+#define AL_PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
	+#define AL_PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
	+#define AL_PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */
	+
	+#define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8 revision */
	+
	+#define AL_PCI_BASE_ADDRESS_SPACE_IO 0x01
	+#define AL_PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */
	+#define AL_PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 /* prefetchable? */
	+#define AL_PCI_BASE_ADDRESS_DEVICE_ID 0x0c
	+
	+#define AL_PCI_BASE_ADDRESS_0 0x10
	+#define AL_PCI_BASE_ADDRESS_0_HI 0x14
	+#define AL_PCI_BASE_ADDRESS_2 0x18
	+#define AL_PCI_BASE_ADDRESS_2_HI 0x1c
	+#define AL_PCI_BASE_ADDRESS_4 0x20
	+#define AL_PCI_BASE_ADDRESS_4_HI 0x24
	+
	+#define AL_PCI_EXP_ROM_BASE_ADDRESS 0x30
	+
	+#define AL_PCI_AXI_CFG_AND_CTR_0 0x110
	+#define AL_PCI_AXI_CFG_AND_CTR_1 0x130
	+#define AL_PCI_AXI_CFG_AND_CTR_2 0x150
	+#define AL_PCI_AXI_CFG_AND_CTR_3 0x170
	+
	+#define AL_PCI_APP_CONTROL 0x220
	+
	+#define AL_PCI_SRIOV_TOTAL_AND_INITIAL_VFS 0x30c
	+
	+#define AL_PCI_VF_BASE_ADDRESS_0 0x324
	+
	+
	+#define AL_PCI_EXP_CAP_BASE 0x40
	+#define AL_PCI_EXP_DEVCAP 4 /* Device capabilities */
	+#define AL_PCI_EXP_DEVCAP_PAYLOAD 0x07 /* Max_Payload_Size */
	+#define AL_PCI_EXP_DEVCAP_PHANTOM 0x18 /* Phantom functions */
	+#define AL_PCI_EXP_DEVCAP_EXT_TAG 0x20 /* Extended tags */
	+#define AL_PCI_EXP_DEVCAP_L0S 0x1c0 /* L0s Acceptable Latency */
	+#define AL_PCI_EXP_DEVCAP_L1 0xe00 /* L1 Acceptable Latency */
	+#define AL_PCI_EXP_DEVCAP_ATN_BUT 0x1000 /* Attention Button Present */
	+#define AL_PCI_EXP_DEVCAP_ATN_IND 0x2000 /* Attention Indicator Present */
	+#define AL_PCI_EXP_DEVCAP_PWR_IND 0x4000 /* Power Indicator Present */
	+#define AL_PCI_EXP_DEVCAP_RBER 0x8000 /* Role-Based Error Reporting */
	+#define AL_PCI_EXP_DEVCAP_PWR_VAL 0x3fc0000 /* Slot Power Limit Value */
	+#define AL_PCI_EXP_DEVCAP_PWR_SCL 0xc000000 /* Slot Power Limit Scale */
	+#define AL_PCI_EXP_DEVCAP_FLR 0x10000000 /* Function Level Reset */
	+#define AL_PCI_EXP_DEVCTL 8 /* Device Control */
	+#define AL_PCI_EXP_DEVCTL_CERE 0x0001 /* Correctable Error Reporting En. */
	+#define AL_PCI_EXP_DEVCTL_NFERE 0x0002 /* Non-Fatal Error Reporting Enable */
	+#define AL_PCI_EXP_DEVCTL_FERE 0x0004 /* Fatal Error Reporting Enable */
	+#define AL_PCI_EXP_DEVCTL_URRE 0x0008 /* Unsupported Request Reporting En. */
	+#define AL_PCI_EXP_DEVCTL_RELAX_EN 0x0010 /* Enable relaxed ordering */
	+#define AL_PCI_EXP_DEVCTL_PAYLOAD 0x00e0 /* Max_Payload_Size */
	+#define AL_PCI_EXP_DEVCTL_EXT_TAG 0x0100 /* Extended Tag Field Enable */
	+#define AL_PCI_EXP_DEVCTL_PHANTOM 0x0200 /* Phantom Functions Enable */
	+#define AL_PCI_EXP_DEVCTL_AUX_PME 0x0400 /* Auxiliary Power PM Enable */
	+#define AL_PCI_EXP_DEVCTL_NOSNOOP_EN 0x0800 /* Enable No Snoop */
	+#define AL_PCI_EXP_DEVCTL_READRQ 0x7000 /* Max_Read_Request_Size */
	+#define AL_PCI_EXP_DEVCTL_BCR_FLR 0x8000 /* Bridge Configuration Retry / FLR */
	+#define AL_PCI_EXP_DEVSTA 0xA /* Device Status */
	+#define AL_PCI_EXP_DEVSTA_CED 0x01 /* Correctable Error Detected */
	+#define AL_PCI_EXP_DEVSTA_NFED 0x02 /* Non-Fatal Error Detected */
	+#define AL_PCI_EXP_DEVSTA_FED 0x04 /* Fatal Error Detected */
	+#define AL_PCI_EXP_DEVSTA_URD 0x08 /* Unsupported Request Detected */
	+#define AL_PCI_EXP_DEVSTA_AUXPD 0x10 /* AUX Power Detected */
	+#define AL_PCI_EXP_DEVSTA_TRPND 0x20 /* Transactions Pending */
	+#define AL_PCI_EXP_LNKCAP 0xC /* Link Capabilities */
	+#define AL_PCI_EXP_LNKCAP_SLS 0xf /* Supported Link Speeds */
	+#define AL_PCI_EXP_LNKCAP_SLS_2_5GB 0x1 /* LNKCAP2 SLS Vector bit 0 (2.5GT/s) */
	+#define AL_PCI_EXP_LNKCAP_SLS_5_0GB 0x2 /* LNKCAP2 SLS Vector bit 1 (5.0GT/s) */
	+#define AL_PCI_EXP_LNKCAP_MLW 0x3f0 /* Maximum Link Width */
	+#define AL_PCI_EXP_LNKCAP_ASPMS 0xc00 /* ASPM Support */
	+#define AL_PCI_EXP_LNKCAP_L0SEL 0x7000 /* L0s Exit Latency */
	+#define AL_PCI_EXP_LNKCAP_L1EL 0x38000 /* L1 Exit Latency */
	+#define AL_PCI_EXP_LNKCAP_CLKPM 0x40000 /* L1 Clock Power Management */
	+#define AL_PCI_EXP_LNKCAP_SDERC 0x80000 /* Surprise Down Error Reporting Capable */
	+#define AL_PCI_EXP_LNKCAP_DLLLARC 0x100000 /* Data Link Layer Link Active Reporting Capable */
	+#define AL_PCI_EXP_LNKCAP_LBNC 0x200000 /* Link Bandwidth Notification Capability */
	+#define AL_PCI_EXP_LNKCAP_PN 0xff000000 /* Port Number */
	+
	+#define AL_PCI_EXP_LNKCTL 0x10 /* Link Control */
	+#define AL_PCI_EXP_LNKCTL_LNK_DIS 0x4 /* Link Disable Status */
	+#define AL_PCI_EXP_LNKCTL_LNK_RTRN 0x5 /* Link Retrain Status */
	+
	+#define AL_PCI_EXP_LNKSTA 0x12 /* Link Status */
	+#define AL_PCI_EXP_LNKSTA_CLS 0x000f /* Current Link Speed */
	+#define AL_PCI_EXP_LNKSTA_CLS_2_5GB 0x01 /* Current Link Speed 2.5GT/s */
	+#define AL_PCI_EXP_LNKSTA_CLS_5_0GB 0x02 /* Current Link Speed 5.0GT/s */
	+#define AL_PCI_EXP_LNKSTA_CLS_8_0GB 0x03 /* Current Link Speed 8.0GT/s */
	+#define AL_PCI_EXP_LNKSTA_NLW 0x03f0 /* Nogotiated Link Width */
	+#define AL_PCI_EXP_LNKSTA_NLW_SHIFT 4 /* start of NLW mask in link status */
	+#define AL_PCI_EXP_LNKSTA_LT 0x0800 /* Link Training */
	+#define AL_PCI_EXP_LNKSTA_SLC 0x1000 /* Slot Clock Configuration */
	+#define AL_PCI_EXP_LNKSTA_DLLLA 0x2000 /* Data Link Layer Link Active */
	+#define AL_PCI_EXP_LNKSTA_LBMS 0x4000 /* Link Bandwidth Management Status */
	+#define AL_PCI_EXP_LNKSTA_LABS 0x8000 /* Link Autonomous Bandwidth Status */
	+
	+#define AL_PCI_EXP_LNKCTL2 0x30 /* Link Control 2 */
	+
	+#define AL_PCI_MSIX_MSGCTRL 0 /* MSIX message control reg */
	+#define AL_PCI_MSIX_MSGCTRL_TBL_SIZE 0x7ff /* MSIX table size */
	+#define AL_PCI_MSIX_MSGCTRL_TBL_SIZE_SHIFT 16 /* MSIX table size shift */
	+#define AL_PCI_MSIX_MSGCTRL_EN 0x80000000 /* MSIX enable */
	+#define AL_PCI_MSIX_MSGCTRL_MASK 0x40000000 /* MSIX mask */
	+
	+#define AL_PCI_MSIX_TABLE 0x4 /* MSIX table offset and bar reg */
	+#define AL_PCI_MSIX_TABLE_OFFSET 0xfffffff8 /* MSIX table offset */
	+#define AL_PCI_MSIX_TABLE_BAR 0x7 /* MSIX table BAR */
	+
	+#define AL_PCI_MSIX_PBA 0x8 /* MSIX pba offset and bar reg */
	+#define AL_PCI_MSIX_PBA_OFFSET 0xfffffff8 /* MSIX pba offset */
	+#define AL_PCI_MSIX_PBA_BAR 0x7 /* MSIX pba BAR */
	+
	+
	+/* Adapter power management register 0 */
	+#define AL_ADAPTER_PM_0 0x80
	+#define AL_ADAPTER_PM_0_PM_NEXT_CAP_MASK 0xff00
	+#define AL_ADAPTER_PM_0_PM_NEXT_CAP_SHIFT 8
	+#define AL_ADAPTER_PM_0_PM_NEXT_CAP_VAL_MSIX 0x90
	+
	+/* Adapter power management register 1 */
	+#define AL_ADAPTER_PM_1 0x84
	+#define AL_ADAPTER_PM_1_PME_EN 0x100 /* PM enable */
	+#define AL_ADAPTER_PM_1_PWR_STATE_MASK 0x3 /* PM state mask */
	+#define AL_ADAPTER_PM_1_PWR_STATE_D3 0x3 /* PM D3 state */
	+
	+/* Sub Master Configuration & Control */
	+#define AL_ADAPTER_SMCC 0x110
	+#define AL_ADAPTER_SMCC_CONF_2 0x114
	+
	+/* Interrupt_Cause register */
	+#define AL_ADAPTER_INT_CAUSE 0x1B0
	+#define AL_ADAPTER_INT_CAUSE_WR_ERR AL_BIT(1)
	+#define AL_ADAPTER_INT_CAUSE_RD_ERR AL_BIT(0)
	+
	+/* AXI_Master_Write_Error_Attribute_Latch register */
	+/* AXI_Master_Read_Error_Attribute_Latch register */
	+#define AL_ADAPTER_AXI_MSTR_WR_ERR_ATTR 0x1B4
	+#define AL_ADAPTER_AXI_MSTR_RD_ERR_ATTR 0x1B8
	+
	+#define AL_ADAPTER_AXI_MSTR_RD_WR_ERR_ATTR_COMP_STAT_MASK AL_FIELD_MASK(1, 0)
	+#define AL_ADAPTER_AXI_MSTR_RD_WR_ERR_ATTR_COMP_STAT_SHIFT 0
	+#define AL_ADAPTER_AXI_MSTR_RD_WR_ERR_ATTR_MSTR_ID_MASK AL_FIELD_MASK(4, 2)
	+#define AL_ADAPTER_AXI_MSTR_RD_WR_ERR_ATTR_MSTR_ID_SHIFT 2
	+#define AL_ADAPTER_AXI_MSTR_RD_WR_ERR_ATTR_ADDR_TO AL_BIT(8)
	+#define AL_ADAPTER_AXI_MSTR_RD_WR_ERR_ATTR_COMP_ERR AL_BIT(9)
	+#define AL_ADAPTER_AXI_MSTR_RD_WR_ERR_ATTR_COMP_TO AL_BIT(10)
	+#define AL_ADAPTER_AXI_MSTR_RD_WR_ERR_ATTR_ERR_BLK AL_BIT(11)
	+#define AL_ADAPTER_AXI_MSTR_RD_ERR_ATTR_RD_PARITY_ERR AL_BIT(12)
	+
	+/* Interrupt_Cause_mask register */
	+#define AL_ADAPTER_INT_CAUSE_MASK 0x1BC
	+#define AL_ADAPTER_INT_CAUSE_MASK_WR_ERR AL_BIT(1)
	+#define AL_ADAPTER_INT_CAUSE_MASK_RD_ERR AL_BIT(0)
	+
	+/* AXI_Master_write_error_address_Latch register */
	+#define AL_ADAPTER_AXI_MSTR_WR_ERR_LO_LATCH 0x1C0
	+
	+/* AXI_Master_write_error_address_high_Latch register */
	+#define AL_ADAPTER_AXI_MSTR_WR_ERR_HI_LATCH 0x1C4
	+
	+/* AXI_Master_read_error_address_Latch register */
	+#define AL_ADAPTER_AXI_MSTR_RD_ERR_LO_LATCH 0x1C8
	+
	+/* AXI_Master_read_error_address_high_Latch register */
	+#define AL_ADAPTER_AXI_MSTR_RD_ERR_HI_LATCH 0x1CC
	+
	+/* AXI_Master_Timeout register */
	+#define AL_ADAPTER_AXI_MSTR_TO 0x1D0
	+#define AL_ADAPTER_AXI_MSTR_TO_WR_MASK AL_FIELD_MASK(31, 16)
	+#define AL_ADAPTER_AXI_MSTR_TO_WR_SHIFT 16
	+#define AL_ADAPTER_AXI_MSTR_TO_RD_MASK AL_FIELD_MASK(15, 0)
	+#define AL_ADAPTER_AXI_MSTR_TO_RD_SHIFT 0
	+
	+/*
	+ * Generic control registers
	+ */
	+
	+/* Control 0 */
	+#define AL_ADAPTER_GENERIC_CONTROL_0 0x1E0
	+/* Control 2 */
	+#define AL_ADAPTER_GENERIC_CONTROL_2 0x1E8
	+/* Control 3 */
	+#define AL_ADAPTER_GENERIC_CONTROL_3 0x1EC
	+/* Control 9 */
	+#define AL_ADAPTER_GENERIC_CONTROL_9 0x218
	+/* Control 10 */
	+#define AL_ADAPTER_GENERIC_CONTROL_10 0x21C
	+/* Control 11 */
	+#define AL_ADAPTER_GENERIC_CONTROL_11 0x220
	+/* Control 12 */
	+#define AL_ADAPTER_GENERIC_CONTROL_12 0x224
	+/* Control 13 */
	+#define AL_ADAPTER_GENERIC_CONTROL_13 0x228
	+/* Control 14 */
	+#define AL_ADAPTER_GENERIC_CONTROL_14 0x22C
	+/* Control 15 */
	+#define AL_ADAPTER_GENERIC_CONTROL_15 0x230
	+/* Control 16 */
	+#define AL_ADAPTER_GENERIC_CONTROL_16 0x234
	+/* Control 17 */
	+#define AL_ADAPTER_GENERIC_CONTROL_17 0x238
	+/* Control 18 */
	+#define AL_ADAPTER_GENERIC_CONTROL_18 0x23C
	+/* Control 19 */
	+#define AL_ADAPTER_GENERIC_CONTROL_19 0x240
	+
	+/* Enable clock gating */
	+#define AL_ADAPTER_GENERIC_CONTROL_0_CLK_GATE_EN 0x01
	+/* When set, all transactions through the PCI conf & mem BARs get timeout */
	+#define AL_ADAPTER_GENERIC_CONTROL_0_ADAPTER_DIS 0x40
	+#define AL_ADAPTER_GENERIC_CONTROL_0_ETH_RESET_1GMAC AL_BIT(18)
	+#define AL_ADAPTER_GENERIC_CONTROL_0_ETH_RESET_1GMAC_ON_FLR AL_BIT(26)
	+
	+/*
	+ * SATA registers only
	+ */
	+/* Select 125MHz free running clock from IOFAB main PLL as SATA OOB clock
	+ * instead of using power management ref clock
	+ */
	+#define AL_ADAPTER_GENERIC_CONTROL_10_SATA_OOB_CLK_SEL AL_BIT(26)
	+/* AXUSER selection and value per bit (1 = address, 0 = register) */
	+/* Rx */
	+#define AL_ADPTR_GEN_CTL_12_SATA_AWUSER_VAL_MASK AL_FIELD_MASK(15, 0)
	+#define AL_ADPTR_GEN_CTL_12_SATA_AWUSER_VAL_SHIFT 0
	+#define AL_ADPTR_GEN_CTL_12_SATA_AWUSER_SEL_MASK AL_FIELD_MASK(31, 16)
	+#define AL_ADPTR_GEN_CTL_12_SATA_AWUSER_SEL_SHIFT 16
	+/* Tx */
	+#define AL_ADPTR_GEN_CTL_13_SATA_ARUSER_VAL_MASK AL_FIELD_MASK(15, 0)
	+#define AL_ADPTR_GEN_CTL_13_SATA_ARUSER_VAL_SHIFT 0
	+#define AL_ADPTR_GEN_CTL_13_SATA_ARUSER_SEL_MASK AL_FIELD_MASK(31, 16)
	+#define AL_ADPTR_GEN_CTL_13_SATA_ARUSER_SEL_SHIFT 16
	+/* Central VMID enabler. If set, then each entry will be used as programmed */
	+#define AL_ADPTR_GEN_CTL_14_SATA_MSIX_VMID_SEL AL_BIT(0)
	+/* Allow access to store VMID values per entry */
	+#define AL_ADPTR_GEN_CTL_14_SATA_MSIX_VMID_ACCESS_EN AL_BIT(1)
	+/* VMID Address select */
	+/* Tx */
	+#define AL_ADPTR_GEN_CTL_14_SATA_VM_ARADDR_SEL_MASK AL_FIELD_MASK(13, 8)
	+#define AL_ADPTR_GEN_CTL_14_SATA_VM_ARADDR_SEL_SHIFT 8
	+/* Rx */
	+#define AL_ADPTR_GEN_CTL_14_SATA_VM_AWADDR_SEL_MASK AL_FIELD_MASK(21, 16)
	+#define AL_ADPTR_GEN_CTL_14_SATA_VM_AWADDR_SEL_SHIFT 16
	+/* Address Value */
	+/* Rx */
	+#define AL_ADPTR_GEN_CTL_15_SATA_VM_AWDDR_HI AL_FIELD_MASK(31, 0)
	+/* Tx */
	+#define AL_ADPTR_GEN_CTL_16_SATA_VM_ARDDR_HI AL_FIELD_MASK(31, 0)
	+
	+/*
	+ * ROB registers
	+ */
	+/* Read ROB_Enable, when disabled the read ROB is bypassed */
	+#define AL_ADPTR_GEN_CTL_19_READ_ROB_EN AL_BIT(0)
	+/* Read force in-order of every read transaction */
	+#define AL_ADPTR_GEN_CTL_19_READ_ROB_FORCE_INORDER AL_BIT(1)
	+/* Read software reset */
	+#define AL_ADPTR_GEN_CTL_19_READ_ROB_SW_RESET AL_BIT(15)
	+/* Write ROB_Enable, when disabled_the_Write ROB is bypassed */
	+#define AL_ADPTR_GEN_CTL_19_WRITE_ROB_EN AL_BIT(16)
	+/* Write force in-order of every write transaction */
	+#define AL_ADPTR_GEN_CTL_19_WRITE_ROB_FORCE_INORDER AL_BIT(17)
	+/* Write software reset */
	+#define AL_ADPTR_GEN_CTL_19_WRITE_ROB_SW_RESET AL_BIT(31)
	+
	+#ifdef __cplusplus
	+}
	+#endif
	+
	+#endif
	Index: sys/arm/annapurna/alpine/std.alpine
	===================================================================
	--- /dev/null
	+++ sys/arm/annapurna/alpine/std.alpine
	@@ -0,0 +1,23 @@
	+# $FreeBSD$
	+
	+makeoption ARM_LITTLE_ENDIAN
	+
	+cpu CPU_CORTEXA
	+machine arm armv6
	+makeoptions CONF_CFLAGS="-march=armv7a -DAL_HAVE_TYPES"
	+
	+makeoptions KERNPHYSADDR=0x00200000
	+options KERNPHYSADDR=0x00200000
	+
	+makeoptions KERNVIRTADDR=0xa0200000
	+options KERNVIRTADDR=0xa0200000
	+
	+makeoptions KERNBASE=0xa0000000
	+options KERNBASE=0xa0000000
	+
	+options ARM_L2_PIPT
	+
	+options IPI_IRQ_START=0
	+options IPI_IRQ_END=15
	+
	+files "../annapurna/alpine/files.alpine"
	Index: sys/arm/conf/ALPINE
	===================================================================
	--- /dev/null
	+++ sys/arm/conf/ALPINE
	@@ -0,0 +1,83 @@
	+# Kernel configuration for Alpine Board.
	+#
	+# For more information on this file, please read the config(5) manual page,
	+# and/or the handbook section on Kernel Configuration Files:
	+#
	+# http://www.FreeBSD.org/doc/en_US.ISO8859-1/books/handbook/kernelconfig-config.html
	+#
	+# The handbook is also available locally in /usr/share/doc/handbook
	+# if you've installed the doc distribution, otherwise always see the
	+# FreeBSD World Wide Web server (http://www.FreeBSD.org/) for the
	+# latest information.
	+#
	+# An exhaustive list of options and more detailed explanations of the
	+# device lines is also present in the ../../conf/NOTES and NOTES files.
	+# If you are in doubt as to the purpose or necessity of a line, check first
	+# in NOTES.
	+#
	+# $FreeBSD$
	+
	+ident ALPINE
	+
	+include "std.armv6"
	+include "../annapurna/alpine/std.alpine"
	+
	+makeoptions MODULES_OVERRIDE=""
	+makeoptions WERROR="-Werror"
	+
	+options HZ=100
	+options SCHED_4BSD # 4BSD scheduler
	+options SMP # Enable multiple cores
	+
	+# Debugging
	+makeoptions DEBUG=-g #Build kernel with gdb(1) debug symbols
	+options BREAK_TO_DEBUGGER
	+options KDB
	+options DDB #Enable the kernel debugger
	+
	+# NFS support
	+options NFSCL #Network Filesystem Client
	+options NFSLOCKD #Network Lock Manager
	+options NFS_ROOT #NFS usable as /, requires NFSCLIENT
	+
	+# Interrupt controller
	+device gic
	+
	+# Pseudo devices
	+device loop
	+device random
	+device pty
	+device md
	+device gpio
	+
	+# ATA controllers
	+device ahci # AHCI-compatible SATA controllers
	+device ata # Legacy ATA/SATA controllers
	+options ATA_STATIC_ID # Static device numbering
	+
	+# ATA/SCSI peripherals
	+device scbus # SCSI bus (required for ATA/SCSI)
	+device ch # SCSI media changers
	+device da # Direct Access (disks)
	+device sa # Sequential Access (tape etc)
	+device cd # CD
	+device pass # Passthrough device (direct ATA/SCSI access)
	+device ses # Enclosure Services (SES and SAF-TE)
	+#device ctl # CAM Target Layer
	+
	+# Serial ports
	+device uart
	+
	+# Ethernet
	+device ether
	+device mii
	+device bpf
	+options DEVICE_POLLING
	+
	+# USB ethernet support, requires miibus
	+device miibus
	+
	+#FDT
	+options FDT
	+options FDT_DTB_STATIC
	+makeoptions FDT_DTS_FILE=annapurna-alpine.dts
	Index: sys/boot/fdt/dts/arm/annapurna-alpine.dts
	===================================================================
	--- /dev/null
	+++ sys/boot/fdt/dts/arm/annapurna-alpine.dts
	@@ -0,0 +1,244 @@
	+/*-
	+ * Copyright (c) 2013 Ruslan Bukin <br@bsdpad.com>
	+ * Copyright (c) 2015 Semihalf
	+ * All rights reserved.
	+ *
	+ * Redistribution and use in source and binary forms, with or without
	+ * modification, are permitted provided that the following conditions
	+ * are met:
	+ * 1. Redistributions of source code must retain the above copyright
	+ * notice, this list of conditions and the following disclaimer.
	+ * 2. Redistributions in binary form must reproduce the above copyright
	+ * notice, this list of conditions and the following disclaimer in the
	+ * documentation and/or other materials provided with the distribution.
	+ *
	+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
	+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
	+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
	+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
	+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
	+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
	+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
	+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
	+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
	+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
	+ * SUCH DAMAGE.
	+ *
	+ * $FreeBSD$
	+ */
	+
	+/dts-v1/;
	+
	+/ {
	+ model = "annapurna,alpine";
	+ #address-cells = <1>;
	+ #size-cells = <1>;
	+
	+ aliases {
	+ serial0 = &serial0;
	+ };
	+
	+ cpus {
	+ #address-cells = <1>;
	+ #size-cells = <0>;
	+
	+ cpu@0 {
	+ device_type = "cpu";
	+ compatible = "arm,cortex-a15";
	+ reg = <0x0>;
	+ d-cache-line-size = <64>; // 64 bytes
	+ i-cache-line-size = <64>; // 64 bytes
	+ d-cache-size = <0x8000>; // L1, 32K
	+ i-cache-size = <0x8000>; // L1, 32K
	+ timebase-frequency = <0>;
	+ bus-frequency = <375000000>;
	+ clock-frequency = <0>;
	+ };
	+
	+ cpu@1 {
	+ device_type = "cpu";
	+ compatible = "arm,cortex-a15";
	+ reg = <0x0>;
	+ d-cache-line-size = <64>; // 64 bytes
	+ i-cache-line-size = <64>; // 64 bytes
	+ d-cache-size = <0x8000>; // L1, 32K
	+ i-cache-size = <0x8000>; // L1, 32K
	+ timebase-frequency = <0>;
	+ bus-frequency = <375000000>;
	+ clock-frequency = <0>;
	+ };
	+
	+ cpu@2 {
	+ device_type = "cpu";
	+ compatible = "arm,cortex-a15";
	+ reg = <0x0>;
	+ d-cache-line-size = <64>; // 64 bytes
	+ i-cache-line-size = <64>; // 64 bytes
	+ d-cache-size = <0x8000>; // L1, 32K
	+ i-cache-size = <0x8000>; // L1, 32K
	+ timebase-frequency = <0>;
	+ bus-frequency = <375000000>;
	+ clock-frequency = <0>;
	+ };
	+
	+ cpu@3 {
	+ device_type = "cpu";
	+ compatible = "arm,cortex-a15";
	+ reg = <0x0>;
	+ d-cache-line-size = <64>; // 64 bytes
	+ i-cache-line-size = <64>; // 64 bytes
	+ d-cache-size = <0x8000>; // L1, 32K
	+ i-cache-size = <0x8000>; // L1, 32K
	+ timebase-frequency = <0>;
	+ bus-frequency = <375000000>;
	+ clock-frequency = <0>;
	+ };
	+ };
	+
	+ memory {
	+ device_type = "memory";
	+ reg = <0x00100000 0x7ff00000>; // 2047MB at 1MB
	+ };
	+
	+ soc {
	+ #address-cells = <1>;
	+ #size-cells = <1>;
	+ compatible = "simple-bus";
	+ ranges = <0x0 0xfb000000 0x03000000>;
	+ bus-frequency = <0>;
	+
	+ MPIC: interrupt-controller {
	+ compatible = "arm,gic";
	+ reg = < 0x1000 0x1000 >, /* Distributor Registers */
	+ < 0x2000 0x2000 >; /* CPU Interface Registers */
	+ interrupt-controller;
	+ #address-cells = <0>;
	+ #interrupt-cells = <3>;
	+
	+ // In intr[2], bits[3:0] are trigger type and level flags.
	+ // 1 = low-to-high edge triggered
	+ // 2 = high-to-low edge triggered
	+ // 4 = active high level-sensitive
	+ // 8 = active low level-sensitive
	+ // The hardware only supports active-high-level or rising-edge.
	+
	+ };
	+
	+ generic_timer {
	+ compatible = "arm,sp804";
	+ reg = <0x02890000 0x1000>;
	+ interrupts = <0 9 4>;
	+ interrupt-parent = <&MPIC>;
	+ clock-frequency = <375000000>;
	+ };
	+
	+ cpu_resume {
	+ compatible = "annapurna-labs,al-cpu-resume";
	+ reg = <0x00ff5ec0 0x30>;
	+ };
	+
	+ nb_service {
	+ compatible = "annapurna-labs,al-nb-service";
	+ reg = <0x00070000 0x10000>;
	+ interrupts = <0 32 4>,
	+ <0 33 4>,
	+ <0 34 4>,
	+ <0 35 4>;
	+ interrupt-parent = <&MPIC>;
	+ };
	+
	+ wdt0 {
	+ compatible = "arm,sp805", "arm,primecell";
	+ reg = <0x288c000 0x1000>;
	+ interrupt-parent = <&MPIC>;
	+ };
	+
	+ serial0: serial@2883000 {
	+ compatible = "ns16550";
	+ reg = <0x2883000 0x20>;
	+ reg-shift = <2>;
	+ current-speed = <115200>;
	+ clock-frequency = <375000000>;
	+ interrupts = <0 17 4>;
	+ interrupt-parent = <&MPIC>;
	+ };
	+ };
	+
	+ pcie-internal {
	+ compatible = "annapurna-labs,al-internal-pcie";
	+ device_type = "pci";
	+ #size-cells = <2>;
	+ #address-cells = <3>;
	+ interrupt-parent = <&MPIC>;
	+ interrupt-map-mask = <0xf800 0 0 7>;
	+ interrupt-map = <0x3000 0 0 1 &MPIC 0 32 4>, // USB adapter
	+ <0x3800 0 0 1 &MPIC 0 36 4>,
	+ <0x4000 0 0 1 &MPIC 0 43 4>, // SATA 0 (PCIe expander)
	+ <0x4800 0 0 1 &MPIC 0 44 1>; // SATA 1 (onboard)
	+
	+ // ranges:
	+ // - ECAM - non prefetchable config space
	+ // - 32 bit non prefetchable memory space
	+ ranges = <0x00000000 0x0 0xfbc00000 0xfbc00000 0x0 0x100000
	+ 0x02000000 0x0 0xfe000000 0xfe000000 0x0 0x1000000>;
	+
	+ bus-range = <0x00 0x00>;
	+ };
	+
	+// WORKAROUND: enabling PCIe controller when no card is plugged in
	+// leads to kernel panic because u-boot disables PCIe controller if no link
	+// is detected. Just be kind and compatible with Linux
	+/* // External PCIe Controller 0
	+ pcie-external0 {
	+ compatible = "annapurna-labs,al-external-pcie";
	+ reg = <0xfd800000 0x00020000>;
	+ device_type = "pci";
	+ #size-cells = <2>;
	+ #address-cells = <3>;
	+ interrupt-parent = <&MPIC>;
	+ interrupt-map-mask = <0x00 0 0 7>;
	+ interrupt-map = <0x0000 0 0 1 &MPIC 0 40 4>;
	+
	+ // ranges:
	+ // Controller 0:
	+ // - ECAM - non prefetchable config space: 2MB
	+ // - IO - IO port space 64KB, reserve 64KB from target memory windows
	+ // real IO address on the pci bus starts at 0x10000
	+ // - 32 bit non prefetchable memory space: 128MB - 64KB
	+
	+ ranges = <0x00000000 0x0 0xfb600000 0xfb600000 0x0 0x00200000
	+ 0x01000000 0x0 0x00010000 0xe0000000 0x0 0x00010000
	+ 0x02000000 0x0 0xe1000000 0xe1000000 0x0 0x06f00000>;
	+
	+ bus-range = <0x00 0xff>;
	+ };
	+
	+ // External PCIe Controllers 1
	+ pcie-external1 {
	+ compatible = "annapurna-labs,al-external-pcie";
	+ reg = <0xfd820000 0x00020000>;
	+ device_type = "pci";
	+ #size-cells = <2>;
	+ #address-cells = <3>;
	+ interrupt-parent = <&MPIC>;
	+ interrupt-map-mask = <0x0 0 0 7>;
	+ interrupt-map = <0x0000 0 0 1 &MPIC 0 41 4>;
	+
	+ // ranges:
	+ // - ECAM - non prefetchable config space: 2MB
	+ // - IO - IO port space 64KB, reserve 64KB from target memory windows
	+ // real IO address on the pci bus starts at 0x20000
	+ // - 32 bit non prefetchable memory space: 64MB - 64KB
	+ ranges = <0x00000000 0x0 0xfb800000 0xfb800000 0x0 0x00200000
	+ 0x01000000 0x0 0x00020000 0xe8000000 0x0 0x00010000
	+ 0x02000000 0x0 0xe8100000 0xe8100000 0x0 0x02ff0000>;
	+
	+ bus-range = <0x00 0xff>;
	+ }; */
	+
	+ chosen {
	+ stdin = "serial0";
	+ stdout = "serial0";
	+ stddbg = "serial0";
	+ };
	+};

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