D59487.diff
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	diff --git a/sys/arm64/iommu/smmu.c b/sys/arm64/iommu/smmu.c
	--- a/sys/arm64/iommu/smmu.c
	+++ b/sys/arm64/iommu/smmu.c
	@@ -567,43 +567,48 @@
	}
	}

	-static int
	-smmu_sync(struct smmu_softc *sc)
	+static void
	+smmu_sync_wait_msi(struct smmu_softc sc, struct smmu_queue q)
	{
	- struct smmu_cmdq_entry cmd;
	- struct smmu_queue *q;
	+ sbintime_t start;
	uint32_t *base;
	- int timeout;
	int prod;

	- q = &sc->cmdq;
	prod = q->lc.prod;

	- /* Enqueue sync command. */
	- cmd.opcode = CMD_SYNC;
	- cmd.sync.msiaddr = q->paddr + Q_IDX(q, prod) * CMDQ_ENTRY_DWORDS * 8;
	- smmu_cmdq_enqueue_cmd(sc, &cmd);
	-
	/* Wait for the sync completion. */
	base = (void *)((uint64_t)q->vaddr +
	Q_IDX(q, prod) * CMDQ_ENTRY_DWORDS * 8);

	- /*
	- * It takes around 200 loops (6 instructions each)
	- * on Neoverse N1 to complete the sync.
	- */
	- timeout = 10000;
	-
	+ start = getsbinuptime();
	do {
	- if (*base == 0) {
	+ if (atomic_load_32(base) == 0) {
	/* MSI write completed. */
	- break;
	+ return;
	}
	- cpu_spinwait();
	- } while (timeout--);
	+ DELAY(100);
	+ } while ((getsbinuptime() - start) < SBT_1S);

	- if (timeout < 0)
	+ if (atomic_load_32(base) != 0)
	device_printf(sc->dev, "Failed to sync\n");
	+}
	+
	+static int
	+smmu_sync(struct smmu_softc *sc)
	+{
	+ struct smmu_cmdq_entry cmd;
	+ struct smmu_queue *q;
	+ int prod;
	+
	+ q = &sc->cmdq;
	+ prod = q->lc.prod;
	+
	+ /* Enqueue sync command. */
	+ cmd.opcode = CMD_SYNC;
	+ cmd.sync.msiaddr = q->paddr + Q_IDX(q, prod) * CMDQ_ENTRY_DWORDS * 8;
	+ smmu_cmdq_enqueue_cmd(sc, &cmd);
	+
	+ smmu_sync_wait_msi(sc, q);

	return (0);
	}