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diff --git a/sys/powerpc/include/openpicreg.h b/sys/powerpc/include/openpicreg.h
--- a/sys/powerpc/include/openpicreg.h
+++ b/sys/powerpc/include/openpicreg.h
@@ -112,7 +112,7 @@
#define OPENPIC_ACTIVITY 0x40000000
#define OPENPIC_PRIORITY_MASK 0x000f0000
#define OPENPIC_PRIORITY_SHIFT 16
-#define OPENPIC_VECTOR_MASK 0x000000ff
+#define OPENPIC_VECTOR_MASK 0x0000ffff
/* interrupt destination cpu */
#ifndef OPENPIC_IDEST
diff --git a/sys/powerpc/include/openpicvar.h b/sys/powerpc/include/openpicvar.h
--- a/sys/powerpc/include/openpicvar.h
+++ b/sys/powerpc/include/openpicvar.h
@@ -32,7 +32,7 @@
#define OPENPIC_DEVSTR "OpenPIC Interrupt Controller"
-#define OPENPIC_IRQMAX 256 /* h/w allows more */
+#define OPENPIC_IRQMAX 512 /* h/w allows more */
#define OPENPIC_QUIRK_SINGLE_BIND 1 /* Bind interrupts to only 1 CPU */
#define OPENPIC_QUIRK_HIDDEN_IRQS 2 /* May have IRQs beyond FRR[NIRQ] */
@@ -59,6 +59,7 @@
u_int sc_nirq;
int sc_psim;
u_int sc_quirks;
+ uint32_t sc_vec_mask;
/* Saved states. */
uint32_t sc_saved_config;
diff --git a/sys/powerpc/powerpc/openpic.c b/sys/powerpc/powerpc/openpic.c
--- a/sys/powerpc/powerpc/openpic.c
+++ b/sys/powerpc/powerpc/openpic.c
@@ -151,6 +151,12 @@
OPENPIC_FEATURE_LAST_CPU_SHIFT) + 1;
sc->sc_nirq = ((x & OPENPIC_FEATURE_LAST_IRQ_MASK) >>
OPENPIC_FEATURE_LAST_IRQ_SHIFT) + 1;
+ /*
+ * Generate the vector mask used for IACK.
+ * Some PICs may not support the full 11 bit vector width, so clamp the
+ * mask to only the next-power-of-2 from the max IRQ.
+ */
+ sc->sc_vec_mask = (1 << fls(sc->sc_nirq)) - 1;
/*
* PSIM seems to report 1 too many IRQs and CPUs
@@ -294,8 +300,8 @@
while (1) {
vector = openpic_read(sc, OPENPIC_PCPU_IACK(cpuid));
- vector &= OPENPIC_VECTOR_MASK;
- if (vector == 255)
+ vector &= sc->sc_vec_mask;
+ if (vector == sc->sc_vec_mask)
break;
powerpc_dispatch_intr(vector, tf);
}

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