D59261.diff
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	diff --git a/stand/powerpc/ofw/cas.c b/stand/powerpc/ofw/cas.c
	--- a/stand/powerpc/ofw/cas.c
	+++ b/stand/powerpc/ofw/cas.c
	@@ -92,7 +92,11 @@
	#define OV5_SUBPROCS 1

	/* byte 23: interrupt controller */
	+#define OV5_INTC_INDEX 23
	#define OV5_INTC_XICS 0
	+#define OV5_INTC_XIVE_SUPPORT 0xc0
	+#define OV5_INTC_XIVE_EITHER 0x80
	+#define OV5_INTC_XIVE_NATIVE 0x40

	/* byte 24: MMU */
	#define OV5_MMU_INDEX 24
	@@ -199,7 +203,7 @@
	ihandle_t inst;
	cell_t err = 0;
	uint8_t buf[16], idx, val;
	- int i, len, rc, radix_mmu;
	+ int i, len, rc, radix_mmu, xive_native;
	const char *var;
	char *ov5;

	@@ -216,6 +220,7 @@
	return (0);

	radix_mmu = 0;
	+ xive_native = 0;
	ov5 = ibm_arch_vec.vec5.data;
	for (i = 0; i < len; i += 2) {
	idx = buf[i];
	@@ -223,6 +228,13 @@
	DPRINTF("idx 0x%02x val 0x%02x\n", idx, val);

	switch (idx) {
	+ case OV5_INTC_INDEX:
	+ if ((val & OV5_INTC_XIVE_NATIVE) \|\|
	+ (val & OV5_INTC_XIVE_EITHER))
	+ xive_native = 1;
	+
	+ break;
	+
	case OV5_MMU_INDEX:
	/*
	* Note that testing for OV5_MMU_RADIX/OV5_MMU_EITHER
	@@ -243,6 +255,12 @@
	}
	}

	+ if ((var = getenv("xive_native")) != NULL && var[0] == '0')
	+ xive_native = 0;
	+
	+ if (xive_native)
	+ ov5[OV5_INTC_INDEX] = OV5_INTC_XIVE_NATIVE;
	+
	if (!radix_mmu)
	/*
	* If radix is not supported, set radix_mmu to 0 to avoid
	@@ -262,6 +280,7 @@

	DPRINTF("MMU 0x%02x RADIX_EXT 0x%02x\n",
	ov5[OV5_MMU_INDEX], ov5[OV5_RADIX_EXT_INDEX]);
	+ DPRINTF("INTC 0x02x", ov5[OV5_INTC_INDEX]);
	rc = OF_call_method("ibm,client-architecture-support",
	inst, 1, 1, &ibm_arch_vec, &err);
	if (rc != 0 \|\| err) {