D57758.id.diff
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D57758.id.diff
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	diff --git a/sys/x86/include/x86_smp.h b/sys/x86/include/x86_smp.h
	--- a/sys/x86/include/x86_smp.h
	+++ b/sys/x86/include/x86_smp.h
	@@ -107,6 +107,8 @@
	void set_interrupt_apic_ids(void);
	void mem_range_AP_init(void);
	void topo_probe(void);
	+int cpu_get_pkg_id(int cpu);
	+int cpu_get_core_id(int cpu);

	/* functions in mp_machdep.c */
	void smp_cache_flush(smp_invl_cb_t curcpu_cb);
	diff --git a/sys/x86/x86/mp_x86.c b/sys/x86/x86/mp_x86.c
	--- a/sys/x86/x86/mp_x86.c
	+++ b/sys/x86/x86/mp_x86.c
	@@ -822,6 +822,28 @@
	}
	}

	+/*
	+ * Physical package (socket) id of a logical CPU: its APIC id with the
	+ * per-package bits shifted out. For drivers mapping per-socket hardware (e.g.
	+ * AMD RAPL package MSRs) onto real sockets, not NUMA domains.
	+ */
	+int
	+cpu_get_pkg_id(int cpu)
	+{
	+ return (cpu_apic_ids[cpu] >> pkg_id_shift);
	+}
	+
	+/*
	+ * Physical core id of a logical CPU: its APIC id with the SMT-thread bits
	+ * shifted out, so a core's two siblings share an id. For drivers mapping
	+ * per-core hardware (e.g. the SMT-shared AMD RAPL per-core MSR) onto real cores.
	+ */
	+int
	+cpu_get_core_id(int cpu)
	+{
	+ return (cpu_apic_ids[cpu] >> core_id_shift);
	+}
	+
	/*
	* Add a scheduling group, a group of logical processors sharing
	* a particular cache (and, thus having an affinity), to the scheduling