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Index: sys/arm/ti/ti_edma3.h
===================================================================
--- sys/arm/ti/ti_edma3.h
+++ sys/arm/ti/ti_edma3.h
@@ -77,5 +77,11 @@
void ti_edma3_param_write(unsigned int ch, struct ti_edma3cc_param_set *prs);
void ti_edma3_param_read(unsigned int ch, struct ti_edma3cc_param_set *prs);
+int ti_edma3_available(void);
+int ti_edma3_transfer_complete(unsigned int tcc);
+void ti_edma3_clear_completion(unsigned int tcc);
+int ti_edma3_event_missed(unsigned int ch);
+void ti_edma3_clear_event_missed(unsigned int ch);
+uint16_t ti_edma3_param_link(unsigned int set);
#endif /* _TI_EDMA3_H_ */
Index: sys/arm/ti/ti_edma3.c
===================================================================
--- sys/arm/ti/ti_edma3.c
+++ sys/arm/ti/ti_edma3.c
@@ -82,6 +82,10 @@
#define TI_EDMA3CC_S_IESRH(p) (0x2064 + ((p)*0x200))
#define TI_EDMA3CC_S_IPR(p) (0x2068 + ((p)*0x200))
#define TI_EDMA3CC_S_IPRH(p) (0x206C + ((p)*0x200))
+#define TI_EDMA3CC_EMR 0x300
+#define TI_EDMA3CC_EMRH 0x304
+#define TI_EDMA3CC_S_ICR(p) (0x2070 + ((p)*0x200))
+#define TI_EDMA3CC_S_ICRH(p) (0x2074 + ((p)*0x200))
#define TI_EDMA3CC_S_QEESR(p) (0x208C + ((p)*0x200))
#define TI_EDMA3CC_PARAM_OFFSET 0x4000
@@ -108,6 +112,16 @@
static struct ti_edma3_softc *ti_edma3_sc = NULL;
+/*
+ * The device tree splits edma3 into a channel controller and separate
+ * transfer controllers. This driver programs the channel controller.
+ */
+static struct ofw_compat_data compat_data[] = {
+ { "ti,edma3-tpcc", 1 },
+ { "ti,edma3", 1 },
+ { NULL, 0 }
+};
+
static struct resource_spec ti_edma3_mem_spec[] = {
{ SYS_RES_MEMORY, 0, RF_ACTIVE },
{ -1, 0, 0 }
@@ -143,7 +157,7 @@
if (!ofw_bus_status_okay(dev))
return (ENXIO);
- if (!ofw_bus_is_compatible(dev, "ti,edma3"))
+ if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
return (ENXIO);
device_set_desc(dev, "TI EDMA Controller");
@@ -178,8 +192,7 @@
return (ENXIO);
}
- /* FIXME: Require DTS from Linux kernel 5.7 */
- /* FIXME: OK to enable clkctrl here? */
+ /* The channel controller node gates the module clock. */
/* Enable Channel Controller */
ti_sysc_clock_enable(device_get_parent(dev));
@@ -418,3 +431,109 @@
bus_read_region_4(ti_edma3_sc->mem_res[0], TI_EDMA3CC_OPT(ch),
(uint32_t *) prs, 8);
}
+
+int
+ti_edma3_available(void)
+{
+
+ return (ti_edma3_sc != NULL);
+}
+
+int
+ti_edma3_transfer_complete(unsigned int tcc)
+{
+ uint32_t reg;
+
+ if (tcc < 32)
+ reg = ti_edma3_cc_rd_4(TI_EDMA3CC_S_IPR(0)) & (1 << tcc);
+ else
+ reg = ti_edma3_cc_rd_4(TI_EDMA3CC_S_IPRH(0)) &
+ (1 << (tcc - 32));
+
+ return (reg != 0);
+}
+
+void
+ti_edma3_clear_completion(unsigned int tcc)
+{
+
+ if (tcc < 32)
+ ti_edma3_cc_wr_4(TI_EDMA3CC_S_ICR(0), 1 << tcc);
+ else
+ ti_edma3_cc_wr_4(TI_EDMA3CC_S_ICRH(0), 1 << (tcc - 32));
+}
+
+int
+ti_edma3_event_missed(unsigned int ch)
+{
+ uint32_t reg;
+
+ if (ch < 32)
+ reg = ti_edma3_cc_rd_4(TI_EDMA3CC_EMR) & (1 << ch);
+ else
+ reg = ti_edma3_cc_rd_4(TI_EDMA3CC_EMRH) & (1 << (ch - 32));
+
+ return (reg != 0);
+}
+
+void
+ti_edma3_clear_event_missed(unsigned int ch)
+{
+
+ if (ch < 32)
+ ti_edma3_cc_wr_4(TI_EDMA3CC_EMCR, 1 << ch);
+ else
+ ti_edma3_cc_wr_4(TI_EDMA3CC_EMCRH, 1 << (ch - 32));
+}
+
+/*
+ * The transfer controllers need no programming, but their target modules stay
+ * clock gated until a driver claims them.
+ */
+static int
+ti_edma3tc_probe(device_t dev)
+{
+
+ if (!ofw_bus_status_okay(dev))
+ return (ENXIO);
+
+ if (!ofw_bus_is_compatible(dev, "ti,edma3-tptc"))
+ return (ENXIO);
+
+ device_set_desc(dev, "TI EDMA Transfer Controller");
+ return (BUS_PROBE_DEFAULT);
+}
+
+static int
+ti_edma3tc_attach(device_t dev)
+{
+
+ if (ti_sysc_clock_enable(device_get_parent(dev)) != 0) {
+ device_printf(dev, "cannot enable the module clock\n");
+ return (ENXIO);
+ }
+
+ return (0);
+}
+
+static device_method_t ti_edma3tc_methods[] = {
+ DEVMETHOD(device_probe, ti_edma3tc_probe),
+ DEVMETHOD(device_attach, ti_edma3tc_attach),
+ DEVMETHOD_END
+};
+
+static driver_t ti_edma3tc_driver = {
+ "ti_edma3tc",
+ ti_edma3tc_methods,
+ 0,
+};
+
+DRIVER_MODULE(ti_edma3tc, simplebus, ti_edma3tc_driver, 0, 0);
+
+/* Link is the offset of the set to reload from, relative to the CC base. */
+uint16_t
+ti_edma3_param_link(unsigned int set)
+{
+
+ return (TI_EDMA3CC_OPT(set));
+}

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